ENPIRION ECJ

EN2390QI
Preliminary Datasheet
9A Voltage Mode Synchronous Buck PWM
DC-DC Converter with Integrated Inductor
2Description
Features
The EN2390QI is a Power System on a Chip
(PowerSoC) DC-DC converter. It integrates MOSFET
switches, small-signal control circuits, compensation
and an integrated inductor in an advanced
11x10x3mm QFN module. It offers high efficiency,
excellent line and load regulation over temperature.
The EN2390QI operates over a wide input voltage
range and is specifically designed to meet the precise
voltage and fast transient requirements of highperformance products. The EN2390 features
frequency synchronization to an external clock, power
OK output voltage monitor, programmable soft-start
along with thermal and over current protection. The
device’s advanced circuit design, ultra high switching
frequency and proprietary integrated inductor
technology delivers high-quality, ultra compact, nonisolated DC-DC conversion.
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The Enpirion solution significantly helps in system
design and productivity by offering greatly simplified
board
design,
layout
and
manufacturing
requirements. In addition, overall system level
reliability is improved given the small number of
components required with the Enpirion solution.
Integrated Inductor, MOSFETS, Controller
Total Solution Size Estimate: 235mm2
Wide Input Voltage Range: 4.5V – 14V
2% VOUT Accuracy (Over Line/Load/Temperature)
Frequency Synchronization (External Clock)
Output Enable Pin and Power OK Signal
Programmable Soft-Start Time
Under Voltage Lockout Protection (UVLO)
Programmable Over Current Protection
Thermal Shutdown and Short Circuit Protection
RoHS compliant, MSL level 3, 260oC reflow
Applications
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All Enpirion products are RoHS compliant and leadfree manufacturing environment compatible.
Space Constrained Applications
Distributed Power Architectures
Output Voltage Ripple Sensitive Applications
Beat Frequency Sensitive Applications
Servers, Embedded Computing Systems,
LAN/SAN Adapter Cards, RAID Storage Systems,
Industrial Automation, Test and Measurement,
and Telecommunications
Sim Efficiency vs. Output Current
100
90
EFFICIENCY (%)
80
70
60
50
40
30
VOUT = 3.3V
20
VOUT = 1.8V
10
VOUT = 1.2V
CONDITIONS
VIN = 12.0V
AVIN = 3.3V
Dual Supply
0
0
Figure 1. Simplified Applications Circuit (Footprint Optimized)
1
2
3
4
5
6
OUTPUT CURRENT (A)
7
8
9
Figure 2. Highest Efficiency in Smallest Solution Size
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EN2390QI
Ordering Information
Part Number
EN2390QI
EN2390QI-E
Package Markings
EN2390QI
EN2390QI
Temp Rating (°C)
-40 to +85
Package Description
76-pin (11mm x 10mm x 3mm) QFN T&R
QFN Evaluation Board
Packing and Marking Information: http://www.enpirion.com/resource-center-packing-and-marking-information.htm
Pin Assignments (Top View)
Figure 3: Pin Out Diagram (Top View)
NOTE A: NC pins are not to be electrically connected to each other or to any external signal, ground, or voltage.
However, they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage.
NOTE B: Shaded area highlights exposed metal below the package that is not to be mechanically or electrically
connected to the PCB. Refer to Figure 10 for details.
NOTE C: White ‘dot’ on top left is pin 1 indicator on top of the device package.
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EN2390QI
Pin Description
I/O Legend:
PIN
P=Power
NAME
G=Ground
I/O
1-19,
29, 30,
61, 67,
72-76
NC
NC
20-28
VOUT
O
31, 32,
69-71
NC(SW)
NC
33-38
PGND
G
39-49
PVIN
P
50
AVINO
O
51
52
PG
BTMP
I/O
I/O
53
VDDB
O
54
BGND
G
55
S_IN
I
56
S_OUT
O
57
POK
O
58
ENABLE
I
59
AVIN
P
60
AGND
G
61
NC
62
VFB
I/O
63
EAIN
O
64
SS
I/O
65
RCLX
I/O
66
FADJ
I/O
NC=No Connect
I=Input O=Output
I/O=Input/Output
FUNCTION
NO CONNECT – These pins may be internally connected. Do not connect them
to each other or to any other electrical signal. Failure to follow this guideline
may result in device damage.
Regulated converter output. Connect these pins to the load and place output
capacitor between these pins and PGND pins 33-38.
NO CONNECT – These pins are internally connected to the common switching
node of the internal MOSFETs. They are not to be electrically connected to any
external signal, ground, or voltage. Failure to follow this guideline may result in
damage to the device.
Input/Output power ground. Connect these pins to the ground electrode of the
input and output filter capacitors. See VOUT and PVIN pin descriptions for more
details.
Input power supply. Connect to input power supply. Decouple with input
capacitor to PGND pins 33-38.
Internal 3.3V linear regulator output. Connect this pin to AVIN (Pin 59) for
applications where operation from a single input voltage (PVIN) is required. If
AVINO is being used, place a 1uF, X5R, capacitor between AVINO and AGND
as close as possible to AVINO.
Place a 0.1uF, X5R, capacitor between this pin and BTMP.
See pin 51 description.
Internal regulated voltage used for the internal control circuitry. Place a 1uF,
X5R, capacitor between this pin and BGND.
See pin 53 description.
Digital Input. This pin accepts either an input clock to phase lock the internal
switching frequency or a S_OUT signal from another EN2390QI. Leave this pin
floating if not used.
Digital Output. PWM signal is output on this pin. Leave this pin floating if not
used.
Power OK is an open drain transistor (pulled up to AVIN or similar voltage) used
for power system state indication. POK is logic high when VOUT is within -10%
to +20% of VOUT nominal.
Input Enable. Applying a logic high to this pin enables the output and initiates a
soft-start. Applying a logic Low disables the output.
3.3V Input power supply for the controller. Place a 0.1uF, X5R, capacitor
between AVIN and AGND
Analog Ground. This is the Ground return for the controller. Needs to be
connected to a quiet ground.
Test pin. For Enpirion Internal Use Only. Connect to GND plane at all times.
External Feedback Input. The feedback loop is closed through this pin. A
voltage divider at VOUT is used to set the output voltage. The mid-point of the
divider is connected to VFB. A phase lead capacitor from this pin to VOUT is
also required to stabilize the loop.
Optional Error Amplifier Input. Allows for customization of the control loop if
necessary.
Soft-Start node. The soft-start capacitor is connected between this pin and
AGND. The value of this capacitor determines the startup time.
Programmable over-current protection. Placement of a resistor on this pin will
adjust the over-current protection threshold. See Table 2 for the recommended
RCLX Value to set OCP at the nominal value specified in the Electrical
Characteristics table.
Adding a resistor (RFADJ) to this pin will adjust the switching frequency of the
EN2390QI. See Table 1 for suggested resistor values on RFADJ for various
PVIN/VOUT combinations to maximize efficiency.
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EN2390QI
PIN
NAME
68
CGND
77
PGND
I/O
FUNCTION
Connect to GND plane at all times.
Not a perimeter pin. Device thermal pad to be connected to the system GND
plane for heat-sinking purposes.
Absolute Maximum Ratings
CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond the recommended operating
conditions is not implied. Stress beyond the absolute maximum ratings may impair device life. Exposure to absolute
maximum rated conditions for extended periods may affect device reliability.
MIN
MAX
UNITS
Voltages on : PVIN, VOUT
PARAMETER
SYMBOL
-0.5
15
V
Pin Voltages – AVINO, AVIN, ENABLE, POK, S_IN, S_OUT
2.5
6.0
V
Pin Voltages – VFB, SS, EAIN, RCLX, FADJ
-0.5
2.75
V
PVIN Slew Rate
0.3
3
V/ms
-65
150
°C
150
°C
Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020A
260
°C
ESD Rating (based on Human Body Model)
2000
V
ESD Rating (based on CDM)
500
V
Storage Temperature Range
TSTG
Maximum Operating Junction Temperature
TJ-ABS Max
Recommended Operating Conditions
SYMBOL
MIN
MAX
UNITS
Input Voltage Range
PARAMETER
PVIN
4.5
14
V
AVIN: Controller Supply Voltage
AVIN
2.5
5.5
V
Output Voltage Range (Note 1)
VOUT
0.75
5
V
Output Current
IOUT
9
A
Operating Ambient Temperature
TA
-40
+85
°C
Operating Junction Temperature
TJ
-40
+125
°C
Thermal Characteristics
PARAMETER
SYMBOL
TYP
UNITS
Thermal Shutdown
TSD
160
°C
Thermal Shutdown Hysteresis
TSDH
35
°C
Thermal Resistance: Junction to Ambient (0 LFM) (Note 2)
θJA
15
°C/W
Thermal Resistance: Junction to Case (0 LFM)
θJC
1.5
°C/W
Note 1: RCLX resistor value may need to be raised for VOUT > VIN – 2.5V to increase current limit threshold.
Note 2: Based on 2oz. external copper layers and proper thermal design in line with EIJ/JEDEC JESD51-7 standard for
high thermal conductivity boards.
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EN2390QI
Electrical Characteristics
NOTE: VIN=12V, Minimum and Maximum values are over operating ambient temperature range unless otherwise noted.
Typical values are at TA = 25°C.
PARAMETER
MAX
UNITS
Operating Input Voltage
SYMBOL
PVIN
TEST CONDITIONS
MIN
4.5
TYP
14.0
V
Controller Input Voltage
AVIN
2.5
5.5
V
PVIN Under Voltage
Lock-out
UVLOPVIN
Voltage above which UVLO is not
asserted
2
V
AVIN Under Voltage
Lock-out rising
AVINUVLOR
Voltage above which UVLO is not
asserted
2.3
V
AVIN Under Voltage
Lock-out falling
AVINOVLOF
Voltage below which UVLO is
asserted
2.1
V
IAVIN
TBD
mA
AVINO
3.3
V
AVIN pin Input Current
Internal Linear
Regulator Output
Voltage
IPVINS
PVIN=12V, AVIN=3.3, ENABLE=0V
300
µA
IAVINS
PVIN=12V, AVIN=3.3, ENABLE=0V
50
µA
Feedback Pin Voltage
VFB
Feedback Pin Voltage
VFB
Feedback pin Input
Leakage Current
IFB
Feedback node voltage at:
VIN = 12V, ILOAD = 0, TA = 25°C
Feedback node voltage at:
4.5V ≤ VIN ≤ 14V
0A ≤ ILOAD ≤ 9A, TA = -40 to 85°C
VFB pin input leakage current
(Note 3)
Shut-Down Supply
Current
VOUT Rise Time
Soft Start Capacitor
Range
Maximum Continuous
Output Current
Over Current Trip Level
tRISE
CSS = 47nF (Note 4 and Note 5)
CSS_RANGE
0.594
0.60
0.606
V
0.588
0.60
0.612
V
5
nA
-5
1.5
2.0
2.5
ms
TBD
47
TBD
nF
9
A
IOUT_Max_Cont
IOCP
Reference Table 2
13.5
A
Disable Threshold
VDISABLE
ENABLE pin logic Low.
0.0
0.6
V
ENABLE Threshold
VENABLE
ENABLE pin logic High
1.8
AVIN
V
ENABLE Lockout Time
ENABLE pin Input
Current
Switching Frequency
TENLOCKOUT
IENABLE
FSW
180kΩ pull down (Note 3)
RFADJ =3kΩ
External SYNC Clock
Frequency Lock Range
FPLL_LOCK
Range of SYNC clock frequency
S_IN Threshold – Low
VS_IN_LO
S_IN clock logic low level
S_IN Threshold – High
VS_IN_HI
S_IN clock logic high level
S_OUT Threshold – Low
VS_OUT_LO
S_OUT clock logic low level
S_OUT Threshold –
High
VS_OUT_HI
S_OUT clock logic high level
POK Lower Threshold
POKLT
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Output voltage as a fraction of
expected output voltage
Enpirion Confidential
8
ms
4
µA
1.0
MHz
0.8
1.8
1.8
90
1.6
MHz
0.8
V
2.5
V
0.8
V
2.5
V
%
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EN2390QI
PARAMETER
SYMBOL
TEST CONDITIONS
POK Output low Voltage
VPOKL
With 4mA current sink into POK
POK Output Hi Voltage
VPOKH
PVIN range: 4.5V ≤ VIN ≤ 14V
POK pin VOH leakage
current
IPOKL
POK high (Note 3)
MIN
TYP
MAX
UNITS
0.4
V
AVIN
V
1
µA
Note 3: Parameter not production tested but is guaranteed by design.
Note 4: Rise time calculation begins when AVIN > VUVLO and ENABLE = HIGH.
Note 5: VOUT Rise Time Accuracy does not include soft-start capacitor tolerance.
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EN2390QI
Typical Performance Curves
Sim Efficiency vs. Output Current
100
90
90
80
80
EFFICIENCY (%)
EFFICIENCY (%)
Sim Efficiency vs. Output Current
100
70
60
50
40
30
VOUT = 3.3V
20
VOUT = 1.8V
10
VOUT = 1.2V
CONDITIONS
VIN = 12.0V
AVIN = 3.3V
Dual Supply
70
60
50
40
30
VOUT = 3.3V
20
VOUT = 1.8V
VOUT = 1.2V
10
0
0
0
1
2
3
4
5
6
OUTPUT CURRENT (A)
7
8
9
0
8.0
7.0
6.0
5.0
4.0
3.0
VOUT = 3.3V
2.0
VOUT = 1.8V
1.0
0.5 1
1.5 2 2.5 3 3.5 4 4.5 5
OUTPUT CURRENT (A)
5.5 6
Output Current De-rating
9.0
MAXIMUM OUTPUT CURRENT (A)
MAXIMUM OUTPUT CURRENT (A)
Output Current De-rating
CONDITIONS
VIN = 12V
TJMAX = 125 C
θJA = 15 C/W
10x11x3mm QFN
No Air Flow
0.0
9.0
8.0
7.0
6.0
5.0
4.0
3.0
VOUT = 3.3V
2.0
VOUT = 1.8V
1.0
CONDITIONS
VIN = 10V
12V
TJMAX = 125 C
θJA = 15 C/W
10x11x3mm QFN
No Air Flow
0.0
55
60
65
70
75
80
AMBIENT TEMPERATURE ( C)
85
55
Output Current De-rating with Air Flow
8.0
7.0
6.0
5.0
4.0
3.0
2.0
VOUT = 3.3V
1.0
60
65
70
75
80
AMBIENT TEMPERATURE ( C)
85
Output Current De-rating with Air Flow
9.0
MAXIMUM OUTPUT CURRENT (A)
MAXIMUM OUTPUT CURRENT (A)
CONDITIONS
V IN = 10.0V
AVIN = 3.3V
Dual Supply
CONDITIONS
VIN = 12V
TJMAX = 125 C
θJA = 12.5
15 C/W
C/W
10x11x3mm QFN
No Flow
Air
Air Flow
(200fpm)
0.0
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
VOUT = 3.3V
1.0
CONDITIONS
VIN = 12V
TJMAX = 125 C
θJA = 11
15 C/W
10x11x3mm QFN
No Flow
Air
Air Flow
(400fpm)
0.0
55
60
65
70
75
80
AMBIENT TEMPERATURE ( C)
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85
55
Enpirion Confidential
60
65
70
75
80
AMBIENT TEMPERATURE ( C)
85
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EN2390QI
Typical Performance Curves
Output Current De-rating
with Heat Sink and Air Flow
MAXIMUM OUTPUT CURRENT (A)
MAXIMUM OUTPUT CURRENT (A)
Output Current De-rating with Heat Sink
9.0
8.0
7.0
6.0
5.0
4.0
3.0
VOUT = 3.3V
2.0
VOUT = 1.8V
1.0
CONDITIONS
VIN = 12V
TJMAX = 125 C
θJA = 14
15 C/W
10x11x3mm QFN
No Air Flow
0.0
55
60
65
70
75
80
AMBIENT TEMPERATURE ( C)
85
9.0
8.0
7.0
6.0
5.0
4.0
3.0
VOUT = 3.3V
2.0
VOUT = 1.8V
1.0
CONDITIONS
VIN = 12V
TJMAX = 125 C
θJA = 11.5
15 C/W
C/W
10x11x3mm QFN
No Flow
Air
Air Flow
(200fpm)
0.0
55
60
65
70
75
80
AMBIENT TEMPERATURE ( C)
85
MAXIMUM OUTPUT CURRENT (A)
Output Current De-rating
with Heat Sink and Air Flow
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
VOUT = 3.3V
1.0
CONDITIONS
VIN = 12V
TJMAX = 125 C
θJA = 10
15 C/W
10x11x3mm QFN
No Flow
Air
Air Flow
(400fpm)
0.0
55
60
65
70
75
80
AMBIENT TEMPERATURE ( C)
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85
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EN2390QI
Typical Performance Characteristics
Output Ripple at 500MHz Bandwidth
VOUT
(AC Coupled)
Output Ripple at 500MHz Bandwidth
VOUT
(AC Coupled)
CONDITIONS
VIN = 12V
VOUT = 1.0V
IOUT = 9A
CIN = 2 x 22µF (1210)
COUT = 2 x 100 µF (1206) + 2 x 22µF (0805)
Load Transient from 0 to 9A
VOUT
(AC Coupled)
LOAD
CONDITIONS
VIN = 12V, VOUT = 1.0V
CIN = 2 x 22µF (1210)
COUT = 2 x 100µF (1206) + 2 x 22µF (0805)
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CONDITIONS
VIN = 12V
VOUT = 2.45V
IOUT = 6A
CIN = 2 x 22µF (1210)
COUT = 2 x 47 µF (1206) + 2 x 22µF(0805)
Load Transient from 0 to 4.5A
VOUT
(AC Coupled)
LOAD
Enpirion Confidential
CONDITIONS
VIN = 12V, VOUT = 1.0V
CIN = 2 x 22µF (1206)
COUT = 2 x 100µF (1206) + 2 x 22µF (0805)
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EN2390QI
Functional Block Diagram
Figure 4: Functional Block Diagram
Functional Description
small size input and output capacitors, as well as a
wide loop bandwidth within a small foot print.
Synchronous Buck Converter
The EN2390QI is a highly integrated synchronous,
buck converter with integrated controller, power
MOSFET switches and integrated inductor. The
nominal input voltage (PVIN) range is 4.5V to 14V
and can support up to 9A of continuous output
current. The output voltage is programmed using
an external resistor divider network. The control
loop utilizes a Type IV Voltage-Mode compensation
network and maximizes on a low-noise PWM
topology. Much of the compensation circuitry is
internal to the device. However, a phase lead
capacitor is required along with the output voltage
feedback resistor divider to complete the Type IV
compensation network.. The high switching
frequency of the EN2390QI enables the use of
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Protection Features:
The power supply has the following protection
features:
• Programmable Over-Current Protection
• Thermal Shutdown with Hysteresis.
• Under-Voltage Lockout Protection
Additional Features:
•
•
•
Switching Frequency Synchronization.
Programmable Soft-Start
Power OK Output Monitoring
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EN2390QI
Power Up Sequence
The EN2390QI is designed to be powered by either
a single input supply (PVIN) or two separate
supplies: one for PVIN and the other for AVIN.
Single Input Supply Application (PVIN):
The EN2390QI has an internal linear regulator that
converts PVIN to 3.3V. The output of the linear
regulator is provided on the AVINO pin. AVINO
should be connected to AVIN on the EN2390QI. In
this application, the following external components
are required: Place a 1µF, X5R, capacitor between
AVINO and AGND as close as possible to AVINO.
Place a 0.1µF, X5R, capacitor between AVIN and
AGND as close as possible to AVIN. In addition,
place a resistor (RVB) between VDDB and AVIN, as
shown in Figure 1. Enpirion recommends
RVB=4.75kΩ. In this application, ENABLE cannot be
asserted before PVIN. If no external enable signal
is used, tying ENABLE to AVIN meets this
requirement.
Dual Input Supply Application (PVIN and AVIN):
In this application, place a 0.1µF, X5R, capacitor
between AVIN and AGND as close as possible to
AVIN. Refer to Figure 5 for a recommended
schematic for a dual input supply application.
For dual input supply applications, the sequencing
of the two input supplies, PVIN and AVIN, is very
important. During power up, neither ENABLE nor
PVIN should be asserted before AVIN. There are
two common acceptable turn-on/off sequences for
the device. ENABLE can be tied to AVIN and come
up with it, and PVIN can be ramped up and down
as needed. Alternatively, PVIN can be brought high
after AVIN is asserted, and the device can be
turned on and off by toggling the ENABLE pin.
Enable Operation
The ENABLE pin provides a means to enable
normal operation or to shut down the device. A
logic high will enable the converter into normal
operation. When the ENABLE pin is asserted (high)
the device will undergo a normal soft-start. A logic
low will disable the converter. A logic low will power
down the device in a controlled manner and the
device is subsequently shut down. The ENABLE
signal has to be low for at least the ENABLE
Lockout Time (8ms) in order for the device to be reenabled.
Pre-Bias Operation
The EN2390QI is not designed to be turned on into
a pre-biased output voltage.
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Figure 5: Dual Input Supply (PVIN and AVIN)
Recommended Schematic
Frequency Synchronization
The switching frequency of the EN2390QI can be
phase-locked to an external clock source to move
unwanted beat frequencies out of band. The
internal switching clock of the EN2390QI can be
phase locked to a clock signal applied to the S_IN
pin. An activity detector recognizes the presence of
an external clock signal and automatically phaselocks the internal oscillator to this external clock.
Phase-lock will occur as long as the input clock
frequency is in the range of 0.8MHz to 1.6MHz.
When no clock is present, the device reverts to the
free running frequency of the internal oscillator.
Adding a resistor (RFS) to the FADJ pin will adjust
the frequency lower. If a 3KΩ resistor is placed on
FADJ the nominal switching frequency of the
EN2390QI is 1MHz. The efficiency performance of
the
EN2390QI
for
various
PVIN/VOUT
combinations can be optimized by adjusting the
switching frequency. Table 1 shows recommended
RFS values for various PVIN/VOUT combinations in
order to optimize performance of the EN2390QI.
PVIN
12V
5V
VOUT
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
RFS
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Table 1: Recommended RFS Values
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EN2390QI
Spread Spectrum Mode
The external clock frequency may be swept
between 0.8MHz and 1.6MHz at repetition
rates of up to 10 kHz in order to reduce EMI
frequency components.
Soft-Start Operation
Soft start is a means to ramp the output voltage
gradually upon start-up. The output voltage rise
time is controlled by the choice of soft-start
capacitor, which is placed between the SS pin (pin
78) and the AGND pin (pin 74).
Rise Time (ms): TR ≈ Css [nF] x 0.067
During start-up of the converter, the reference
voltage to the error amplifier is linearly increased to
its final level by an internal current source of
approximately 10µA. Typical soft-start rise time is
~3.2ms with SS capacitor value of 47nF. The rise
time is measured from when VIN > VUVLOR and
ENABLE pin voltage crosses its logic high
threshold to when VOUT reaches its programmed
value.
POK Operation
The POK signal is an open drain signal (requires a
pull up resistor to AVIN or similar voltage) from the
converter indicating the output voltage is within the
specified range. Typically, a 100kΩ or lower
resistance is used as the pull-up resistor. The POK
signal will be logic high (AVIN) when the output
voltage is above 90% of the programmed VOUT. If
the output voltage goes outside of this range, the
POK signal will be a logic low.
Over-Current Protection (OCP)
The current limit function is achieved by sensing
the current flowing through a sense PFET. When
the sensed current exceeds the current limit, both
power FETs are turned off for the rest of the
switching cycle. If the over-current condition is
removed, the over-current protection circuit will reenable PWM operation. If the over-current condition
persists, the circuit will continue to protect the load.
The OCP trip point is nominally set as specified in
the Electrical Characteristics table. In the event the
Enpirion 2012 all rights reserved, E&OE
OCP circuit trips consistently in normal operation,
the device enters a hiccup mode. While in hiccup
mode, the device is disabled for a short while and
restarted with a normal soft-start. The hiccup time
is approximately 32ms. This cycle can continue
indefinitely as long as the over current condition
persists.
The OCP trip point can be programmed to trip at a
lower level via the RCLX pin. The value of the
resistor connected between RCLX and ground will
determine the OCP trip point. Generally, the higher
the RCLX value, the higher the current limit
threshold. Note that if RCLX pin is left open the
output current will be unlimited and the device will
not have current limit protection. Reference Table 2
for a list of recommended resistor values on RCLX
that will set the OCP trip point at the typical value of
13.5A,
also
specified
in
the
Electrical
Characteristics table. This table assumes VOUT < VIN
– 2.5V. Contact techsupport@enpirion.com for
specific RCLX values to be use for special cases.
VOUT Range
0.6V < VOUT ≤ 0.9V
0.9V < VOUT ≤ 1.2V
1.2V < VOUT ≤ 2.0V
2.0V < VOUT ≤ 5.0V
RCLX Value
36.5k
38.4k
40.2k
45.3k
Table 2: Recommended RCLX Values vs. VOUT
Thermal Overload Protection
Thermal shutdown circuit will disable device
operation when the junction temperature exceeds
approximately 150ºC. After a thermal shutdown
event, when the junction temperature drops by
approx 20ºC, the converter will re-start with a
normal soft-start.
Input Under-Voltage Lock-Out (UVLO)
Internal circuits ensure that the converter will not
start switching until the input voltage is above the
specified minimum voltage. Hysteresis, input deglitch and output leading edge blanking ensures
high noise immunity and prevents false UVLO
triggers.
Enpirion Confidential
www.enpirion.com, Page 12
EN2390QI
Application Information
Output Voltage Programming and Loop
Compensation
The EN2390QI output voltage is programmed using
a simple resistor divider network. A phase lead
capacitor (CA) plus a resistor (RCA) are required for
stabilizing the loop. Figure 6 shows the required
components and the equations to calculate their
The EN2390QI output voltage is determined by the
voltage presented at the VFB pin. This voltage is
set by way of a resistor divider between VOUT and
AGND with the midpoint going to VFB.
The EN2390QI uses a Type IV compensation
network.
Most of this network is integrated.
However a phase lead capacitor and a resistor are
required in parallel with the upper resistor of the
external feedback network (see Figure 6). Total
compensation is optimized for either low output
ripple or small solution size, and will result in a wide
loop bandwidth and excellent load transient
performance for most applications. See Table 5 for
compensation values for both options based on
input and output voltage conditions.
In some cases modifications to the compensation
may be required. The EN2390QI provides the
capability to modify the control loop response to
allow for customization for specific applications.
For more information, contact Enpirion Applications
Engineering support (techsupport@enpirion.com).
rated. Y5V or equivalent dielectric formulations
must not be used as these lose too much
capacitance with frequency, temperature and
bias voltage. In some applications, lower value
capacitors are needed in parallel with the larger,
capacitors in order to provide high frequency
decoupling.
Table 3 contains a list of
recommended input capacitors.
Recommended Input Capacitors
Description
MFG
P/N
22µF, 16V, X5R,
10%, 1206
Murata
GRM31CR61C226ME15
22µF, 16V, X5R,
20%, 1206
Taiyo
Yuden
EMK316ABJ226ML-T
Table 3: Recommended Input Capacitors
Output Capacitor Selection
As seen from Table 5, the EN2390QI has been
optimized for use with two 47µF/0805 and two
22µF/0805 output capacitors for best performance.
For smallest solution size, various combinations of
output capacitance may be used. See Table 5 for
details. Low ESR ceramic capacitors are required
with X5R or X7R rated dielectric formulation. Y5V
or equivalent dielectric formulations must not
be used as these lose too much capacitance
with frequency, temperature and bias voltage.
Table 4 contains a list of recommended output
capacitors
Output ripple voltage is determined by the
aggregate output capacitor impedance. Capacitor
impedance, denoted as Z, is comprised of
capacitive reactance, effective series resistance,
ESR, and effective series inductance, ESL
reactance.
Figure 6: VOUT Resistor Divider & Compensation
Components. RA equation is only valid
for Best Performance option. For Small
Solution Size option, see Table 5.
Input Capacitor Selection
The EN2390QI requires two 22µF/1206 input
capacitor. Low-cost, low-ESR ceramic capacitors
should be used as input capacitors for this
converter. The dielectric must be X5R or X7R
Enpirion 2012 all rights reserved, E&OE
values. The values recommended for CA and RCA
will vary with each PVIN and VOUT combination.
The EN2390 solution can be optimized for either
smallest size or highest performance. Please see
Table 5 for a list of recommended CA and RCA
values for each solution option.
Placing output capacitors in parallel reduces the
impedance and will hence result in lower ripple
voltage.
Enpirion Confidential
1
Z Total
=
1
1
1
+
+ ... +
Z1 Z 2
Zn
www.enpirion.com, Page 13
EN2390QI
Recommended Output Capacitors
Description
47µF, 6.3V, X5R,
20%, 1206
47µF, 10V, X5R,
20%, 1206
22µF, 10V, X5R,
20%, 0805
22µF, 10V, X5R,
20%, 0805
100µF, 6.3V, X5R,
20%, 1206
MFG
P/N
Murata
GRM31CR60J476ME19L
Taiyo
Yuden
LMK316BJ476ML-T
Panasonic
ECJ-2FB1A226M
Taiyo
Yuden
LMK212BJ226MG-T
Murata
GRM31CR60J107ME39L
Taiyo
Yuden
JMK316BJ107ML-T
Table 4: Recommended Output Capacitors
Enpirion 2012 all rights reserved, E&OE
Enpirion Confidential
www.enpirion.com, Page 14
EN2390QI
Best Performance
Smallest Solution Size
Cin = 2 x 22uF/1206
Cin = 2 x 22uF/1206
Cout = 3 x 47uF/0805 + 2 x 22uF/0805
Vout ≤ 1.8V, Cout = 2x47uF (0805)-6.3V
(Vout≤3.3V)
3.3V
> Vout > 1.8V, Cout = 2x47uF (1206)Cout = 2 x 47uF/1206 + 2 x 22uF/0805
10V
(Vout>3.3V)
Nominal
Nominal
Nominal Nominal
RA
CA
RCA
RA
CA
RCA
PVIN VOUT
Ripple
Deviation
Ripple
Deviation
(KΩ)
(pF) (KΩ)
(KΩ)
(pF)
(KΩ)
(mV)
(mV)
(mV)
(mV)
0.9V
200
39
16
12
91
75
18
8.2
15
93
1.2V
200
33
15
13
96
75
18
8.2
21
104
1.5V
200
27
13
14
109
75
18
8.2
27
110
14V
1.8V
200
22
12
16
116
75
18
8.2
35
120
2.5V
200
18
8.2
20
143
75
15
8.2
54
150
3.3V
200
12
4.3
30
196
75
10
8.2
81
215
5.0V
200
5.6
0
46
295
75
12
8.2
106
305
0.9V
200
47
12
11
97
75
27
5.1
15
96
1.2V
200
39
10
12
106
75
27
5.1
21
104
1.5V
200
33
9.1
13
113
75
27
5.1
27
112
12V
1.8V
200
27
7.5
15
123
75
27
5.1
34
130
2.5V
200
22
3.9
18
149
75
22
5.1
52
162
3.3V
200
15
0
26
198
75
15
5.1
77
221
5.0V
200
6.8
0
39
306
75
18
5.1
96
313
0.9V
200
56
7.5
10
101
75
56
2
15
99
1.2V
200
47
6.2
11
113
75
56
2
20
107
1.5V
200
47
4.3
12
116
75
39
2
26
122
10V
1.8V
200
39
3.0
13
121
75
39
2
33
126
2.5V
200
27
0
16
157
75
33
2
50
169
3.3V
200
18
0
23
216
75
22
2
71
241
5.0V
200
8.2
0
34
333
75
22
2
82
290
0.9V
200
82
3.3
9
110
75
100
0
15
108
1.2V
200
68
1.6
10
115
75
100
0
20
113
1.5V
200
56
0
10
123
75
82
0
25
122
8.0V
1.8V
200
47
0
11
132
75
68
0
31
136
2.5V
200
39
0
14
160
75
47
0
46
183
3.3V
200
27
0
20
210
75
33
0
62
253
5.0V
200
12
0
25
338
75
33
0
62
301
0.9V
200
100
0
8
117
75
100
0
14
121
1.2V
200
82
0
8
124
75
100
0
19
128
1.5V
200
82
0
9
130
75
100
0
24
138
6.6V
1.8V
200
68
0
9
142
75
100
0
29
149
2.5V
200
47
0
12
175
75
68
0
41
188
3.3V
200
33
0
16
222
75
47
0
53
239
0.9V
200
150
0
7
132
75
100
0
13
152
1.2V
200
120
0
7
138
75
100
0
18
161
1.5V
200
120
0
8
142
75
100
0
22
177
5V
1.8V
200
100
0
8
154
75
100
0
25
183
2.5V
200
68
0
9
185
75
100
0
33
216
3.3V
200
47
0
12
231
75
68
0
36
265
Table 5: RA, CA, and RCA Values for Various PVIN/VOUT Combinations: Low VOUT Ripple vs. Smallest Solution Size. Use
the equations in Figure 6 to calculate RA (for low VOUT ripple option) and RB.
Note 6: Nominal Deviation is for a 9A load transient step.
Note 7: For compensation values of output voltage in between the specified output voltages, choose compensation values
of the lower output voltage setting.
Enpirion 2012 all rights reserved, E&OE
Enpirion Confidential
www.enpirion.com, Page 15
EN2390QI
Thermal Considerations
Thermal considerations are important power supply
design facts that cannot be avoided in the real
world. Whenever there are power losses in a
system, the heat that is generated by the power
dissipation needs to be accounted for. The Enpirion
PowerSoC helps alleviate some of those concerns.
The Enpirion EN2390QI DC-DC converter is
packaged in an 8x11x3mm 68-pin QFN package.
The QFN package is constructed with copper lead
frames that have exposed thermal pads. The
exposed thermal pad on the package should be
soldered directly on to a copper ground pad on the
printed circuit board (PCB) to act as a heat sink.
The recommended maximum junction temperature
for continuous operation is 125°C. Continuous
operation above 125°C may reduce long-term
reliability. The device has a thermal overload
protection circuit designed to turn off the device at
an approximate junction temperature value of
150°C.
The EN2390QI is guaranteed to support the full 4A
output current up to 85°C ambient temperature.
The following example and calculations illustrate
the thermal performance of the EN2390QI.
For VIN = 12V, VOUT = 1.2V at 9A, η ≈ 80%
η = POUT / PIN = 80% = 0.8
PIN = POUT / η
PIN ≈ 10.8W / 0.8 ≈ 13.5W
The power dissipation (PD) is the power loss in the
system and can be calculated by subtracting the
output power from the input power.
PD = PIN – POUT
≈ 13.5W – 10.8W ≈ 2.7W
With the power dissipation known, the temperature
rise in the device may be estimated based on the
theta JA value (θJA). The θJA parameter estimates
how much the temperature will rise in the device for
every watt of power dissipation. The EN2390QI has
a θJA value of 16 ºC/W without airflow.
Determine the change in temperature (∆T) based
on PD and θJA.
∆T = PD x θJA
∆T ≈ 2.7W x 16°C/W = 43.2°C ≈ 43°C
VIN = 12V
The junction temperature (TJ) of the device is
approximately the ambient temperature (TA) plus
the change in temperature. We assume the initial
ambient temperature to be 25°C.
VOUT = 1.2V
TJ = TA + ∆T
IOUT = 9A
TJ ≈ 25°C + 43°C ≈ 67°C
First calculate the output power.
The maximum operating junction temperature
(TJMAX) of the device is 125°C, so the device can
operate at a higher ambient temperature. The
maximum ambient temperature (TAMAX) allowed can
be calculated.
Example:
POUT = 1.2V x 9A = 10.8W
Next, determine the input power based on the
efficiency (η) shown in Figure 7.
TAMAX = TJMAX – PD x θJA
Sim Efficiency vs. Output Current
≈ 125°C – 43°C ≈ 82°C
100
The maximum ambient temperature the device can
reach is 82°C given the input and output conditions.
Note that the efficiency will be slightly lower at
higher temperatures and this calculation is an
estimate.
90
EFFICIENCY (%)
80
70
60
50
40
30
VOUT = 3.3V
20
VOUT = 1.8V
10
VOUT = 1.2V
CONDITIONS
VIN = 12.0V
AVIN = 3.3V
Dual Supply
0
0
1
2
3
4
5
6
OUTPUT CURRENT (A)
7
8
9
Figure 7: Efficiency vs. Output Current
Enpirion 2012 all rights reserved, E&OE
Enpirion Confidential
www.enpirion.com, Page 16
EN2390QI
Engineering Schematic
TBD
Figure 8: Engineering Schematic with Engineering Notes
Enpirion 2012 all rights reserved, E&OE
Enpirion Confidential
www.enpirion.com, Page 17
EN2390QI
Layout Recommendation
TBD
Figure 9: Top Layer Layout with Critical Components
(Top View). See Figure 8 for corresponding schematic.
This layout only shows the critical components and
top layer traces for minimum footprint in singlesupply mode with ENABLE tied to AVIN. Alternate
circuit configurations & other low-power pins need
to be connected and routed according to customer
application. Please see the Gerber files at
www.enpirion.com for details on all layers.
Recommendation 1: Input and output filter
capacitors should be placed on the same side of
the PCB, and as close to the EN2390QI package
as possible. They should be connected to the
device with very short and wide traces. Do not use
thermal reliefs or spokes when connecting the
capacitor pads to the respective nodes. The +V and
GND traces between the capacitors and the
EN2390QI should be as close to each other as
possible so that the gap between the two nodes is
minimized, even under the capacitors.
Recommendation 2: The PGND connections for
the input and output capacitors on layer 1 need to
have a slit between them in order to provide some
separation between input and output current loops.
Recommendation 3: The system ground plane
should be the first layer immediately below the
surface layer. This ground plane should be
continuous and un-interrupted below the converter
and the input/output capacitors.
Recommendation 4: The thermal pad underneath
the component must be connected to the system
ground plane through as many vias as possible.
The drill diameter of the vias should be 0.33mm,
and the vias must have at least 1 oz. copper plating
on the inside wall, making the finished hole size
around 0.20-0.26mm. Do not use thermal reliefs or
Enpirion 2012 all rights reserved, E&OE
spokes to connect the vias to the ground plane.
This connection provides the path for heat
dissipation from the converter.
Recommendation 5: Multiple small vias (the same
size as the thermal vias discussed in
recommendation 4) should be used to connect
ground terminal of the input capacitor and output
capacitors to the system ground plane. It is
preferred to put these vias along the edge of the
GND copper closest to the +V copper. These vias
connect the input/output filter capacitors to the
GND plane, and help reduce parasitic inductances
in the input and output current loops. If vias cannot
be placed under the capacitors, then place them on
both sides of the slit in the top layer PGND copper.
Recommendation 6: AVIN is the power supply for
the small-signal control circuits. It should be
connected to the input voltage at a quiet point. In
Figure 9 this connection is made at the input
capacitor.
Recommendation 7: The layer 1 metal under the
device must not be more than shown in Figure 9.
Refer to the section regarding Exposed Metal on
Bottom of Package. As with any switch-mode
DC/DC converter, try not to run sensitive signal or
control lines underneath the converter package on
other layers.
Recommendation 8: The VOUT sense point should
be just after the last output filter capacitor. Keep the
sense trace short in order to avoid noise coupling
into the node. Contact Enpirion Technical Support
for any remote sensing applications.
Recommendation 9: Keep RA, CA, RB, and RCA
close to the VFB pin (Refer to Figure 9). The VFB
pin is a high-impedance, sensitive node. Keep the
trace to this pin as short as possible. Whenever
possible, connect RB directly to the AGND pins 52
and 53 instead of going through the GND plane.
Recommendation 10: Follow all the layout
recommendations as close as possible to optimize
performance. Enpirion provides schematic and
layout reviews for all customer designs. Contact
Enpirion Applications Engineering for detailed
support (techsupport@enpirion.com).
Enpirion Confidential
www.enpirion.com, Page 18
EN2390QI
Design Considerations for Lead-Frame Based Modules
Exposed Metal on Bottom of Package
Lead-frames offer many advantages in thermal performance, in reduced electrical lead resistance, and in
overall foot print. However, they do require some special considerations.
In the assembly process lead frame construction requires that, for mechanical support, some of the lead-frame
cantilevers be exposed at the point where wire-bond or internal passives are attached. This results in several
small pads being exposed on the bottom of the package, as shown in Figure 10.
Only the thermal pad and the perimeter pads are to be mechanically or electrically connected to the PC board.
The PCB top layer under the EN2390QI should be clear of any metal (copper pours, traces, or vias) except for
the thermal pad. The “shaded-out” area in Figure 10 represents the area that should be clear of any metal on
the top layer of the PCB. Any layer 1 metal under the shaded-out area runs the risk of undesirable shorted
connections even if it is covered by soldermask.
The solder stencil aperture should be smaller than the PCB ground pad. This will prevent excess solder from
causing bridging between adjacent pins or other exposed metal under the package. Please consult the
Enpirion Manufacturing Application Note for more details and recommendations.
Figure 10: Lead-Frame exposed metal (Bottom View)
Shaded area highlights exposed metal that is not to be mechanically or electrically connected to the PCB.
Enpirion 2012 all rights reserved, E&OE
Enpirion Confidential
www.enpirion.com, Page 19
EN2390QI
Recommended PCB Footprint
Figure 11: EN2390QI PCB Footprint (Top View)
Enpirion 2012 all rights reserved, E&OE
Enpirion Confidential
www.enpirion.com, Page 20
EN2390QI
Package and Mechanical
Figure 12: EN2390QI Package Dimensions (Bottom View)
Packing and Marking Information: http://www.enpirion.com/resource-center-packing-and-marking-information.htm
Contact Information
Enpirion, Inc.
Perryville III Corporate Park
53 Frontage Road - Suite 210
Hampton, NJ 08827 USA
Phone: 1.908.894.6000
Fax: 1.908.894.6090
Enpirion reserves the right to make changes in circuit design and/or specifications at any time without notice. Information furnished by Enpirion is
believed to be accurate and reliable. Enpirion assumes no responsibility for its use or for infringement of patents or other third party rights, which may
result from its use. Enpirion products are not authorized for use in nuclear control systems, as critical components in life support systems or equipment
used in hazardous environment without the express written authority from Enpirion
Enpirion 2012 all rights reserved, E&OE
Enpirion Confidential
www.enpirion.com, Page 21