ONSEMI AMIS-30543-D

AMIS-30543
Micro-Stepping Motor
Driver
Introduction
The AMIS−30543 is a micro−stepping stepper motor driver for
bipolar stepper motors. The chip is connected through I/O pins and an
SPI interface with an external microcontroller. It has an on−chip
voltage regulator, reset−output and watchdog reset, able to supply
peripheral devices. AMIS−30543 contains a current−translation table
and takes the next micro−step depending on the clock signal on the
“NXT” input pin and the status of the “DIR” (=direction) register or
input pin. The chip provides a so−called “speed and load angle”
output. This allows the creation of stall detection algorithms and
control loops based on load−angle to adjust torque and speed. It is
using a proprietary PWM algorithm for reliable current control.
The AMIS−30543 is implemented in I2T100 technology, enabling
both high−voltage analog circuitry and digital functionality on the
same chip. The chip is fully compatible with the automotive voltage
requirements.
The AMIS−30543 is ideally suited for general−purpose stepper
motor applications in the automotive, industrial, medical, and marine
environment. With the on−chip voltage regulator it further reduces the
BOM for mechatronic stepper applications.
http://onsemi.com
1
32
QFN32
CASE 485J
MARKING DIAGRAM
32
1
AMIS30543
0C543−001
AWLYYWWG
Key Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Dual H−Bridge for 2−Phase Stepper Motors
Programmable Peak−Current Up to 3 A
On−Chip Current Translator
SPI Interface
Speed and Load Angle Output
Eleven Step Modes from Full Step Up to 128 Micro−Steps
Fully Integrated Current−Sense
PWM Current Control with Automatic Selection of Fast and Slow
Decay
Low EMC PWM with Selectable Voltage Slopes
Active Fly−Back Diodes
Full Output Protection and Diagnosis
Thermal Warning and Shutdown
Compatible with 5 V and 3.3 V Microcontrollers
Integrated 5 V Regulator to Supply External Microcontroller
Integrated Reset Function to Reset External Microcontroller
Integrated Watchdog Function
These Devices are Pb−Free and are RoHS Compliant
© Semiconductor Components Industries, LLC, 2012
November, 2012 − Rev. 1
1
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 37 of this data sheet.
Publication Order Number:
AMIS−30543/D
AMIS−30543
BLOCK DIAGRAM
CLK
Timebase
VDD
CPN CPP VCP
Vreg
Chargepump
POR
EMC
CS
DI
DO
NXT
Logic &
Registers
DIR
P
W
M
T
R
A
N
S
L
A
T
O
R
OTP
SPI
Load
Angle
SLA
I−sense
EMC
P
W
M
Temp
.
Sense
POR/WD
AMIS−30543
Band−
gap
TST0
GND
Figure 1. Block Diagram AMIS−30543
28
MOTXP
29
VBB
30
MOTXP
31
POR/WD
TSTO
DO
DI
CLK
NXT
VDD
GND
32
27
26
25
1
24
GND
2
23
GND
3
22
4
21
AMIS−30543
MOTXN
MOTXN
20
MOTYN
6
19
7
18
8
17
MOTYN
GND
GND
DIR
5
ERR
SLA
14
15
16
MOTYP
13
MOTYP
VBB
12
CS
CPP
CPN
11
VCP
10
CLR
9
Figure 2. Pin Out AMIS−30543
http://onsemi.com
2
MOTXP
MOTXN
MOTYP
MOTYN
I−sense
CLR
ERR
VBB
AMIS−30543
Table 1. PIN LIST AND DESCRIPTION
Description
Equivalent
Schematic
Name
Pin
Type
GND
1
Ground
Supply
DI
2
SPI Data In
Digital Input
Type 2
CLK
3
SPI Clock Input
Digital Input
Type 2
NXT
4
Next micro−step input
Digital Input
Type 2
DIR
5
Direction input
Digital Input
Type 2
ERR
6
Error output (open drain)
Digital Output
Type 4
SLA
7
Speed load angle output
Analog Output
Type 5
/
8
No function (to be left open in normal operation)
CPN
9
Negative connection of charge pump capacitor
High Voltage
CPP
10
Positive connection of charge pump capacitor
High Voltage
VCP
11
Charge pump filter−capacitor
High Voltage
CLR
12
“Clear” = chip reset input
Digital Input
Type 1
CS
13
SPI chip select input
Digital Input
Type 2
Type 3
VBB
14
High voltage supply Input
Supply
MOTYP
15, 16
Negative end of phase Y coil output
Driver Output
GND
17, 18
Ground, heat sink
Supply
MOTYN
19, 20
Positive end of phase Y coil output
Driver Output
MOTXN
21, 22
Positive end of phase X coil output
Driver Output
GND
23, 24
Ground, heat sink
Supply
MOTXP
25, 26
Negative end of phase X coil output
Driver Output
VBB
27
High voltage supply input
Supply
Type 3
POR/WD
28
Power−on−reset and watchdog reset output (open drain)
Digital Output
Type 4
TST0
29
Test pin input (to be tied to ground in normal operation)
Digital Input
/
30
No function (to be left open in normal operation)
DO
31
SPI data output (open drain)
Digital Output
Type 4
VDD
32
Logic supply output (needs external decoupling capacitor)
Supply
Type 3
Table 2. ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Min
Max
Unit
VBB
Analog DC supply voltage (Note 1)
−0.3
+40
V
TST
Storage temperature
−55
+160
°C
Junction Temperature under bias (Note 2)
−50
+175
°C
VESD
Electrostatic discharges on component level, All pins (Note 3)
−2
+2
kV
VESD
Electrostatic discharges on component level, HiV pins (Note 4)
−8
+8
kV
TJ
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. For limited time < 0.5 s.
2. Circuit functionality not guaranteed.
3. Human body model (100 pF via 1.5 kW, according to JEDEC EIA−JESD22−A114−B).
4. HiV = High Voltage Pins MOTxx, VBB, GND; (100 pF via 1.5 kW, according to JEDEC EIA−JESD22−A114−B).
http://onsemi.com
3
AMIS−30543
EQUIVALENT SCHEMATICS
Following figure gives the equivalent schematics of the user relevant inputs and outputs. The diagrams are simplified
representations of the circuits used.
4K
IN
OUT
Rin
TYPE 1: CLR input
IN
TYPE 4: DO, ERRB and PORB/WD open drain outputs
4K
Rout
TYPE 2 : CLK , DI, CSB , NXT , DIR inputs
TYPE 5: SLA analog output
VDD
VBB
VDD
VBB
.
TYPE 3: VDD and VBB power supply inputs
Figure 3. In− and Output Equivalent Diagrams
http://onsemi.com
4
SLA
AMIS−30543
PACKAGE THERMAL CHARACTERISTICS
The AMIS−30543 is available in a NQFP32 package. For
cooling optimizations, the NQFP has an exposed thermal
pad which has to be soldered to the PCB ground plane. The
ground plane needs thermal vias to conduct the heat to the
bottom layer. Figure 4 gives an example for good power
distribution solutions.
For precise thermal cooling calculations the major
thermal resistances of the device are given in Table 5. The
thermal media to which the power of the devices has to be
given are:
• Static environmental air (via the case)
• PCB board copper area (via the exposed pad)
The major thermal resistances of the device are the Rth
from the junction to the ambient (Rthja) and the overall Rth
from the junction to exposed pad (Rthjp). In Table 4 below
one can find the values for the Rthja and Rthjp, simulated
according to JESD−51.
The Rthja for 2S2P is simulated conform JEDEC
JESD−51 as follows:
• A 4−layer printed circuit board with inner power planes
and outer (top and bottom) signal layers is used
• Board thickness is 1.46 mm (FR4 PCB material)
• The 2 signal layers: 70 mm thick copper with an area of
5500 mm2 copper and 20% conductivity
• The 2 power internal planes: 36 mm thick copper with
an area of 5500 mm2 copper and 90% conductivity
The Rthja for 1S0P is simulated conform to JEDEC
JESD−51 as follows:
• A 1−layer printed circuit board with only 1 layer
• Board thickness is 1.46 mm (FR4 PCB material)
• The layer has a thickness of 70 mm copper with an area
of 5500 mm2 copper and 20% conductivity
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
NQFP−32
Figure 4. Example of NQFP−32 PCB Ground Plane Layout in Top View (Preferred Layout at Top and Bottom)
ELECTRICAL SPECIFICATION
Recommend Operation Conditions
Operating ranges define the limits for functional
operation and parametric characteristics of the device. Note
that the functionality of the chip outside these operating
ranges is not guaranteed. Operating outside the
recommended operating ranges for extended periods of time
may affect device reliability.
Table 3. OPERATING RANGES
Symbol
VBB
TJ
Parameter
Min
Max
Unit
Analog DC Supply
+6
+30
V
Junction Temperature (Note 5)
−40
+172
°C
5. No more than 100 cumulative hours in life time above Ttw.
http://onsemi.com
5
AMIS−30543
Table 4. DC PARAMETERS (The DC parameters are given for VBB and temperature in their operating ranges unless otherwise
specified) Convention: currents flowing in the circuit are defined as positive.
Symbol
Pin(s)
Parameter
Remark/Test Conditions
Min
Typ
Max
Unit
30
V
12
mA
5.5
V
5.5
V
8
mA
200
mA
SUPPLY AND VOLTAGE REGULATORS
VBB
Nominal operating supply range
VBB
IBB
VDD
VDD_SLP
IINT
ILOAD
VDD
IDDLIM
ILOAD_SLP
6
Total internal current consumption
(Note 6)
Unloaded outputs
Regulated Output Voltage
ILOAD within limits
Regulated Output Voltage in Sleep
Mode
−1 mA ≤ ILOAD ≤ 0 mA
VBB > 9 V
Internal load current (Note 6)
Unloaded outputs
Max Output Current
6 V v VBB < 8 V
15
8 V v VBB v 30 V
40
Current limitation
Pin shorted to ground
Current Consumption when in
Sleep Mode
VBB > 9 V
4.5
5
4
230
mA
POWER−ON−RESET (POR)
VDDH
Internal POR comparator threshold VDD rising
VDDL
VDD
VDDHYS
3.9
4.2
4.4
V
Internal POR comparator threshold VDD falling
3.86
V
Internal POR comparator
hysteresis
0.35
V
3000
mA
MOTORDRIVER
IMDmax,Peak
MOTXP
MOTXN
MOTYP
MOTYN
RHS
Max current through motor coil in
normal operation
On−resistance high−side driver,
CUR[4:0] = 0...31 (Note 7)
RLS3
On−resistance low−side driver,
CUR[4:0] = 16...25 (Note 7)
RLS2
On−resistance low−side driver,
CUR[4:0] = 10...15 (Note 7)
RLS1
On−resistance low−side driver,
CUR[4:0] = 3...9 (Note 7)
RLS0
On−resistance low−side driver,
CUR[4:0] = 0...2 (Note 7)
TJ = 130°C
0.15
TJ = 160°C
0.1
TJ = 160°C
0.2
TJ = 160°C
0.4
TJ = 160°C
0.8
TJ = 160°C
0.4
W
0.45
W
0.4
W
0.45
W
0.7
W
0.8
W
1.1
W
1.25
W
2.2
W
2.50
W
1
mA
0.65
V
DIGITAL INPUTS
Ileak
VIL
VIH
DI, CLK
NXT, DIR
CLR, CS
Input Leakage (Note 8)
TJ = 160°C
Logic Low Threshold
0
Logic High Threshold
2.35
Rpd_CLR
CLR
Internal Pulldown Resistor
120
Rpd_TST
TST0
Internal Pulldown Resistor
3
200
VDD
V
300
kW
9
kW
6. Current with oscillator running, all analogue cells active, SPI communication and NXT pulses applied. No floating inputs. Parameter
guaranteed by design.
7. Characterization Data Only
8. Not valid for pins with internal Pulldown resistor
http://onsemi.com
6
AMIS−30543
Table 4. DC PARAMETERS (The DC parameters are given for VBB and temperature in their operating ranges unless otherwise
specified) Convention: currents flowing in the circuit are defined as positive.
Symbol
Pin(s)
Parameter
Remark/Test Conditions
Min
Typ
Max
Unit
0.5
V
170
°C
DIGITAL OUTPUTS
VOL
DO, ERR,
POR/WD
Logic Low level open drain
IOL = 5 mA
THERMAL WARNING AND SHUTDOWN
Ttw
Thermal Warning
Ttsd
Thermal shutdown (Notes 9
and 10)
150
160
Ttw + 20
°C
2 * VBB – 2
V
CHARGE PUMP
Vcp
Output voltage
6 V< VBB < 15 V
VBB + 9
VBB + 12.5
VBB+16
V
External buffer capacitor
15 V < VBB < 30 V
180
220
470
nF
External pump capacitor
180
220
470
nF
VCP
Cbuffer
Cpump
CPP CPN
PACKAGE THERMAL RESISTANCE VALUE
Rthja
NQFP
Rthjp
NQFP
Thermal Resistance
Junction−to−Ambient
Simulated Conform JEDEC
JESD−51, 2S2P
30
K/W
Simulated Conform JEDEC
JESD−51, 1S0P
60
K/W
0.95
K/W
Thermal Resistance
Junction−to−Exposed Pad
SPEED AND LOAD ANGLE OUTPUT
Vout
Voff
Gsla
Rout
SLA
Output Voltage Range
0.2
VDD −
0.2
V
Output Offset SLA pin
−50
50
mV
1
kW
Gain of SLA Pin = VBEMF / VCOIL
SLAG = 0
0.5
SLAG = 1
0.25
Output Resistance SLA pin
9. No more than 100 cumulated hours in life time above Ttw.
10. Thermal shutdown is derived from thermal warning. Characterization Data Only.
http://onsemi.com
7
AMIS−30543
Table 5. AC PARAMETERS (The AC parameters are given for VBB and temperature in their operating ranges)
Symbol
Pin(s)
Parameter
Remark/Test Conditions
Min
Typ
Max
Unit
3.6
4
4.4
MHz
20.5
22.8
25.1
kHz
41.0
45.6
50.2
kHz
INTERNAL OSCILLATOR
Frequency of internal oscillator
fosc
MOTOR DRIVER
fPWM
MOTxx
PWM frequency
Frequency depends only on
internal oscillator
Double PWM frequency
tbrise
MOTxx
Turn−on voltage slope, 10% to
90%
tbfall
MOTxx
Turn−off voltage slope, 90% to
10%
EMC[1:0] = 00
200
V/ms
EMC[1:0] = 01
140
V/ms
EMC[1:0] = 10
70
V/ms
EMC[1:0] = 11
35
V/ms
EMC[1:0] = 00
200
V/ms
EMC[1:0] = 01
140
V/ms
EMC[1:0] = 10
70
V/ms
EMC[1:0] = 11
35
V/ms
DIGITAL OUTPUTS
tH2L
DO
ERR
Output fall−time from VinH to VinL
Capacitive load 400 pF and
pullup resistor of 1.5 kW
50
ns
CHARGE PUMP
fCP
CPN CPP
tCPU
MOTxx
Charge pump frequency
250
Startup time of charge pump
(Note 11)
Spec external components
kHz
5
ms
CLR FUNCTION
CLR
tCLR
Hard reset duration time
100
ms
POWER−UP
tPU
tPOR
POR/WD
tRF
Powerup time
VBB = 12 V, ILOAD = 50 mA,
CLOAD = 220 nF
100
ms
Reset duration
See Figure 16
100
ms
Reset filter time
See Figure 16
0.5
ms
WATCHDOG
Watchdog time out interval
tWDTO
tWDPR
POR/WD
32
Prohibited watchdog
acknowledge delay
512
2
ms
ms
NXT FUNCTION
tNXT_HI
NXT Minimum, High Pulse Width
See Figure 5
2
ms
tNXT_HI
NXT Minimum, Low Pulse Width
See Figure 5
2
ms
NXT Hold Time, Following
Change of DIR
See Figure 5
0.5
ms
NXT Hold Time, Before Change
of DIR
See Figure 5
0.5
ms
tDIR_SET
NXT
tDIR_HOLD
11. Guaranteed by design
http://onsemi.com
8
AMIS−30543
tNXT_LO
tNXT_HI
0.5 VCC
NXT
tDIR_SET
ÌÌÌ
ÌÌÌ
ÌÌÌ
DIR
tDIR_HOLD
ÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌ
VALID
Figure 5. NXT−Input Timing Diagram
Table 6. SPI TIMING PARAMETERS
Symbol
tCLK
Parameter
Min
Max
Unit
1
ms
tCLK_HIGH
SPI Clock High Time
100
ns
tCLK_LOW
SPI Clock Low Time
100
ns
DI Set Up Time, Valid Data Before Rising Edge of CLK
50
ns
DI Hold Time, Hold Data After Rising Edge of CLK
50
ns
tCSB_HIGH
CS High Time
2.5
ms
tSET_CSB
CS Set Up Time, CS Low Before Rising Edge of CLK
100
ns
tSET_CLK
CLK Set Up Time, CLK Low Before Rising Edge of CS
100
ns
tSET_DI
tHOLD_DI
SPI Clock Period
Typ
0. 2 VCC
CS
0 .2 VCC
tSET _CSB
tCLK
tSET_CLK
0 .8 VCC
CLK
0 ,2 VCC
0.2 VCC
tCLK_HI
ÌÌÌ
ÌÌÌ
ÌÌÌ
DI
tSET_DI
tCLK _LO
tHOLD_DI
0.8 VCC
VALID
ÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌ
Figure 6. SPI Timing
http://onsemi.com
9
AMIS−30543
TYPICAL APPLICATION SCHEMATIC
100 nF
100 nF
C2
C4
C5
R2
100 nF
R3
D1
100 nF
C6
R4
VDD
VBB
32
14
DIR
VBB
4
DO
31
3
CS
10
25, 26
2
CLK
21, 22
13
CLR
15, 16
12
ERR
6
SLA
C8
9
AMIS−30543
NXT
DI
mC
28
5
100mF
220 nF
27
11
POR/WD
V BAT
C1
C3
19, 20
VCP
CPN
C7
220 nF
CPP
MOTXP
MOTXN
MOTYP
M
MOTYN
7
R1
1
17
18 23 24 29
TSTO
GND
Figure 7. Typical Application Schematic AMIS−30543
Table 7. EXTERNAL COMPONENTS LIST AND DESCRIPTION
Component
Typ Value
Tolerance
Unit
VBB Buffer Capacitor (Note 12)
100
−20 +80%
mF
VBB Decoupling Block Capacitor
(Note 13)
100
−20 +80%
nF
C4
VDD Buffer Capacitor
100
$20%
nF
C5
VDD Buffer Capacitor
100
$20%
nF
C6
Charge Pump Buffer Capacitor
220
$20%
nF
C7
Charge Pump Pumping Capacitor
220
$20%
nF
C8
Low Pass Filter SLA
1
$20%
nF
R1
Low Pass Filter SLA
5.6
$1%
kW
R2, R3, R4
Pullup Resistor Open Drain Output
4.7
$1%
kW
D1
Optional Reverse Protection Diode
MURD530
C1
C2, C3
Function
12. ESR < 1 W.
13. ESR < 50 mW.
http://onsemi.com
10
AMIS−30543
FUNCTIONAL DESCRIPTION
H−Bridge Drivers
A full H−bridge is integrated for each of the two stator
windings. Each H−bridge consists of two low−side and two
high−side N−type MOSFET switches. Writing logic ‘0’ in
bit <MOTEN> disables all drivers (high−impedance).
Writing logic ‘1’ in this bit enables both bridges and current
can flow in the motor stator windings.
In order to avoid large currents through the H−bridge
switches, it is guaranteed that the top− and bottom−switches
of the same half−bridge are never conductive
simultaneously (interlock delay).
A two−stage protection against shorts on motor lines is
implemented. In a first stage, the current in the driver is
limited. Secondly, when excessive voltage is sensed across
the transistor, the transistor is switched off.
In order to reduce the radiated/conducted emission,
voltage slope control is implemented in the output switches.
The output slope is defined by the gate−drain capacitance of
output transistor and the (limited) current that drives the
gate. There are two trimming bits for slope control (see
Table 12 SPI Control Parameter Overview EMC[1:0]).
The power transistors are equipped with so−called “active
diodes”: when a current is forced trough the transistor switch
in the reverse direction, i.e. from source to drain, then the
transistor is switched on. This ensures that most of the
current flows through the channel of the transistor instead of
through the inherent parasitic drain−bulk diode of the
transistor.
Depending on the desired current range and the
micro−step position at hand, the RDS(on) of the low−side
transistors will be adapted such that excellent current−sense
accuracy is maintained. The RDS(on) of the high−side
transistors remain unchanged; see Table 4 DC Parameters
for more details.
PWM Current Control
A PWM comparator compares continuously the actual
winding current with the requested current and feeds back
the information to a digital regulation loop. This loop then
generates a PWM signal, which turns on/off the H−bridge
switches. The switching points of the PWM duty−cycle are
synchronized to the on−chip PWM clock. The frequency of
the PWM controller can be doubled and an artificial jitter
can be added (see Table 12 SPI Control Parameter Overview
PWMJ). The PWM frequency will not vary with changes in
the supply voltage. Also variations in motor−speed or
load−conditions of the motor have no effect. There are no
external components required to adjust the PWM frequency.
Automatic Forward and Slow−Fast Decay
The PWM generation is in steady−state using a
combination of forward and slow−decay. The absence of
fast−decay in this mode, guarantees the lowest possible
current−ripple “by design”. For transients to lower current
levels, fast−decay is automatically activated to allow
high−speed response. The selection of fast or slow decay is
completely transparent for the user and no additional
parameters are required for operation.
Icoil
Set value
Actual value
t
0
TPWM
Forward & Slow Decay
Forward & Slow Decay
Fast Decay & Forward
Figure 8. Forward and Slow/Fast Decay PWM
http://onsemi.com
11
AMIS−30543
Automatic Duty Cycle Adaptation
In case the supply voltage is lower than 2*Bemf, then the
duty cycle of the PWM is adapted automatically to > 50% to
maintain the requested average current in the coils. This
process is completely automatic and requires no additional
parameters for operation. The over−all current−ripple is
divided by two if PWM frequency is doubled (see Table 12
SPI Control Parameter Overview PWMF)
Icoil
Duty Cycle
< 50%
Duty Cycle < 50%
Duty Cycle > 50%
Actual value
Set value
t
Figure 9. Automatic Duty Cycle Adaption
TPWM
Step Translator and Step Mode
The step translator provides the control of the motor by
means of SM[2:0], ESM[2:0], SPI register DIRCTRL and
input pins DIR and NXT. It is translating consecutive steps
in corresponding currents in both motor coils for a given step
mode.
One out of eleven possible stepping modes can be selected
through SPI−bits SM[2:0] and ESM[2:0] (see Table 12 SPI
Control Parameter Overview). After power−on or hard
reset, the coil−current translator is set to the default 1/32
micro−stepping at position ‘0’. When remaining in the same
step mode, subsequent translator positions are all in the same
column and increased or decreased with 1. Table 9 lists the
output current vs. the translator position.
As shown in Figure 10 the output current−pairs can be
projected approximately on a circle in the (Ix, Iy) plane.
There are, however, two exceptions: uncompensated half
step and uncompensated full step. In these step modes the
currents are not regulated to a fraction of Imax but are in all
intermediate steps regulated at 100%. In the (Ix, Iy) plane the
current−pairs are projected on a square. Table 8 lists the
output current vs. the translator position for these cases.
Table 8. SQUARE TRANSLATOR TABLE FOR UNCOMPENSATED FULL STEP AND UNCOMPENSATED HALF
STEP
Stepmode ( SM[2:0] )
% of Imax
101
110
MSP[8:0]
Uncompensated Half Step
Uncompensated Full Step
Coil x
Coil y
0 0000 0000
0
−
0
100
0 0100 0000
1
1
100
100
0 1000 0000
2
−
100
0
0 1100 0000
3
2
100
−100
1 0000 0000
4
−
0
−100
1 0100 0000
5
3
−100
−100
1 1000 0000
6
−
−100
0
1 1100 0000
7
0
−100
100
http://onsemi.com
12
AMIS−30543
Table 9. CIRCULAR TRANSLATOR TABLE
SM[2:0]
xxx
xxx
000
001
010
011
100
xxx
xxx
000
000
011
100
Comp
full
2ph
Comp
full
1ph
Coil X
Coil Y
0
0
100
1
100
2
100
4
100
5
100
6
100
7
100
9
100
10
100
11
99
12
99
13
99
15
99
16
99
17
99
18
98
20
98
21
98
22
98
23
97
24
97
25
97
27
96
28
96
29
96
30
95
31
95
33
95
34
94
35
94
36
93
37
93
38
92
39
92
41
91
42
91
43
90
44
90
45
89
46
89
47
88
48
88
49
87
ESM[2:0]
001
010
000
000
000
MSP[8:0]
1/128
1/64
1/32
1/16
1/8
1/4
Comp
1/2
000000000
0
0
0
0
0
0
0
000000001
1
000000010
2
000000011
3
000000100
4
000000101
5
000000110
6
000000111
7
000001000
8
000001001
9
000001010
10
000001011
11
000001100
12
000001101
13
000001110
14
000001111
15
000010000
16
000010001
17
000010010
18
000010011
19
000010100
20
000010101
21
000010110
22
000010111
23
000011000
24
000011001
25
000011010
26
000011011
27
000011100
28
000011101
29
000011110
30
000011111
31
000100000
32
000100001
33
000100010
34
000100011
35
000100100
36
000100101
37
000100110
38
000100111
39
000101000
40
000101001
41
000101010
42
1
2
1
3
4
2
1
5
6
3
7
8
4
2
1
9
10
5
11
12
6
3
13
14
7
15
16
8
4
2
1
17
18
9
19
20
10
5
21
http://onsemi.com
13
% of Imax
AMIS−30543
Table 9. CIRCULAR TRANSLATOR TABLE (continued)
SM[2:0]
xxx
xxx
000
001
010
011
100
xxx
xxx
000
000
011
100
1/4
Comp
1/2
Comp
full
2ph
Comp
full
1ph
ESM[2:0]
001
MSP[8:0]
1/128
000101011
43
000101100
44
000101101
45
000101110
46
000101111
47
000110000
48
000110001
49
000110010
50
000110011
51
000110100
52
000110101
53
000110110
54
000110111
55
000111000
56
000111001
57
000111010
58
000111011
59
000111100
60
000111101
61
000111110
62
000111111
63
001000000
64
001000001
65
001000010
66
001000011
67
001000100
68
001000101
69
001000110
70
001000111
71
001001000
72
001001001
73
001001010
74
001001011
75
001001100
76
001001101
77
001001110
78
001001111
79
001010000
80
001010001
81
001010010
82
001010011
83
001010100
84
001010101
85
010
1/64
22
000
1/32
000
1/16
000
1/8
11
23
24
12
6
3
25
26
13
27
28
14
7
29
30
15
31
32
16
8
4
2
33
34
17
35
36
18
9
37
38
19
39
40
20
10
5
41
42
21
http://onsemi.com
14
1
0
% of Imax
Coil X
Coil Y
50
86
51
86
52
85
53
84
55
84
56
83
57
82
58
82
59
81
60
80
61
80
62
79
62
78
63
77
64
77
65
76
66
75
67
74
68
73
69
72
70
72
71
71
72
70
72
69
73
68
74
67
75
66
76
65
77
64
77
63
78
62
79
62
80
61
80
60
81
59
82
58
82
57
83
56
84
55
84
53
85
52
86
51
86
50
AMIS−30543
Table 9. CIRCULAR TRANSLATOR TABLE (continued)
SM[2:0]
xxx
xxx
000
001
010
011
100
xxx
xxx
000
000
011
100
1/4
Comp
1/2
Comp
full
2ph
Comp
full
1ph
ESM[2:0]
001
010
MSP[8:0]
1/128
1/64
001010110
86
43
001010111
87
001011000
88
001011001
89
001011010
90
001011011
91
001011100
92
001011101
93
001011110
94
001011111
95
001100000
96
001100001
97
001100010
98
001100011
99
001100100
100
001100101
101
001100110
102
001100111
103
001101000
104
001101001
105
001101010
106
001101011
107
001101100
108
001101101
109
001101110
110
001101111
111
001110000
112
001110001
113
001110010
114
001110011
115
001110100
116
001110101
117
001110110
118
001110111
119
001111000
120
001111001
121
001111010
122
001111011
123
001111100
124
001111101
125
001111110
126
001111111
127
010000000
128
44
000
1/32
22
000
1/16
000
1/8
11
45
46
23
47
48
24
12
6
3
49
50
25
51
52
26
13
53
54
27
55
56
28
14
7
57
58
29
59
60
30
15
61
62
31
63
64
32
16
8
4
http://onsemi.com
15
2
1
% of Imax
Coil X
Coil Y
87
49
88
48
88
47
89
46
89
45
90
44
90
43
91
42
91
41
92
39
92
38
93
37
93
36
94
35
94
34
95
33
95
31
95
30
96
29
96
28
96
27
97
25
97
24
97
23
98
22
98
21
98
20
98
18
99
17
99
16
99
15
99
13
99
12
99
11
100
10
100
9
100
7
100
6
100
5
100
4
100
2
100
1
100
0
AMIS−30543
Table 9. CIRCULAR TRANSLATOR TABLE (continued)
SM[2:0]
xxx
xxx
000
001
010
011
100
xxx
xxx
000
000
011
100
1/4
Comp
1/2
Comp
full
2ph
Comp
full
1ph
ESM[2:0]
001
MSP[8:0]
1/128
010000001
129
010000010
130
010000011
131
010000100
132
010000101
133
010000110
134
010000111
135
010001000
136
010001001
137
010001010
138
010001011
139
010001100
140
010001101
141
010001110
142
010001111
143
010010000
144
010010001
145
010010010
146
010010011
147
010010100
148
010010101
149
010010110
150
010010111
151
010011000
152
010011001
153
010011010
154
010011011
155
010011100
156
010011101
157
010011110
158
010011111
159
010100000
160
010100001
161
010100010
162
010100011
163
010100100
164
010100101
165
010100110
166
010100111
167
010101000
168
010101001
169
010101010
170
010101011
171
010
1/64
000
1/32
000
1/16
000
1/8
65
66
33
67
68
34
17
69
70
35
71
72
36
18
9
73
74
37
75
76
38
19
77
78
39
79
80
40
20
10
5
81
82
41
83
84
42
21
85
http://onsemi.com
16
% of Imax
Coil X
Coil Y
100
−1
100
−2
100
−4
100
−5
100
−6
100
−7
100
−9
100
−10
99
−11
99
−12
99
−13
99
−15
99
−16
99
−17
98
−18
98
−20
98
−21
98
−22
97
−23
97
−24
97
−25
96
−27
96
−28
96
−29
95
−30
95
−31
95
−33
94
−34
94
−35
93
−36
93
−37
92
−38
92
−39
91
−41
91
−42
90
−43
90
−44
89
−45
89
−46
88
−47
88
−48
87
−49
86
−50
AMIS−30543
Table 9. CIRCULAR TRANSLATOR TABLE (continued)
SM[2:0]
xxx
xxx
000
001
010
011
100
xxx
xxx
000
000
011
100
1/4
Comp
1/2
Comp
full
2ph
Comp
full
1ph
ESM[2:0]
001
010
000
MSP[8:0]
1/128
1/64
1/32
010101100
172
86
43
010101101
173
010101110
174
010101111
175
010110000
176
010110001
177
010110010
178
010110011
179
010110100
180
010110101
181
010110110
182
010110111
183
010111000
184
010111001
185
010111010
186
010111011
187
010111100
188
010111101
189
010111110
190
010111111
191
011000000
192
011000001
193
011000010
194
011000011
195
011000100
196
011000101
197
011000110
198
011000111
199
011001000
200
011001001
201
011001010
202
011001011
203
011001100
204
011001101
205
011001110
206
011001111
207
011010000
208
011010001
209
011010010
210
011010011
211
011010100
212
011010101
213
011010110
214
000
1/16
000
1/8
87
88
44
22
11
89
90
45
91
92
46
23
93
94
47
95
96
48
24
12
6
97
98
49
99
100
50
25
101
102
51
103
104
52
26
13
105
106
53
107
http://onsemi.com
17
3
1
% of Imax
Coil X
Coil Y
86
−51
85
−52
84
−53
84
−55
83
−56
82
−57
82
−58
81
−59
80
−60
80
−61
79
−62
78
−62
77
−63
77
−64
76
−65
75
−66
74
−67
73
−68
72
−69
72
−70
71
−71
70
−72
69
−72
68
−73
67
−74
66
−75
65
−76
64
−77
63
−77
62
−78
62
−79
61
−80
60
−80
59
−81
58
−82
57
−82
56
−83
55
−84
53
−84
52
−85
51
−86
50
−86
49
−87
AMIS−30543
Table 9. CIRCULAR TRANSLATOR TABLE (continued)
SM[2:0]
xxx
xxx
000
001
010
011
100
xxx
xxx
000
000
011
100
1/4
Comp
1/2
Comp
full
2ph
Comp
full
1ph
ESM[2:0]
001
MSP[8:0]
1/128
011010111
215
011011000
216
011011001
217
011011010
218
011011011
219
011011100
220
011011101
221
011011110
222
011011111
223
011100000
224
011100001
225
011100010
226
011100011
227
011100100
228
011100101
229
011100110
230
011100111
231
011101000
232
011101001
233
011101010
234
011101011
235
011101100
236
011101101
237
011101110
238
011101111
239
011110000
240
011110001
241
011110010
242
011110011
243
011110100
244
011110101
245
011110110
246
011110111
247
011111000
248
011111001
249
011111010
250
011111011
251
011111100
252
011111101
253
011111110
254
011111111
255
100000000
256
100000001
257
010
1/64
108
000
1/32
54
000
1/16
000
1/8
27
109
110
55
111
112
56
28
14
7
113
114
57
115
116
58
29
117
118
59
119
120
60
30
15
121
122
61
123
124
62
31
125
126
63
127
128
64
32
16
8
http://onsemi.com
18
4
2
% of Imax
Coil X
Coil Y
48
−88
47
−88
46
−89
45
−89
44
−90
43
−90
42
−91
41
−91
39
−92
38
−92
37
−93
36
−93
35
−94
34
−94
33
−95
31
−95
30
−95
29
−96
28
−96
27
−96
25
−97
24
−97
23
−97
22
−98
21
−98
20
−98
18
−98
17
−99
16
−99
15
−99
13
−99
12
−99
11
−99
10
−100
9
−100
7
−100
6
−100
5
−100
4
−100
2
−100
1
−100
0
−100
−1
−100
AMIS−30543
Table 9. CIRCULAR TRANSLATOR TABLE (continued)
SM[2:0]
xxx
xxx
000
001
010
011
100
xxx
xxx
000
000
011
100
1/4
Comp
1/2
Comp
full
2ph
Comp
full
1ph
ESM[2:0]
001
010
MSP[8:0]
1/128
1/64
100000010
258
129
100000011
259
100000100
260
100000101
261
100000110
262
100000111
263
100001000
264
100001001
265
100001010
266
100001011
267
100001100
268
100001101
269
100001110
270
100001111
271
100010000
272
100010001
273
100010010
274
100010011
275
100010100
276
100010101
277
100010110
278
100010111
279
100011000
280
100011001
281
100011010
282
100011011
283
100011100
284
100011101
285
100011110
286
100011111
287
100100000
288
100100001
289
100100010
290
100100011
291
100100100
292
100100101
293
100100110
294
100100111
295
100101000
296
100101001
297
100101010
298
100101011
299
100101100
300
130
000
1/32
000
1/16
000
1/8
65
131
132
66
33
133
134
67
135
136
68
34
17
137
138
69
139
140
70
35
141
142
71
143
144
72
36
18
9
145
146
73
147
148
74
37
149
150
75
http://onsemi.com
19
% of Imax
Coil X
Coil Y
−2
−100
−4
−100
−5
−100
−6
−100
−7
−100
−9
−100
−10
−100
−11
−99
−12
−99
−13
−99
−15
−99
−16
−99
−17
−99
−18
−98
−20
−98
−21
−98
−22
−98
−23
−97
−24
−97
−25
−97
−27
−96
−28
−96
−29
−96
−30
−95
−31
−95
−33
−95
−34
−94
−35
−94
−36
−93
−37
−93
−38
−92
−39
−92
−41
−91
−42
−91
−43
−90
−44
−90
−45
−89
−46
−89
−47
−88
−48
−88
−49
−87
−50
−86
−51
−86
AMIS−30543
Table 9. CIRCULAR TRANSLATOR TABLE (continued)
SM[2:0]
xxx
xxx
000
001
010
011
100
xxx
xxx
000
000
011
100
1/4
Comp
1/2
Comp
full
2ph
Comp
full
1ph
ESM[2:0]
001
MSP[8:0]
1/128
100101101
301
100101110
302
100101111
303
100110000
304
100110001
305
100110010
306
100110011
307
100110100
308
100110101
309
100110110
310
100110111
311
100111000
312
100111001
313
100111010
314
100111011
315
100111100
316
100111101
317
100111110
318
100111111
319
101000000
320
101000001
321
101000010
322
101000011
323
101000100
324
101000101
325
101000110
326
101000111
327
101001000
328
101001001
329
101001010
330
101001011
331
101001100
332
101001101
333
101001110
334
101001111
335
101010000
336
101010001
337
101010010
338
101010011
339
101010100
340
101010101
341
101010110
342
101010111
343
010
1/64
000
1/32
000
1/16
000
1/8
151
152
76
38
19
153
154
77
155
156
78
39
157
158
79
159
160
80
40
20
10
161
162
81
163
164
82
41
165
166
83
167
168
84
42
21
169
170
85
171
http://onsemi.com
20
5
2
% of Imax
Coil X
Coil Y
−52
−85
−53
−84
−55
−84
−56
−83
−57
−82
−58
−82
−59
−81
−60
−80
−61
−80
−62
−79
−62
−78
−63
−77
−64
−77
−65
−76
−66
−75
−67
−74
−68
−73
−69
−72
−70
−72
−71
−71
−72
−70
−72
−69
−73
−68
−74
−67
−75
−66
−76
−65
−77
−64
−77
−63
−78
−62
−79
−62
−80
−61
−80
−60
−81
−59
−82
−58
−82
−57
−83
−56
−84
−55
−84
−53
−85
−52
−86
−51
−86
−50
−87
−49
−88
−48
AMIS−30543
Table 9. CIRCULAR TRANSLATOR TABLE (continued)
SM[2:0]
xxx
xxx
000
001
010
011
100
xxx
xxx
000
000
011
100
1/4
Comp
1/2
Comp
full
2ph
Comp
full
1ph
ESM[2:0]
001
010
000
000
MSP[8:0]
1/128
1/64
1/32
1/16
101011000
344
172
86
43
101011001
345
101011010
346
101011011
347
101011100
348
101011101
349
101011110
350
101011111
351
101100000
352
101100001
353
101100010
354
101100011
355
101100100
356
101100101
357
101100110
358
101100111
359
101101000
360
101101001
361
101101010
362
101101011
363
101101100
364
101101101
365
101101110
366
101101111
367
101110000
368
101110001
369
101110010
370
101110011
371
101110100
372
101110101
373
101110110
374
101110111
375
101111000
376
101111001
377
101111010
378
101111011
379
101111100
380
101111101
381
101111110
382
101111111
383
110000000
384
110000001
385
110000010
386
000
1/8
173
174
87
175
176
88
44
22
11
177
178
89
179
180
90
45
181
182
91
183
184
92
46
23
185
186
93
187
188
94
47
189
190
95
191
192
96
48
24
12
193
http://onsemi.com
21
6
3
% of Imax
Coil X
Coil Y
−88
−47
−89
−46
−89
−45
−90
−44
−90
−43
−91
−42
−91
−41
−92
−39
−92
−38
−93
−37
−93
−36
−94
−35
−94
−34
−95
−33
−95
−31
−95
−30
−96
−29
−96
−28
−96
−27
−97
−25
−97
−24
−97
−23
−98
−22
−98
−21
−98
−20
−98
−18
−99
−17
−99
−16
−99
−15
−99
−13
−99
−12
−99
−11
−100
−10
−100
−9
−100
−7
−100
−6
−100
−5
−100
−4
−100
−2
−100
−1
−100
0
−100
1
−100
2
AMIS−30543
Table 9. CIRCULAR TRANSLATOR TABLE (continued)
SM[2:0]
xxx
xxx
000
001
010
011
100
xxx
xxx
000
000
011
100
1/4
Comp
1/2
Comp
full
2ph
Comp
full
1ph
ESM[2:0]
001
MSP[8:0]
1/128
110000011
387
110000100
388
110000101
389
110000110
390
110000111
391
110001000
392
110001001
393
110001010
394
110001011
395
110001100
396
110001101
397
110001110
398
110001111
399
110010000
400
110010001
401
110010010
402
110010011
403
110010100
404
110010101
405
110010110
406
110010111
407
110011000
408
110011001
409
110011010
410
110011011
411
110011100
412
110011101
413
110011110
414
110011111
415
110100000
416
110100001
417
110100010
418
110100011
419
110100100
420
110100101
421
110100110
422
110100111
423
110101000
424
110101001
425
110101010
426
110101011
427
110101100
428
110101101
429
010
1/64
194
000
1/32
000
1/16
000
1/8
97
195
196
98
49
197
198
99
199
200
100
50
25
201
202
101
203
204
102
51
205
206
103
207
208
104
52
26
13
209
210
105
211
212
106
53
213
214
107
http://onsemi.com
22
% of Imax
Coil X
Coil Y
−100
4
−100
5
−100
6
−100
7
−100
9
−100
10
−99
11
−99
12
−99
13
−99
15
−99
16
−99
17
−98
18
−98
20
−98
21
−98
22
−97
23
−97
24
−97
25
−96
27
−96
28
−96
29
−95
30
−95
31
−95
33
−94
34
−94
35
−93
36
−93
37
−92
38
−92
39
−91
41
−91
42
−90
43
−90
44
−89
45
−89
46
−88
47
−88
48
−87
49
−86
50
−86
51
−85
52
AMIS−30543
Table 9. CIRCULAR TRANSLATOR TABLE (continued)
SM[2:0]
xxx
xxx
000
001
010
011
100
xxx
xxx
000
000
011
100
1/4
Comp
1/2
Comp
full
2ph
Comp
full
1ph
ESM[2:0]
001
010
MSP[8:0]
1/128
1/64
110101110
430
215
110101111
431
110110000
432
110110001
433
110110010
434
110110011
435
110110100
436
110110101
437
110110110
438
110110111
439
110111000
440
110111001
441
110111010
442
110111011
443
110111100
444
110111101
445
110111110
446
110111111
447
111000000
448
111000001
449
111000010
450
111000011
451
111000100
452
111000101
453
111000110
454
111000111
455
111001000
456
111001001
457
111001010
458
111001011
459
111001100
460
111001101
461
111001110
462
111001111
463
111010000
464
111010001
465
111010010
466
111010011
467
111010100
468
111010101
469
111010110
470
111010111
471
111011000
472
216
000
1/32
108
000
1/16
54
000
1/8
27
217
218
109
219
220
110
55
221
222
111
223
224
112
56
28
14
225
226
113
227
228
114
57
229
230
115
231
232
116
58
29
233
234
117
235
236
118
59
http://onsemi.com
23
7
3
% of Imax
Coil X
Coil Y
−84
53
−84
55
−83
56
−82
57
−82
58
−81
59
−80
60
−80
61
−79
62
−78
62
−77
63
−77
64
−76
65
−75
66
−74
67
−73
68
−72
69
−72
70
−71
71
−70
72
−69
72
−68
73
−67
74
−66
75
−65
76
−64
77
−63
77
−62
78
−62
79
−61
80
−60
80
−59
81
−58
82
−57
82
−56
83
−55
84
−53
84
−52
85
−51
86
−50
86
−49
87
−48
88
−47
88
AMIS−30543
Table 9. CIRCULAR TRANSLATOR TABLE (continued)
SM[2:0]
xxx
xxx
000
001
010
011
100
xxx
xxx
000
000
011
100
1/4
Comp
1/2
Comp
full
2ph
Comp
full
1ph
ESM[2:0]
001
MSP[8:0]
1/128
111011001
473
111011010
474
111011011
475
111011100
476
111011101
477
111011110
478
111011111
479
111100000
480
111100001
481
111100010
482
111100011
483
111100100
484
111100101
485
111100110
486
111100111
487
111101000
488
111101001
489
111101010
490
111101011
491
111101100
492
111101101
493
111101110
494
111101111
495
111110000
496
111110001
497
111110010
498
111110011
499
111110100
500
111110101
501
111110110
502
111110111
503
111111000
504
111111001
505
111111010
506
111111011
507
111111100
508
111111101
509
111111110
510
111111111
511
010
1/64
000
1/32
000
1/16
000
1/8
237
238
119
239
240
120
60
30
15
241
242
121
243
244
122
61
245
246
123
247
248
124
62
31
249
250
125
251
252
126
63
253
254
127
255
http://onsemi.com
24
% of Imax
Coil X
Coil Y
−46
89
−45
89
−44
90
−43
90
−42
91
−41
91
−39
92
−38
92
−37
93
−36
93
−35
94
−34
94
−33
95
−31
95
−30
95
−29
96
−28
96
−27
96
−25
97
−24
97
−23
97
−22
98
−21
98
−20
98
−18
98
−17
99
−16
99
−15
99
−13
99
−12
99
−11
99
−10
100
−9
100
−7
100
−6
100
−5
100
−4
100
−2
100
−1
100
AMIS−30543
IY
IY
IY
Start = 0
Start = 0
Start = 0
Step 1
Step 2
Step 1
Step 1
Step 3
Step 2
Step 2
IX
IX
IX
Step 3
Step 3
1/4th micro step
Uncompensated
half step
IY
Compensated
half step
IY
Step 3
IY
Start = 0
Start = 0
Step 3
Step 3
Step 1
IX
IX
Uncompensated
full step
IX
Step 2
Step 1
Step 2
Start = 0
Step 1
Step 2
Compensated full
step, 1 phase on
Compensated full
step, 2 phase on
Figure 10. Translator Table: Circular and Square
Direction
The direction of rotation is selected by means of following
combination of the DIR input pin and the SPI−controlled
direction bit <DIRCTRL>. (see Table 12 SPI Control
Parameter Overview)
Parameter Overview), the next step is initiated either on the
rising edge or the falling edge of the NXT input.
Translator Position
The translator position MSP[8:0] can be read in SPI Status
Register 3 and Status Register 4 (See Table 14 SR3 and
SR4). This is a 9−bit number equivalent to the 1/128th
micro−step (see Table 9 “Circular Translator Table”). The
translator position is updated immediately following a NXT
trigger.
NXT Input
Changes on the NXT input will move the motor current
one step up/down in the translator table (even when the
motor is disabled: <MOTEN> = 0). Depending on the
NXT−polarity bit <NXTP> (see Table 12 SPI Control
NXT
Update
Translator Position
Update
Translator Position
Figure 11. Translator Position Timing Diagram
Synchronization of Step Mode and NXT Input
When step mode is re−programmed to another resolution
(Figure 12), then this is put in effect immediately upon the
first arriving “NXT” input. If the micro−stepping resolution
is increased, the coil currents will be regulated to the nearest
micro−step, according to the fixed grid of the increased
resolution. If however the micro−stepping resolution is
decreased, then it is possible to introduce an offset (or phase
shift) in the micro−step translator table.
If the step resolution is decreased at a translator table
position that is shared both by the old and new resolution
setting, then the offset is zero and micro−stepping is
proceeds according to the translator table.
If the translator position is not shared both by the old and
new resolution setting, then the micro−stepping proceeds
with an offset relative to the translator table (See Figure 12
right hand side).
http://onsemi.com
25
AMIS−30543
Change from lower to higher resolution
Iy
Iy
DIR
endpos
NXT3
NXT2
Change from higher to lower resolution
Iy
DIR
NXT1
NXT4
NXT1
endpos
startpos
Ix
DIR
startpos
NXT2
Ix
Ix
1/4th step
Halfstep
Iy
DIR
Ix
NXT3
1/8th step
Halfstep
PC20070604.6
Figure 12. NXT−Step Mode Synchronization
Left: Change from lower to higher resolution. The left−hand side depicts the ending half−step position during which a new
step mode resolution was programmed. The right−hand side diagram shows the effect of subsequent NXT commands on the
micro−step position.
Right: Change from higher to lower resolution. The left−hand side depicts the ending micro−step position during which a new
step mode resolution was programmed. The right−hand side diagram shows the effect of subsequent NXT commands on the
half−step position.
Note: It is advised to reduce the micro−stepping resolution only at micro−step positions that overlap with desired micro−step
positions of the new resolution.
Programmable Peak−Current
The amplitude of the current waveform in the motor coils
(coil peak current = Imax) is adjusted by means of an SPI
parameter “CUR[4:0]” (see Table 12 SPI Control Parameter
Overview). Whenever this parameter is changed, the
coil−currents will be updated immediately at the next PWM
period. Figure 13 presents the Peak−Current and Current
Ratings in conjunction to the Current setting CUR[4:0].
Peak Current
3090 mA
Current Range 3
CUR[4:0] = 16 −> 25
1205 mA
Current Range 2
CUR[4:0] = 10 −> 15
680 mA
Current Range 1
CUR[4:0] = 3 −> 9
305 mA
Current Range 0
CUR[4:0] = 0 −> 2
0
2
9
15
Figure 13. Programmable Peak−Current Overview
http://onsemi.com
26
25
CUR[4:0]
AMIS−30543
Speed and Load Angle Output
The SLA−pin provides an output voltage that indicates the
level of the Back−e.m.f. voltage of the motor. This
Back−e.m.f. voltage is sampled during every so−called ”coil
current zero crossings”. Per coil, two zero−current positions
exist per electrical period, yielding in total four zero−current
observation points per electrical period.
V BEMF
I COIL
t
ZOOM
Previous
Micro−step
I COIL
Coil Current Zero Crossing
Next
Micro−step
Current Decay
Zero Current
t
V COIL
Voltage Transient
VBB
|V BEMF |
t
Figure 14. Principle of Bemf Measurement
behavior of the coil voltage is not visible anymore, this mode
generates smoother Back e.m.f. input for post−processing,
e.g. by software.
In order to bring the sampled Back e.m.f. to a descent
output level (0 V to 5 V), the sampled coil voltage VCOIL is
divided by 2 or by 4. This divider is set through an SPI bit
<SLAG>. (see Table 12 SPI Control Parameter Overview)
The following drawing illustrates the operation of the
SLA−pin and the transparency−bit. “PWMsh” and “ICOIL =
0” are internal signals that define together with SLAT the
sampling and hold moments of the coil voltage.
Because of the relatively high recirculation currents in the
coil during current decay, the coil voltage VCOIL shows a
transient behavior. As this transient is not always desired in
application software, two operating modes can be selected
by means of the bit <SLAT> (see “SLA−transparency” in
Table 12 SPI Control Parameter Overview). The SLA pin
shows in “transparent mode” full visibility of the voltage
transient behavior. This allows a sanity−check of the
speed−setting versus motor operation and characteristics
and supply voltage levels. If the bit “SLAT” is cleared, then
only the voltage samples at the end of each coil current zero
crossing are visible on the SLA−pin. Because the transient
http://onsemi.com
27
AMIS−30543
VCOIL
div2
div4
Ssh
Sh
buf
SLA−pin
Ch
Csh
Icoil=0
PWMsh
SLAT
NOT(Icoil=0)
PWMsh
Icoil=0
SLAT
VCOIL
t
SLA−pin
last sample
is retained
VBEMF
retain last sample
previous output is kept at SLA pin
SLAT = 1 => SLA−pin is “transparent” during
VBEMF sampling @ Coil Current Zero
Crossing. SLA−pin is updated “real−time”.
t
SLAT = 0 => SLA−pin is not “transparent” during
VBEMF sampling @ Coil Current Zero Crossing.
SLA−pin is updated when leaving current−less state.
Figure 15. Timing Diagram of SLA−Pin
Open Coil/Current Not Reached Detection
Open coil detection is based on the observation of 100%
duty cycle of the PWM regulator. If in a coil 100% duty cycle
is detected for longer than 200 ms then the related driver
transistors are disabled (high−impedance) and an
appropriate bit in the SPI status register is set (<OPENX> or
<OPENY>). (Table 14)
When the resistance of a motor coil is very large and the
supply voltage is low, it can happen that the motor driver is
not able to deliver the requested current to the motor. Under
these conditions the PWM controller duty cycle will be
100% and after 200 ms the error pin and <OPENX>,
<OPENY> will flag this situation (motor current is kept
alive). This feature can be used to test if the operating
conditions (supply voltage, motor coil resistance) still allow
reaching the requested coil−current or else the coil current
should be reduced.
Warning, Error Detection and Diagnostics
Feedback
Thermal Warning and Shutdown
When junction temperature rises above TTW, the thermal
warning bit <TW> is set (Table 14 SPI Status registers
Address SR0). If junction temperature increases above
thermal shutdown level, then the circuit goes in “Thermal
Shutdown” mode (<TSD>) and all driver transistors are
disabled (high impedance) (see Table 14 SPI Status registers
Address SR2). The conditions to reset flag <TSD> is to be
at a temperature lower than Ttw and to clear the <TSD> flag
by reading it using any SPI read command.
Overcurrent Detection
The overcurrent detection circuit monitors the load
current in each activated output stage. If the load current
exceeds the over−current detection threshold, then the
overcurrent flag is set and the drivers are switched off to
reduce the power dissipation and to protect the integrated
circuit. Each driver transistor has an individual detection bit
(see Table 14 SPI Status Registers Address SR1 and SR2:
<OVCXij> and <OVCYij>). Error condition is latched
and the microcontroller needs to clean the status bits to
reactivate the drivers.
Note: Successive reading the SPI Status Registers 1 and 2 in
case of a short circuit condition, may lead to damage to the
drivers.
Charge Pump Failure
The charge pump is an important circuit that guarantees
low RDS(on) for all drivers, especially for low supply
voltages. If supply voltage is too low or external components
are not properly connected to guarantee RDS(on) of the
drivers, then the bit <CPFAIL> is set (Table 14). Also after
POR the charge pump voltage will need some time to exceed
the required threshold. During that time <CPFAIL> will be
set to “1”.
http://onsemi.com
28
AMIS−30543
Error Output
This is a digital output to flag a problem to the external
microcontroller. The signal on this output is active low and
the logic combination of:
NOT(ERRB) = <TW> OR <TSD> OR <OVCXij> OR
<OVCYij> OR <OPENi> OR <CPFAIL>
circuitry, the specified Iload should be reduced with the
consumption of internal circuitry (unloaded outputs) and the
loads connected to logic outputs. See Table 4. DC
parameters
Power−On Reset (POR) Function
The open drain output pin POR/WD provides an “active
low” reset for external purposes. At powerup of
AMIS−30543, this pin will be kept low for some time to reset
for example an external microcontroller. A small analogue
filter avoids resetting due to spikes or noise on the VDD
supply.
Logic Supply Regulator
AMIS−30543 has an on−chip 5 V low−drop regulator
with external capacitor to supply the digital part of the chip,
some low−voltage analog blocks and external circuitry. The
voltage level is derived from an internal bandgap reference.
To calculate the available drive−current for external
VBB
t
VDD
tPD
tPU
VDDH
VDDL
t
< tRF
POR/WD pin
tPOR
tRF
Figure 16. Power−on−Reset Timing Diagram
Watchdog Function
The watchdog function is enabled/disabled through
<WDEN> bit (Table 11: SPI CONTROL REGISTERS).
Once this bit has been set to “1” (watchdog enable), the
microcontroller needs to re−write this bit to clear an internal
timer before the watchdog timeout interval expires. In case
the timer is activated and WDEN is acknowledged too early
(before tWDPR) or not within the interval (after tWDTO), then
a reset of the microcontroller will occur through POR/WD
pin. In addition, a warm/cold boot bit <WD> is available (see
Tables 14 and 15) for further processing when the external
microcontroller is alive again.
The voltage regulator and charge pump remains
functional during and after the reset and the POR/WD pin is
not activated. Watchdog function is reset completely.
Sleep Mode
The bit <SLP> in SPI Control Register 2 (See Table 10)
is provided to enter a so−called “sleep mode”. This mode
allows reduction of current−consumption when the motor is
not in operation. The effect of sleep mode is as follows:
• The drivers are put in HiZ
• All analog circuits are disabled and in low−power mode
• All internal registers are maintaining their logic content
• NXT and DIR inputs are forbidden
• SPI communication remains possible (slight current
increase during SPI communication)
• Oscillator and digital clocks are silent, except during
SPI communication
• Registers cannot be cleared by using the CLR pin
CLR pin (=Hard Reset)
Logic 0 on CLR pin allows normal operation of the chip.
To reset the complete digital inside AMIS−30543, the input
CLR needs to be pulled to logic 1 during minimum time
given by tCLR (Table 5 AC Parameters). This reset function
clears all internal registers without the need of a
power−cycle, except in sleep mode. Logic 0 on CLR pin
resumes normal operation again.
VBB should be minimum 9 V to be able to enter
Sleep Mode.
http://onsemi.com
29
AMIS−30543
Normal operation is resumed after writing logic ‘0’ to bit
<SLP>. A startup time is needed for the charge pump to
stabilize. After this time, NXT commands can be issued.
The voltage regulator remains active but with reduced
current−output capability (ILOADSLP). The watchdog timer
stops running and it’s value is kept in the counter. Upon
leaving sleep mode, this timer continues from the value it
had before entering sleep mode.
VBB
t
VDD
tPU
VDDH
t
tPOR
POR/WD pin
tWDRD tPOR
tDSPI
Enable WD
= tWDPR or = tWDTO
> tWDPR and < tWDTO
Acknowledge WD
t
tWDTO
WD timer
t
Figure 17. Watchdog Timing Diagram
NOTE:
tDSPI is the time needed by the external microcontroller to shift−in the <WDEN> bit after a powerup.
The duration of the watchdog timeout interval is programmable through the WDT[3:0] bits (See also Table 11: SPI
CONTROL REGISTERS. The timing is given in Table 10 below.
Table 10. WATCHDOG TIMEOUT INTERVAL AS FUNCTION OF WDT[3.0]
Index WDT[3:0]
tWDTO (ms)
Index WDT[3:0]
tWDTO (ms)
0
0000
32
8
1000
288
1
0001
64
9
1001
320
2
0010
96
10
1010
352
3
0011
128
11
1011
384
4
0100
160
12
1100
416
5
0101
192
13
1101
448
6
0110
224
14
1110
480
7
0111
256
15
1111
512
http://onsemi.com
30
AMIS−30543
SPI INTERFACE
DO signal is the output from the Slave (AMIS−30543), and
DI signal is the output from the Master. A chip select line
(CS) allows individual selection of a Slave SPI device in a
multiple−slave system. The CS line is active low. If
AMIS−30543 is not selected, DO is pulled up with the
external pull up resistor. Since AMIS−30543 operates as a
Slave in MODE 0 (CPOL = 0; CPHA = 0) it always clocks
data out on the falling edge and samples data in on rising
edge of clock. The Master SPI port must be configured in
MODE 0 too, to match this operation. The SPI clock idles
low between the transferred bytes.
The diagram below is both a Master and a Slave timing
diagram since CLK, DO and DI pins are directly connected
between the Master and the Slave.
The serial peripheral interface (SPI) allows an external
microcontroller (Master) to communicate with
AMIS−30543. The implemented SPI block is designed to
interface directly with numerous micro−controllers from
several manufacturers. AMIS−30543 acts always as a Slave
and can’t initiate any transmission. The operation of the
device is configured and controlled by means of SPI
registers which are observable for read and/or write from the
Master.
SPI Transfer Format and Pin Signals
During a SPI transfer, data is simultaneously transmitted
(shifted out serially) and received (shifted in serially). A
serial clock line (CLK) synchronizes shifting and sampling
of the information on the two serial data lines (DO and DI).
1
# CLK cycle
2
3
4
5
6
7
8
CS
CLK
DI
MSB
6
5
4
3
2
1
LSB
DO
MSB
6
5
4
3
2
1
LSB
Figure 18. Timing Diagram of a SPI Transfer
NOTE:
ÌÌÌÌ
ÌÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
At the falling edge of the eight clock pulse the data−out shift register is updated with the content of the addressed internal SPI
register. The internal SPI registers are updated at the first rising edge of the AMIS−30543 system clock when CS = High
Transfer Packet:
Serial data transfer is assumed to follow MSB first rule.
The transfer packet contains one or more bytes.
BYTE 1
BYTE 2
Command and SPI Register Address
Data
MSB
CMD2
LSB
CMD1
Command
MSB
CMD0 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0
D7
LSB
D6
D5
D4
D3
D2
D1
D0
SPI Register Address
Figure 19. SPI Transfer Packet
Byte 1 contains the Command and the SPI Register
Address and indicates to AMIS−30543 the chosen type of
operation and addressed register. Byte 2 contains data, or
sent from the Master in a WRITE operation, or received
from AMIS−30543 in a READ operation.
http://onsemi.com
31
AMIS−30543
READ command. This READ command contains the
address of the SPI register to be read out. At the falling edge
of the eight clock pulse the data−out shift register is updated
with the content of the corresponding internal SPI register.
In the next 8−bit clock pulse train this data is shifted out via
DO pin. At the same time the data shifted in from DI
(Master) should be interpreted as the following successive
command or dummy data.
Two command types can be distinguished in the
communication between master and AMIS−30543:
• READ from SPI Register with address ADDR[4:0]:
CMD2 = “0”
• WRITE to SPI Register with address ADDR[4:0]:
CMD2 = “1”
READ Operation
If the Master wants to read data from Status or Control
Registers, it initiates the communication by sending a
Registers are updated with internal status at the rising
edge of the internal AMIS−30543 clock when CS = 1
CS
COMMAND
DI
READ DATA from ADDR 1
COMMAND or DUMMY
DATA from previous command or
NOT VALID after POR or RESET
DO
DATA
DATA
OLD DATA or NOT VALID
DATA from ADDR1
Figure 20. Single READ Operation where DATA from SPI Register with Address 1 is Read by the Master
All 4 Status Registers (see SPI Registers) contain 7 data
bits and a parity check bit. The most significant bit (D7)
represents a parity of D[6:0]. If the number of logical ones
in D[6:0] is odd, the parity bit D7 equals “1”. If the number
of logical ones in D[6:0] is even then the parity bit D7 equals
“0”. This simple mechanism protects against noise and
increases the consistency of the transmitted data. If a parity
check error occurs it is recommended to initiate an
additional READ command to obtain the status again.
Also the Control Registers can be read out following the
same routine. Control Registers don’t have a parity check.
The CS line is active low and may remain low between
successive READ commands as illustrated in Figure 22.
There is however one exception. In case an error condition
is latched in one of Status Registers (see SPI Registers) the
ERR pin is activated (See Section Error Output). This signal
flags a problem to the external microcontroller. By reading
the Status Registers information about the root cause of the
problem can be determined. After this READ operation the
Status Registers are cleared. Because the Status Registers
and ERR pin (see SPI Registers) are only updated by the
internal system clock when the CS line is high, the Master
should force CS high immediately after the READ
operation. For the same reason it is recommended to keep
the CS line high always when the SPI bus is idle.
WRITE Operation
If the Master wants to write data to a Control Register it
initiates the communication by sending a WRITE
command. This contains the address of the SPI register to
write to. The command is followed with a data byte. This
incoming data will be stored in the corresponding Control
Register after CS goes from low to high! AMIS−30543
responds on every incoming byte by shifting out via DO the
data stored in the last received address.
It is important that the writing action (command − address
and data) to the Control Register is exactly 16 bits long. If
more or less bits are transmitted the complete transfer packet
is ignored.
A WRITE command executed for a read−only register
(e.g. Status Registers) will not affect the addressed register
and the device operation.
Because after a power−on−reset the initial address is
unknown the data shifted out via DO is not valid.
http://onsemi.com
32
AMIS−30543
The NEW DATA is written into the corresponding
internal register at the rising edge of CS
CS
COMMAND
DI
DATA
NEW DATA for ADDR3
WRITE DATA to ADDR3
DATA from previous command or
NOT VALID after POR or RESET
DATA
DO
DATA
OLD DATA or NOT VALID
OLD DATA from ADDR3
Figure 21. Single WRITE Operation Where DATA from the Master is Written in SPI Register with Address 3
Examples of combined READ and WRITE
Operations
In the following examples successive READ and WRITE
operations are combined. In Figure 22 the Master first reads
the status from Register at ADDR4 and at ADDR5 followed
CS
Registers are updated with the internal
status at the rising edge of the internal
AMIS−30543 clock when CS = 1
COMMAND
READ DATA
from ADDR4
DI
DATA from previous
command or NOT VALID
after POR or RESET
DO
by writing a control byte in Control Register at ADDR2.
Note that during the write command the old data of the
pointed register is returned at the moment the new data is
shifted in
DATA
OLD DATA
or NOT VALID
The NEW DATA is written into the
corresponding internal register at
the rising edge of CS
COMMAND
COMMAND
DATA
READ DATA
from ADDR5
WRITE DATA
to ADDR 2
NEW DATA
for ADDR2
DATA
DATA
DATA
DATA
from ADDR4
DATA
from ADDR5
OLD DATA
from ADDR2
Figure 22. 2 Successive READ Commands Followed by a WRITE Command
transmitted. This rule also applies when the master device
wants to initiate an SPI transfer to read the Status Registers.
Because the internal system clock updates the Status
Registers only when CS line is high, the first read out byte
might represent old status information.
After the write operation the Master could initiate a read
back command in order to verify the data correctly written
as illustrated in Figure 23. During reception of the READ
command the old data is returned for a second time. Only
after receiving the READ command the new data is
http://onsemi.com
33
AMIS−30543
The NEW DATA is written into the
corresponding internal register at
the rising edge of CS
Registers are updated with
the internal status at the
rising edge of CS
CS
DI
COMMAND
DATA
COMMAND
WRITE DATA
to ADDR2
NEW DATA
for ADDR2
READ DATA
from ADDR2
DATA from previous
command or NOT VALID
after POR or RESET
DATA
DO
DATA
DATA
OLD DATA
from ADDR2
NEW DATA
from ADDR2
DATA
OLD DATA
or NOT VALID
OLD DATA
from ADDR2
COMMAND
or DUMMY
Figure 23. A WRITE Operation Where DATA from the Master is Written in SPI Register with Address 2 Followed by
a READ Back Operation to Confirm a Correct WRITE Operation
NOTE:
The internal data−out shift buffer of AMIS−30543 is updated with the content of the selected SPI register only at the last (every
eight) falling edge of the CLK signal (see SPI Transfer Format and Pin Signals). As a result, new data for transmission cannot be
written to the shift buffer at the beginning of the transfer packet and the first byte shifted out might represent old data.
Table 11. SPI CONTROL REGISTERS (All SPI control registers have Read/Write Access and default to “0” after power−on or hard
reset)
Structure
Content
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
Reset
0
0
0
0
0
0
0
0
WR (00h)
Data
WDEN
−
−
−
CR0 (01h)
Data
CR1 (02h)
Data
DIRCTRL
NXTP
−
−
PWMF
PWMJ
CR2 (03h)
Data
MOTEN
SLP
SLAG
SLAT
−
−
CR3 (09h)
Data
−
−
−
−
−
Where:
R/W
Reset:
WDT[3:0]
SM[2:0]
CUR[4:0]
Read and Write access
Status after power−On or hard reset
http://onsemi.com
34
EMC[1:0]
−
ESM[2:0]
−
AMIS−30543
Table 12. SPI CONTROL PARAMETER OVERVIEW
Symbol
Description
DIRCTRL
Controls the direction of rotation (in combination with
logic level on input DIR)
Status
<DIR> = 0
<DIR> = 1
NXTP
EMC[1:0]
Selects if NXT triggers on rising or falling edge
Turn On – Turn−off Slopes of motor driver (Note 14)
Value
<DIRCTRL> = 0
CW motion (Note 15)
<DIRCTRL> = 1
CCW motion
(Note 15)
<DIRCTRL> = 0
CCW motion
(Note 15)
<DIRCTRL> = 1
CW motion (Note 15)
<NXTP> = 0
Trigger on rising edge
<NXTP> = 1
Trigger on falling edge
00
Very Fast
01
Fast
10
Slow
11
Very Slow
SLAT
Speed load angle transparency bit
<SLAT> = 0
SLA is not transparent
<SLAT> = 1
SLA is transparent
SLAG
Speed load angle gain setting
<SLAG> = 0
Gain = 0.5
<SLAG> = 1
Gain = 0.25
PWMF
Enables doubling of the PWM frequency (Note 14)
<PWMF> = 0
Default Frequency
<PWMF> = 1
Double Frequency
<PWMJ> = 0
Jitter disabled
PWMJ
SM[2:0]
ESM[2:0]
SLP
MOTEN
Enables jittery PWM
Stepmode (only valid if ESM[2:0] = 000)
Stepmode
Enables sleep mode (if VBB > 9 V)
Activates the motor driver outputs
<PWMJ> = 1
Jitter enabled
000
1/32 Micro − Step
001
1/16 Micro − Step
010
1/8 Micro − Step
011
1/4 Micro − Step
100
Compensated Half Step
101
Uncompensated Half Step
110
Uncompensated full step
111
Uncompensated full step
001
1/128 Micro−Step
010
1/64 Micro−Step
011
Compensated full step, 2 phase on
100
Compensated full step, 1 phase on
Other
Stepping mode defined by SM[2:0]
<SLP> = 0
Active mode
<SLP> = 1
Sleep mode
<MOTEN> = 0
Drivers disabled
<MOTEN> = 1
Drivers enabled
14. The typical values can be found in Table 4: DC Parameters and in Table 5: AC parameters
15. Depending on the wiring of the motor connections
http://onsemi.com
35
AMIS−30543
CUR[4:0]
Selects IMCmax peak. This is the peak or amplitude of the regulated current waveform in the motor coils.
Table 13. SPI CONTROL PARAMETER OVERVIEW CUR[4:0]
Current Range
(Note 17)
0
1
2
Current (mA)
(Note 16)
Index CUR[4:0]
Current Range
(Note 17)
Index CUR[4:0]
Current (mA)
(Note 16)
0
00000
132
16
10000
1405
1
00001
245
17
10001
1520
2
00010
355
18
10010
1695
3
00011
395
19
10011
1850
4
00100
445
20
10100
2070
5
00101
485
21
10101
2240
6
00110
540
22
10110
2440
7
00111
585
23
10111
2700
8
01000
640
24
11000
2845
3
9
01001
715
25
11001
3000
10
01010
780
26
11010
3000
11
01011
870
27
11011
3000
12
01100
955
28
11100
3000
13
01101
1060
29
11101
3000
14
01110
1150
30
11110
3000
15
01111
1260
31
11111
3000
16. Typical current amplitude at TJ = 125
17. Reducing the current over different current ranges might trigger overcurrent detection. See dedicated application note for solutions
SPI Status Register Description
All 4 SPI status registers have Read Access and are default to “0” after power−on or hard reset.
Table 14. SPI STATUS REGISTERS
Structure
Content
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Access
R
R
R
R
R
R
R
R
Address
Reset
0
0
0
0
0
0
0
0
SR0 (04h)
Data is not latched
PAR
TW
CPFAIL
WD
SR1 (05h)
Data is latched
PAR
OVCXPT
OVCXPB
OVCXNT
OVCXNB
−
−
−
SR2 (06h)
Data is latched
PAR
OVCYPT
OVCYPB
OVCYNT
OVCYNB
TSD
−
−
SR3 (07h)
Data is not latched
PAR
MSP[8:2]
SR4 (0Ah)
Data is not latched
PAR
MSP[6:0]
Where:
R
Reset
PAR
Read only mode access
Status after power−on or hard reset
Parity check
http://onsemi.com
36
OPENCOIL_X
OPENCOIL_Y
AMIS−30543
Table 15. SPI STATUS FLAGS OVERVIEW
Mnemonic
Flag
Length
(bit)
Related
SPI Register
CPFail
Charge pump failure
1
Status Register 0
MSP[8:0]
Micro−step position
9
OPENX
OPEN Coil X
1
Status Register 0
‘1’ = Open coil detected
‘0’
OPENY
OPEN Coil Y
1
Status Register 0
‘1’ = Open coil detected
‘0’
OVCXNB
OVer Current on X
H−bridge; MOTXN
terminal; Bottom
tran.
1
Status Register 1
‘0’ = no failure
‘1’ = failure: indicates that over current is detected
at bottom transistor XN−terminal
‘0’
OVCXNT
OVer Current on X
H−bridge; MOTXN
terminal; Top transist.
1
Status Register 1
‘0’ = no failure
‘1’ = failure: indicates that over current is detected
at top transistor XN−terminal
‘0’
OVCXPB
OVer Current on X
H−bridge; MOTXP
terminal; Bottom
tran.
1
Status Register 1
‘0’ = no failure
‘1’ = failure: indicates that over current is detected
at bottom transistor XP−terminal
‘0’
OVCXPT
OVer Current on X
H−bridge; MOTXP
terminal; Top transist.
1
Status Register 1
‘0’ = no failure
‘1’ = failure: indicates that over current is detected
at top transistor XP−terminal
‘0’
OVCYNB
OVer Current on Y
H−bridge; MOTYN
terminal; Bottom
tran.
1
Status Register 2
‘0’ = no failure
‘1’ = failure: indicates that over current is detected
at bottom transistor YN−terminal
‘0’
OVCYNT
OVer Current on Y
H−bridge; MOTYN
terminal; Top transist.
1
Status Register 2
‘0’ = no failure
‘1’ = failure: indicates that over current is detected
at top transistor YN−terminal
‘0’
OVCYPB
OVer Current on Y
H−bridge; MOTYP
terminal; Bottom
tran.
1
Status Register 2
‘0’ = no failure
‘1’ = failure: indicates that over current is detected
at bottom transistor YP−terminal
‘0’
OVCYPT
OVer Current on Y
H−bridge; MOTYP
terminal; Top transist.
1
Status Register 2
‘0’ = no failure
‘1’ = failure: indicates that over current is detected
at top transistor YP−terminal
‘0’
TSD
Thermal shutdown
1
Status Register 2
‘0’
TW
Thermal warning
1
Status Register 0
‘0’
Watchdog event
1
Status Register 0
WD
NOTE:
Reset
State
Comment
‘0’ = no failure
‘1’ = failure: indicates that the charge pump does
not reach the required voltage level. Note 1
‘0’
Status Register 3 and Translator micro step position
Status Register 4
‘1’ = watchdog reset after time−out
‘000000000’
‘0’
WD − This bit indicates that the watchdog timer has not been cleared properly. If the master reads that WD is set to “1” after reset,
it means that a watchdog reset occurred (warm boot) instead of POR (cold boot). WD bit will be cleared only when the master
writes “0” to WDEN bit.
Table 16. ORDERING INFORMATION
Peak Current
Temperature
Range
AMIS30543C5431G
3000 mA
AMIS30543C5431RG
3000 mA
Part No.
Package
Shipping†
−40°C to 125°C
NQFP−32 (7 x 7 mm)
(Pb−Free)
Units / Tubes
−40°C to 125°C
NQFP−32 (7 x 7 mm)
(Pb−Free)
Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
37
AMIS−30543
PACKAGE DIMENSIONS
QFN32
CASE 485J−02
ISSUE C
A B
D
PIN 1
LOCATION
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
E
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
2X
0.15 C
2X
0.15 C
TOP VIEW
(A3)
0.10 C
MILLIMETERS
MIN
NOM MAX
0.800 0.900 1.000
0.000 0.025 0.050
0.200 REF
0.250 0.250 0.350
7.00 BSC
5.160 5.260 5.360
7.00 BSC
5.160 5.260 5.360
0.650 BSC
0.200
−−−
−−−
0.300 0.400 0.500
A
0.08 C
SEATING
PLANE
A1
SIDE VIEW
C
D2
L
9
32X
EXPOSED PAD
e
K
16
4X
17
8
8
e
1
b
E2
24
32
25
32X NOTE 3
0.10
C A B
0.05
C
BOTTOM VIEW
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
http://onsemi.com
38
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
AMIS−30543/D