AMIS 30532 D

AMIS-30532
Micro-Stepping Motor
Driver
Introduction
The AMIS−30532 is a micro−stepping stepper motor driver for
bipolar stepper motors. The chip is connected through I/O pins and an
SPI interface with an external microcontroller. It has an on−chip
voltage regulator, reset−output and watchdog reset, able to supply
peripheral devices. The AMIS−30532 contains a current−translation
table and takes the next micro−step depending on the clock signal on
the “NXT” input pin and the status of the “DIR” (=direction) register
or input pin. The chip provides a so−called “speed and load angle”
output. This allows the creation of stall detection algorithms and
control loops based on load−angle to adjust torque and speed. It is
using a proprietary PWM algorithm for reliable current control.
The AMIS−30532 is implemented in I2T100 technology, enabling
both high−voltage analog circuitry and digital functionality on the
same chip. The chip is fully compatible with the automotive voltage
requirements.
The AMIS−30532 is ideally suited for general−purpose stepper
motor applications in the automotive, industrial, medical, and marine
environment. With the on−chip voltage regulator it further reduces the
BOM for mechatronic stepper applications.
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NQFP−32, 7x7
CASE 560AA
MARKING DIAGRAM
Key Features
• Dual H−Bridge for 2−Phase Stepper Motors
• Programmable Peak−Current up to 1.6 A Continuous† (3.0 A Short
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Time) using a 5−bit Current DAC
On−Chip Current Translator
SPI Interface
Speed and Load Angle Output
Seven Step Modes from Full−Step Up to 32 Micro−Steps
Fully Integrated Current−Sense
PWM Current Control with Automatic Selection of Fast and Slow
Decay
Low EMC PWM with Selectable Voltage Slopes
Active Fly−Back Diodes
Full Output Protection and Diagnosis
Thermal Warning and Shutdown
Compatible with 5 V and 3.3 V Microcontrollers
Integrated 5 V Regulator to Supply External Microcontroller
Integrated Reset Function to Reset External Microcontroller
Integrated Watchdog Function
These Devices are Pb−Free and are RoHS Compliant*
A
WL
YY
WW
G
CCCCC
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Designator
= Country of Assembly
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 27 of this data sheet.
†Output current level may be limited by ambient temperature and heat sinking.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2015
March, 2015 − Rev. 2
1
Publication Order Number:
AMIS−30532/D
AMIS−30532
Block DIAGRAM
CLK
Timebase
VDD
CPN CPP VCP
Vreg
Chargepump
POR
VBB
EMC
MOTXP
CS
DI
OTP
SPI
DO
NXT
Logic &
Registers
DIR
Load
Angle
SLA
T
R
A
N
S
L
A
T
O
R
Temp .
Sense
POR/WD
P
W
M
MOTXN
I−sense
EMC
MOTYP
P
W
M
MOTYN
I−sense
CLR
Band−
gap
ERR
AMIS−30532
GND
Figure 1. Block Diagram AMIS−30532
Table 1. PIN LIST AND DESCRIPTION
Description
Type
Equivalent
Schematic
Name
Pin
GND
1
Ground
Supply
DI
2
SPI Data In
Digital Input
Type 2
CLK
3
SPI Clock Input
Digital Input
Type 2
NXT
4
Next Micro−Step Input
Digital Input
Type 2
DIR
5
Direction Input
Digital Input
Type 2
ERR
6
Error Output (Open Drain)
Digital Output
Type 4
SLA
7
Speed Load Angle Output
Analog Output
Type 5
/
8
No Function (to be left open in normal operation)
CPN
9
Negative Connection of Charge Pump Capacitor
High Voltage
CPP
10
Positive Connection of Charge Pump Capacitor
High Voltage
VCP
11
Charge−Pump Filter−Capacitor
High Voltage
CLR
12
“Clear” = Chip Reset Input
Digital Input
Type 1
CS
13
SPI Chip Select Input
Digital Input
Type 2
VBB
14
High Voltage Supply Input
Supply
Type 3
MOTYP
15, 16
Negative End of Phase Y Coil Output
Driver Output
GND
17, 18
Ground, Heat Sink
Supply
MOTYN
19, 20
Positive End of Phase Y Coil Output
Driver Output
MOTXN
21, 22
Positive End of Phase X Coil Output
Driver Output
GND
23, 24
Ground, Heat Sink
Supply
MOTXP
25, 26
Negative End of Phase X Coil Output
Driver Output
VBB
27
High Voltage Supply Input
Supply
Type 3
/
30
No Function (to be left open in normal operation)
POR/WD
28
Power−On−Reset and Watchdog Reset Output (Open Drain)
Digital Output
Type 2
TST0
29
Test Pin Input (to be tied to ground in normal operation)
Digital Input
DO
31
SPI Data Output (Open Drain)
Digital Output
Type 4
VDD
32
Logic Supply Output (needs external decoupling capacitor)
Supply
Type 6
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2
AMIS−30532
PIN DESCRIPTION
VBB
MOTXP
MOTXP
30
TST0
31
POR/WD
DO
VDD
32
29
28
27
26
25
GND
1
24
GND
DI
CLK
NXT
2
23
GND
3
22
4
21
MOTXN
MOTXN
DIR
5
AMIS −30532
20
MOTYN
ERR
6
19
SLA
7
18
8
17
MOTYN
GND
GND
9
10
11
12
13
14
15
16
CPN
CPP
VCP
CLR
CS
VBB
MOTYP
MOTYP
Figure 2. Pin Out AMIS−30532
Table 2. ABSOLUTE MAXIMUM RATINGS
Symbol
Min
Max
Unit
VBB
Analog DC Supply Voltage (Note 1)
−0.3
+40
V
TST
Storage Temperature
−55
+160
°C
Junction Temperature under bias (Note 2)
−50
+175
°C
VESD
Electrostatic discharges on component level, All pins (Note 3)
−2
+2
kV
VESD
Electrostatic discharges on component level, HiV pins (Note 4)
−8
+8
kV
TJ
Parameter
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. For limited time < 0.5 s.
2. Circuit functionality not guaranteed.
3. Human Body Model (100 pF via 1.5 kW, according to JEDEC EIA−JESD22−A114−B).
4. HiV = High Voltage Pins MOTxx, VBB, GND; (100 pF via 1.5 kW, according to JEDEC EIA−JESD22−A114−B).
Table 3. THERMAL RESISTANCE
Thermal resistance
Junction – to – Ambient
Package
Junction – to – Exposed Pad
1S0P board
2S2P board
Unit
NQFP−32
0,95
60
30
K/W
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3
AMIS−30532
EQUIVALENT SCHEMATICS
Following figure gives the equivalent schematics of the user relevant inputs and outputs. The diagrams are simplified
representations of the circuits used.
4K
IN
OUT
Rin
TYPE 1: CLR input
TYPE 4: DO and ERRB open drain outputs
4K
Rout
IN
SLA
TYPE 2 : CLK , DI, CSB , NXT , DIR inputs
TYPE 5: SLA analog output
VDD
VBB
VDD
VBB
.
TYPE 3: VDD and VBB power supply inputs
Figure 3. In− and Output Equivalent Diagram
PACKAGE THERMAL CHARACTERISTICS
The Rthja for 2S2P is simulated conform JEDEC
JESD−51 as follows:
• A 4−layer printed circuit board with inner power planes
and outer (top and bottom) signal layers is used
• Board thickness is 1.46 mm (FR4 PCB material)
• The 2 signal layers: 70 mm thick copper with an area of
5500 mm2 copper and 20% conductivity
• The 2 power internal planes: 36 mm thick copper with
an area of 5500 mm2 copper and 90% conductivity
The Rthja for 1S0P is simulated conform to JEDEC
JESD−51 as follows:
• A 1−layer printed circuit board with only 1 layer
• Board thickness is 1.46 mm (FR4 PCB material)
• The layer has a thickness of 70 mm copper with an area
of 5500 mm2 copper and 20% conductivity
The AMIS−30532 is available in a NQFP32 package. For
cooling optimizations, the NQFP has an exposed thermal
pad which has to be soldered to the PCB ground plane. The
ground plane needs thermal vias to conduct the heat to the
bottom layer. Figure 3 gives an example for good power
distribution solutions.
For precise thermal cooling calculations the major
thermal resistances of the device are given. The thermal
media to which the power of the devices has to be given are:
• Static environmental air (via the case)
• PCB board copper area (via the exposed pad)
The thermal resistances are presented in Table 5: DC
Parameters.
The major thermal resistances of the device are the Rth
from the junction to the ambient (Rthja) and the overall Rth
from the junction to exposed pad (Rthjp). In Table 5 below
one can find the values for the Rthja and Rthjp, simulated
according to JESD−51:
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4
AMIS−30532
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
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ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
NQFP−32
Figure 4. Example of NQFP-32 PCB Ground Plane Layout in Top View (Preferred Layout at Top and Bottom)
ELECTRICAL SPECIFICATION
Recommend Operation Conditions
Operating ranges define the limits for functional
operation and parametric characteristics of the device. Note
that the functionality of the chip outside these operating
ranges is not guaranteed. Operating outside the
recommended operating ranges for extended periods of time
may affect device reliability.
Table 4. OPERATING RANGES
Symbol
VBB
TJ
Parameter
Min
Max
Unit
Analog DC Supply
+6
+30
V
Junction Temperature (Note 5)
−40
+172
°C
5. No more than 100 cumulative hours in life time above Ttw.
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AMIS−30532
Table 5. DC PARAMETERS (The DC parameters are given for VBB and temperature in their operating ranges unless otherwise
specified) Convention: currents flowing in the circuit are defined as positive.
Symbol
Pin(s)
Parameter
Remark/Test Conditions
Min
Typ
Max
Unit
30
V
8
mA
5.50
V
8
mA
SUPPLY AND VOLTAGE REGULATORS
Nominal operating supply range
VBB
VBB
IBB
Total current consumption (Note 6)
6
Unloaded outputs
VDD
Regulated output voltage
IINT
Internal load current (Note 6)
Unloaded outputs
Max output current (external and
internal loads)
6 V < VBB < 8 V
20
8 V < VBB < 30 V
50
Current limitation
Pin shorted to ground
ILOAD
VDD
IDDLIM
ILOAD_PD
4.50
Output current in powerdown
5
mA
mA
150
1
mA
mA
POWER−ON−RESET (POR)
VDDH
VDD
VDDL
Internal POR comparator threshold VDD rising
4.0
4.25
4.4
V
Internal POR comparator threshold VDD falling
3.68
V
IMDmax,Peak
Max current through motor coil in
normal operation
3015
mA
IMDmax,RMS
Max RMS current through coil in
normal operation
2132
mA
MOTORDRIVER
IMDabs
Absolute error on coil current
−10
10
%
IMDrel
Error on current ratio Icoilx / Icoily
−7
7
%
ISET_TC1
Temperature coefficient of coil current set−level, CUR[4:0] = 0...27
−40°C v TJ v 160°C
−250
ppm/k
ISET_TC2
Temperature coefficient of coil current set−level, CUR[4:0] = 28...31
−40°C v TJ v 160°C
−460
ppm/k
On−resistance high−side driver,
CUR[4:0] = 0...31 (Note 7)
VBB = 12 V, TJ = 27°C
On−resistance low−side driver,
CUR[4:0] = 23...31 (Note 7)
VBB = 12 V, TJ = 27°C
On−resistance low−side driver,
CUR[4:0] = 16...22 (Note 7)
VBB = 12 V, TJ = 27°C
On−resistance low−side driver,
CUR[4:0] = 9...15 (Note 7)
VBB = 12 V, TJ = 27°C
RLS0
On−resistance low−side driver,
CUR[4:0] = 0...8 (Note 7)
VBB = 12 V, TJ = 27°C
VBB = 12 V, TJ = 160°C
3.2
IMpd
Pulldown current
HiZ mode
5.0
Input leakage (Note 8)
TJ = 160°C
RHS
RLS3
MOTXP
MOTXN
MOTYP
MOTYN
RLS2
RLS1
VBB = 12 V, TJ = 160°C
0.47
VBB = 12 V, TJ = 160°C
0.56
VBB = 12 V, TJ = 160°C
0.9
VBB = 12 V, TJ = 160°C
1.7
0.35
W
0.70
W
0.35
W
0.70
W
0.65
W
1.25
W
1.25
W
2.5
W
2.5
W
5.0
W
mA
DIGITAL INPUTS
Ileak
VinL
DI, CLK
NXT, DIR
CLR, CS
VinH
1
mA
Logic low threshold
0
0.65
V
Logic high threshold
2.35
VDD
V
Rpd_CLR
CLR
Internal pulldown resistor
120
300
kW
Rpd_TST
TST0
Internal pulldown resistor
3
9
kW
6. Current with oscillator running, all analogue cells active, SPI communication and NXT pulses applied. No floating inputs. Parameter
guaranteed by design.
7. Characterization Data Only
8. Not valid for pins with internal pulldown resistor.
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6
AMIS−30532
Table 5. DC PARAMETERS (The DC parameters are given for VBB and temperature in their operating ranges unless otherwise
specified) Convention: currents flowing in the circuit are defined as positive.
Symbol
Pin(s)
Parameter
Remark/Test Conditions
Min
Typ
Max
Unit
0.5
V
152
°C
DIGITAL OUTPUTS
VOL
DO, ERR,
POR/WD
Logic Low level open drain
IOL = 5 mA
THERMAL WARNING AND SHUTDOWN
Ttw
Thermal warning
Ttsd
Thermal shutdown (Notes 9
and 10)
138
145
Ttw + 20
°C
2*VBB–1.5
V
CHARGE PUMP
Vcp
Output voltage
6 V< VBB < 15 V
15 V < VBB < 30 V
VBB+8
VBB+11.5
VBB+15
V
External buffer capacitor
180
220
470
nF
External pump capacitor
180
220
470
nF
VCP
Cbuffer
Cpump
CPP CPN
PACKAGE THERMAL RESISTANCE VALUE
Rthja
Rthjp
Thermal Resistance Junction−to−
Ambient
NQFP
Simulated Conform JEDEC
JESD−51, (2S2P)
Thermal Resistance Junction−to−
Exposed Pad
30
K/W
0.95
K/W
SPEED AND LOAD ANGLE OUTPUT
Vout
Output Voltage Range
Voff
Output Offset SLA Pin
Gsla
SLA
Gain of SLA Pin = VBEMF/Vcoil
Rout
Output Resistance SLA Pin
CLOAD
Load Capacitance SLA Pin
0.2
VDD −
0.2
V
SLAG = 0
−50
50
mV
SLAG = 1
−30
30
mV
1.0
kW
50
pF
SLAG = 0
0.5
SLAG = 1
0.25
0.23
9. No more than 100 cumulated hours in life time above Ttw.
10. Thermal shutdown is derived from thermal warning Characterization Data Only.
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AMIS−30532
Table 6. AC PARAMETERS (The AC parameters are given for VBB and temperature in their operating ranges)
Symbol
Pin(s)
Parameter
Remark/Test Conditions
Min
Typ
Max
Unit
3.6
4.0
4.4
MHz
20.8
22.8
24.8
kHz
41.6
45.6
49.6
kHz
INTERNAL OSCILLATOR
fosc
Frequency of internal oscillator
MOTORDRIVER
fPWM
Frequency depends only on
internal oscillator
PWM frequency
MOTxx
fd
Double PWM frequency
PWM Jitter depth (Note 11)
Tbrise
Turn−on voltage slope, 10% to 90%
MOTxx
Tbfall
Turn−off voltage slope, 90% to 10%
MOTxx
10
% fPWM
EMC[1:0] = 00
350
V/ms
EMC[1:0] = 01
250
V/ms
EMC[1:0] = 10
200
V/ms
EMC[1:0] = 11
100
V/ms
EMC[1:0] = 00
350
V/ms
EMC[1:0] = 01
250
V/ms
EMC[1:0] = 10
200
V/ms
EMC[1:0] = 11
100
V/ms
DIGITAL OUTPUTS
DO
ERR
TH2L
Output fall−time from VinH to VinL
Capacitive load 400 pF and
pullup resistor of 1.5 kW
50
ns
CHARGE PUMP
fCP
CPN CPP Charge pump frequency
TCPU
MOTxx
250
Start−up time of charge pump
(Note 12)
Spec external components in
Table 8
kHz
5
ms
CLR FUNCTION
TCLR
CLR
Hard reset duration time
ms
100
POWERUP
tPU
tPOR
POR /
WD
tRF
110
ms
Powerup time
VBB = 12 V, ILOAD = 50 mA,
CLOAD = 220 nF
Reset duration
See Figure 16
100
ms
Reset filter time
See Figure 16
1.0
ms
WATCHDOG
tWDTO
tWDPR
Watchdog time out interval
POR /
WD
32
Prohibited watchdog acknowledge
delay
512
2.0
ms
ms
NXT FUNCTION
tNXT_HI
NXT Minimum, High Pulse Width
See Figure 5
2.0
ms
tNXT_HI
NXT Minimum, Low Pulse Width
See Figure 5
2.0
ms
NXT Hold Time, Following Change of
DIR
See Figure 5
0.5
ms
NXT Hold Time, Before Change of DIR See Figure 5
0.5
ms
tDIR_SET
tDIR_HOLD
NXT
11. Characterization Data Only
12. Guaranteed by design
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AMIS−30532
tNXT_LO
tNXT_HI
0.5 VCC
NXT
tDIR_SET
ÎÎ
ÎÎ
ÎÎ
DIR
tDIR_HOLD
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
VALID
Figure 5. NXT−Input Timing Diagram
Table 7. SPI TIMING PARAMETERS
Symbol
tCLK
Parameter
Min
SPI Clock Period
Typ
Max
Unit
1
ms
tCLK_HIGH
SPI Clock High Time
100
ns
tCLK_LOW
SPI Clock Low Time
100
ns
DI Set Up Time, Valid Data Before Rising Edge of CLK
50
ns
DI Hold Time, Hold Data After Rising Edge of CLK
50
ns
tSET_DI
tHOLD_DI
tCSB_HIGH
CS High Time
2.5
ms
tSET_CSB
CS Set Up Time, CS Low Before Rising Edge of CLK
100
ns
tSET_CLK
CLK Set Up Time, CLK Low Before Rising Edge of CS
100
ns
0. 2 V CC
CS
0 .2 VCC
tSET _CSB
tCLK
tSET_CLK
0 .8 V CC
CLK
0 .2 VCC
0.2 VCC
tCLK_HI
ÎÎÎ
ÎÎÎ
ÎÎÎ
DI
tSET_DI
tCLK _LO
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
tHOLD_DI
0.8 VCC
VALID
Figure 6. SPI Timing
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AMIS−30532
TYPICAL APPLICATION SCHEMATIC
100 nF
100 nF
C2
C4
C5
R2
100 nF
R3
R4
D1
100 nF
VDD
C6
VBB
32
14
VBB
DIR
5
4
DO
31
CLK
CS
25, 26
2
3
21, 22
13
CLR
ERR
SLA
C8
9
AMIS−3053 210
NXT
DI
μC
28
R1
15, 16
12
6
19, 20
100 μF
220 nF
27
11
POR/WD
VBAT
C1
C3
VCP
CPN
CPP
C7
220 nF
MOTXP
MOTXN
MOTYP
M
MOTYN
7
1
17 18 23 24 29
TSTO
GND
Figure 7. Typical Application Schematic AMIS−30532
Table 8. EXTERNAL COMPONENTS LIST AND DESCRIPTION
Component
Typ Value
Tolerance
Unit
VBB Buffer Capacitor (Note 13)
100
−20 +80%
mF
VBB Decoupling Block Capacitor
100
−20 +80%
nF
C4
VDD Buffer Capacitor
100
$20%
nF
C5
VDD Buffer Capacitor
100
$20%
nF
C6
Charge Pump Buffer Capacitor
220
$20%
nF
C7
Charge Pump Pumping Capacitor
220
$20%
nF
C8
Low Pass Filter SLA
1
$20%
nF
R1
Low Pass Filter SLA
5.6
$1%
kW
R2, R3, R4
Pullup Resistor Open Drain Output
4.7
$1%
kW
D1
Optional Reverse Protection Diode
MURD530
C1
C2, C3
Function
13. ESR < 1 W.
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AMIS−30532
FUNCTIONAL DESCRIPTION
H−Bridge Drivers
A full H−bridge is integrated for each of the two stator
windings. Each H−bridge consists of two low−side and two
high−side N−type MOSFET switches. Writing logic ‘0’ in
bit <MOTEN> disables all drivers (high−impedance).
Writing logic ‘1’ in this bit enables both bridges and current
can flow in the motor stator windings.
In order to avoid large currents through the H−bridge
switches, it is guaranteed that the top− and bottom−switches
of the same half−bridge are never conductive
simultaneously (interlock delay).
A two−stage protection against shorts on motor lines is
implemented. In a first stage, the current in the driver is
limited. Secondly, when excessive voltage is sensed across
the transistor, the transistor is switched−off.
In order to reduce the radiated/conducted emission,
voltage slope control is implemented in the output switches.
The output slope is defined by the gate−drain capacitance of
output transistor and the (limited) current that drives the
gate. There are two trimming bits for slope control (see SPI
Control Parameter Overview EMC[1:0]).
The power transistors are equipped with so−called “active
diodes”: when a current is forced trough the transistor switch
in the reverse direction, i.e. from source to drain, then the
transistor is switched on. This ensures that most of the
current flows through the channel of the transistor instead of
through the inherent parasitic drain−bulk diode of the
transistor.
Depending on the desired current range and the
micro−step position at hand, the RDS(on) of the low−side
transistors will be adapted such that excellent current−sense
accuracy is maintained. The RDS(on) of the high−side
transistors remain unchanged, see Table 5 DC Parameters
for more details.
PWM Current Control
A PWM comparator compares continuously the actual
winding current with the requested current and feeds back
the information to a digital regulation loop. This loop then
generates a PWM signal, which turns on/off the H−bridge
switches. The switching points of the PWM duty−cycle are
synchronized to the on−chip PWM clock. The frequency of
the PWM controller can be doubled and an artificial jitter
can be added (see SPI Control Parameter Overview PWMJ).
The PWM frequency will not vary with changes in the
supply voltage. Also variations in motor−speed or
load−conditions of the motor have no effect. There are no
external components required to adjust the PWM frequency.
Automatic Forward and Slow−Fast Decay
The PWM generation is in steady−state using a
combination of forward and slow−decay. The absence of
fast−decay in this mode, guarantees the lowest possible
current−ripple “by design”. For transients to lower current
levels, fast−decay is automatically activated to allow
high−speed response. The selection of fast or slow decay is
completely transparent for the user and no additional
parameters are required for operation.
Icoil
Set value
Actual value
t
0
TPWM
Forward & Slow Decay
Forward & Slow Decay
Fast Decay & Forward
Figure 8. Forward and Slow/Fast Decay PWM
www.onsemi.com
11
AMIS−30532
Automatic Duty Cycle Adaptation
process is completely automatic and requires no additional
parameters for operation. The over−all current−ripple is
divided by two if PWM frequency is doubled (see SPI
Control Parameter Overview PWMF).
In case the supply voltage is lower than 2*Bemf, then the
duty cycle of the PWM is adapted automatically to > 50% to
maintain the requested average current in the coils. This
Icoil
Duty Cycle
< 50%
Duty Cycle < 50%
Duty Cycle >50%
Actual value
Set value
t
TPWM
Figure 9. Automatic Duty Cycle Adaptation
Step Translator and Step Mode
When remaining in the same step mode, subsequent
translator positions are all in the same column and increased
or decreased with 1. Table 10 lists the output current versus
the translator position.
As shown in Figure 10 the output current−pairs can be
projected approximately on a circle in the (Ix, Iy) plane.
There are, however, two exceptions: uncompensated half
step and full step. In these step modes the currents are not
regulated to a fraction of Imax but are in all intermediate steps
regulated at 100%. In the (Ix, Iy) plane the current−pairs are
projected on a square. Table 9 lists the output current versus
the translator position for these cases.
The step translator provides the control of the motor by
means of SPI register Stepmode: SM[2:0], SPI register
DIRCNTRL, and input pins DIR and NXT. It is translating
consecutive steps in corresponding currents in both motor
coils for a given step mode.
One out of seven possible stepping modes can be selected
through SPI−bits SM[2:0] (see SPI Control Parameter
Overview). After power−on or hard reset, the coil−current
translator is set to the default 1/32 micro−stepping at
position ‘0’. Upon changing the step mode, the translator
jumps to position 0* of the corresponding stepping mode.
Table 9. SQUARE TRANSLATOR TABLE FOR FULL STEP AND UNCOMPENSATED HALF STEP
Stepmode ( SM[2:0] )
% of Imax
101
110
MSP[6:0]
Uncompensated Half−Step
Full Step
Coil x
Coil y
000 0000
0*
−
0
100
001 0000
1
1
100
100
010 0000
2
−
100
0
011 0000
3
2
100
−100
100 0000
4
−
0
−100
101 0000
5
3
−100
−100
110 0000
6
−
−100
0
111 0000
7
0
−100
100
www.onsemi.com
12
AMIS−30532
Table 10. CIRCULAR TRANSLATOR TABLE
Stepmode (SM[2:0])
% of Imax
000
001
010
011
100
MSP[6:0]
1/32
1/16
1/8
1/4
1/2
Coil x
000 0000
‘0’
0*
0*
0*
0*
0
100
000 0001
1
−
−
−
−
3.5
98.8
000 0010
2
1
−
−
−
8.1
97.7
000 0011
3
−
−
−
−
12.7
96.5
000 0100
4
2
1
−
−
17.4
95.3
000 0101
5
−
−
−
−
22.1
94.1
000 0110
6
3
−
−
−
26.7
93
000 0111
7
−
−
−
−
31.4
91.8
000 1000
8
4
2
1
−
34.9
89.5
000 1001
9
−
−
−
−
38.3
87.2
000 1010
10
5
−
−
−
43
84.9
000 1011
11
−
−
−
−
46.5
82.6
000 1100
12
6
3
−
−
50
79
000 1101
13
−
−
−
−
54.6
75.5
000 1110
14
7
−
−
−
58.1
72.1
000 1111
15
−
−
−
−
61.6
68.6
001 0000
16
8
4
2
1
65.1
65.1
001 0001
17
−
−
−
−
68.6
61.6
001 0010
18
9
−
−
−
72.1
58.1
001 0011
19
−
−
−
−
75.5
54.6
001 0100
20
10
5
−
−
79
50
001 0101
21
−
−
−
−
82.6
46.5
001 0110
22
11
−
−
−
84.9
43
001 0111
23
−
−
−
−
87.2
38.3
001 1000
24
12
6
3
−
89.5
34.9
001 1001
25
−
−
−
−
91.8
31.4
001 1010
26
13
−
−
−
93
26.7
001 1011
27
−
−
−
−
94.1
22.1
001 1100
28
14
7
−
−
95.3
17.4
001 1101
29
−
−
−
−
96.5
12.7
001 1110
30
15
−
−
−
97.7
8.1
001 1111
31
−
−
−
−
98.8
3.5
010 0000
32
16
8
4
2
100
0
010 0001
33
−
−
−
−
98.8
−3.5
010 0010
34
17
−
−
−
97.7
−8.1
010 0011
35
−
−
−
−
96.5
−12.7
010 0100
36
18
9
−
−
95.3
−17.4
010 0101
37
−
−
−
−
94.1
−22.1
010 0110
38
19
−
−
−
93
−26.7
010 0111
39
−
−
−
−
91.8
−31.4
010 1000
40
20
10
5
−
89.5
−34.9
010 1001
41
−
−
−
−
87.2
−38.3
010 1010
42
21
−
−
−
84.9
−43
010 1011
43
−
−
−
−
82.6
−46.5
010 1100
44
22
11
−
−
79
−50
010 1101
45
−
−
−
−
75.5
−54.6
010 1110
46
23
−
−
−
72.1
−58.1
010 1111
47
−
−
−
−
68.6
−61.6
011 0000
48
24
12
6
3
65.1
−65.1
011 0001
49
−
−
−
−
61.6
−68.6
011 0010
50
25
−
−
−
58.1
−72.1
011 0011
51
−
−
−
−
54.6
−75.5
011 0100
52
26
13
−
−
50
−79
011 0101
53
−
−
−
−
46.5
−82.6
011 0110
54
27
−
−
−
43
−84.9
011 0111
55
−
−
−
−
38.3
−87.2
011 1000
56
28
14
7
−
34.9
−89.5
011 1001
57
−
−
−
−
31.4
−91.8
011 1010
58
29
−
−
−
26.7
−93
011 1011
59
−
−
−
−
22.1
−94.1
011 1100
60
30
15
−
−
17.4
−95.3
011 1101
61
−
−
−
−
12.7
−96.5
011 1110
62
31
−
−
−
8.1
−97.7
011 1111
63
−
−
−
−
3.5
−98.8
www.onsemi.com
13
Coil y
AMIS−30532
Table 11. CIRCULAR TRANSLATOR TABLE (CONTINUED)
Stepmode (SM[2:0])
% of Imax
000
001
010
011
100
MSP[6:0]
1/32
1/16
1/8
1/4
1/2
Coil x
100 0000
64
32
16
8
4
0
−100
100 0001
65
−
−
−
−
−3.5
−98.8
100 0010
66
33
−
−
−
−8.1
−97.7
100 0011
67
−
−
−
−
−12.7
−96.5
100 0100
68
34
17
−
−
−17.4
−95.3
100 0101
69
−
−
−
−
−22.1
−94.1
100 0110
70
35
−
−
−
−26.7
−93
100 0111
71
−
−
−
−
−31.4
−91.8
100 1000
72
36
18
9
−
−34.9
−89.5
100 1001
73
−
−
−
−
−38.3
−87.2
100 1010
74
37
−
−
−
−43
−84.9
100 1011
75
−
−
−
−
−46.5
−82.6
100 1100
76
38
19
−
−
−50
−79
100 1101
77
−
−
−
−
−54.6
−75.5
100 1110
78
39
−
−
−
−58.1
−72.1
100 1111
79
−
−
−
−
−61.6
−68.6
101 0000
80
40
20
10
5
−65.1
−65.1
101 0001
81
−
−
−
−
−68.6
−61.6
101 0010
82
41
−
−
−
−72.1
−58.1
101 0011
83
−
−
−
−
−75.5
−54.6
101 0100
84
42
21
−
−
−79
−50
101 0101
85
−
−
−
−
−82.6
−46.5
101 0110
86
43
−
−
−
−84.9
−43
101 0111
87
−
−
−
−
−87.2
−38.3
101 1000
88
44
22
11
−
−89.5
−34.9
101 1001
89
−
−
−
−
−91.8
−31.4
101 1010
90
45
−
−
−
−93
−26.7
101 1011
91
−
−
−
−
−94.1
−22.1
101 1100
92
46
23
−
−
−95.3
−17.4
101 1101
93
−
−
−
−
−96.5
−12.7
101 1110
94
47
−
−
−
−97.7
−8.1
101 1111
95
−
−
−
−
−98.8
−3.5
110 0000
96
48
24
12
6
−100
0
110 0001
97
−
−
−
−
−98.8
3.5
110 0010
98
49
−
−
−
−97.7
8.1
110 0011
99
−
−
−
−
−96.5
12.7
110 0100
100
50
25
−
−
−95.3
17.4
110 0101
101
−
−
−
−
−94.1
22.1
110 0110
102
51
−
−
−
−93
26.7
110 0111
103
−
−
−
−
−91.8
31.4
110 1000
104
52
26
13
−
−89.5
34.9
110 1001
105
−
−
−
−
−87.2
38.3
110 1010
106
53
−
−
−
−84.9
43
110 1011
107
−
−
−
−
−82.6
46.5
110 1100
108
54
27
−
−
−79
50
110 1101
109
−
−
−
−
−75.5
54.6
110 1110
110
55
−
−
−
−72.1
58.1
110 1111
111
−
−
−
−
−68.6
61.6
111 0000
112
56
28
14
7
−65.1
65.1
111 0001
113
−
−
−
−
−61.6
68.6
111 0010
114
57
−
−
−
−58.1
72.1
111 0011
115
−
−
−
−
−54.6
75.5
111 0100
116
58
29
−
−
−50
79
111 0101
117
−
−
−
−
−46.5
82.6
111 0110
118
59
−
−
−
−43
84.9
111 0111
119
−
−
−
−
−38.3
87.2
111 1000
120
60
30
15
−
−34.9
89.5
111 1001
121
−
−
−
−
−31.4
91.8
111 1010
122
61
−
−
−
−26.7
93
111 1011
123
−
−
−
−
−22.1
94.1
111 1100
124
62
31
−
−
−17.4
95.3
111 1101
125
−
−
−
−
−12.7
96.5
111 1110
126
63
−
−
−
−8.1
97.7
111 1111
127
−
−
−
−
−3.5
98.8
www.onsemi.com
14
Coil y
AMIS−30532
Iy
Iy
Start = 0
Iy
Step 1
Start = 0
Step 1
Step 2
Start = 0
Step 1
Step 3
Ix
Step 2
Step 3
1/4th micro step
SM[2:0] = 011
Ix
Ix
Step 3
Uncompensated Half Step
SM[2:0] = 101
Step 2
Full Step
SM[2:0] = 110
Figure 10. Translator Table: Circular and Square
Direction
NXT−polarity bit <NXTP> (see Table 14 SPI Control
Parameter Overview), the next step is initiated either on the
rising edge or the falling edge of the NXT input.
The direction of rotation is selected by means of following
combination of the DIR input pin and the SPI−controlled
direction bit <DIRCTRL>. (see Table 14 SPI Control
Parameter Overview)
Translator Position
The translator position MSP[6:0] can be read in SPI Status
Register 3 (See Table 15 SR3). This is a 7−bit number
equivalent to the 1/32th micro−step from Table 10: Circular
Translator Table. The translator position is updated
immediately following a NXT trigger.
NXT Input
Changes on the NXT input will move the motor current
one step up/down in the translator table (even when the
motor is disabled <MOTEN>=0>). Depending on the
NXT
Update
Translator Position
Update
Translator Position
Figure 11. Translator Position Timing Diagram
Synchronization of Step Mode and NXT Input
If the step resolution is decreased at a translator table
position that is shared both by the old and new resolution
setting, then the offset is zero and micro−stepping is
proceeds according to the translator table.
If the translator position is not shared both by the old and
new resolution setting, then the micro−stepping proceeds
with an offset relative to the translator table (See Figure 12
right hand side).
When step mode is re−programmed to another resolution
(Figure 12), then this is put in effect immediately upon the
first arriving “NXT” input. If the micro−stepping resolution
is increased, the coil currents will be regulated to the nearest
micro−step, according to the fixed grid of the increased
resolution. If however the micro−stepping resolution is
decreased, then it is possible to introduce an offset (or phase
shift) in the micro−step translator table.
www.onsemi.com
15
AMIS−30532
Change from lower to higher resolution
Iy
Iy
DIR
endpos
NXT3
NXT2
Change from higher to lower resolution
Iy
DIR
NXT1
NXT4
NXT1
endpos
startpos
Ix
DIR
startpos
NXT2
Ix
Ix
1/4th step
Halfstep
Iy
DIR
1/8th step
Ix
NXT3
Halfstep
Figure 12. NXT−Step Mode Synchronization
Left: Change from lower to higher resolution. The left−hand side depicts the ending half−step position during which a new
step mode resolution was programmed. The right−hand side diagram shows the effect of subsequent NXT commands on the
micro−step position.
Right: Change from higher to lower resolution. The left−hand side depicts the ending micro−step position during which a new
step mode resolution was programmed. The right−hand side diagram shows the effect of subsequent NXT commands on the
half−step position.
Note: It is advised to reduce the micro−stepping resolution only at micro−step positions that overlap with desired micro−step
positions of the new resolution.
Programmable Peak−Current
The amplitude of the current waveform in the motor coils
(coil peak current = Imax) is adjusted by means of an SPI
parameter ”CUR[4:0]” (see Table 14 SPI Control Parameter
Overview). Whenever this parameter is changed, the
coil−currents will be updated immediately at the next PWM
period. Figure 13 presents the Peak−Current and Current
Ratings in conjunction to the Current setting CUR[4:0].
Peak Current
3.02 A
Current Range 3
CUR[ 4:0] = 23 −> 31
1.26 A
Current Range 2
CUR [4:0] = 16 −> 22
654 mA
Current Range 1
CUR[4:0] = 9 −> 15
328 mA
Current Range 0
CUR[4:0] = 0 −> 8
0
8
15
22
Figure 13. Programmable Peak−Current Overview
www.onsemi.com
16
31
CUR[4:0]
AMIS−30532
Speed and Load Angle Output
The SLA−pin provides an output voltage that indicates the
level of the Back−e.m.f. voltage of the motor. This
Back−e.m.f. voltage is sampled during every so−called “coil
current zero crossings”. Per coil, two zero−current positions
exist per electrical period, yielding in total four zero−current
observation points per electrical period.
V BEMF
I COIL
t
ZOOM
Previous
M icro −step
I COIL
Coil Current Zero Crossing
Next
M icr o −step
Current Decay
Zero Current
t
V COIL
Voltage Transient
V BB
|V BEMF |
t
Figure 14. Principle of Bemf Measurement
of the coil voltage is not visible anymore, this mode
generates smoother Back e.m.f. input for post−processing,
e.g. by software.
In order to bring the sampled Back e.m.f. to a descent
output level (0 V to 5 V), the sampled coil voltage VCOIL is
divided by 2 or by 4. This divider is set through an SPI bit
<SLAG>. (see SPI Control Parameter Overview)
The following drawing illustrates the operation of the
SLA−pin and the transparency−bit. “PWMsh” and “ICOIL =
0” are internal signals that define together with SLAT the
sampling and hold moments of the coil voltage.
Because of the relatively high recirculation currents in the
coil during current decay, the coil voltage VCOIL shows a
transient behavior. As this transient is not always desired in
application software, two operating modes can be selected
by means of the bit <SLAT> (see “SLA−transparency” in
see SPI Control Parameter Overview). The SLA pin shows
in ”transparent mode” full visibility of the voltage transient
behavior. This allows a sanity−check of the speed−setting
versus motor operation and characteristics and supply
voltage levels. If the bit “SLAT” is cleared, then only the
voltage samples at the end of each coil current zero crossing
are visible on the SLA−pin. Because the transient behavior
www.onsemi.com
17
AMIS−30532
Ssh
VCOIL
Sh
div2
div4
buf
SLA−pin
Ch
Csh
Icoil=0
PWMsh
SLAT
NOT(Icoil=0)
PWMsh
Icoil=0
SLAT
VCOIL
t
SLA−pin
last sample
is retained
VBEMF
retain last sample
previous output is kept at SLA pin
t
SLAT=1 => SLA−pin is ”transparent” during
VBEMF sampling @ Coil Current Zero
Crossing. SLA−pin is updated ”real−time”.
SLAT=0 => SLA−pin is not ”transparent” during
VBEMF sampling @ Coil Current Zero Crossing.
SLA−pin is updated when leaving current−less state.
Figure 15. Timing Diagram of SLA−pin
Warning, Error Detection and Diagnostics
Feedback
Note: Successive reading the SPI StatusRegisters 1 and 2 in
case of a short circuit condition, may lead to damage to the
drivers.
Thermal Warning and Shutdown
When junction temperature rises above TTW, the thermal
warning bit <TW> is set (Table 16 SPI Status registers
Address SR0). If junction temperature increases above
thermal shutdown level, then the circuit goes in “Thermal
Shutdown” mode (<TSD>) and all driver transistors are
disabled (high impedance) (see Table 16 SPI Status registers
Address SR2). The conditions to reset flag <TSD> is to be
at a temperature lower than TTW and to clear the <TSD> flag
by reading it using any SPI read command.
Open Coil/Current Not Reached Detection
Open coil detection is based on the observation of 100%
duty cycle of the PWM regulator. If in a coil 100% duty cycle
is detected for longer than 200 ms then the related driver
transistors are disabled (high−impedance) and an
appropriate bit in the SPI status register is set (<OPENX> or
<OPENY>). (Table 16)
When the resistance of a motor coil is very large and the
supply voltage is low, it can happen that the motor driver is
not able to deliver the requested current to the motor. Under
these conditions the PWM controller duty cycle will be
100% and after 200 ms the error pin and <OPENX>,
<OPENY> will flag this situation (motor current is kept
alive). This feature can be used to test if the operating
conditions (supply voltage, motor coil resistance) still allow
reaching the requested coil−current or else the coil current
should be reduced.
Overcurrent Detection
The overcurrent detection circuit monitors the load
current in each activated output stage. If the load current
exceeds the overcurrent detection threshold, then the
over−current flag is set and the drivers are switched off to
reduce the power dissipation and to protect the integrated
circuit. Each driver transistor has an individual detection bit
in (see Table 16 SPI Status registers Address SR1 and SR2:
<OVCXij> and <OVCYij>). Error condition is latched and
the microcontroller needs to clean the status bits to reactivate
the drivers.
Charge Pump Failure
The charge pump is an important circuit that guarantees
low RDS(on) for all drivers, especially for low supply
www.onsemi.com
18
AMIS−30532
voltages. If supply voltage is too low or external components
are not properly connected to guarantee RDS(on) of the
drivers, then the bit <CPFAIL> is set (Table 16). Also after
POR the charge pump voltage will need some time to exceed
the required threshold. During that time <CPFAIL> will be
set to “1”.
some low−voltage analog blocks and external circuitry. The
voltage is derived from an internal bandgap reference. To
calculate the available drive−current for external circuitry,
the specified Iload should be reduced with the consumption
of internal circuitry (unloaded outputs) and the loads
connected to logic outputs. See Table 5 DC Parameters.
Error Output
Power−On Reset (POR) Function
The open drain output pin POR/WD provides an “active
low” reset for external purposes. At power−up of
AMIS−30532, this pin will be kept low for some time to reset
for example an external microcontroller. A small analog
filter avoids resetting due to spikes or noise on the VDD
supply.
This is a digital output to flag a problem to the external
microcontroller. The signal on this output is active low and
the logic combination of:
NOT(ERRB) = <TW> OR <TSD> OR <OVCXij> OR
<OVCYij> OR <OPENi> OR <CPFAIL>
Logic Supply Regulator
AMIS−30532 has an on−chip 5 V low−drop regulator
with external capacitor to supply the digital part of the chip,
VBB
t
VDD
tPD
tPU
VDDH
VDDL
t
< tRF
POR/WD pin
tPOR
tRF
Figure 16. Power−on−Reset Timing Diagram
Watchdog Function
The watchdog function is enabled/disabled through
<WDEN> bit (Table 13: SPI CONTROL REGISTERS (ALL
SPI control registers have Read/Write Access and default to
”0” after power−on or hard reset.)). Once this bit has been set
to “1” (watchdog enable), the microcontroller needs to
re−write this bit to clear an internal timer before the
watchdog timeout interval expires. In case the timer is
activated and WDEN is acknowledged too early (before
tWDPR) or not within the interval (after tWDTO), then a reset
of the microcontroller will occur through POR/WD pin. In
addition, a warm/cold boot bit <WD> is available (see
Tables 16 and 17) for further processing when the external
microcontroller is alive again.
analog circuits is depending on the reset state of the digital,
charge pump remains active. Logic 0 on CLR pin resumes
normal operation again.
The voltage regulator remains functional during and after
the reset and the POR/WD pin is not activated. Watchdog
function is reset completely.
Sleep Mode
The bit <SLP> in SPI Control Register 2 (See Table 12)
is provided to enter a so−called “sleep mode”. This mode
allows reduction of current−consumption when the motor is
not in operation. The effect of sleep mode is as follows:
• The drivers are put in HiZ
• All analog circuits are disabled and in low−power mode
• All internal registers are maintaining their logic content
• NXT and DIR inputs are forbidden
• SPI communication remains possible (slight current
increase during SPI communication)
• Reset of chip is possible through CLR pin
CLR Pin (=Hard Reset)
Logic 0 on CLR pin allows normal operation of the chip.
To reset the complete digital inside AMIS−30532, the input
CLR needs to be pulled to logic 1 during minimum time
given by tCLR. (Table 6 AC Parameters). This reset function
clears all internal registers without the need of a
power−cycle, except in sleep mode. The operation of all
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19
AMIS−30532
• Oscillator and digital clocks are silent, except during
leaving sleep mode, this timer continues from the value it
had before entering sleep mode.
Normal operation is resumed after writing logic ‘0’ to bit
<SLP>. A start−up time is needed for the charge pump to
stabilize. After this time, NXT commands can be issued.
SPI communication
The voltage regulator remains active but with reduced
current−output capability (ILOADSLP). The watchdog timer
stops running and it’s value is kept in the counter. Upon
VBB
t
VDD
tPU
VDDH
t
tPOR
POR/WD pin
tWDRD tPOR
tDSPI
Enable WD
= tWDPR or = tWDTO
> tWDPR and < tWDTO
Acknowledge WD
t
tWDTO
WD timer
t
Figure 17. Watchdog Timing Diagram
Note: tDSPI is the time needed by the external microcontroller to shift−in the <WDEN> bit after a power−up.
The duration of the watchdog timeout interval is programmable through the WDT[3:0] bits (See also Table 13: SPI
CONTROL REGISTERS (ALL SPI control registers have Read/Write Access and default to “0” after power−on or hard reset.).
The timing is given in Table 12 below.
Table 12. WATCHDOG TIMEOUT INTERVAL AS FUNCTION OF WDT[3.0]
Index WDT[3:0]
tWDTO (ms)
Index WDT[3:0]
tWDTO (ms)
0
0000
32
8
1000
288
1
0001
64
9
1001
320
2
0010
96
10
1010
352
3
0011
128
11
1011
384
4
0100
160
12
1100
416
5
0101
192
13
1101
448
6
0110
224
14
1110
480
7
0111
256
15
1111
512
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20
AMIS−30532
SPI INTERFACE
DO signal is the output from the Slave (AMIS−30532), and
DI signal is the output from the Master. A chip select line
(CS) allows individual selection of a Slave SPI device in a
multiple−slave system. The CS line is active low. If
AMIS−30532 is not selected, DO is pulled up with the
external pull up resistor. Since AMIS−30532 operates as a
Slave in MODE 0 (CPOL = 0; CPHA = 0) it always clocks
data out on the falling edge and samples data in on rising
edge of clock. The Master SPI port must be configured in
MODE 0 too, to match this operation. The SPI clock idles
low between the transferred bytes.
The diagram below is both a Master and a Slave timing
diagram since CLK, DO and DI pins are directly connected
between the Master and the Slave.
The serial peripheral interface (SPI) allows an external
microcontroller (Master) to communicate with
AMIS−30532. The implemented SPI block is designed to
interface directly with numerous micro−controllers from
several manufacturers. AMIS−30532 acts always as a Slave
and can’t initiate any transmission. The operation of the
device is configured and controlled by means of SPI
registers which are observable for read and/or write from the
Master.
SPI Transfer Format and Pin Signals
During a SPI transfer, data is simultaneously transmitted
(shifted out serially) and received (shifted in serially). A
serial clock line (CLK) synchronizes shifting and sampling
of the information on the two serial data lines (DO and DI).
1
# CLK cycle
2
3
4
5
6
7
8
CS
CLK
DI
MSB
6
5
4
3
2
1
LSB
DO
MSB
6
5
4
3
2
1
LSB
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Figure 18. Timing Diagram of an SPI Transfer
NOTE:
At the falling edge of the eight clock pulse the data−out shift register is updated with the content of the addressed internal SPI
register. The internal SPI registers are updated at the first rising edge of the AMIS−30532 system clock when CS = High
Transfer Packet
Serial data transfer is assumed to follow MSB first rule.
The transfer packet contains one or more 8−bit characters
(bytes).
BYTE 1
BYTE 2
Command and SPI Register Address
Data
MSB
CMD2
LSB
CMD1 CMD0
Command
MSB
ADDR4 ADDR3 ADDR2 ADDR1 ADDR0
D7
LSB
D6
D5
D4
D3
D2
D1
D0
SPI Register Address
Figure 19. SPI Transfer Packet
Byte 1 contains the Command and the SPI Register
Address and indicates to AMIS−30532 the chosen type of
operation and addressed register. Byte 2 contains data, or
sent from the Master in a WRITE operation, or received
from AMIS−30532 in a READ operation.
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21
AMIS−30532
READ command. This READ command contains the
address of the SPI register to be read out. At the falling edge
of the eight clock pulse the data−out shift register is updated
with the content of the corresponding internal SPI register.
In the next 8−bit clock pulse train this data is shifted out via
DO pin. At the same time the data shifted in from DI
(Master) should be interpreted as the following successive
command or dummy data.
Two command types can be distinguished in the
communication between master and AMIS−30532:
• READ from SPI Register with address ADDR[4:0]:
CMD2 = “0”
• WRITE to SPI Register with address ADDR[4:0]:
CMD2 = “1”
READ Operation
If the Master wants to read data from Status or Control
Registers, it initiates the communication by sending a
Registers are updated with internal status at the rising
edge of the internal AMIS−30532 clock when CS = 1
CS
COMMAND
DI
COMMAND or DUMMY
READ DATA from ADDR 1
DATA from previous command or
NOT VALID after POR or RESET
DATA
DO
DATA
OLD DATA or NOT VALID
DATA from ADDR 1
Figure 20. Single READ Operation where DATA from SPI register with Address 1 is read by the Master
All 4 Status Registers (see SPI Registers) contain 7 data
bits and a parity check bit The most significant bit (D7)
represents a parity of D[6:0]. If the number of logical ones
in D[6:0] is odd, the parity bit D7 equals “1”. If the number
of logical ones in D[6:0] is even then the parity bit D7 equals
“0”. This simple mechanism protects against noise and
increases the consistency of the transmitted data. If a parity
check error occurs it is recommended to initiate an
additional READ command to obtain the status again.
Also the Control Registers can be read out following the
same routine. Control Registers don’t have a parity check.
The CS line is active low and may remain low between
successive READ commands as illustrated in Figure 22.
There is however one exception. In case an error condition
is latched in one of Status Registers (see SPI Registers) the
ERRB pin is activated. (See Section Error Output). This
signal flags a problem to the external microcontroller. By
reading the Status Registers information about the root
cause of the problem can be determined. After this READ
operation the Status Registers are cleared. Because the
Status Registers and ERRB pin (see SPI Registers) are only
updated by the internal system clock when the CS line is
high, the Master should force CS high immediately after the
READ operation. For the same reason it is recommended to
keep the CS line high always when the SPI bus is idle.
WRITE Operation
If the Master wants to write data to a Control Register it
initiates the communication by sending a WRITE
command. This contains the address of the SPI register to
write to. The command is followed with a data byte. This
incoming data will be stored in the corresponding Control
Register after CS goes from low to high! AMIS−30532
responds on every incoming byte by shifting out via DO the
data stored in the last received address.
It is important that the writing action (command − address
and data) to the Control Register is exactly 16 bits long. If
more or less bits are transmitted the complete transfer packet
is ignored.
A WRITE command executed for a read−only register
(e.g. Status Registers) will not affect the addressed register
and the device operation.
Because after a power−on−reset the initial address is
unknown the data shifted out via DO is not valid.
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22
AMIS−30532
The NEW DATA is written into the corresponding
internal register at the rising edge of CS
CS
COMMAND
DI
DATA
WRITE DATA to ADDR 3
DATA from previous command or
NOT VALID after POR or RESET
NEW DATA for ADDR 3
DATA
DO
DATA
OLD DATA or NOT VALID
OLD DATA from ADDR 3
Figure 21. Single WRITE Operation where DATA from the Master is written in SPI register with Address 3
Examples of Combined READ and WRITE
Operations
In the following examples successive READ and WRITE
operations are combined. In Figure 22 the Master first reads
the status from Register at ADDR4 and at ADDR5 followed
CS
by writing a control byte in Control Register at ADDR2.
Note that during the write command the old data of the
pointed register is returned at the moment the new data is
shifted in.
Registers are updated with the internal
status at the rising edge of the internal
AMIS−30532 clock when CS = 1
DI
The NEW DATA is written into the
correspondinginternal register at
the rising edge of CS
COMMAND
COMMAND
COMMAND
DATA
READ DATA
from ADDR4
READ DATA
from ADDR5
WRITE DATA
to ADDR 2
NEW DATA
for ADDR2
DATA
DATA
DATA from previous
command or NOT VALID
after POR or RESET
DATA
DO
OLD DATA
or NOT VALID
DATA
DATA
from ADDR4
DATA
from ADDR5
OLD DATA
from ADDR2
Figure 22. 2 Successive READ Commands Followed by a WRITE Command
After the write operation the Master could initiate a read
back command in order to verify the data correctly written
as illustrated in Figure 23. During reception of the READ
command the old data is returned for a second time. Only
after receiving the READ command the new data is
transmitted. This rule also applies when the master device
wants to initiate an SPI transfer to read the Status Registers.
Because the internal system clock updates the Status
Registers only when CS line is high, the first read out byte
might represent old status information.
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23
AMIS−30532
Registers are updated with
the internal status at the
rising edge of CS
The NEW DATA is written into the
correspondinginternal register at
the rising edge of CS
CS
DI
COMMAND
DATA
COMMAND
WRITE DATA
to ADDR2
NEW DATA
for ADDR2
READ DATA
from ADDR2
COMMAND
or DUMMY
DATA
DATA
OLD DATA
from ADDR2
NEW DATA
from ADDR2
DATA from previous
command or NOT VALID
after POR or RESET
DATA
DATA
OLD DATA
or NOT VALID
DO
OLD DATA
from ADDR2
Figure 23. A WRITE Operation Where DATA from the Master is Written in SPI Register with Address 2 Followed by
a READ Back Operation to Confirm a Correct WRITE Operation
NOTE:
The internal data−out shift buffer of AMIS−30532 is updated with the content of the selected SPI register only at the last (every
eight) falling edge of the CLK signal (see SPI Transfer Format and Pin Signals). As a result, new data for transmission cannot be
written to the shift buffer at the beginning of the transfer packet and the first byte shifted out might represent old data.
Table 13. SPI CONTROL REGISTERS (All SPI control registers have Read/Write Access and default to “0” after power−on or
hard reset)
Structure
Content
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
−
−
−
Address
Reset
0
WR (00h)
Data
WDEN
CR0 (01h)
Data
CR1 (02h)
Data
DIRCTRL
NXTP
−
−
PWMF
PWMJ
CR2 (03h)
Data
MOTEN
SLP
SLAG
SLAT
−
−
CR2 (08h)
Data
−
StrC
Where:
R/W
Reset:
WDT[3:0]
SM[2:0]
CUR[4:0]
M[1:0]
StrB[1:0]
Read and Write access
Status after power-On or hard reset
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24
EMC[1:0]
−
−
StrE[1:0]
AMIS−30532
Table 14. SPI CONTROL PARAMETER OVERVIEW
Symbol
Description
Status
<DIR> = 0
DIRCTRL
NXTP
EMC[1:0]
Controls the direction of rotation (in combination
with logic level on input DIR)
<DIR> = 1
Selects if NXT triggers on rising or falling edge
Turn On – Turn−off Slopes of motor driver
(Note 14)
SLAT
Speed load angle transparency bit
SLAG
Speed load angle gain setting
PWMF
Enables doubling of the PWM frequency (Note 14)
PWMJ
SM[2:0]
SLP
MOTEN
M[1:0]
Enables jittery PWM
Stepmode
Enables sleep mode
Activates the motor driver outputs
PWM Mode Control
Value
<DIRCTRL> = 0
CW motion (Note 15)
<DIRCTRL> = 1
CCW motion (Note 15)
<DIRCTRL> = 0
CCW motion (Note 15)
<DIRCTRL> = 1
CW motion (Note 15)
<NXTP> = 0
Trigger on rising edge
<NXTP> = 1
Trigger on falling edge
00
Very Fast
01
Fast
10
Slow
11
Very Slow
<SLAT> = 0
SLA is transparent
<SLAT> = 1
SLA is NOT transparent
<SLAG> = 0
Gain = 0.5
<SLAG> = 1
Gain = 0.25
<PWMF> = 0
Default Frequency
<PWMF> = 1
Double Frequency
<PWMJ> = 0
Jitter disabled
<PWMJ> = 1
Jitter enabled
000
1/32 Micro − Step
001
1/16 Micro − Step
010
1/8 Micro − Step
011
1/4 Micro − Step
100
Compensated Half Step
101
Uncompensated Half Step
110
Full Step
111
n.a.
<SLP> = 0
Active mode
<SLP> = 1
Sleep mode
<MOTEN> = 0
Drivers disabled
<MOTEN> = 1
Drivers enabled
00
Default PWM control
01
DCMin Mode 1
10
DCMin Mode 2
11
DCMin Mode 3
00
4 PWM clock cycles
StrB[1:0]
PWM Strobe B Control: DON mask comparator
time (Note 16)
01
8 PWM clock cycles
10
12 PWM clock cycles
11
19 PWM clock cycles
StrC
PWM Strobe C Control: Switch time top/bottom
regulation
<StrC> = 0
86% duty cycle PWM regulator
<StrC> = 1
75% duty cycle PWM regulator
00
4 PWM clock cycles
StrE[1:0]
PWM Strobe E Control: Compensation bridge
active time (Note 16)
01
8 PWM clock cycles
10
12 PWM clock cycles
11
19 PWM clock cycles
14. The typical values can be found in Table 5: DC Parameters and in Table 6: AC parameters
15. Depending on the wiring of the motor connections
16. The duration is depending on the selected PWM frequency
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25
AMIS−30532
Selects IMCmax peak. This is the peak or amplitude of the regulated current waveform in the motor coils.
CUR[4:0]
Table 15. SPI CONTROL PARAMETER OVERVIEW CUR[4:0]
Current Range
(Note 18)
0
1
Index
CUR[4:0]
Current (mA)
(Note 17)
Current Range
(Note 18)
Index
CUR[4:0]
Current (mA)
(Note 17)
0
00000
66
16
10000
735
1
00001
135
17
10001
800
2
00010
189
18
10010
883
3
00011
200
19
10011
975
4
00100
221
20
10100
1077
5
00101
244
21
10101
1189
6
00110
269
22
10110
1255
7
00111
297
23
10111
1485
8
01000
328
24
11000
1625
9
01001
366
25
11001
1767
10
01010
400
26
11010
1950
11
01011
442
27
11011
2153
12
01100
488
28
11100
2378
13
01101
538
29
11101
2552
14
01110
594
30
11110
2775
15
01111
654
31
11111
3015
2
3
17. Typical current amplitude at TJ = 125°C
18. Reducing the current over different current ranges might trigger overcurrent detection. See dedicated application note for solutions
SPI Status Register Description
All 4 SPI status registers have Read Access and are default to ”0” after power-on or hard reset.
Table 16. SPI STATUS REGISTERS
Structure
Address
Content
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
SR0 (04h)
Data is not
latched
PAR
TW
CPfail
WD
OPENX
OPENY
−
−
SR1 (05h)
Data is
latched
PAR
OVCXPT
OVCXPB
OVCXNT
OVCXNB
−
−
−
SR2 (06h)
Data is
latched
PAR
OVCYPT
OVCYPB
OVCYYNT
OVCYNB
TSD
−
−
SR3 (07h)
Data is not
latched
PAR
Where:
R
Reset
PAR
MSP[6:0]
Read only mode access
Status after power-on or hard reset
Parity check
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26
AMIS−30532
Table 17. SPI STATUS FLAGS OVERVIEW
Mnemonic
Flag
Length
(bit)
Related SPI Register
Comment
CPFail
Charge pump failure
1
Status Register 0
‘0’ = no failure
‘1’ = failure: indicates that the charge pump does
not reach the required voltage level. Note 1
MSP[6:0]
Micro−step position
7
Status Register 3
Translator micro step position
OPENX
OPEN Coil X
1
Status Register 0
‘1’ = Open coil detected
‘0’
OPENY
OPEN Coil Y
1
Status Register 0
‘1’ = Open coil detected
‘0’
OVCXNB
OVer Current on X
H−bridge; MOTXN
terminal; Bottom
tran.
1
Status Register 1
‘0’ = no failure
‘1’ = failure: indicates that over current is
detected at bottom transistor XN−terminal
‘0’
OVCXNT
OVer Current on X
H−bridge; MOTXN
terminal; Top
transist.
1
Status Register 1
‘0’ = no failure
‘1’ = failure: indicates that over current is
detected at top transistor XN−terminal
‘0’
OVCXPB
OVer Current on X
H−bridge; MOTXP
terminal; Bottom
tran.
1
Status Register 1
‘0’ = no failure
‘1’ = failure: indicates that over current is
detected at bottom transistor XP−terminal
‘0’
OVCXPT
OVer Current on X
H−bridge; MOTXP
terminal; Top
transist.
1
Status Register 1
‘0’ = no failure
‘1’ = failure: indicates that over current is
detected at top transistor XP−terminal
‘0’
OVCYNB
OVer Current on Y
H−bridge; MOTYN
terminal; Bottom
tran.
1
Status Register 2
‘0’ = no failure
‘1’ = failure: indicates that over current is
detected at bottom transistor YN−terminal
‘0’
OVCYNT
OVer Current on Y
H−bridge; MOTYN
terminal; Top
transist.
1
Status Register 2
‘0’ = no failure
‘1’ = failure: indicates that over current is
detected at top transistor YN−terminal
‘0’
OVCYPB
OVer Current on Y
H−bridge; MOTYP
terminal; Bottom
tran.
1
Status Register 2
‘0’ = no failure
‘1’ = failure: indicates that over current is
detected at bottom transistor YP−terminal
‘0’
OVCYPT
OVer Current on Y
H−bridge; MOTYP
terminal; Top
transist.
1
Status Register 2
‘0’ = no failure
‘1’ = failure: indicates that over current is
detected at top transistor YP−terminal
‘0’
TSD
Thermal shutdown
1
Status Register 2
‘0’
TW
Thermal warning
1
Status Register 0
‘0’
WD
Watchdog event
1
Status Register 0
NOTE:
Reset
State
‘0’
‘0000000’
‘1’ = watchdog reset after time−out
‘0’
WD − This bit indicates that the watchdog timer has not been cleared properly. If the master reads that WD is set to “1” after reset,
it means that a watchdog reset occurred (warm boot) instead of POR (cold boot). WD bit will be cleared only when the master
writes “0” to WDEN bit.
Table 18. ORDERING INFORMATION
Peak Current
Temperature
Range
AMIS30532C5321RG
1600 mA
AMIS30532C5321G
1600 mA
Part No.
Package
Shipping†
−40°C to 125°C
NQFP−32 (7 x 7 mm)
(Pb−Free)
Tape & Reel
−40°C to 125°C
NQFP−32 (7 x 7 mm)
(Pb−Free)
Tube
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
27
AMIS−30532
PACKAGE DIMENSIONS
NQFP−32, 7x7
CASE 560AA
ISSUE O
www.onsemi.com
28
AMIS−30532
PACKAGE DIMENSIONS
NQFP−32, 7x7
CASE 560AA
ISSUE O
ON Semiconductor and
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