M48T559Y 64 Kbit (8Kb x8) TIMEKEEPER® SRAM with ADDRESS/DATA MULTIPLEXED ■ SOFTWARE and HARDWARE RESET for WATCHDOG TIMER ■ REGISTER COMPATIBLE with M48T59 TIMEKEEPER SRAM ■ ADDRESS/DATA MULTIPLEXED I/O PINS ■ WATCHDOG TIMER - MONITORS OUT of CONTROL PROCESSOR or HUNG BUS ■ ALARM with WAKE-UP in BATTERY MODE ■ INTEGRATED ULTRA LOW POWER SRAM, REAL TIME CLOCK, POWER-FAIL CONTROL CIRCUIT and BATTERY ■ FREQUENCY TEST OUTPUT for REAL TIME CLOCK ■ AUTOMATIC POWER-FAIL CHIP DESELECT and WRITE PROTECTION ■ WRITE PROTECT VOLTAGE (VPFD = Power-fail Deselect Voltage): SNAPHAT (SH) Battery/Crystal 28 1 SOH28 (MH) Figure 1. Logic Diagram – M48T559Y: 4.2V ≤ VPFD ≤ 4.5V ■ ■ PACKAGING INCLUDES a 28-LEAD SOIC and SNAPHAT® TOP (to be Ordered Separately) SOIC PACKAGE PROVIDES DIRECT CONNECTION for a SNAPHAT TOP CONTAINS the BATTERY and CRYSTAL ■ MICROPROCESSOR POWER-ON RESET (Valid even during battery back-up mode) ■ PROGRAMMABLE ALARM OUTPUT ACTIVE in the BATTERY BACK-UP MODE DESCRIPTION The M48T559Y TIMEKEEPER ® RAM is an 8K x 8 non-volatile static RAM and real time clock. The monolithic chip is available in the SNAPHAT package to provide a highly integrated battery backedup memory and real time clock solution. The 28 pin 330mil SOIC provides sockets with gold plated contacts at both ends for direct connection to a separate SNAPHAT housing containing the battery and crystal. The unique design allows the SNAPHAT battery package to be mounted on top of the SOIC package after the completion of the surface mount process. February 2000 VCC 8 AS0 AD0-AD7 AS1 RST W R M48T559Y IRQ/FT RSTIN1 RSTIN2 E WDI VSS AI01674B 1/18 M48T559Y Figure 2. SOIC Connections RST WDI RSTIN1 RSTIN2 DU NC NC NC NC AD0 AD1 AD2 VSS VSS Table 1. Signal Names 28 1 27 2 26 3 25 4 24 5 23 6 22 7 M48T559Y 21 8 20 9 19 10 18 11 17 12 16 13 15 14 VCC W IRQ/FT DU DU AS1 AS0 R E AD7 AD6 AD5 AD4 AD3 AI01675B AD0-AD7 Address/Data AS0-AS1 Address Strobes W Write Enable R Read Enable E Chip Enable WDI Watchdog Input RSTIN1-RSTIN2 Reset Input RST Power Fail Reset Output (Open Drain) IRQ/FT Interrupt / Frequency Test Output (Open Drain) VCC Supply Voltage VSS Ground NC Not Connected Internally DU Don’t Use must be connected to VCC or VSS Table 2. Absolute Maximum Ratings Symbol Value Unit 0 to 70 °C Storage Temperature (VCC Off, Oscillator Off) –40 to 85 °C VIO Input or Output Voltages –0.3 to 7 V VCC Supply Voltage –0.3 to 7 V IO Output Current 20 mA PD Power Dissipation 1 W TA TSTG Parameter Ambient Operating Temperature Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect reliability. CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode. CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets. Insertion of the SNAPHAT housing after reflow prevents potential battery and crystal damage due to the high temperatures required for device surface-mounting. The SNAPHAT housing is keyed to prevent reverse insertion. The SOIC and battery/crystal packages are shipped separately in plastic anti-static tubes or in Tape & Reel form. For the 28 lead SOIC, the battery/crystal package (i.e. SNAPHAT) part number is "M4T28-BR12SH1". Caution: Do not place the SNAPHAT battery/crystal top in conductive foam, as this will drain the lithium button-cell battery. As Figure 3 shows, the static memory array and the quartz controlled clock oscillator of the M48T559Y are integrated on one silicon chip. The 2/18 two circuits are interconnected at the upper eight memory locations to provide user accessible BYTEWIDE™ clock information in the bytes with addresses 1FF8h-1FFFh. The clock locations contain the year, month, date, day, hour, minute, and second in 24 hour BCD format. Corrections for 28, 29 (leap year), 30, and 31 day months are made automatically. Byte 1FF8h is the clock control register. This byte controls user access to the clock information and also stores the clock calibration setting. The eight clock bytes are not the actual clock counters themselves; they are memory locations consisting of BiPORT™ read/write memory cells. The M48T559Y includes a clock control circuit which updates the clock bytes with current infor- M48T559Y Figure 3. Block Diagram IRQ/FT OSCILLATOR AND CLOCK CHAIN 16 x 8 BiPORT SRAM ARRAY W DATA TRANSCEIVER 32,768 Hz CRYSTAL R POWER 8176 x 8 SRAM ARRAY LITHIUM CELL UPPER ADDRESS LATCH AD0-AD7 AS1 VOLTAGE SENSE AND SWITCHING CIRCUITRY VPFD LOWER ADDRESS LATCH AS0 RSTIN1 VCC RST VSS E RSTIN2 AI01676B Table 3. Operating Modes (1) Mode VCC E R W AD0-AD7 Power VIH X X High Z Standby (3) VIL VIH VIL DIN Active Read VIL VIL VIH DOUT Active Read VIL VIH VIH High Z Active Deselect Write 4.5V to 5.5V Deselect VSO to VPFD (min) (2) X X X High Z CMOS Standby Deselect ≤ VSO X X X High Z Battery Back-up Mode Note: 1. X = VIH or VIL; VSO = Battery Back-up Switchover Voltage. 2. See Table 7 for details. 3. AD0-AD7, AS0, AS1 active when E is high and VCC > V PFD. mation once per second. The information can be accessed by the user in the same manner as any other location in the static memory array. The M48T559Y also has its own Power-fail Detect circuit. The control circuitry constantly monitors the single 5V supply for an out of tolerance condition. When V CC is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low VCC. As VCC falls below approximately 3V, the control circuitry connects the battery which maintains data and clock operation until valid power returns. 3/18 M48T559Y Table 4. AC Measurement Conditions Figure 4. AC Testing Load Circuit ≤ 5ns Input Rise and Fall Times Input Pulse Voltages 5V 0 to 3V Input and Output Timing Ref. Voltages 1.5V 1.9kΩ Note that Output Hi-Z is defined as the point where data is no longer driven. DEVICE UNDER TEST OUT 1kΩ CL = 100pF CL includes JIG capacitance AI01673 Table 5. Capacitance (1, 2) (TA = 25 °C, f = 1 MHz) Symbol CIN CIO (3) Parameter Test Condition Max Unit VIN = 0V 10 pF VOUT = 0V 10 pF Max Unit 0V ≤ VIN ≤ VCC ±1 µA 0V ≤ VOUT ≤ VCC ±5 µA 0V ≤ VIN ≤ VCC 100 µA Outputs open 50 mA E = VIH 10 mA E = VCC – 0.2V 7 mA Input Capacitance Input / Output Capacitance Min Note: 1. Effective capacitance measured with power supply at 5V. 2. Sampled only, not 100% tested. 3. Outputs deselected. Table 6. DC Characteristics (TA = 0 to 70 °C; VCC = 4.5V to 5.5V) Symbol Parameter ILI (1) Input Leakage Current ILO (1) Output Leakage Current ILRST (2) Input Leakage Current ICC Supply Current ICC1 Supply Current (Standby) TTL Test Condition Min ICC2 (3) Supply Current (Standby) CMOS VIL (4) Input Low Voltage –0.3 0.8 V VIH Input High Voltage 2.2 VCC + 0.3 V VOL VOH (6) Note: 1. 2. 3. 4. 5. 6. 4/18 Output Low Voltage IOL = 2.1mA 0.4 V Output Low Voltage (IRQ/FT) (5) IOL = 10mA 0.4 V Output High Voltage IOH = –1mA Outputs deselected. Input leakage current on input RESET pins. AD0-AD7, AS0, AS1 active when E is high and VCC > V PFD. Negative spikes of –1V allowed for up to 10ns once per cycle. The IRQ pins is Open Drain. Measured with Control Bits set as follows: R = '1'; W, ST, FT = '0'. 2.4 V M48T559Y Table 7. Power Down/Up Trip Points DC Characteristics (1) (TA = 0 to 70 °C) Symbol Parameter VPFD Power-fail Deselect Voltage VSO Battery Back-up Switchover Voltage tDR (2) Min Typ Max Unit 4.2 4.35 4.5 V 3.0 Expected Data Retention Time V 7 YEARS Note: 1. All voltages referenced to VSS. 2. At 25°C. Table 8. Power Down/Up AC Characteristics (TA = 0 to 70 °C) Symbol Parameter Min E at VIH before Power Down tPD Max Unit 0 µs tF (1) VPFD (max) to VPFD (min) VCC Fall Time 300 µs tFB (2) VPFD (min) to VSS VCC Fall Time 10 µs tR VPFD (min) to VPFD (max) VCC Rise Time 10 µs tRB VSS to VPFD (min) VCC Rise Time 1 µs tREC VPFD (max) to RST High 40 200 ms Note: 1. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after VCC passes V PFD (min). 2. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data. Figure 5. Power Down/Up Mode AC Waveforms VCC VPFD (max) VPFD (min) VSO tF tDR tR tFB tRB tPD tREC RST INPUTS RECOGNIZED DON'T CARE RECOGNIZED HIGH-Z OUTPUTS VALID (PER CONTROL INPUT) VALID (PER CONTROL INPUT) AI01384D 5/18 M48T559Y Table 9. AC Characteristics (TA = 0 to 70 °C; VCC = 4.5V to 5.5V) M48T559Y Symbol Parameter Unit Min Max tAS Address Setup Time 20 ns tAH Address Hold Time 0 ns tDS Data Setup Time 60 ns tDH Data Hold Time 0 ns tRLDV Read Enable Access Time tRLRH R Pulse Width Low tRHDZ Read Enable High to Output High Z tWLWH W Pulse Width Low 50 ns tELEH E Pulse Width Low 50 ns tASLASH AS0, AS1 Pulse Width Low 15 ns tASHRL AS0, AS1 High to R Low 15 ns tASHWL AS0, AS1 High to W Low 15 ns tELRL Chip Enable Low to Read Enable Low 0 ns tEHDZ Chip Enable High to Data Output Hi-Z 0 ns tELWL Chip Enable Low to Write Enable Low 0 ns RAM OPERATION Four control signals, AS0, AS1, R and W, are used to access the M48T559Y. The address latches are loaded from the address/data bus in response to rising edge signals applied to the Address Strobe 0 (AS0) and Address Strobe 1 (AS1) signals. AS0 is used to latch the lower 8 bits of address, and AS1 is used to latch the upper 5 bits of address. It is not however necessary to follow any particular order. The inputs are in parallel for the two address bytes (upper and lower) and can be latched in any order as long as the correct strobe is used. It is necessary to meet the set-up and hold times given in the AC specifications with valid address information in order to properly latch the address. If the upper and/or lower order addresses are correct from a prior cycle, it is not necessary to repeat the address latching sequence. A write operation requires valid data to be placed on the bus (AD0-AD7), followed by the activation of the Write Enable (W) line. Data on the bus will be written to the RAM, provided that the write timing specifications are met. During a read cycle, the Read Enable (R) signal is driven active. Data from the RAM will become valid on the bus provided that the RAM read access timing specifications are met. 6/18 70 70 ns ns 25 ns The W and R signals should never be active at the same time. In addition, E must be active before any control line is recognized (except for AD0-AD7 and AS0, AS1). RESET INPUT The M48T559Y provides two debounced inputs which can generate an output Reset. The duration and function of the Reset output is identical to a Reset generated by a power cycle. Pulses shorter than tR1 and tR2 will not generate a Reset condition (see Table 12 and Figure 13). DATA RETENTION MODE Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself when V CC falls within the VPFD (max), VPFD (min) window. All outputs become high impedance, and all inputs are treated as "don't care." Note: A power failure during a write cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the RAM's content. At voltages below V PFD (min), the user can be assured the memory will be in a write protected state, provided the V CC fall time is not less than tF. M48T559Y Figure 6. Read Mode AC Waveforms tELEH E tELRL tEHDZ tASLASH AS0 tASLASH AS1 tASHRL tRLRH R tRLDV tAS AD0-AD7 tAH LOW ADDRESS VALID tAS tRHDZ tAH DATA OUT VALID UPPER ADDRESS VALID AI01671B Note: AD5-AD7 are don’t care when latching upper address. Figure 7. Write Mode AC Waveform tELEH E tELWL tEHDZ tASLASH AS0 tASLASH AS1 tASHWL tWLWH W tAS AD0-AD7 tAH LOW ADDRESS VALID tAS tAH UPPER ADDRESS VALID tDS tDH DATA IN VALID AI01672B Note: AD5-AD7 are don’t care when latching upper address. 7/18 M48T559Y Table 10. Register Map Data Address D7 1FFFh D6 D5 D4 D3 D2 10 Years 10 M D0 Year Year 00-99 Month Month 01-12 Date Date 01-31 Day 01-07 Hours Hour 00-23 1FFEh 0 0 1FFDh 0 0 1FFCh 0 FT 1FFBh 0 0 1FFAh 0 10 Minutes Minutes Minutes 00-59 1FF9h ST 10 Seconds Seconds Seconds 00-59 1FF8h W R S 1FF7h WDS BMB4 BMB3 BMB2 BMB1 BMB0 RB1 RB0 Watchdog 1FF6h AFE Y ABE Y Y Y Y Y Interrupts 1FF5h RPT4 Y Al. 10 Date Alarm Date Alarm Date 01-31 1FF4h RPT3 Y Al. 10 Hours Alarm Hours Alarm Hours 00-23 1FF3h RPT2 Alarm 10 Minutes Alarm Minutes Alarm Minutes 00-59 1FF2h RPT1 Alarm 10 Seconds Alarm Seconds Alarm Seconds 00-59 1FF1h Y Y Y Y Y Y Y Y Unused 1FF0h WDF AF Z BL Z Z Z Z Flags Keys: 0 D1 Function/Range BCD Format 10 Date 0 0 0 Day 10 Hours Calibration S = SIGN Bit FT = FREQUENCY TEST Bit R = READ Bit W = WRITE Bit ST = STOP Bit 0 = Must be set to zero Y = ’1’ or ’0’ Z = ’0’ and are Read only AF = Alarm Flag The M48T559Y may respond to transient noise spikes on VCC that reach into the deselect window during the time the device is sampling V CC. Therefore, decoupling of the power supply lines is recommended. When V CC drops below VSO, the control circuit switches power to the internal battery which preserves data and powers the clock. The internal button cell will maintain data in the M48T559Y for an accumulated period of at least 7 years when VCC is less than VSO. As system power returns and VCC rises above VSO, the battery is disconnected, and the power supply is switched to exter- 8/18 Control BL = Battery Low WDS = Watchdog Steering Bit BMB0-BMB4 = Watchdog Multiplier Bits RB0-RB1 = Watchdog Resolution Bits AFE = Alarm Flag Enable ABE = Alarm in Battery Back-up Mode Enable RPT1-RPT4 = Alarm Repeat Mode Bits WDF = Watchdog Flag nal V CC. Write protection continues until VCC reaches VPFD (max) plus tREC. For more information on Battery Storage Life refer to the Application Note AN1012. POWER-ON RESET The M48T559Y continuously monitors V CC. When VCC falls to the power fail detect trip point, the RST pulls low (open drain) and remains low on powerup for 40ms to 200ms after V CC passes VPFD. An external pull-up resistor to VCC is required (1kΩ resistor is recommended). The reset pulse remains active with VCC at VSS. M48T559Y CLOCK OPERATIONS Reading the Clock Updates to the TIMEKEEPER registers should be halted before clock data is read to prevent reading data in transition. Because the BiPORT TIMEKEEPER cells in the RAM array are only data registers, and not the actual clock counters, updating the registers can be halted without disturbing the clock itself. Updating is halted when a '1' is written to the READ bit, D6 in the Control register (1FF8h). As long as a '1' remains in that position, updating is halted. After a halt is issued, the registers reflect the count; that is, the day, date, and the time that were current at the moment the halt command was issued. All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an update in progress. Updating is within a second after the bit is reset to a '0'. Setting the Clock Bit D7 of the Control register (1FF8h) is the WRITE bit. Setting the WRITE bit to a '1', like the READ bit, halts updates to the TIMEKEEPER registers. The user can then load them with the correct day, date, and time data in 24 hour BCD format (see Table 9). Resetting the WRITE bit to a '0' then transfers the values of all time registers (1FF9h-1FFFh) to the actual TIMEKEEPER counters and allows normal operation to resume. After the WRITE bit is reset, the next clock update will occur in one second. See the Application Note AN923 "TIMEKEEPER rolling into the 21st century" for information on Century Rollover. Stopping and Starting the Oscillator The oscillator may be stopped at any time. If the device is going to spend a significant amount of time on the shelf, the oscillator can be turned off to minimize current drain on the battery. The STOP bit is the MSB of the seconds register. Setting it to a ’1’ stops the oscillator. The M48T559Y is shipped from STMicroelectronics with the STOP bit set to a ’1’. When reset to a ’0’, the M48T559Y oscillator starts within one second. Calibrating the Clock The M48T559Y is driven by a quartz controlled oscillator with a nominal frequency of 32,768Hz. The devices are tested not to exceed 35 ppm (parts per million) oscillator frequency error at 25°C, which equates to about ±1.53 minutes per month. With the calibration bits properly set, the accuracy of each M48T559Y improves to better than ±4 ppm at 25°C. The oscillation rate of any crystal changes with temperature (see Figure 10). Most clock chips compensate for crystal frequency and temperature shift error with cumbersome trim capacitors. The M48T559Y design, however, employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure 9. The number of times pulses are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five bit Calibration byte found in the Control Register. Adding counts speeds the clock up, subtracting counts slows the clock down. Figure 8. Clock Calibration NORMAL POSITIVE CALIBRATION NEGATIVE CALIBRATION AI00594B 9/18 M48T559Y Figure 9. Crystal Accuracy Across Temperature ppm 20 0 -20 -40 ∆F = -0.038 ppm (T - T )2 ± 10% 0 F C2 -60 T0 = 25 °C -80 -100 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 °C AI02124 The Calibration byte occupies the five lower order bits (D4-D0) in the Control register (1FF8h). These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a Sign bit; ’1’ indicates positive calibration, ’0’ indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary ’1’ is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is, +4.068 or -2.034 ppm of adjustment per calibration step in the calibration register. Assuming that the oscillator is in fact running at exactly 32,768Hz, each of the 31 increments in the Calibration byte would represent +10.7 or -5.35 seconds per month which corresponds to a total range of +5.5 or - 2.75 minutes per month. Two methods are available for ascertaining how much calibration a given M48T559Y may require. 10/18 The first involves simply setting the clock, letting it run for a month and comparing it to a known accurate reference (like WWV broadcasts). While that may seem crude, it allows the designer to give the end user the ability to calibrate his clock as his environment may require, even after the final product is packaged in a non-user serviceable enclosure. All the designer has to do is provide a simple utility that accesses the Calibration byte. The second approach is better suited to a manufacturing environment, and involves the use of the IRQ/FT pin. The pin will toggle at 512Hz when the Stop bit (D7 of 1FF9h) is ’0’, the FT bit (D6 of 1FFCh) is ’1’, the AFE bit (D7 of 1FF6h) is ’0’, and the Watchdog Steering bit (D7 of 1FF7h) is ’1’ or the Watchdog Register is reset (1FF7h = 0). Any deviation from 512Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.01024 Hz would indicate a +20 ppm oscillator frequency error, requiring a -10 (WR001010) to be loaded into the Calibration Byte for correction. Note that setting or changing the Calibration Byte does not affect the Frequency test output frequency. The FT bit is cleared on power-down. M48T559Y For more information on calibration, see the Application Note AN934 "TIMEKEEPER Calibration". The IRQ/FT pin is an open drain output which requires a pull-up resistor for proper operation. A 500-10kΩ resistor is recommended in order to control the rise time. SETTING ALARM CLOCK Registers 1FF5h-1FF2h contain the alarm settings. The alarm can be configured to go off at a prescribed time on a specific day of the month or repeat every day, hour, minute, or second. It can also be programmed to go off while the M48T559Y is in the battery back-up mode of operation to serve as a system wake-up call. RPT1-RPT4 put the alarm in the repeat mode of operation. Table 11 shows the possible configurations. Codes not listed in the table default to the once per second mode to quickly alert the user of an incorrect alarm setting. Note: User must transition address (or toggle chip enable) to see Flag bit change. When the clock information matches the alarm clock settings based on the match criteria defined by RPT1-RPT4, AF (Alarm Flag) is set. If AFE (Alarm Flag Enable) is also set, the alarm condition activates the IRQ/FT pin. To disable alarm, write ’0’ to the Alarm Date registers and RPT1-4. The alarm flag and the IRQ/FT output are cleared by a read to the Flags register as shown in Figure 11. Note: If an alarm condition occurs while the flags register address is latched into the address buffer, the alarm flag will not be set until an address other than the flags register (1FF0h) is latched into the address buffer. This will insure that the alarm flag will not be inadvertently reset while reading the flag register. To properly check to see if an alarm condition has occurred while reading the flag register, the user is required to latch, read or write to an alternate address and then re-read the alarm flag. The IRQ/FT pin can also be activated in the battery back-up mode. The IRQ/FT will go low if an alarm occurs and both ABE (Alarm in Battery Back-up Mode Enable) and AFE are set. The ABE and AFE bits are reset during power-up, therefore an alarm generated during power-up will only set AF. The user can read the Flag Register at system boot-up to determine if an alarm was generated while the M48T559Y was in the deselect mode during power-up. Figure 12 illustrates the back-up mode alarm timing. Table 11. Alarm Repeat Mode RPT4 RPT3 RPT2 RPT1 Alarm Activated 1 1 1 1 Once per Second 1 1 1 0 Once per Minute 1 1 0 0 Once per Hour 1 0 0 0 Once per Day 0 0 0 0 Once per Month Figure 10. Interrupt Reset Waveforms AD0-AD7 ADDRESS 1FF0h R ACTIVE FLAG BIT IRQ/FT AI01677B 11/18 M48T559Y Figure 11. Back-up Mode Alarm Waveforms tREC VCC VPFD (max) VPFD (min) VSO AFE bit in Interrupt Register AF bit in Flags Register IRQ/FT HIGH-Z HIGH-Z AI01678C WATCHDOG TIMER The watchdog timer can be used to detect an outof-control microprocessor. The user programs the watchdog timer by setting the desired amount of time-out into the eight bit Watchdog Register (Address 1FF7h). The five bits (BMB4-BMB0) store a binary multiplier and the two lower order bits (RB1RB0) select the resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1 second, and 11 = 4 seconds. The amount of time-out is then determined to be the multiplication of the five bit multiplier value with the resolution. (For example: writing 00001110 in the Watchdog Register = 3 x 1 or 3 seconds). Note: Accuracy of timer is within ± the selected resolution. If the processor does not reset the timer within the specified period, the M48T559Y sets the WDF (Watchdog Flag) and generates a watchdog interrupt or a microprocessor reset. WDF is reset by reading the Flags Register (Address 1FF0h). The most significant bit of the Watchdog Register is the Watchdog Steering Bit. When set to a '0', the watchdog will activate the IRQ/FT pin when timedout. When WDS is set to a '1', the watchdog will output a negative pulse on the RST pin for a duration of 40ms to 200ms. The Watchdog register will reset to a '0' at the end of a watchdog time-out when the WDS bit is set to a '1'. 12/18 The watchdog timer can be reset by two methods: – a transition (high-to-low or low-to-high) can be applied to the Watchdog input pin (WDI) or – the microprocessor can perform a write of the Watchdog Register. The time-out period then starts over The WDI pin contains a pull-up resistor and therefore can be left unconnected if not used. The watchdog timer will be reset on each transition (edge) seen by the WDI pin. In order to perform a software reset of the Watchdog timer, the original time-out period can be written into the Watchdog Register, effectively restarting the count-down cycle. Should the watchdog timer time-out, and the WDS bit is programmed to output an interrupt, a value of 00h needs to be written to the Watchdog Register in order to clear the IRQ/FT pin. This will also disable the watchdog function until it is again programmed correctly. A read of the Flags Register will reset the Watchdog Flag (D7; Register MSB15). The watchdog function is automatically disabled upon power-down and the Watchdog Register is cleared. If the watchdog function is set to output to the IRQ/FT pin and the frequency test function is activated, the watchdog or alarm function prevails and the frequency test function is denied. M48T559Y Figure 12. Reset Timing Waveforms RSTIN1 RSTIN2 tR2 Hi-Z Hi-Z RST tR1 tR1HRZ tR2HRZ AI01679 Table 12. Reset AC Characteristics (TA = 0 to 70°C; VCC = 4.5V to 5.5V) Symbol Parameter Min Max Unit tR1 RSTIN1 Low to RST Low 50 200 ns tR2 RSTIN2 Low to RST Low 20 100 ms tR1HRZ RSTIN1 High to RST Hi-Z 40 200 ms tR2HRZ RSTIN2 High to RST Hi-Z 40 200 ms BATTERY LOW WARNING The M48T559Y checks its battery voltage on power-up. The BL (Battery Low) bit (D4 of 1FF0h) will be set on power-up if the battery voltage is less than 2.5V (typical). POWER-ON DEFAULTS Upon application of power to the device, the following register bits are set to a ’0’ state: WDS; BMB0-BMB4; RB0-RB1; AFE; ABE; W; R; FT. POWER SUPPLY DECOUPLING and UNDERSHOOT PROTECTION ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store energy, which stabilizes the V CC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1µF (as shown in Figure 14) is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate neg- ative voltage spikes on V CC that drive it to values below V SS by as much as one Volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, it is recommended to connect a schottky diode from V CC to VSS (cathode connected to VCC, anode to VSS). Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount. Figure 13. Supply Voltage Protection VCC VCC 0.1µF DEVICE VSS AI02169 13/18 M48T559Y Table 13. Ordering Information Scheme Example: M48T559Y MH 1 TR Device Type M48T Supply Voltage and Write Protect Voltage 559Y = VCC = 4.5V to 5.5V; VPFD = 4.2V to 4.5V Package MH (1) = SOH28 Temperature Range 1 = 0 to 70 °C Shipping Method for SOIC blank = Tubes TR = Tape & Reel Note: 1. The SOIC package (SOH28) requires the battery/crystal package (SNAPHAT) which is ordered separately under the part number "M48T28-BR12SH1" in plastic tube or "M4T28-BR12SH1TR" in Tape & Reel form. Caution: Do not place the SNAPHAT battery/crystal package "M4T28-BR12SH1" in conductive foam since will drain the lithium button-cell battery. For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. Table 14. Revision History Date Revision Details June 1998 First Issue 02/07/00 Description Paragraph changed Setting Alarm Clock paragraph changed M4T28-BR12SH SNAPHAT Housing for 48mAh Battery & Crystal Package added (Table 16) Power Down/Up Mode AC Waveforms changed (Figure 5) Back-up Mode Alarm Waveforms changed (Figure 11) 14/18 M48T559Y Table 15. SOH28 - 28 lead Plastic Small Outline, 4-socket battery SNAPHAT, Package Mechanical Data mm inches Symb Typ Min Max A Typ Min 3.05 Max 0.120 A1 0.05 0.36 0.002 0.014 A2 2.34 2.69 0.092 0.106 B 0.36 0.51 0.014 0.020 C 0.15 0.32 0.006 0.012 D 17.71 18.49 0.697 0.728 E 8.23 8.89 0.324 0.350 – – – – eB 3.20 3.61 0.126 0.142 H 11.51 12.70 0.453 0.500 L 0.41 1.27 0.016 0.050 α 0° 8° 0° 8° N 28 e 1.27 0.050 28 CP 0.10 0.004 Figure 14. SOH28 - 28 lead Plastic Small Outline, 4-socket battery SNAPHAT, Package Outline A2 A C B eB e CP D N E H A1 α L 1 SOH-A Drawing is not to scale. 15/18 M48T559Y Table 16. M4T28-BR12SH SNAPHAT Housing for 48mAh Battery & Crystal, Package Mechanical Data mm inches Symb Typ Min A Max Typ Min Max 9.78 0.385 A1 6.73 7.24 0.265 0.285 A2 6.48 6.99 0.255 0.275 A3 0.38 0.015 B 0.46 0.56 0.018 0.022 D 21.21 21.84 0.835 0.860 E 14.22 14.99 0.560 0.590 eA 15.55 15.95 0.612 0.628 eB 3.20 3.61 0.126 0.142 L 2.03 2.29 0.080 0.090 Figure 15. M4T28-BR12SH SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline A1 eA A2 A A3 B L eB D E SHTK-A Drawing is not to scale. 16/18 M48T559Y Table 17. M4T28-BR12SH SNAPHAT Housing for 120mAh Battery & Crystal, Package Mechanical Data mm inches Symb Typ Min A Max Typ Min Max 10.54 0.415 A1 8.00 8.51 0.315 0.335 A2 7.24 8.00 0.285 0.315 A3 0.38 0.015 B 0.46 0.56 0.018 0.022 D 21.21 21.84 0.835 0.860 E 17.27 18.03 0.680 0.710 eA 15.55 15.95 0.612 0.628 eB 3.20 3.61 0.126 0.142 L 2.03 2.29 0.080 0.090 Figure 16. M4T28-BR12SH SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline A1 eA A2 A A3 B L eB D E SHTK-A Drawing is not to scale. 17/18 M48T559Y . Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics 1998 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 18/18