RENESAS HD4074019S

To all our customers
Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand
names are mentioned in the document, these names have in fact all been changed to Renesas
Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and
corporate statement, no changes whatsoever have been made to the contents of the document, and
these changes do not constitute any alteration to the contents of the document itself.
Renesas Technology Home Page: http://www.renesas.com
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
Cautions
Keep safety first in your circuit designs!
1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better
and more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
(iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas
Technology Corporation product best suited to the customer's application; they do not convey any
license under any intellectual property rights, or any other rights, belonging to Renesas Technology
Corporation or a third party.
2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any
third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or
circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and
algorithms represents information on products at the time of publication of these materials, and are
subject to change by Renesas Technology Corporation without notice due to product improvements or
other reasons. It is therefore recommended that customers contact Renesas Technology Corporation
or an authorized Renesas Technology Corporation product distributor for the latest product information
before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss
rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corporation by various
means, including the Renesas Technology Corporation Semiconductor home page
(http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data, diagrams,
charts, programs, and algorithms, please be sure to evaluate all information as a total system before
making a final decision on the applicability of the information and products. Renesas Technology
Corporation assumes no responsibility for any damage, liability or other loss resulting from the
information contained herein.
5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device
or system that is used under circumstances in which human life is potentially at stake. Please contact
Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor
when considering the use of a product contained herein for any specific purposes, such as apparatus or
systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in
whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must be
exported under a license from the Japanese government and cannot be imported into a country other
than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the
country of destination is prohibited.
8. Please contact Renesas Technology Corporation for further details on these materials or the products
contained therein.
HD404019R Series
Rev. 6.0
Sept. 1998
Description
The HD404019R series are HMCS400-series CMOS 4-bit single-chip microcomputers. Each device
incorporates a ROM, RAM, I/O, serial interface, and two timer/counters, and contains high-voltage I/O
pins including high-current output pins to directly drive fluorescent displays.
The HD404019R series includes four chips. The HD404019R and HD40L4019R are Mask ROM versions.
The HD4074019 and HD407L4019 are PROM versions. The HD40L4019R and HD407L4019 are lowvoltage operation versions.
Features
• 16,384-word × 10-bit ROM
 Mask ROM: HD404019R, HD40L4019R
 PROM: HD4074019, HD407L4019
• 992-digit × 4-bit RAM
• 58 I/O pins, including 26 high-voltage I/O pins (40 V max.)
• Two timer/counters
 8-bit free-running timer
 8-bit auto-reload timer/counter
• Clock synchronous 8-bit serial interface
• Five interrupt sources
 Two by external sources
 Two by timer/counters
 One by serial interface
• Subroutine stack, up to 16 levels including interrupts
• Minimum instruction execution time: 0.89 µs
• Low-power dissipation modes
 Standby: Stops instruction execution while allowing clock oscillation and interrupt functions to
operate
 Stop: Stops instruction execution and clock oscillation while retaining RAM data
HD404019R Series
• On-chip oscillator
 Crystal or ceramic oscillator
 External clock
• Packages
 64-pin shrink type plastic DIP
 64-pin flat plastic package
 64-pin shrink type ceramic DIP with window
Ordering Information
Type
Product Name
Model Name
Package
Mask ROM
HD404019R
HD404019RS
DP-64S
HD404019RH
FP-64A
HD404019RFS
FP-64B
HD40L4019RS
DP-64S
HD40L4019RH
FP-64A
HD4074019S
DP-64S
HD4074019H
FP-64A
HD4074019FS
FP-64B
HD4074019C
DC-64S
HD407L4019S
DP-64S
HD407L4019H
FP-64A
HD40L4019R
ZTAT
HD4074019
HD407L4019
ZTAT: Zero Turn Around Time. ZTAT is a trademark of Hitachi Ltd.
2
HD404019R Series
Differences between ZTAT and Mask ROM Version
ZTAT
Mask ROM Version
Item
HD4074019
HD407L4019
HD404019R
HD40L4019R
Power supply
voltage (V)
4.5 to 5.5 V
3.0 to 5.5 V
3.5 to 6.0 V
2.7 to 6.0 V
Instruction cycle
time (tcyc )
0.89 to 20 µs
1.12 to 20 µs
0.89 to 10 µs
1.12 to 10 µs
ROM (word)
16,384 × 10-bit
16,384 × 10-bit
16,384 × 10-bit
16,384 × 10-bit
992 × 4-bit
992 × 4-bit
992 × 4-bit
992 × 4-bit
RAM
1
I/O pin circuit*
Oscillator
stabilization*2
Package
Standard pins
NMOS open drain NMOS open
drain
Each pin can be without pull-up
MOS (NMOS open drain), with
pull-up MOS, or CMOS
High voltage
pins
PMOS open drain PMOS open
drain
Each pin can be without pull-down
MOS (PMOS open drain) or with
pull-down MOS
Crystal
Available
Available
Available
Available
Ceramic
Available
Available
Available
Available
DP-64S
Available
Available
Available
Available
FP-64A
Available
Available
Available
Available
FP-64B
Available
—
Available
—
DC-64S
Available
—
—
—
—:
Not available
Notes: 1. See table 17.
2. See table 20.
3
HD404019R Series
17
50
DP-64S
DC-64S
49
48
18
47
19
46
20
45
21
44
22
43
23
42
24
41
25
40
26
39
27
38
28
37
29
36
30
35
31
34
32
33
42
11
41
12
40
13
39
14
38
15
37
16
36
17
35
18
34
19
33
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
FP-64A
Top view
4
52
43
FP-64B
10
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
53
44
9
R51
R52
R53
R60
R61
R62
R63
VCC
R40/SCK
R41/SI
R42/SO
R43
R70
R71
R72
R73
R03
R10
R11
R12
R13
R20
R21
R22
R23
RA0
RA1/Vdisp
R30
R31
R32/INT0
R33/INT1
R50
54
45
8
32
16
46
7
31
15
55
51
47
6
30
52
14
56
13
48
5
29
53
57
12
49
4
28
54
58
11
3
27
55
59
10
50
26
56
60
9
51
2
25
57
61
58
8
1
24
7
R01
R02
R03
R10
R11
R12
R13
R20
R21
R22
R23
RA0
RA1/Vdisp
R30
R31
R32/INT0
R33/INT1
R50
R51
62
59
23
60
6
22
61
5
63
62
4
64
3
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
GND
OSC2
OSC1
TEST
RESET
R93
R92
R91
R90
R83
R82
R81
R80
R73
R72
R71
R70
R43
R42/SO
R41/SI
R40/SCK
21
63
20
64
2
R52
R53
R60
R61
R62
R63
VCC
R40/SCK
R41/SI
R42/SO
R43
R70
R71
1
R02
R01
R00
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D11
D12
D13
D14
D15
R00
R01
R02
R03
R10
R11
R12
R13
R20
R21
R22
R23
RA0
RA1/Vdisp
R30
R31
R32/INT0
R33/INT1
R50
R51
R52
R53
R60
R61
R62
R63
VCC
R00
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
Pin Arrangement
D2
D1
D0
GND
OSC2
OSC1
TEST
RESET
R93
R92
R91
R90
R83
R82
R81
R80
D3
D2
D1
D0
GND
OSC2
OSC1
TEST
RESET
R93
R92
R91
R90
R83
R82
R81
R80
R73
R72
R8
R7
R6
R5
R83
R82
R81
R80
R73
R72
R71
R70
R63
R62
R61
R60
R53
R52
R51
R50
B
PC
D port
A
R0
CA
R1
ALU
ST
Instruction
decoder
16,384 × 10-bit
ROM
R10
R11
R12
R13
R2
SPY
Y
SP
System control
R00
R01
R02
R03
R20
R21
R22
R23
R3
SPX
X
992 × 4-bit RAM
RESET
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
R30
R31
R32/INT0
R33/INT1
R4
W
R33/INT1
External interrupt
R32/INT0
Interrupt control
Timer
B
GND
VCC
indicates highvoltage I/O pins
R9
R42/SO
R41/SI
R40/SCK
R93
R92
R91
R90
Timer
A
TEST
Serial
interface
OSC1
RA
OSC2
RA1/Vdisp
RA0
HD404019R Series
Block Diagram
R40/SCK
R41/SI
R42/SO
R43
5
HD404019R Series
Pin Functions
Power Supply
VCC: Apply the power supply voltage to this pin.
GND: Connect to ground.
Vdisp: Power supply pin (multiplexed with RA1) for high-voltage I/O pins with a maximum voltage of 40 V
(V CC – 40 V). For details, see the Input/Output section.
TEST: For test purposes only. Connect it to VCC.
RESET: Resets the MCU. For details, see the Reset section.
Oscillators
OSC 1, OSC 2: OSC1 and OSC 2 can be connected to a crystal resonator, ceramic resonator or an external
oscillator circuit. For details, see the Internal Oscillator Circuit section.
Ports
D0 to D15 (D Port): An input/output port addressed by bits. These 16 pins are all input/output pins. D0 to D3
are standard pins and D4 to D15 are high-voltage pins. The circuit type for each pin can be selected using a
mask option. For details, see the Input/Output section.
R0 to RA 1 (R Ports): R0 to R9 are 4-bit I/O ports. Only RA is a 2-bit port. R9 and RA are input ports, and
R0 to R8 are I/O ports. R0, R1, R2, and RA are high-voltage ports, and R3 to R9 are standard ports. Each
pin has a mask option which selects its circuit type. The pins R32, R33, R40, R4 1, and R42 are multiplexed
with INT0, INT 1, SCK, SI, and SO, respectively. For details, see the Input/Output section.
Interrupts
INT0, INT1: External interrupts for the MCU. INT1 can be used as an external event input pin for timer B.
INT 0 and INT1 are multiplexed with R32 and R33, respectively. For details, see the Interrupt section.
Serial Interface
SCK, SI, SO: The transmit clock I/O pin (SCK), serial data input pin (SI), and serial data output pin (SO)
are used for serial interface. SCK, SI, and SO are multiplexed with R40, R41, and R4 2, respectively. For
details, see the Serial Interface section.
6
HD404019R Series
Memory Map
ROM Memory Map
The MCU contains a 16,384-word × 10-bit ROM (mask ROM or PROM). It is described in the following
paragraphs and by the ROM memory map in figure 1.
Vector Address Area ($0000 to $000F): Locations $0000 through $000F are reserved for JMPL
instructions to branch to the starting address of the initialization program and of the interrupt programs.
After reset or an interrupt routine is processed, the program is executed from the vector address.
Zero-Page Subroutine Area ($0000 to $003F): Locations $0000 through $003F are reserved for
subroutines. The CAL instruction branches to subroutines.
Pattern Area ($0000 to $0FFF): Locations $0000 through $0FFF are reserved for ROM data. The P
instruction can refer to the ROM data as a pattern.
Program Area ($0000 to $3FFF): Locations from $0000 to $3FFF can be used for program code.
0
$0000
Vector address
$000F
$0010
15
16
Zero-page subroutine
(64 words)
63
64
$003F
$0040
Pattern
(4096 words)
4095
4096
$0FFF
$1000
Program
(16,384 words)
16383
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
JMPL instruction
(jump to reset routine)
JMPL instruction
(jump to INT0 routine)
JMPL instruction
(jump to INT1 routine)
JMPL instruction
(jump to timer A routine)
JMPL instruction
(jump to timer B routine)
JMPL instruction
(jump to serial routine)
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
$3FFF
Figure 1 ROM Memory Map
7
HD404019R Series
RAM Memory Map
The MCU also contains a 992-digit × 4-bit RAM as the data and stack area. In addition to these areas,
interrupt control bits and special function registers are also mapped on the RAM memory space. The RAM
memory map (figure 2) is described in the following paragraphs.
Interrupt Control Bits Area ($000 to $003): The interrupt control bits area (figure 3) is used for interrupt
control. It is accessible only by RAM bit manipulation instructions. However, the interrupt request flag
cannot be set by software. The RSP bit is used only to reset the stack pointer.
Special Function Registers Area ($004 to $00B): The special function registers are the mode or data
registers for the external interrupt, the serial interface, and the timer/counters. These registers are classified
into three types: write-only, read-only, and read/write as shown in figure 2. These registers cannot be
accessed by RAM bit manipulation instructions.
Data Area ($020 to $3BF): The 16 digits, $020 through $02F, of the data area are called memory registers
(MR) and are accessible by the LAMR and XMRA instructions (figure 4).
Stack Area ($3C0 to $3FF): Locations $3C0 through $3FF are reserved for LIFO stacks to save the
contents of the program counter (PC), status flag (ST), and carry flag (CA) when subroutine calls (CAL
instruction, CALL instruction) or interrupts are processed. This area can be used as a 16-level nesting stack
in which one level requires 4 digits. Figure 4 shows the save condition. The program counter is restored by
the RTN and RTNI instructions. The status and carry flags are restored only by the RTNI instruction. This
area, when not used as a stack, is available as a data area.
8
HD404019R Series
0
$000
RAM-mapped registers
31
32
Memory registers (MR)
47
48
$01F
$020
$02F
$030
Data
(928 digits)
959
960
0
1
2
3
4
5
6
7
8
9
10
11
12
Interrupt control bits area
(PMR)
Port mode register
(SMR)
Serial mode register
Serial data register lower (SRL)
Serial data register upper (SRU)
(TMA)
Timer mode register A
(TMB)
Timer mode register B
(TCBL/TLRL)
Timer B*
(TCBU/TLRU)
$3BF
$3C0
Stack
(64 digits)
W
W
R/W
R/W
W
W
R/W
R/W
Not used
$01F
31
1023
$000
$001
$002
$003
$004
$005
$006
$007
$008
$009
$00A
$00B
$00C
$3FF
*: Two registers are mapped on the same address.
R:
Read only
W:
Write only
R/W: Read/write
10
Timer counter B lower
(TCBL)
R
Timer load register B
lower (TLRL)
W
$00A
11
Timer counter B upper
(TCBU)
R
Timer load register B
upper (TLRU)
W
$00B
Figure 2 RAM Memory Map
9
HD404019R Series
Bit 3
Bit 2
Bit 1
Bit 0
0
IM0
(IM of INT0)
IF0
(IF of INT0)
RSP
(Reset SP bit)
IE
(Interrupt enable flag)
$000
1
IMTA
(IM of timer A)
IFTA
(IF of timer A)
IM1
(IM of INT1)
IF1
(IF of INT1)
$001
2
Not used
Not used
IMTB
(IM of timer B)
IFTB
(IF of timer B)
$002
3
Not used
Not used
IMS
(IM of serial)
IFS
(IF of serial)
$003
IF:
IM:
IE:
SP:
Interrupt request flag
Interrupt mask
Interrupt enable flag
Stack pointer
Note: Each bit of the interrupt control bit area is set by the SEM/SEMD instruction, reset by the
REM/REMD instruction, and tested by the TM/TMD instruction. It is not affected by other
instructions. Furthermore the interrupt request flag is not affected by the SEM/SEMD
instruction. The value of the status flag becomes invalid when the unusable bits are tested.
Figure 3 Interrupt Control Bits Area Configuration
Memory registers
Stack area
32 MR (0) $020 960 Level 16 $3C0
33 MR (1) $021
Level 15
34 MR (2) $022
Level 14
35 MR (3) $023
Level 13
36 MR (4) $024
Level 12
37 MR (5) $025
Level 11
38 MR (6) $026
Level 10
39 MR (7) $027
Level 9
40 MR (8) $028
Level 8
41 MR (9) $029
Level 7
42 MR (10) $02A
Level 6
43 MR (11) $02B
Level 5
44 MR (12) $02C
Level 4
45 MR (13) $02D
Level 3
46 MR (14) $02E
Level 2
47 MR (15) $02F 1023 Level 1 $3FF
Bit 3
Bit 2
Bit 1
Bit 0
1020
ST
PC13
PC12
PC11
$3FC
1021
PC10
PC9
PC8
PC7
$3FD
1022
CA
PC6
PC5
PC4
$3FE
1023
PC3
PC2
PC1
PC0
$3FF
PC13 to PC0: Program counter
ST: Status flag
CA: Carry flag
Figure 4 Configuration of Memory Registers, Stack Area, and Stack Position
10
HD404019R Series
Functional Description
Registers and Flags
The MCU has nine registers and two flags for the CPU operations (figure 5).
3
0
A
Accumulator
3
0
B
B register
1
0
W
3
W register
0
X
3
X register
0
Y
3
Y register
0
SPX
3
SPX register
0
SPY
SPY register
0
CA
Carry flag
0
ST
13
Status flag
0
PC
Program counter
9
1
5
1
1
1
0
SP
Stack pointer
Figure 5 Registers and Flags
Accumulator (A), B Register (B): The 4-bit accumulator and B register hold the results from the
arithmetic logic unit (ALU), and transfer data to/from memory, I/O, and other registers.
W Register (W), X Register (X), Y Register (Y): The 2-bit W register, and the 4-bit X and Y registers
indirectly address RAM. The Y register is also used for D-port addressing.
SPX Register (SPX), SPY Register (SPY): The 4-bit registers SPX and SPY assist the X and Y registers,
respectively.
Carry Flag (CA): The carry flag (CA) stores the overflow from the ALU generated by an arithmetic
operation. It is also affected by the SEC, REC, ROTL, and ROTR instructions.
11
HD404019R Series
During an interrupt, a carry is pushed onto the stack. It is restored by the RTNI instruction, but not by the
RTN instruction.
Status Flag (ST): The status flag (ST) holds the ALU overflow, ALU non-zero, and the results of a bit test
instruction for the arithmetic or compare instructions. It is a branch condition of the BR, BRL, CAL, or
CALL instruction. The value for the status flag remains unchanged until the next arithmetic, compare, or
bit test instruction is executed. The status becomes a 1 after the BR, BRL, CAL, or CALL instruction is
either executed or skipped. During an interrupt, the status is pushed onto the stack. It is restored back from
the stack by the RTNI instruction, but not by the RTN instruction.
Program Counter (PC): The program counter is a 14-bit binary counter which controls the sequence in
which the instructions stored in ROM are executed.
Stack Pointer (SP): The stack pointer (SP) points to the address of the next stack area (up to 16 levels).
The stack pointer is initialized to RAM address $3FF. It is decremented by 4 when data is pushed onto the
stack, and incremented by 4 when data is restored from it. The stack can only be used up to 16 levels deep
because the high-order four bits of the stack pointer are fixed at 1111.
The stack pointer is initialized to $3FF by either MCU reset or by the RSP bit reset from the REM/REMD
instruction.
12
HD404019R Series
Interrupts
Five interrupt sources are available on the MCU: external requests (INT0, INT1), timer/counters (timers A
and B), and serial port (serial). For each source, an interrupt request flag (IF) interrupt mask (IM), and
interrupt vector addresses control and maintain the interrupt request. The interrupt enable flag (IE) also
controls interrupt operations.
Interrupt Control Bits and Interrupt Processing: The interrupt control bits are mapped on $000 through
$003 of the RAM space. They are accessible by RAM bit manipulation instructions. (The interrupt request
flag (IF) cannot be set by software.) The interrupt enable flag (IE) and IF are cleared to 0, and the interrupt
mask (IM) is set to 1 by MCU reset.
Figure 6 is a block diagram of the interrupt control circuit. Table 1 shows the interrupt priority and vector
addresses, and table 2 shows the interrupt conditions corresponding to each interrupt source.
An interrupt request is generated when IF is set to 1 and IM is 0. If IE is 1 at this time, the interrupt will be
activated and vector addresses will be generated from the priority PLA corresponding to the interrupt
source.
Table 1
Vector Addresses and Interrupt Priority
Reset/Interrupt
Priority
Vector Addresses
RESET
—
$0000
INT0
1
$0002
INT1
2
$0004
Timer A
3
$0006
Timer B
4
$0008
Serial
5
$000C
Table 2
Interrupt Conditions
Interrupt Source
Interrupt Control Bit
INT0
INT1
Timer A
Timer B
Serial
IE
1
1
1
1
1
IF0 · IM0
1
0
0
0
0
IF1 · IM1
*
1
0
0
0
IFTA · IMTA
*
*
1
0
0
IFTB · IMTB
*
*
*
1
0
IFS · IMS
*
*
*
*
1
Note: * Indicates don’t care
13
HD404019R Series
Figure 7 shows the interrupt processing sequence, and figure 8 shows the interrupt processing flowchart. If
an interrupt is requested, the instruction being executed finishes in the first cycle. The IE is reset in the
second cycle. In the second and third cycles, the carry flag, status flag, and program counter are pushed
onto the stack. In the third cycle, the instruction is re-executed after jumping to the vector address.
At each vector address, program the JMPL instruction to branch to the starting address of the interrupt
program. The IF which caused the interrupt must be reset by software in the interrupt program.
$000,0
IE
Sequence control
• Push PC/CA/ST
• Reset IE
• Jump to vector address
$000,2
IF0
$000,3
IM0
Priority control
logic
$001,0
IF1
$001,1
IM1
$001,2
IFTA
$001,3
IMTA
$002,0
IFTB
$002,1
IMTB
$003,0
IFS
$003,1
IMS
Note: $m, n is RAM address $m, bit number n.
Figure 6 Interrupt Control Circuit Block Diagram
14
Vector
address
HD404019R Series
Instruction cycles
1
2
3
4
5
6
Instruction
execution*
Interrupt
acceptance
Stacking
IE reset
Vector address
generation
Execution of JMPL
instruction at vector address
Note: * The stack is accessed and the IE reset after the instruction
is executed, even if it is a two-cycle instruction.
Execution of
instruction at
start address
of interrupt
routine
Figure 7 Interrupt Processing Sequence
15
HD404019R Series
Power on
RESET = 1?
No
Yes
Interrupt
request?
Yes
No
No
IE = 1?
Yes
Reset MCU
Execute instruction
Accept interrupt
IE ← 0
PC ← (PC) + 1
Stack ← (PC)
Stack ← (CA)
Stack ← (ST)
PC ← $0002
Yes
INT0
interrupt?
No
PC ← $0004
Yes
INT1
interrupt?
No
PC ← $0006
Yes
Timer A
interrupt?
No
PC ← $0008
Yes
Timer B
interrupt?
No
PC ← $000C
(serial interrupt)
Figure 8 Interrupt Processing Flowchart
16
HD404019R Series
Interrupt Enable Flag (IE: $000, Bit 0): The interrupt enable flag enables/disables interrupt requests as
shown in table 3. It is reset by an interrupt and set by the RTNI instruction.
Table 3
Interrupt Enable Flag
IE
Interrupt Enable/Disable
0
Disabled
1
Enabled
External Interrupts (INT0, INT1): The external interrupt request inputs (INT0, INT1) can be selected by
the port mode register (PMR: $004). Setting bit 3 and bit 2 of PMR causes the R3 3/INT1 and R32/INT0 pins
to be used as INT 1 and INT0, respectively.
The external interrupt request flags (IF0, IF1) are set at the falling edge of the INT0 and INT1 inputs. (Refer
to table 4.)
The INT1 input can be used as a clock signal input to timer B in which timer B counts up at each falling
edge of the INT1 input. When INT1 is used as the timer B external event input, the external interrupt mask
(IM1) has to be set so that the interrupt request by INT1 will not be accepted. (Refer to table 5.)
Table 4
External Interrupt Request Flags
IF0, IF1
Interrupt Request
0
No
1
Yes
Table 5
External Interrupt Masks
IM0, IM1
Interrupt Request
0
Enabled
1
Disabled (masked)
External Interrupt Request Flags (IF0: $000, Bit 2; IF1: $001, Bit 0): The external interrupt request
flags (IF0, IF1) are set at the falling edge of the INT0 and INT1 inputs, respectively.
External Interrupt Masks (IM0: $000, Bit 3; IM1: $001, Bit 1): The external interrupt masks mask the
external interrupt requests.
Port Mode Register (PMR: $004): The port mode register is a 4-bit write-only register which controls the
R3 2/INT0 pin, R33/INT1 pin, R41/SI pin, and R42/SO pin as shown in table 6. The port mode register will be
initialized to $0 by MCU reset. These pins are therefore initially used as ports.
17
HD404019R Series
Table 6
Port Mode Register
PMR3
R3 3/INT1 Pin
0
Used as R33 port input/output pin
1
Used as INT1 input pin
PMR2
R3 2/INT0 Pin
0
Used as R32 port input/output pin
1
Used as INT0 input pin
PMR1
R4 1/SI Pin
0
Used as R41 port input/output pin
1
Used as SI input pin
PMR0
R4 2/SO Pin
0
Used as R42 port input/output pin
1
Used as SO output pin
18
HD404019R Series
Serial Interface
The serial interface is used to transmit/receive 8-bit data serially. It consists of the serial data register, the
serial mode register, the octal counter, and the multiplexer as illustrated in figure 9. Pin R40/SCK and the
transmit clock signal are controlled by the serial mode register. The contents of the serial data register can
be written into or read out by software. The data in the serial data register can be shifted synchronously
with the transmit clock signal.
The STS instruction initiates serial interface operations and resets the octal counter to $0. The counter starts
to count at the falling edge of the transmit clock (SCK) signal and increments by one at the rising edge of
SCK. When the octal counter is reset to $0 after eight transmit clock signals, or a transmit/receive operation
is discontinued, the serial interrupt request flag will be set.
OC (3 bits)
Octal counter
Prescaler (11 bits)
SROF
IFS
Serial
interface
interrupt
request flag
÷2
÷8
÷ 32
÷ 128
÷ 512
÷ 2048
System
clock
÷2
Serial MPX
Internal bus line (S1)
MPX
4
SCK
3
4
SMR (4 bits)
Serial mode register
Internal bus line (S2)
4
SR (8 bits)
Serial data register
4
4
4
Internal bus-line (S2)
PMR (4 bits)
Port mode register
SCK
2
R40/SCK
port
SCK
R41/SI
port
R42/SO
port
SI
SO
Figure 9 Serial Interface Block Diagram
Serial Mode Register (SMR: $005): The 4-bit write-only serial mode register controls the R4 0/SCK pin,
prescaler divide ratio, and transmit clock source as shown in table 7.
The write signal to the serial mode register controls the operating state of the serial interface.
The write signal to the serial mode register stops the serial data register and octal counter from accepting
the transmit clock, and it also resets the octal counter to $0 simultaneously. Therefore, when the serial
interface is in the transfer state, the write signal causes the serial mode register to cease the data transmit
and to set the serial interrupt request flag.
19
HD404019R Series
The contents of the serial mode register will be changed on the second instruction cycle after the serial
mode register has been written to. Therefore, the STS instruction must be executed after the data in the
serial mode register has been changed completely. The serial mode register will be reset to $0 by MCU
reset.
Table 7
Serial Mode Register
SMR3
R4 0/SCK
0
Used as R40 port input/output pin
1
Used as SCK input/output pin
Transmit Clock
SMR2
SMR1
SMR0
R4 0/SCK Port
Clock Source
Prescaler Divide System Clock
Ratio
Divide Ratio
0
0
0
SCK output
Prescaler
÷ 2048
÷ 4096
1
SCK output
Prescaler
÷ 512
÷ 1024
0
SCK output
Prescaler
÷ 128
÷ 256
1
SCK output
Prescaler
÷ 32
÷ 64
0
SCK output
Prescaler
÷8
÷ 16
1
SCK output
Prescaler
÷2
÷4
0
SCK output
System clock
—
÷1
1
SCK input
External clock
—
—
1
1
0
1
Serial Data Register (SRL: $006, SRU: $007): The 8-bit read/write serial data register consists of a loworder digit (SRL: $006) and a high-order digit (SRU: $007).
The data in the serial data register is output from the SO pin, from LSB to MSB, synchronously with the
falling edge of the transmit clock signal. At the same time, external data is input from the SI pin to the
serial data register, MSB first, synchronously with the rising edge of the transmit clock. Figure 10 shows
the I/O timing chart of the transmit clock signal and the data.
The read/write operations of the serial data register should be performed after the completion of data
transmit/receive. Otherwise the data may not be guaranteed.
Transmit clock
1
Serial output data
2
3
4
5
6
LSB
Serial input data
latch timing
Figure 10 Serial Interface I/O Timing
20
7
8
MSB
HD404019R Series
Serial Interrupt Request Flag (IFS: $003, Bit 0): The serial interrupt request flag will be set when the
octal counter counts eight transmit clock signals, or when data transfer is discontinued by resetting the
octal counter. Refer to table 8.
Table 8
Serial Interrupt Request Flag
IFS
Interrupt Request
0
No
1
Yes
Serial Interrupt Mask (IMS: $003, Bit 1): The serial interrupt mask masks the interrupt request. Refer to
table 9.
Table 9
Serial Interrupt Mask
IMS
Interrupt Request
0
Enabled
1
Disabled (masked)
Selection and Change of the Operation Mode: Table 10 shows the serial interface operation modes
which are determined by a combination of the value in the port mode register and in the serial mode
register.
Initialize the serial interface by a write signal to the serial mode register when the operation mode has
changed.
Table 10
Serial Interface Operation Mode
SMR3
PMR1
PMR0
Serial Interface Operating Mode
1
0
0
Clock continuous output mode
1
Transmit mode
0
Receive mode
1
Transmit/receive mode
1
Operating State of Serial Interface: The serial interface has three operating states: the STS waiting state,
transmit clock wait state, and transfer state, as shown in figure 11.
The STS waiting state is the initialization state of the serial interface. The serial interface enters this state in
one of two ways: either by the operation mode changing through a change in the data in the port mode
register, or by data being written into the serial mode register. In this state, the serial interface does not
operate even if the transmit clock is applied. If the STS instruction is executed, the serial interface shifts to
the transmit clock wait state.
21
HD404019R Series
In the transmit clock wait state the falling edge of the first transmit clock causes the serial interface to shift
to the transfer state. The octal counter then counts up and the serial data register shifts simultaneously. As
an exception, if the clock continuous output mode is selected, the serial interface stays in the transmit clock
wait state while the transmit clock outputs continuously.
The octal counter becomes 000 again after 8 transmit clocks or the execution of the STS instruction, so the
serial interface returns to the transmit clock wait state and the serial interrupt request flag is set
simultaneously.
When the internal transmit clock is selected, the transmit clock output is triggered by the execution of the
STS instruction, and stops after 8 clocks.
STS waiting state
octal counter = 000
transmit clock disable
Change PMR *
Write to SMR
Change PMR*
Write to
SMR
STS
instruction
(IFS ← 1)
Transmit clock
Transmit clock wait state
(octal counter = 000)
8 transmit clocks,
STS instruction
(IFS ← 1)
Transfer state
(octal counter ≠ 000)
Note: * Change PMR means the operation mode changes as shown below.
Clock
continuous
output mode
• Transmit mode
• Receive mode
• Transmit/receive mode
Figure 11 Serial Interface Operation State
Transmit Clock Error Detection Example: The serial interface functions abnormally when the transmit
clock is disturbed by external noise. Transmit clock errors can be detected by the procedure shown in figure
12.
If more than 8 transmit clocks occur in the transfer state, the state of the serial interface shifts as follows:
transfer state, transmit clock wait state, and transfer state. The serial interrupt flag should be reset before
entering into the STS state by writing data to SMR. This procedure sets the IFS again.
22
HD404019R Series
Transmit/receive
(IFS ← 1)
Interrupt
disable
IFS ← 0
Write to SMR
IFS = 1?
Yes
Transmit clock
error processing
No
Normal end
Figure 12 Transmit Clock Error Detection Example
23
HD404019R Series
Timers
The MCU contains a prescaler and two timer/counters (timers A and B). See figure 13. The prescaler is an
11-bit binary counter, timer A an 8-bit free-running timer, and timer B is an 8-bit auto-reload timer/event
counter.
Internal bus line (S1)
Timer mode register B
4
TMB (4 bits)
INT1
TL (4 bits)
Timer latch register
3
CPTB
4
Prescaler (11 bits)
Timer A MPX
TBOF
TCB (8 bits)
Timer counter B
IFTB
Interrupt
request flag
of timer B
TLR (8 bits)
Timer load register B
4
Internal bus line (S2)
÷2
÷4
÷8
÷32
÷128
÷512
÷1024
÷2048
System
clock
÷2048
÷2
÷4
÷8
÷32
÷128
÷512
Timer B MPX
4
CPTA
TCA (8 bits)
Timer counter A
TAOF
3
TMA (3 bits)
IFTA
Interrupt
request flag
of timer A
Timer mode register A
Figure 13 Timer/Counter Block Diagram
Prescaler: The input to the prescaler is the system clock signal. The prescaler is initialized to $0000 by
MCU reset, and it starts to count up with the system clock signal as soon as RESET input goes to logic 0.
The prescaler keeps counting up except at MCU reset and stop mode. The prescaler provides clock signals
to timer A, timer B, and the serial interface. The prescaler divide ratio is selected by timer mode register A
(TMA), timer mode register B (TMB), or the serial mode register (SMR).
Timer A Operation: After timer A is initialized to $00 by MCU reset, it counts up at every clock input
signal. When the next clock signal is applied after timer A becomes $FF, it generates an overflow and
becomes $00. This overflow causes the timer A interrupt request flag (IFTA: $001, bit 2) to go to 1. This
timer can function as an interval timer periodically generating overflow output at every 256th clock signal
input.
The clock input signals to timer A are selected by timer mode register A (TMA: $008).
Timer B Operation: Timer mode register B (TMB: $009) selects the auto-reload function, input clock
source, and the prescaler divide ratio of timer B. When the external event input is used as an input clock
signal to timer B, select R33/INT1 as INT1 and set the external interrupt mask (IM1) to prevent an external
interrupt request from occurring.
24
HD404019R Series
Timer B is initialized according to the data written into timer load register B by software. Timer B counts
up at every clock input signal. When the next clock signal is applied to timer B after it is set to $FF, it will
generate an overflow output. In this case, if the autoreload function is selected, timer B is initialized
according to the value of timer load register B. If it is not selected, timer B goes to $00. The timer B
interrupt request flag (IFTB: $002, bit 0) will be set at this overflow output.
Timer Mode Register A (TMA: $008): Timer mode register A is a 3-bit write-only register. The TMA
controls the prescaler divide ratio of timer A clock input as shown in table 11. Timer mode register A is
initialized to $0 by MCU reset.
Table 11
Timer Mode Register A
TMA2
TMA1
TMA0
Prescaler Divide Ratio
0
0
0
÷ 2048
1
÷ 1024
0
÷ 512
1
÷ 128
0
÷ 32
1
÷8
0
÷4
1
÷2
1
1
0
1
Timer Mode Register B (TMB: $009): Timer mode register B (TMB) is a 4-bit write-only register which
selects the auto-reload function, the prescaler divide ratio, and the source of the clock input signal, as
shown in table 12. Timer mode register B is initialized to $0 by MCU reset.
The operation mode of timer B changes at the second instruction cycle after timer mode register B is
written to. Timer B should be initialized by writing data into timer load register B after the contents of
TMB are changed. The configuration and function of timer mode register B is shown in figure 14.
Table 12
Timer Mode Register B
TMB3
Auto-Reload Function
0
No
1
Yes
25
HD404019R Series
TMB2
TMB1
TMB0
Prescaler Divide Ratio, Clock Input Source
0
0
0
÷ 2048
1
÷ 512
0
÷ 128
1
÷ 32
0
÷8
1
÷4
0
÷2
1
INT1 (external event input)
1
1
0
1
PMR: $004
SMR: $005
PMR3 PMR2 PMR1 PMR0
SMR3 SMR2 SMR1 SMR0
Transmit clock selection
R40/SCK pin mode selection
R42/SO pin mode selection
R41/SI pin mode selection
R32/INT0 pin mode selection
R33/INT1 pin mode selection
TMA: $008
TMA2 TMA1 TMA0
TMB: $009
TMB3 TMB2 TMB1 TMB0
Timer B input clock selection
Auto-reload function selection
Timer A input clock selection
Figure 14 Mode Register Configuration and Function
Timer B (TCBL: $00A, TCBU: $00B, TLRL: $00A, TLRU: $00B): Timer B consists of an 8-bit writeonly timer load register, and an 8-bit read-only timer counter. Each of them has a low-order digit (TCBL:
$00A, TLRL: $00A) and a high-order digit (TCBU: $00B, TLRU: $00B). (Refer to figure 2.)
Timer counter B can be initialized by writing data into timer load register B. Write the low-order digit first,
and then the high-order digit. The timer counter is initialized when the high-order digit is written. The timer
load register is initialized to $00 by the MCU reset.
26
HD404019R Series
The counter value of timer B can be obtained by reading timer counter B. In this case, read the high-order
digit first, and then the low-order digit. The count value of the low-order digit is latched at the time when
the high-order digit is read.
Timer A Interrupt Request Flag (IFTA: $001, Bit 2): The timer A interrupt request flag is set by the
overflow output of timer A (table 13).
Table 13
Timer A Interrupt Request Flag
IFTA
Interrupt Request
0
No
1
Yes
Timer A Interrupt Mask (IMTA: $001, Bit 3): The timer A interrupt mask prevents an interrupt request
from being generated by the timer A interrupt request flag (table 14).
Table 14
Timer A Interrupt Mask
IMTA
Interrupt Request
0
Enabled
1
Disabled (masked)
Timer B Interrupt Request Flag (IFTB: $002, Bit 0): The timer B interrupt request flag is set by the
overflow output of timer B (table 15).
Table 15
Timer B Interrupt Request Flag
IFTB
Interrupt Request
0
No
1
Yes
Timer B Interrupt Mask (IMTB: $002, Bit 1): The timer B interrupt mask prevents an interrupt request
from being generated by the timer B interrupt request flag (table 16).
Table 16
Timer B Interrupt Mask
IMTB
Interrupt Request
0
Enabled
1
Disabled (masked)
27
HD404019R Series
Input/Output
The MCU has 58 I/O pins, 32 standard and 26 high voltage. One of three circuit types can be selected by
the mask option for each standard pin: CMOS, with pull-up MOS, and without pull-up MOS (NMOS open
drain); and one of two circuit types can be selected for each high-voltage pin: with pull-down MOS and
without pull-down MOS (PMOS open drain). Since the pull-down MOS is connected to the internal Vdisp
line, the RA 1/Vdisp pin must be selected as V disp via the mask option when the option with pull-down MOS is
selected for at least one high-voltage pin. See table 17 for I/O pin circuit types.
When every input/output pin is used as an input pin, the mask option and output data must be selected in
the manner specified in table 18.
Output Circuit Operation of With Pull-Up MOS Standard Pins: In the standard pin option with pull-up
MOS, the circuit shown in figure 15 is used to shorten the rise time of the output.
When the MCU executes an output instruction, it generates a write pulse to the R port addressed by this
instruction. This pulse will switch the PMOS (B) on and shorten the rise time. The write pulse keeps the
PMOS in the on state for one-eighth of the instruction cycle time. While the write pulse is 0, a high output
level is maintained by the pull-up MOS (C).
When the HLT signal becomes 0 in the stop mode, MOS (A), (B), and (C) turn off.
D Port: I/O port D has 16 discrete I/O pins, each of which can be addressed independently. It can be
set/reset through the SED/RED and SEDD/REDD instructions, and can be tested through the TD and TDD
instructions. See tables 17 and 18 for the classification of standard pin, high-voltage pin, and the I/O pin
circuit types.
R Ports: The eleven R ports are composed of 36 I/O pins and 6 input-only pins. Data is input through the
LAR and LBR instructions and output through the LRA and LRB instructions. The MCU will not be
affected by writing into the input-only and/or non-existing ports, while invalid data will be read when the
output-only and/or non-existing ports are read.
The R3 2 , R33 , R40 , R4 1 , and R42 pins are multiplexed with the INT0 , INT1 , SC K, SI, and SO pins,
respectively. See tables 17 and 18 for the classification of standard pins, high-voltage pins and selectable
circuit types of these I/O pins.
Unused I/O Pins: If unused I/O pins are left floating, the LSI may malfunction because of noise. The I/O
pins should be fixed as follows to prevent malfunction.
High-voltage pins: Select without pull-down MOS (PMOS open drain) via the mask option and connect to
VCC on the printed circuit board.
Standard pins: Select without pull-up MOS (NMOS open drain) via the mask option and connect to GND
on the printed circuit board.
R4 0/SCK and R42/SO should be used as R40 and R42 by the serial mode register and port mode register,
respectively.
28
HD404019R Series
Table 17
I/O Pin Circuit Types
Standard Pins
Without Pull-Up MOS
(NMOS Open Drain) (A) With Pull-Up MOS (B)
I/O
common
pins
HLT
D0–D 3,
Input
data
HLT
Input
data
VCC VCC
HLT
Write
pulse
HLT
HLT
Applicable
Pins
CMOS (C)
Input
data
R3 0–R3 3,
VCC
R4 0–R4 3,
HLT
Output
data
R5 0–R5 3,
R6 0–R6 3,
Output
data
Output
data
R7 0–R7 3,
R8 0–R8 3
VCC
Input pins
HLT
Input
data
HLT
—
HLT
R9 0–R9 3
Input
data
High Voltage Pins
Without Pull-Down MOS
(PMOS Open Drain) (D)
I/O
common
pins
Applicable
Pins
With Pull-Up MOS (E)
VCC
VCC
D4–D 15 ,
HLT
Output
data
HLT
HLT
Output
data
VCC
Vdisp
Input
data
HLT
Input
data
R1 0–R1 3,
R2 0–R2 3
HLT
HLT
Input pins
R0 0–R0 3,
Input
data
Input
data
RA 0
VCC
Vdisp
Input pins
HLT
Input
data
—
RA 1
29
HD404019R Series
Standard Pins
Without Pull-Up MOS
(NMOS Open Drain) or CMOS (A or C) With Pull-Up MOS (B)
I/O
common
pins
Applicable
Pins
SCK
SCK
HLT
HLT
VCC
HLT + mode select
HLT +
mode select
VCC
VCC
Internal SCK
VCC
Output
pins
HLT
SCK*
(output mode)
Internal SCK
VCC
SO
VCC
HLT
SO
SO
INT0, INT1
Input pins
Input
data
HLT
Input
data
SI, SCK
HLT
(input mode)
Notes: In the stop mode, HLT is 0, HLT is 1 and I/O pins are in high impedance.
* If the MCU is interrupted by the serial interface in the external clock input mode, the SCK terminal
becomes input only.
Table 18
Data Input from Common Input/Output Pins
I/O Pin Circuit Type
Standard pins
High voltage pins
30
Input Possible
Input Pin State
CMOS
No
—
Without pull-up MOS (NMOS open drain)
Yes
1
With pull-up MOS
Yes
1
Without pull-down MOS (PMOS open drain)
Yes
0
With pull-down MOS
Yes
0
HD404019R Series
VCC
VCC
PMOS (B)
Write pulse
(output
instruction)
HLT
Pull-up MOS (C)
NMOS (A)
Data
MOS Buffer
On-Resistance Value
A
Approximately 250 Ω
B
Approximately 1 kΩ
C
Approximately 30 kΩ to 160 kΩ (VCC = 5 V)
1 instruction cycle
Output instruction execution
Write pulse
Figure 15 Output Circuit Operation of With Pull-Up MOS Standard Pins
31
HD404019R Series
Reset
Pulling the RESET pin high resets the MCU. At power-on or when cancelling the stop mode, the reset must
satisfy tRC for the oscillator to stabilize. In all other cases, at least two instruction cycles are required for the
MCU to be reset.
Table 19 shows the components initialized by MCU reset, and the status of each.
Table 19
Initial Values After MCU Reset
Item
Initial Value by
MCU Reset
Contents
Program counter (PC)
$0000
Execute program from the top of
ROM address
Status flag (ST)
1
Enable branching with conditional
branch instructions
Stack pointer (SP)
$3FF
Stack level is 0
(A) Without pull-up
MOS
1
Enable to input
(B) With pull-up
MOS
1
Enable to input
(C) CMOS
1
—
0
Enable to input
(E) With pull- down 0
MOS
Enable to input
I/O pins, output Standard
register
pins
High-voltage (D) Without pullpins
down MOS
Interrupt flags
Mode registers
Interrupt enable flag (IE)
0
Inhibit all interrupts
Interrupt request flag (IF)
0
No interrupt request
Interrupt mask (IM)
1
Mask interrupt request
Port mode register (PMR)
0000
See Port Mode Register section
Serial mode register (SMR)
0000
See Serial Mode Register section
Timer mode register A (TMA)
000
See Timer Mode Register A section
Timer mode register B (TMB)
0000
See Timer Mode Register B section
$000
—
Timer counter A (TCA)
$00
—
Timer counter B (TCB)
$00
—
Timer load register (TLR)
$00
—
Octal counter
000
—
Timer/counters Prescaler
32
HD404019R Series
After MCU Reset to Recover from After MCU Reset to Recover from
Stop Mode
Other Modes
Item
Carry flag
(CA)
The contents of the items before
MCU reset are not retained. It is
necessary to initialize them by
software.
Accumulator
(A)
B register
(B)
W register
(W)
X/SPX register
(X/SPX)
Y/SPY register
(Y/SPY)
Serial data register
(SR)
RAM
The contents of the items before
MCU reset are not retained. It is
necessary to initialize them by
software.
The contents of RAM before MCU Same as above for RAM
reset (just before STOP instruction)
are retained
Internal Oscillator Circuit
Figure 16 outlines the internal oscillator circuit. A crystal oscillator or ceramic oscillator can be selected as
the oscillator type. Refer to table 20 to select the oscillator type. In addition, see figure 17 for the layout of
the crystal or ceramic oscillator.
OSC1
Oscillator
1/4
divider
circuit
Timing
generator
circuit
System
clock
OSC2
Figure 16 Internal Oscillator Circuit
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
GND ,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
OSC,,,,,,,,,,,,,,,,,,,,,,,,
2
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
OSC,,,,,,,,,,,,,,,,,,,,,,,,
1
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
TEST,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
RESET,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
D,,,,,,,,,,,,,,,,,,,,,,,,
0
,,,,,,,,,,,,,,,,,,,,,,,,
Figure 17 Layout of Crystal or Ceramic Oscillator
33
HD404019R Series
Table 20
Examples of Oscillator Circuits
Circuit Configuration
External clock
operation
(OSC1, OSC 2)
Circuit Constants
Oscillator
OSC1
Open
OSC2
Ceramic oscillator
(OSC1, OSC 2)
Ceramic oscillator
C1
OSC1
Ceramic
oscillator
CSA4.00MG (Murata)
Rf: 1 MΩ ±20%
Rf
C1: 30 pF ±20%
OSC2
C2
C2: 30 pF ±20%
GND
Crystal oscillator
(OSC1, OSC 2)
Rf: 1 MΩ ±20%
C1
C1: 10 pF to 22 pF ±20%
OSC1
Crystal
C2: 10 pF to 22 pF ±20%
Rf
Crystal: Equivalent circuit shown
at bottom left
OSC2
C2
GND
Co: 7 pF max.
Rs: 100 Ω max.
AT-cut parallel
resonance crystal
OSC1
L
C1
RS
f: 1.0 MHz to 4.5 MHz
OSC2
C0
Notes: 1. The circuit parameters written above are recommended by the crystal or ceramic oscillator
manufacturer. The circuit parameters are affected by the crystal, ceramic resonator, and the
floating capacitance when designing the board.
When using the resonator, consult with the crystal or ceramic oscillator manufacturer to
determine the circuit parameters.
2. Wiring among OSC1, OSC 2, and other elements should be as short as possible, and avoid
crossing other wires. Refer to the recommended layout of the crystal and ceramic oscillator.
Refer to figure 17.
34
HD404019R Series
Operating Modes
The MCU has two low-power dissipation modes, standby mode and stop mode (table 21). Figure 18 is a
mode transition diagram for these modes.
Standby Mode: Executing the SBY instruction puts the MCU into standby mode. In standby mode, the
oscillator circuit is active, and the interrupts, timer/counters, and serial interface remain working. On the
other hand, the CPU stops since the clock related to the instruction execution stops. Registers, RAM, and
I/O pins retain the states they were in just before the MCU went into standby mode.
Table 21
Low-Power Dissipation Modes
Condition
Standby Mode
Stop Mode
Instruction
SBY instruction
STOP instruction
Oscillator circuit
Active
Stopped
Instruction execution
Stopped
Stopped
Registers, flags
Retained
Reset*1
Interrupt function
Active
Stopped
RAM
Retained
Retained
2
Input/output pins
Retained*
High impedance
Timer/counters, serial interface
Active
Stopped
Cancellation method
RESET input, interrupt request
RESET input
Notes: 1. The MCU recovers from the stop mode by RESET input. Refer to table 19 for the contents of
flags and registers.
2. When I/O circuits are active, an I/O current may flow in the standby mode, depending on the
state of the I/O pins. This is an additional current added to the standby mode current dissipation.
Active
mode
SBY
instruction
STOP
instruction
Interrupt
request
Standby
mode
RESET = 1
RESET = 0
RESET = 1
Stop
mode
RESET = 1
Reset
Figure 18 MCU Operating Mode Transition
35
HD404019R Series
Standby mode may be cancelled by inputting RESET or by asserting an interrupt request. In the former
case the MCU is reset. In the later case, the MCU becomes active and executes the next instruction
following the SBY instruction. If the interrupt enable flag is 1 when an interrupt request is asserted, the
interrupt is executed, while if it is 0, the interrupt request is put on hold and normal instruction execution
continues.
Figure 19 shows the flowchart of the standby mode.
Standby
Oscillator: Active
Peripheral clocks: Active
All other clocks: Stop
RESET
= 1?
Yes
No
IF0 = 1?
No
Yes
IM0 = 0?
IF1 = 1?
No
Yes
IFTA = 1?
No
Yes
IM1 = 0?
No
Yes
No
Yes
IMTA = 0?
IFTB = 1?
No
No
Yes
IFS = 1?
No
Yes
IMTB = 0?
Yes
No
Yes
IMS = 0?
Yes
Restart
processor clocks
Restart
processor clocks
Execute next
instruction
(active mode)
No
Reset MCU
Execute
instruction
IE = 1?
Yes
Accept
interrupt
Figure 19 MCU Operating Flowchart in Standby Mode
36
No
HD404019R Series
Stop Mode: Executing the STOP instruction brings the MCU into stop mode, in which the oscillator circuit
and every function of the MCU stop.
The stop mode may be cancelled by resetting the MCU. At this time, as shown in figure 20, reset input
must be applied for at least tRC for oscillation to be stabilized. (Refer to the AC Characteristics table.) After
the stop mode is cancelled, RAM retains the state it was in just before the MCU went into stop mode, but
the accumulator, B register, W register, X/SPX registers, Y/SPY registers, carry flag, and serial data
register will not retain their contents.
Stop mode
Oscillator
Internal clock
RESET
tres
STOP instruction
execution
tres ≥ tRC (stabilization time)
Figure 20 Timing of Stop Mode Cancellation
37
HD404019R Series
PROM Mode Pin Description
Table 22 describes the pin functions in PROM mode.
Table 22
PROM Mode Signals
Pin Number
MCU Mode
PROM Mode
DC-64S,
DP-64S
FP-64B
FP-64A
Symbol
I/O
Symbol
1
59
57
D11
I/O
VCC
2
60
58
D12
I/O
3
61
59
D13
I/O
4
62
60
D14
I/O
5
63
61
D15
I/O
6
64
62
R0 0
I/O
A1
I
7
1
63
R0 1
I/O
A2
I
8
2
64
R0 2
I/O
A3
I
9
3
1
R0 3
I/O
A4
I
10
4
2
R1 0
I/O
A5
I
11
5
3
R1 1
I/O
A6
I
12
6
4
R1 2
I/O
A7
I
13
7
5
R1 3
I/O
A8
I
14
8
6
R2 0
I/O
A0
I
15
9
7
R2 1
I/O
A10
I
16
10
8
R2 2
I/O
A11
I
17
11
9
R2 3
I/O
A12
I
18
12
10
RA 0
I
VCC
19
13
11
RA 1/V disp
I
20
14
12
R3 0
I/O
A13
I
21
15
13
R3 1
I/O
A14
I
22
16
14
R3 2/INT0
I/O
23
17
15
R3 3/INT1
I/O
24
18
16
R5 0
I/O
25
19
17
R5 1
I/O
26
20
18
R5 2
I/O
27
21
19
R5 3
I/O
28
22
20
R6 0
I/O
29
23
21
R6 1
I/O
38
I/O
HD404019R Series
Pin Number
MCU Mode
PROM Mode
DC-64S,
DP-64S
FP-64B
FP-64A
Symbol
I/O
30
24
22
R6 2
I/O
31
25
23
R6 3
I/O
32
26
24
VCC
33
27
25
R4 0/SCK
I/O
O4
I/O
34
28
26
R4 1/SI
I/O
O5
I/O
35
29
27
R4 2/SO
I/O
O6
I/O
36
30
28
R4 3
I/O
O7
I/O
37
31
29
R7 0
I/O
CE
I
38
32
30
R7 1
I/O
OE
I
39
33
31
R7 2
I/O
40
34
32
R7 3
I/O
O4
I/O
41
35
33
R8 0
I/O
O3
I/O
42
36
34
R8 1
I/O
O2
I/O
43
37
35
R8 2
I/O
O1
I/O
44
38
36
R8 3
I/O
O0
I/O
45
39
37
R9 0
I
VPP
46
40
38
R9 1
I
A9
I
47
41
39
R9 2
I
M0
I
48
42
40
R9 3
I
M1
I
49
43
41
RESET
I
RESET
I
50
44
42
TEST
I
TEST
I
51
45
43
OSC 1
I
52
46
44
OSC 2
53
47
45
GND
54
48
46
D0
I/O
O0
I/O
55
49
47
D1
I/O
O1
I/O
56
50
48
D2
I/O
O2
I/O
57
51
49
D3
I/O
O3
I/O
58
52
50
D4
I/O
59
53
51
D5
I/O
Symbol
I/O
VCC
GND
39
HD404019R Series
Pin Number
MCU Mode
PROM Mode
DC-64S,
DP-64S
FP-64B
FP-64A
Symbol
I/O
60
54
52
D6
I/O
61
55
53
D7
I/O
62
56
54
D8
I/O
63
57
55
D9
I/O
64
58
56
D10
I/O
Symbol
I/O
VCC
Notes: 1. I/O: Input/output pins
I:
Input pins
O:
Output pins
2. Connect each pair of O 4, O3, O2, O1, and O 0. Hitachi supplies the socket adapter on which these
pairs are internally connected.
40
HD404019R Series
Programmable ROM Operation
The on-chip PROM of HD4074019 and HD407L4019 are programmed in PROM mode. The PROM mode
is set by pulling TEST, M0, and M1 low, and RESET high as shown in figure 21. In PROM mode, the MCU
does not operate. It can be programmed like a standard 27256 EPROM using a standard PROM
programmer and a 64-to-28-pin socket adapter. Table 24 lists the recommended PROM programmers and
socket adapters.
Since the instruction of the HMCS400 series consists of 10 bits, the HMCS400-series microcom puter
incorporates a conversion circuit used as a general-purpose PROM programmer. By this circuit, an
instruction is read or programmed using 2 addresses, the low-order 5 bits and the high-order 5 bits. For
example, if 8 kwords of an on-chip PROM are programmed by a general purpose PROM programmer, 16
kbytes of addresses ($0000 to $3FFF) should be specified.
Programming and Verification
The HD4074019 and HD407L4019 can be programmed at high-speed without causing voltage stress or
affecting data reliability.
Table 23 shows how programming and verification modes are selected.
Erasing
PROMs with ceramic window packages can be erased by ultraviolet light. All erased bits become 1s.
The erasing specifications are as follows: ultraviolet (UV) light with wavelength 2537 Å with a minimum
irradiation of 15 W sec/cm2. These conditions are satisfied by exposing the LSI to a 12,000-µW/cm2 UV
source for 15 to 20 minutes at a distance of 1 inch.
Precautions
1. Addresses $0000 to $7FFF should be specified if the PROM is programmed by a PROM programmer.
Note that the plastic package type cannot be erased and reprogrammed.
(Only ceramic window packages can be erased and reprogrammed.)
2. Make sure that the PROM programmer, socket adapter, and LSI match properly. Using the wrong
programmer for the socket adapter may cause an overvoltage and damage the LSI. Make sure that the
LSI is firmly fixed in the socket adapter, and that the socket adapter is firmly fixed to the programmer.
3. The PROM should be programmed with VPP = 12.5 V. Other PROMs use 21 V. If 21 V is applied to the
HD4074019 and HD407L4019, the LSI may be permanently damaged. 12.5 V is the voltage for VPP of
Intel’s 27256.
41
HD404019R Series
Table 23
PROM Modes Selection
Pin
Mode
CE
OE
VPP
O0 to O7
Programming
Low
High
VPP
Data input
Verify
High
Low
VPP
Data output
Programming
inhibited
High
High
VPP
High impedance
Table 24
Recommended PROM Programmers and Socket Adapters
PROM Programmer*
Socket Adapter
Maker
Type Name
Package Type
Type Name
Maker
DATA I/O
280
DP-64S
HS409ESS11H
Hitachi
201
DC-64S
29B + UniPak2B
FP-64B
HS409ESF01H
S22
FP-64A
HS409ESH01H
PKW-1000
DP-64S
HS409ESS21H
PKW-1100
DC-64S
PKW-1600
FP-64B
HS409ESF01H
PKW-3100
FP-64A
HS409ESH01H
AVAL DATA Corp.
Hitachi
Note: * Since the address pins of the HD4074019 and HD407L4019 are high voltage pins, errors may
occur in device insertion tests if a PROM programmer other than those listed above is used.
42
HD404019R Series
VCC
VCC
RESET
VCC
TEST
M0
M1
VPP
R90/VPP
O0 to O7
Data
O0 to O7
A0 to A14
Address
A0 to A14
OE
OE
CE
CE
GND
Figure 21 PROM Mode Function Diagram
43
HD404019R Series
Addressing Modes
RAM Addressing Modes
As shown in figure 22, the MCU has three RAM addressing modes: register indirect addressing, direct
addressing, and memory register addressing.
W register
W1 W0
X register
X3
X2
X1
Y register
X0
Y3
Y2
Y1
Y0
RAM address AP9 AP8 AP 7 AP6 AP 5 AP 4 AP 3 AP 2 AP 1 AP 0
Register Indirect Addressing
Instruction 1st word
Instruction 2nd word
Opcode
d9
d8
d7
d6
d5
d4
d3
d2
d1
d0
RAM address AP9 AP8 AP 7 AP6 AP 5 AP 4 AP 3 AP 2 AP 1 AP 0
Direct Addressing
Instruction
Opcode
0
0
0
0
m3 m2 m1
1
m0
0
RAM address AP9 AP8 AP 7 AP6 AP 5 AP 4 AP 3 AP 2 AP 1 AP 0
Memory Register Addressing
Figure 22 RAM Addressing Modes
Register Indirect Addressing Mode: The W register, X register, and Y register contents (10 bits) are
used as the RAM address.
Direct Addressing Mode: A direct addressing instruction consists of two words, with the word (10 bits)
following the opcode used as the RAM address.
Memory Register Addressing Mode: The memory registers (16 digits from $020 to $02F) are accessed
by executing the LAMR and XMRA instructions.
44
HD404019R Series
ROM Addressing Modes and the P Instruction
The MCU has four kinds of ROM addressing modes as shown in figure 23.
[JMPL]
[BRL]
[CALL]
Instruction 1st word
Opcode
p3
Instruction 2nd word
p2
p1
p0
d9
d8
d7
d6
d5
d4
d3
d2
d1
d0
Program counter PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0
Direct Addressing
Instruction
[BR] Opcode
b7
b6
b5
b4
b3
b2
b1
b0
Program counter PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0
Current Page Addressing
Instruction
[CAL]
0
0
0
0
a5
Opcode
0
0
0
a4
a3
a2
a1
a0
0
Program counter PC13 PC12 PC11PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0
Zero Page Addressing
Instruction
[TBR]
Opcode
p3
p2
p1
p0
B register
B3
0
B2
B1
Accumulator
B0 A 3 A 2
A1 A0
0
Program counter PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0
Table Data Addressing
Figure 23 ROM Addressing Modes
45
HD404019R Series
Direct Addressing Mode: The program can branch to any address in ROM memory space by executing
the JMPL, BRL, or CALL instruction. These instructions replace the 14 program counter bits (PC 13 to PC0)
with 14-bit immediate data.
Current Page Addressing Mode: The MCU has 8 pages of ROM with 256 words per page. By executing
the BR instruction, the program can branch to an address on the current page. This instruction replaces the
low-order eight bits of the program counter (PC7 to PC0) with 8-bit immediate data.
When the BR instruction is on a page boundary (256n + 255) (figure 24), executing it transfers the PC
contents to the next page, due to the hardware architecture. Consequently, the program branches to the next
page when the BR instruction is used on a page boundary. The HMCS400-series cross macroassembler has
an automatic paging facility for ROM pages.
Zero-Page Addressing Mode: By executing the CAL instruction, the program can branch to the zero-page
subroutine area, which is located at $0000 to $003F. When the CAL instruction is executed, 6 bits of
immediate data are placed in the low-order six bits of the program counter (PC 5 to PC0) and 0s are placed in
the high-order eight bits (PC13 to PC6).
Table Data Addressing Mode: By executing the TBR instruction, the program can branch to the address
determined by the contents of the 4-bit immediate data, accumulator, and B register.
P Instruction: ROM data addressed by table data addressing can be referenced by the P instruction (figure
25). When bit 8 in the referred ROM data is 1, 8 bits of ROM data are written into the accumulator and B
register. When bit 9 is 1, 8 bits of ROM data are written into the R1 and R2 port output registers. When
both bits 8 and 9 are 1, ROM data are written into the accumulator and B register, and also to the R1 and
R2 port output registers at the same time.
The P instruction has no effect on the program counter.
46
HD404019R Series
BR AAA
256(n – 1) + 255
256n
AAA NOP
BR AAA
BR BBB
256n + 254
256n + 255
256(n + 1)
BBB NOP
Figure 24 BR Instruction Branch Destination on a Page Boundary
47
HD404019R Series
Instruction
[P]
Opcode
p3
0
p2
p1
p0
B register
B3
0
B2
B1
Accumulator
B0
A3
A2
A1
A0
Referred ROM address RA13 RA12 RA11 RA10 RA 9 RA 8 RA 7 RA 6 RA 5 RA 4 RA 3 RA 2 RA 1 RA 0
Address Designation
ROM data
RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0
Accumulator, B register
ROM data
B3 B2
B1
B0
A3
A2
A1
A 0 If RO 8 = 1
RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0
Output registers R1, R2 R23 R2 2 R21 R2 0 R13 R12 R11 R10 If RO 9 = 1
Pattern
Figure 25 P Instruction
48
HD404019R Series
Absolute Maximum Ratings
Item
Symbol
Value
Unit
Notes
Supply voltage
VCC
–0.3 to +7.0
V
Programming voltage
VPP
–0.3 to +14
V
10
Pin voltage
VT
–0.3 to VCC + 0.3
V
1
VCC – 45 to VCC + 0.3
V
2
Total permissible input current
∑Io
50
mA
3
Maximum input current
Io
15
mA
5, 6
Maximum output current
–I o
4
mA
6, 7
6
mA
7, 8
30
mA
7, 9
4
Total permissible output current
–∑Io
150
mA
Operating temperature
Topr
–20 to +75
°C
Storage temperature
Tstg
–55 to +125
°C
Notes: Permanent damage may occur if these absolute maximum ratings are exceeded. Normal operation
should be under the conditions of the electrical characteristics. If these conditions are exceeded, it
may cause a malfunction or affect the reliability of the LSI.
All voltages are with respect to GND.
1. Standard pins.
2. High voltage pins.
3. Total permissible input current is the total sum of input currents which flow in from all I/O pins to
GND simultaneously.
4. Total permissible output current is the total sum of the output currents which flow out from VCC to
all I/O pins simultaneously.
5. Maximum input current is the maximum amount of input current from each I/O pin to GND.
6. D0 to D3 and R3 to R8.
7. Maximum output current is the maximum amount of output current from VCC to each I/O pin.
8. R0 to R2.
9. D4 to D15 .
10. Applied to HD4074019 and HD407L4019.
49
HD404019R Series
Electrical Characteristics
DC Characteristics
(HD404019R: V CC = 3.5 V to 6 V, GND = 0 V, Vdisp = VCC – 40 V to VCC, Ta = –20°C to +75°C
HD40L4019R: VCC = 2.7 V to 6 V, GND = 0 V, Vdisp = VCC – 40 V to VCC, Ta = –20°C to +75°C
HD4074019: VCC = 4.5 V to 5.5 V, GND = 0 V, Vdisp = VCC – 40 V to VCC, Ta = –20°C to +75°C
HD407L4019: VCC = 3.0 V to 5.5 V, GND = 0 V, Vdisp = VC C – 40 V to V CC , Ta = –20°C to +75°C
unless otherwise specified)
Item
Symbol Pin
Input high
voltage
VIH
VCC + 0.3 V
HD404019R, HD4074019
0.9 VCC
—
VCC + 0.3 V
HD40L4019R
0.8 VCC
—
VCC + 0.3 V
HD407L4019: VCC = 4.5 V to 5.5 V
0.9 VCC
—
VCC + 0.3 V
HD407L4019
0.7 VCC
—
VCC + 0.3 V
HD404019R, HD4074019
0.8 VCC
—
VCC + 0.3 V
HD40L4019R
0.7 VCC
—
VCC + 0.3 V
HD407L4019: VCC = 4.5 V to 5.5 V
0.9 VCC
—
VCC + 0.3 V
HD407L4019
VCC –0.5
—
VCC + 0.3 V
HD404019R, HD4074019,
HD407L4019
VCC –0.3
—
VCC + 0.3 V
HD40L4019R
RESET, –0.3
SCK,
INT0, INT1
—
0.2 VCC
V
HD404019R, HD4074019
–0.3
—
0.1 VCC
V
HD40L4019R
–0.3
—
0.2 VCC
V
HD407L4019: VCC = 4.5 V to 5.5 V
–0.3
—
0.1 VCC
V
HD407L4019
–0.3
—
0.3 VCC
V
HD404019R, HD4074019
–0.3
—
0.2 VCC
V
HD40L4019R
–0.3
—
0.3 VCC
V
HD407L4019: VCC = 4.5 V to 5.5 V
–0.3
—
0.1 VCC
V
HD407L4019
–0.3
—
0.5
V
HD404019R, HD4074019,
HD407L4019
–0.3
—
0.3
V
HD40L4019R
SCK, SO VCC –1.0
—
—
V
–I OH = 1.0 mA
VCC –0.5
—
—
V
–I OH = 0.5 mA
SI
Input low
voltage
VIL
Output high VOH
voltage
50
Unit Test Conditions
—
OSC 1
VIL
Typ Max
RESET, 0.8 VCC
SCK,
INT0, INT1
SI
Input low
voltage
Min
OSC 1
Note
HD404019R Series
Item
Symbol
Pin
Min Typ
Max Unit Test Conditions
Notes
Output low
voltage
VOL
SCK, SO
—
—
0.4
V
I OL = 1.6 mA
Input/output
leakage
current
| IIL |
RESET,
—
SCK, INT0,
INT1, SI,
SO, OSC 1
—
1
µA
Vin = 0 V to VCC
1
Current
dissipation in
active mode
I CC
VCC
—
—
8.0
mA
HD404019R, HD4074019:
VCC = 5 V, fOSC = 4 MHz, divide by 4
2
—
—
8.0
mA
HD40L4019R, HD407L4019:
VCC = 5 V, fOSC = 4 MHz, divide by 4
2
—
—
3.0
mA
HD40L4019R, HD407L4019:
VCC = 3 V,
f OSC = 3.58 MHz, divide by 4
2
3
Current
dissipation in
standby mode
I SBY
VCC
—
—
2.0
mA
VCC = 5 V, fOSC = 4 MHz, divide by 4
Current
dissipation in
stop mode
I STOP
VCC
—
—
10
µA
HD404019R, HD40L4019R:
4
Vin (TEST, R9 0) = VCC – 0.3 V to VCC,
Vin (RESET) = 0 V to 0.3 V
—
—
10
µA
HD4074019, HD407L4019:
Vin (TEST, R9 0) = VCC – 0.3 V to VCC,
Vin (RESET) = 0 V to 0.3 V
2
—
—
V
Stop mode
retaining
voltage
VSTOP
VCC
Notes: 1. Excluding pull-up MOS current and output buffer current (HD404019R, HD40L4019R) Excluding
output buffer current (HD4074019, HD407L4019)
2. The MCU is in the reset state. Input/output current does not flow.
• MCU in reset state, operation mode
• RESET, TEST: VCC
• D0 to D3, R3 to R9: V CC
• D4 to D15 , R0 to R2, RA0, RA 1: Vdisp
3. The timer/counter operates with the fastest clock. Input/output current does not flow.
• MCU in standby mode
• Input/output in reset state
• Serial interface: stop
• RESET: GND
• TEST: VCC
• D0 to D3, R3 to R9: V CC
• D4 to D15 , R0 to R2, RA0, RA 1: Vdisp
4. Excluding pull-down MOS current.
51
HD404019R Series
Input/Output Characteristics for Standard Pins
(HD404019R: V CC = 3.5 V to 6 V, GND = 0 V, Vdisp = VCC – 40 V to VCC, Ta = –20°C to +75°C
HD40L4019R: VCC = 2.7 V to 6 V, GND = 0 V, Vdisp = VCC – 40 V to VCC, Ta = –20°C to +75°C
HD4074019: VCC = 4.5 V to 5.5 V, GND = 0 V, Vdisp = VCC – 40 V to VCC, Ta = –20°C to +75°C
HD407L4019: VCC = 3.0 V to 5.5 V, GND = 0 V, Vdisp = VC C – 40 V to V CC , Ta = –20°C to +75°C
unless otherwise specified)
Item
Symbol
Pin
Min
Typ
Max
Unit Test Conditions
Input high
voltage
VIH
D0 to D3,
R3 to R9
0.7 VCC
—
VCC + 0.3 V
HD404019R, HD4074019
0.8 VCC
—
VCC + 0.3 V
HD40L4019R
0.7 VCC
—
VCC + 0.3 V
Note
HD407L4019:
VCC = 4.5 V to 5.5 V
Input low
voltage
VIL
D0 to D3,
R3 to R9
0.8 VCC
—
VCC + 0.3 V
HD407L4019
–0.3
—
0.3 VCC
V
HD404019R, HD4074019
–0.3
—
0.2 VCC
V
HD40L4019R
–0.3
—
0.3 VCC
V
HD407L4019:
VCC = 4.5 V to 5.5 V
–0.3
Output high VOH
voltage
D0 to D3,
R3 to R8
—
VCC – 1.0 —
0.2 VCC
V
HD407L4019
—
V
HD404019R, HD40L4019R: 1
–I OH = 1.0 mA
VCC – 0.5 —
—
V
HD404019R, HD40L4019R: 1
–I OH = 0.5 mA
Output low VOL
voltage
D0 to D3,
R3 to R8
—
—
0.4
V
I OL = 1.6 mA
Input/output | IIL |
leakage
current
D0 to D3,
R3 to R9
—
—
1
µA
HD404019R, HD40L4019R: 2
Pull-up
MOS
current
Notes: 1.
2.
3.
4.
52
–I PU
Vin = 0 V to VCC
1
µA
D0 to D3,
—
R3 to R8,
R9 1 to R93
—
R9 0
—
—
20
µA
D0 to D3,
R3 to R9
30
—
150
µA
HD4074019, HD407L4019:
3
Vin = 0 V to VCC
HD404019R, HD40L4019R: 4
VCC = 5 V, Vin = 0 V
Applied to I/O pins selected as CMOS output by mask option.
Excluding pull-up MOS current and output buffer current.
Excluding output buffer current.
Applied to I/O pins selected as with pull-up MOS by mask option.
HD404019R Series
Input/Output Characteristics for High Voltage Pins
(HD404019R: V CC = 3.5 V to 6 V, GND = 0 V, Vdisp = VCC – 40 V to VCC, Ta = –20°C to +75°C
HD40L4019R: VCC = 2.7 V to 6 V, GND = 0 V, Vdisp = VCC – 40 V to VCC, Ta = –20°C to +75°C
HD4074019: VCC = 4.5 V to 5.5 V, GND = 0 V, Vdisp = VCC – 40 V to VCC, Ta = –20°C to +75°C
HD407L4019: VCC = 3.0 V to 5.5 V, GND = 0 V, Vdisp = VC C – 40 V to V CC , Ta = –20°C to +75°C
unless otherwise specified)
Item
Symbol
Pin
Min
Typ Max
Unit Test Conditions
Input high
voltage
VIH
D4 to D15 ,
R0 to R2,
RA 0, RA 1
0.7 VCC
—
VCC + 0.3 V
HD404019R, HD4074019
0.8 VCC
—
VCC + 0.3 V
HD40L4019R:
Note
VCC = 3.5 V to 6.0 V
0.7 VCC
—
VCC + 0.3 V
HD407L4019:
VCC = 4.5 V to 5.5 V
Input low
voltage
VIL
D4 to D15 ,
R0 to R2,
RA 0, RA 1
0.8 VCC
—
VCC + 0.3 V
HD407L4019
VCC – 40
—
0.3 VCC
V
HD404019R, HD4074019
VCC – 40
—
0.2 VCC
V
HD40L4019R:
VCC = 3.5 V to 6.0 V
VCC – 40
—
0.3 VCC
V
HD407L4019:
VCC = 4.5 V to 5.5 V
VCC – 40
Output high
voltage
VOH
—
D4 to D15 VCC – 3.0 —
0.2 VCC
V
HD407L4019
—
V
HD404019R, HD40L4019R:
–I OH = 15 mA,
VCC = 5 V ± 20%
VCC – 2.0 —
—
V
HD404019R, HD40L4019R:
–I OH = 10 mA,
VCC = 5 V ± 20%
VCC – 1.0 —
—
V
HD404019R, HD40L4019R:
–I OH = 4 mA
VCC – 3.0 —
—
V
HD4074019: –I OH = 15 mA
VCC – 2.0 —
—
V
HD4074019: –I OH = 10 mA
VCC – 1.0 —
—
V
HD4074019: –I OH = 4 mA
VCC – 3.0 —
—
V
HD407L4019: –I OH = 15 mA,
VCC = 4.5 V to 5.5 V
VCC – 2.0 —
—
V
HD407L4019: –I OH = 10 mA
VCC – 1.0 —
—
V
HD407L4019: –I OH = 4 mA
53
HD404019R Series
Item
Symbol
Output high VOH
voltage
Pin
Min
Typ Max
Unit Test Conditions
R0 to R2
VCC – 3.0
—
V
—
Note
HD404019R, HD40L4019R:
–I OH = 3 mA, VCC = 5 V ± 20%
VCC – 2.0
—
—
V
HD404019R, HD40L4019R:
–I OH = 2 mA, VCC = 5 V ± 20%
VCC – 1.0
—
—
V
HD404019R, HD40L4019R:
–I OH = 0.8 mA
VCC – 3.0
—
—
V
HD4074019: –I OH = 3 mA
VCC – 2.0
—
—
V
HD4074019: –I OH = 2 mA
VCC – 1.0
—
—
V
HD4074019: –I OH = 0.8 mA
VCC – 3.0
—
—
V
HD407L4019: –I OH = 3 mA,
VCC = 4.5 V to 5.5 V
Output low VOL
voltage
D4 to D15 ,
VCC – 2.0
—
—
V
HD407L4019: –I OH = 2 mA
VCC – 1.0
—
—
V
HD407L4019: –I OH = 0.8 mA
—
—
VCC – 37 V
HD404019R, HD40L4019R:
1
Vdisp = VCC – 40 V
R0 to R2
—
—
VCC – 37 V
HD404019R, HD40L4019R:
2
150 kΩ at V CC – 40 V
—
—
VCC – 37 V
HD4074019, HD407L4019:
150 kΩ at V CC – 40 V
Input/output | IIL |
leakage
current
D4 to D15 ,
—
—
20
µA
HD404019R, HD40L4019R:
3
Vin = VCC – 40 V to VCC
R0 to R2,
RA 0, RA 1
—
—
20
µA
HD4074019, HD407L4019:
4
Vin = VCC – 40 V to VCC
Pull-down
MOS
current
Notes: 1.
2.
3.
4.
54
I PD
D4 to D15 ,
R0 to R2,
125
—
900
µA
HD404019R, HD40L4019R:
Vdisp = VCC – 35 V, Vin = VCC
RA 0, RA 1
Applied to I/O pins selected as with pull-up MOS by mask option.
Applied to I/O pins selected as with pull-up MOS (PMOS open drain) by mask option.
Excluding pull-down MOS current and output buffer current.
Excluding output buffer current.
1
HD404019R Series
AC Characteristics
(HD404019R: V CC = 3.5 V to 6 V, GND = 0 V, Vdisp = VCC – 40 V to VCC, Ta = –20°C to +75°C
HD40L4019R: VCC = 2.7 V to 6 V, GND = 0 V, Vdisp = VCC – 40 V to VCC, Ta = –20°C to +75°C
HD4074019: VCC = 4.5 V to 5.5 V, GND = 0 V, Vdisp = VCC – 40 V to VCC, Ta = –20°C to +75°C
HD407L4019: VCC = 3.0 V to 5.5 V, GND = 0 V, Vdisp = VC C – 40 V to V CC , Ta = –20°C to +75°C
unless otherwise specified)
Item
Symbol
Pin
Min
Typ
Max
Unit
Test Conditions
Oscillation
frequency
f OSC
OSC 1,
OSC 2
0.4
4
4.5
MHz
HD404019R: divide by 4
0.4
4
4.5
MHz
HD40L4019R:
Note
VCC = 3.5 V to 6.0 V, divide by 4
0.4
—
3.58
MHz
HD40L4019R: divide by 4
0.2
4
4.5
MHz
HD4074019: divide by 4
0.2
4
4.5
MHz
HD407L4019:
VCC = 4.5 V to 5.5 V, divide by 4
Instruction
cycle time
t cyc
0.2
—
3.58
MHz
HD407L4019
0.89
1
20
µs
HD404019R
0.89
1
10
µs
HD40L4019R:
VCC = 3.5 V to 6.0 V
1.12
—
10
µs
HD40L4019R
0.89
1
20
µs
HD4074019: divide by 4
0.89
1
20
µs
HD407L4019:
VCC = 4.5 V to 5.5 V, divide by 4
Oscillation
stabilization
time
t RC
OSC 1,
OSC 2
1.12
—
20
µs
HD407L4019
—
—
20
ms
HD404019R, HD4074019
1
—
—
20
ms
HD40L4019R:
1
VCC = 3.5 V to 6.0 V
—
—
40
ms
HD40L4019R
1
—
—
20
ms
HD407L4019:
1
VCC = 4.5 V to 5.5 V
—
—
40
ms
HD407L4019
1
Notes: 1. The oscillator stabilization time is the period from when VCC reaches its minimum allowable
voltage (HD404019R/HD40L4019R: 3.5 V, HD4074019: 4.5 V, HD407L4019: 3.0 V (3.5 V when
VCC = 3.5 V to 6.0 V)) at power-on until when the oscillator stabilizes, or after RESET goes high
by MCU reset to quit stop mode. At power-on or when recovering from stop mode, apply the
RESET input for more than tRC to meet the necessary time for oscillator stabilization. When using
a crystal or ceramic oscillator, consult with the crystal oscillator manufacturer since the oscillator
stabilization time depends on the circuit constants and stray capacitance. (See figure 26.)
55
HD404019R Series
Item
Symbol
Pin
Min
Typ
Max
Unit
Test Conditions
Note
External clock
high width
t CPH
OSC 1
92
—
—
ns
HD404019R, HD4074019:
divide by 4
1
92
—
—
ns
HD40L4019R:
1
VCC = 3.5 V to 6.0 V, divide by 4
120
—
—
ns
HD40L4019R: divide by 4
1
92
—
—
ns
HD407L4019:
1
VCC = 4.5 V to 5.5 V, divide by 4
External clock
low width
t CPL
OSC 1
115
—
—
ns
HD407L4019
1
92
—
—
ns
HD404019R, HD4074019:
divide by 4
1
92
—
—
ns
HD40L4019R:
1
VCC = 3.5 V to 6.0 V, divide by 4
120
—
—
ns
HD40L4019R: divide by 4
1
92
—
—
ns
HD407L4019:
1
VCC = 4.5 V to 5.5 V, divide by 4
115
—
—
ns
HD407L4019
1
External clock
rise time
t CPr
OSC 1
—
—
20
ns
1
External clock
fall time
t CPf
OSC 1
—
—
20
ns
1
INT0 high width t IH
INT0
2
—
—
t cyc
2
INT0 low width
t IL
INT0
2
—
—
t cyc
2
INT1 high width t IH
INT1
2
—
—
t cyc
2
INT1 low width
t IL
INT1
2
—
—
t cyc
2
RESET high
width
t RSTH
RESET
2
—
—
t cyc
3
Input
capacitance
Cin
All pins
—
—
30
pF
RESET fall
time
f = 1 MHz, Vin = 0 V
t RSTf
Notes: 1. See figure 26.
2. See figure 27.
3. See figure 28.
56
HD404019R, HD40L4019R:
All pins
—
except R9 0
—
30
pF
R9 0
—
—
180
pF
—
—
20
ms
HD4074019, HD407L4019:
f = 1 MHz, Vin = 0 V
3
HD404019R Series
Serial Interface Timing Characteristics
(HD404019R: V CC = 3.5 V to 6 V, GND = 0 V, Vdisp = VCC – 40 V to VCC, Ta = –20°C to +75°C
HD40L4019R: VCC = 2.7 V to 6 V, GND = 0 V, Vdisp = VCC – 40 V to VCC, Ta = –20°C to +75°C
HD4074019: VCC = 4.5 V to 5.5 V, GND = 0 V, Vdisp = VCC – 40 V to VCC, Ta = –20°C to +75°C
HD407L4019: VCC = 3.0 V to 5.5 V, GND = 0 V, Vdisp = VC C – 40 V to V CC , Ta = –20°C to +75°C
unless otherwise specified)
Item
Symbol
Pin
Min
Typ
Max
Unit
Test Conditions
Notes
Transmit clock t Scyc
cycle time
SCK output
1
—
—
t cyc
Load shown in figure 30
1, 2
Transmit clock t SCKH
high widths
SCK output
0.4
—
—
t cyc
1, 2
Transmit clock t SCKL
low widths
SCK output
0.4
—
—
t cyc
1, 2
Transmit clock t SCKr
rise time
SCK output
—
—
40
ns
HD404019R, HD4074019,
HD407L4019
1, 2
—
—
40
ns
HD40L4019R:
1, 2
VCC = 3.5 V to 6.0 V
Transmit clock t SCKf
fall time
SCK output
—
—
200
ns
HD40L4019R
1, 2
—
—
40
ns
HD404019R, HD4074019,
HD407L4019
1, 2
—
—
40
ns
HD40L4019R:
1, 2
VCC = 3.5 V to 6.0 V
—
—
200
ns
HD40L4019R
1, 2
Transmit clock t Scyc
cycle time
SCK input
1
—
—
t cyc
1
Transmit clock t SCKH
high width
SCK input
0.4
—
—
t cyc
1
Transmit clock t SCKL
low width
SCK input
0.4
—
—
t cyc
1
Transmit clock t SCKHD
completion
detect time
SCK input
1
—
—
t cyc
3
Transmit clock t SCKr
rise time
SCK input
—
—
40
ns
1
Transmit clock t SCKf
fall time
SCK input
—
—
40
ns
1
Notes: 1. See figure 29.
2. See figure 30.
3. Transmit clock completion detect time is the high level period after 8 pulses of transmit clock are
input. The serial interrupt request flag is not set when the next transmit clock is input before the
transmit clock completion detect time has passed.
57
HD404019R Series
Item
Symbol
Serial output
t DSO
data delay time
Pin
Min
Typ
Max
Unit
Test Conditions
Notes
SO
—
—
300
ns
HD404019R
1, 2
—
—
300
ns
HD40L4019R:
1, 2
VCC = 3.5 V to 6.0 V
—
—
500
ns
HD40L4019R
1, 2
—
—
200
ns
HD4074019
1, 2
—
—
200
ns
HD407L4019:
1, 2
VCC = 4.5 V to 5.5 V
Serial input
t SSI
data setup time
SI
—
—
400
ns
HD407L4019
1, 2
100
—
—
ns
HD404019R
1
100
—
—
ns
HD40L4019R:
1
VCC = 3.5 V to 6.0 V
Serial input
t SSI
data setup time
Serial input
data hold time
t HSI
SI
SI
300
—
—
ns
HD40L4019R
1
200
—
—
ns
HD4074019, HD407L4019
1
200
—
—
ns
HD404019R
1
200
—
—
ns
HD40L4019R:
1
VCC = 3.5 V to 6.0 V
400
—
—
ns
HD40L4019R
1
100
—
—
ns
HD4074019
1
100
—
—
ns
HD407L4019:
1
VCC = 4.5 V to 5.5 V
200
Notes: 1. See figure 29.
2. See figure 30.
58
—
—
ns
HD407L4019
1
HD404019R Series
HD404019R
HD4074019
HD407L4019
1/fCP
VCC – 0.5
tCPH
0.5
tCPr
tCPL
tCPf
HD40L4019R
1/fCP
VCC – 0.3
tCPH
0.3
tCPr
tCPL
tCPf
Figure 26 Oscillator Timing
HD404019R
HD4074019
HD407L4019 (VCC = 4.5 V to 5.5 V)
INT0, INT1
0.8 VCC
0.2 VCC
tIH
tIL
tIH
tIL
HD40L4019R
HD407L4019 (VCC = 3.0 V to 4.5 V)
INT0, INT1
0.9 VCC
0.1 VCC
Figure 27 Interrupt Timing
HD404019R
HD4074019
HD407L4019 (VCC = 4.5 V to 5.5 V)
RESET
0.8 VCC
0.2 VCC
tRSTH
tRSTf
HD40L4019R
HD407L4019 (VCC = 3.0 V to 4.5 V)
RESET
0.9 VCC
0.1 VCC
tRSTH
tRSTf
Figure 28 Reset Timing
59
HD404019R Series
HD404019R
HD4074019
HD407L4019 (VCC = 4.5 V to 5.5 V)
tScyc
tSCKf
SCK
VCC – 2.0 V (0.8 VCC)*
0.8 V (0.2 VCC)*
tSCKr
tSCKL
tSCKHD
tSCKH
tDSO
VCC – 2.0 V
SO
0.8 V
tSSI
tHSI
0.7 VCC
0.3 VCC
SI
Note: * VCC – 2.0 V and 0.8 V are the threshold voltages for transmit clock output.
0.8 VCC and 0.2 VCC are the threshold voltages for transmit clock input.
HD40L4019R
HD407L4019 (VCC = 3.0 V to 4.5 V)
tScyc
tSCKf
SCK
VCC – 2.0 V (0.9
0.8 V (0.1
VCC)*
VCC)*
tSCKr
tSCKL
tSCKHD
tSCKH
tDSO
VCC – 2.0 V
SO
0.8 V
tSSI
tHSI
0.7 VCC
0.3 VCC
SI
Note: * VCC – 2.0 V and 0.8 V are the threshold voltages for transmit clock output.
0.9 VCC and 0.1 VCC are the threshold voltages for transmit clock input.
Figure 29 Timing of Serial Interface
VCC
RL = 2.6 kΩ
Test
point
C
30 pF
R
12 kΩ
1S2074 H
or equivalent
Figure 30 Timing Load Circuit
60
HD404019R Series
HD404019R Option List
Date of order
Customer
Please check off the appropriate applications and enter
the necessary information.
Dept.
Name
5 V operation: HD404019R
ROM code name
Low-voltage operation: HD40L4019R
LSI type number
(Hitachi's entry)
Note: I/O options masked by
1. I/O option
R1
R2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Pin
E
R3
R4
R5
R6
R7
R8
R9
RA
R30
R31
R32
R33
R40
R41
R42
R43
R50
R51
R52
R53
R60
R61
R62
R63
R70
R71
R72
R73
R80
R81
R82
R83
R90
R91
R92
R93
RA0
RA1
I/O
Standard pins
High voltage pins
A
High
voltage
pins
R0
R00
R01
R02
R03
R10
R11
R12
R13
R20
R21
R22
R23
High voltage pins
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
I/O
Standard
pins
Pin
I/O option
B C D
A
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
are not available.
I/O option
B C D
E
Please mark on RA1/Vdisp
A: Without pull-up MOS (NMOS open drain)
B: With pull-up MOS
C: CMOS (not be used as input)
D: Without pull-down MOS (PMOS open drain)
E: With pull-down MOS
61
HD404019R Series
HD404019R Option List
2. RA1/Vdisp
RA1: Without pull-down MOS (D)
3. Divider (DIV)
Divide by 4
Vdisp
Note: If even one high-voltage pin is selected with
I/O option E, pin RA1/Vdisp must be selected
to function as Vdisp.
4. ROM code media
Please specify the first type below (the upper bits and lower bits are mixed together), when using the
EPROM on-package microcomputer type (including ZTATTM version).
EPROM: The upper bits and lower bits are mixed together. The upper five bits and lower five bits are
programmed to the same EPROM in alternating order (i.e., LULULU...).
EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are
programmed to different EPROMS.
5. System oscillator (OSC1 and OSC2)
Ceramic oscillator
Crystal oscillator
External clock
6. Stop mode
Used
Not used
7. Package
HD404019R
DP-64S
FP-64A
FP-64A
FP-64B
62
HD40L4019R
DP-64S
HD404019R Series
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
63