Sitronix ST7063C

ST
Sitronix
ST7063C
80CH Segment Driver for Dot Matrix LCD
!"Functions
!"Features
#"Dot matrix LCD driver with two 40 channel
#"Display driving bias : static to 1/5
#"Power supply for logic : 2.7V ~ 5.5V
#"Power supply for LCD voltage (VDD~VEE) :
outputs
#"Bias voltage (V1 ~ V4)
#"input/output signals
3V ~ 11V
!"Input : Serial display data and control
100 Pin QFP package and bare chip available
pulse from controller IC
!"Output : 40 X 2 channels waveform for
LCD driving
!"Description
ST7063CC is a segment driver for dot matrix type
waveforms to the LCD panel. The ST7063C is
LCD display. It features 80 channels with 40 X 2
designed for general purpose LCD drivers. It can
bits bi-directional shift registers, data latches,
drive both static and dynamic drive LCD. The LSI
LCD drivers and logic control circuits. It is
can be used as segment driver.
fabricated by high voltage CMOS process with
The ST7063C has pin function compatibility with
low current consumption.
the KS0063(B) that allows the user to easily
The ST7063C can convert serial data received
replace it with an ST7063C.
from an LCD controller, such as ST7066U, into
parallel
V1.3
data
and
send
out
LCD
driving
1/12
2001/05/04
ST7063C
ST7063C Specification Revision Hist
History
ory
Version
V1.3
Date
Description
1.1
2000/07/31 First Edition
1.2
2000/11/14 Added QFP Pad Configuration(Page 6)
1.2a
2001/02/26 Changed Application Circuit(Page 11)
1.3
2001/05/04
1.
2.
ST7063 Transition to ST7063C
Moved QFP Package Dimensions Page 12 to Page 5
2/12
2001/05/04
ST7063C
!"Functional Block Diagram
V1
V2
V3
V4
M
CL1
CL2
S1...............................S40
S41...............................S80
SEGMENT DRIVER
SEGMENT DRIVER
VDD
VSS
VEE
DATA LATCH(40bits)
DATA LATCH(40bits)
BIDIRECTIONAL
SHIFTER(40bits)
BIDIRECTIONAL
SHIFTER(40bits)
CONTOL
DL1 SHL1 DR1
V1.3
DL2 SHL2 DR2
3/12
2001/05/04
ST7063C
!"Pad Arrangement
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
76
79
47
77
80
46
78
81
45
40
82
"G7063" Marking : Easy to find the PAD
29
44
22
83
(0,0)
21
43
6
7
8
14
15
16
17
18
PAD Size : 90x90μm
13
19
Min. PAD Pitch : 120μm
Coordinate : center
Size : 3800x2600μm
20
84
12
42
11
85
10
41
9
86
87
Circle here to find the first PAD
5
23
24
25
26
27
28
G793E
30
31
32
33
34
35
36
37
39
4
88
3
38
2
89
90
91
92
93
94
95
96
1
2001/05/04
4/12
V1.3
ST7063C
!"Package Dimensions
V1.3
5/12
2001/05/04
ST7063C
!"Pin Configuration(QFP 100)
S
3
1
S
3
2
S
3
3
S
3
4
S
3
5
S
3
6
S
3
7
S
3
8
S
3
9
S
4
0
S
8
0
S
7
9
S
7
8
S
7
7
S
7
6
S
7
5
S
7
4
S
7
3
S
7
2
S
7
1
1
0
0
9
9
9
8
9
7
9
6
9
5
9
4
9
3
9
2
9
1
9
0
8
9
8
8
8
7
8
6
8
5
8
4
8
3
8
2
8
1
80
S70
79
S69
3
78
S68
S27
4
77
S67
S26
5
76
S66
S25
6
75
S65
S24
7
74
S64
S23
8
73
S63
S22
9
72
S62
S21
10
71
S61
S20
11
70
S60
S19
12
69
S59
S18
13
68
S58
S17
14
67
S57
S16
15
66
S56
S15
16
65
S55
S14
17
64
S54
S13
18
63
S53
S12
19
62
S52
S11
20
61
S51
S10
21
60
S50
S09
22
59
S49
S08
23
58
S48
S07
24
57
S47
S06
25
56
S46
S05
26
55
S45
S04
27
54
S44
S03
28
53
S43
S02
29
52
S42
S01
30
51
S41
S30
1
S29
2
S28
V1.3
3
1
3
2
3
3
3
4
3
5
3
6
3
7
3
8
3
9
4
0
4
1
4
2
4
3
4
4
4
5
4
6
4
7
4
8
4
9
5
0
V
E
E
V
1
V
2
V
3
V
4
V
S
S
C
L
1
S
H
L
1
S
H
L
2
N
C
N
C
V
D
D
C
L
2
D
L
1
D
R
1
D
L
2
D
R
2
M N
C
N
C
6/12
2001/05/04
ST7063C
!"Pad Name and Coordinates
Pad No.
1
Pad
X
Y
Name
S42 -1760 -1160
33
Pad
Name
S74
1760 -780
Pad No.
X
Y
65
Pad
Name
S15
-180 1160
Pad No.
X
Y
2
S43
-1630 -1160
34
S75
1760 -660
66
S14
-300 1160
3
S44
-1500 -1160
35
S76
1760 -540
67
S13
-420 1160
4
S45
-1380 -1160
36
S77
1760 -420
68
S12
-540 1160
5
S46
-1260 -1160
37
S78
1760 -300
69
S11
-660 1160
6
S47
-1140 -1160
38
S79
1760 -180
70
S10
-780 1160
7
S48
-1020 -1160
39
S80
1760 -60
71
S9
-900 1160
8
S49
-900 -1160
40
S40
1760
60
72
S8
-1020 1160
9
S50
-780 -1160
41
S39
1760 180
73
S7
-1140 1160
10
S51
-660 -1160
42
S38
1760 300
74
S6
-1260 1160
11
S52
-540 -1160
43
S37
1760 420
75
S5
-1380 1160
12
S53
-420 -1160
44
S36
1760 540
76
S4
-1500 1160
13
S54
-300 -1160
45
S35
1760 660
77
S3
-1630 1160
14
S55
-180 -1160
46
S34
1760 780
78
S2
-1760 1160
15
S56
-60 -1160
47
S33
1760 900
79
S1
-1760 1030
16
S57
60
-1160
48
S32
1760 1030
80
VEE
-1760 900
17
S58
180 -1160
49
S31
1760 1160
81
V1
-1760 780
18
S59
300 -1160
50
S30
1630 1160
82
V2
-1760 660
19
S60
420 -1160
51
S29
1500 1160
83
V3
-1760 540
20
S61
540 -1160
52
S28
1380 1160
84
V4
-1760 420
21
S62
660 -1160
53
S27
1260 1160
85
VSS
-1760 300
22
S63
780 -1160
54
S26
1140 1160
86
CL1
-1760 180
23
S64
900 -1160
55
S25
1020 1160
87
SHL1 -1760 60
24
S65
1020 -1160
56
S24
900 1160
88
SHL2 -1760 -60
25
S66
1140 -1160
57
S23
780 1160
89
VDD
-1760 -180
26
S67
1260 -1160
58
S22
660 1160
90
CL2
-1760 -300
27
S68
1380 -1160
59
S21
540 1160
91
DL1
-1760 -420
28
S69
1500 -1160
60
S20
420 1160
92
DR1
-1760 -540
29
S70
1630 -1160
61
S19
300 1160
93
DL2
-1760 -660
30
S71
1760 -1160
62
S18
180 1160
94
DR2
-1760 -780
31
S72
1760 -1030
63
S17
60
1160
95
M
-1760 -900
32
S73
1760 -900
64
S16
-60
1160
96
S41
-1760 -1030
V1.3
7/12
2001/05/04
ST7063C
!"Pin Description
V1.3
Pin Name
Purpose
Description
I/O
VDD
POWER
for logic
N/A
VSS
GROUND
for logic
N/A
VEE
LCD GND
for LCD driving voltage
N/A
V1 V2
LCD output
used as select voltage level
I
V3 V4
LCD output
used as non select voltage level
I
S1-S40
segment
LCD driver output for part 1
O
SHL1
direction
direction control for part 1 segments
I
DL1, DR1
data in /out
If SHL1 = 1 then DL1=out, DR1=in
If SHL1 = 0 then DL1=in, DR1=out
I/O
S41-S80
segment
LCD driver output for part 2
O
SHL2
direction
direction control for part 2 segments
I
DL2, DR2
data in/out
If SHL2 = 1 then DL2=out, DR2=in
If SHL2 = 0 then DL2=in, DR2=out
I/O
M
alternation
Alternate the LCD driving waveform
I
CL1
latch clock
latch the data after shift is completed
I
CL2
shift clock
shift the data into the segments
I
8/12
2001/05/04
ST7063C
!"Functional Description
Clock
The CL1 is the clock to latch data on the falling edge. It latches the data input from
the bi-directional shift register at the falling edge of CL1 and transfers its outputs to
the LCD driver circuit. The CL2 is the clock to shift data on the falling edge. It shifts
the serial data at the falling of CL2 and transfers the output of each bit of the register
to the latch circuit.
Shift Registers And Data I/O
The ST7063C supplies two sets of 40-bit shift register, which controls the shift
direction by SHL1 & SHL2. The SHL1 controls the 1st 40-bit shift register, and SHL2
controls the 2nd 40-bit shift register. When SHL1 is connected to VDD, the 1st shift
direction is from S40 to S1; when SHL1 is connected to VSS, the shift direction
changes from S1 to S40. When SHL2 is connected to VDD, the 2nd shift direction is
from S80 to S41; when SHL2 is connected to VSS, the shift direction changes from
S41 to S80.
The DL1, DR1, DL2, DR2 are data input or output option function.
Shift Direction of Channel 1
SHL1
Shift Direction
DL1
DR1
0
S1 $ S40
IN
OUT
1
S40 $ S1
OUT
IN
Shift Direction of Channel 2
V1.3
SHL2
Shift Direction
DL2
DR2
0
S41 $ S80
IN
OUT
1
S80 $ S41
OUT
IN
9/12
2001/05/04
ST7063C
!"LCD Output Waveforms
Output of LATCH
(DATA)
M
V2
V2
V4
Output
(S1 ~ S80)
V4
V3
V3
V1
V1
!"Timing Characteristics
TWCKL
CL2
VIH
VIL
TWCKH
TR
TF
TDH
TSU
Data in
(DL1, DL2)
(DR1, DR2)
TD
Data out
(DL1, DL2)
(DR1, DR2)
VOH
VOL
TSL
TLS
TLS
CL1
TWCKH
TR
TSU
M
V1.3
10/12
2001/05/04
ST7063C
!"D.C Characteristics
Symbol
Parameter
Test Condition Min. Typ. Max. Unit
Applicable pin
VDD
Operating Voltage
-
2.7
-
5.5
V
-
VLCD
Driver Supply Voltage
VDD-VEE
3
-
11
V
-
VIH
Input High Voltage
-
0.7
VDD
-
VDD
V
V
CL1,CL2,M,SHL1,SHL
2
DL1,DL2,DR1,DR2
VIL
Input Low Voltage
-
0
-
0.3
VDD
ILKG
Input Leakage Current
VIN =0 ~ VDD
-5
-
5
uA
VOH
Output High Voltage
IOH = -0.4mA
VDD
-0.4
-
-
V
VOL
Output Low Voltage
IOL = +0.4mA
-
-
0.4
V
IDD
Operating Current
FCL2 = 400KHZ
-
100
300
uA
VDD,VEE
IV
Leakage Current
VIN =VDD ~ VEE
-10
-
10
uA
V1 ~ V4
DL1,DL2,DR1,DR2
V1~V4, S1~S80
!"A.C Characteristics
Symbol
Parameter
Test
Test Condition Min. Max. Unit
Applicable pin
FCL
Data Shift Frequency
-
-
400
KHZ
CL2
TWCKH
Clock High Level Width
-
800
-
ns
CL1,CL2
TWCKL
Clock Low Level Width
-
800
-
ns
CL2
TSL
TLS
TR/TF
Clock Set-up Time
Clock Set-up Time
Clock Rise/Fall Time
CL2 $ CL1
CL1 $ CL2
-
500
500
-
200
ns
ns
ns
CL1,CL2
CL1,CL2
CL1,CL2
TSU
Data Set-up Time
-
300
-
ns
DL1,DL2,DR1,DR2
TDH
Data Hold Time
-
300
-
ns
DL1,DL2,DR1,DR2
TD
Data Delay Time
CL = 15 PF
-
500
ns
DL1,DL2,DR1,DR2
!"Maximum Absolute Ratings
Symbol
Parameters
Min.
Max.
Unit
VDD
Supply Voltage
-0.3
7
V
TOPR
Operating Temperature
-20
75
℃
TSTG
Storage Temperature
-55
125
℃
V1.3
11/12
2001/05/04
ST7063C
!"Application Circuit : (2Line x 40Word)
Com 1-16
D
VCC
GND
CL2
CL1
M
V1
V2
V3
V4
V5
Seg 1-40
ST7066U
DB0-DB7
To MPU
Vcc(+5V)
Regsister
DL1
VDD
SHL1
SHL2
VSS
VEE
V1
V4
Regsister
DR2
DL2
DR1
CL1
CL2
M
Regsister
Dot Matrix LCD Panel
Seg 1-80
V3
ST7063C
V2
Regsister
Regsister
DL1
VDD
SHL1
SHL2
VSS
VEE
V1
Seg 1-80
V3
DR2
DL2
DR1
CL1
CL2
M
-V or GND
V4
ST7063C
V2
VR
VR=10K~30Kohm
Note:Regsister=2.2K~10K ohm
2001/05/04
12/12
V1.3