GSM793E Syntek Semiconductor Co., Ltd. (80CH Segment Driver For Dot Matrix LCD) Introduction : GSM793E is a segment driver for dot matrix type LCD display. It features 80 channels with 40 X 2 bits bi-directional shift registers, data latches, LCD drivers and logic control circuits. It is fabricated by high voltage CMOS process with low current consumption. The GSM793E can convert serial data received from an LCD controller, such as GSM7980, into parallel data and send out LCD driving waveforms to the LCD panel. The GSM793E is designed for general purpose LCD drivers. It can drive both static and dynamic drive LCD. The LSI can be used as segment driver. The GSM793E has pin function compatibility with the KS0063(B) that allows the user to easily replace it with an GSM793E. Functions : l Dot matrix LCD driver with two 40 channel outputs l Bias voltage (V1 ~ V4) l input/output signals n n Input : Serial display data and control pulse from controller IC Output : 40 X 2 channels waveform for LCD driving Features : l Display driving bias : static to 1/5 l Power supply for logic : 2.7V ~ 5.5V l Power supply for LCD voltage (VDD~VEE) : 3V ~ 11V 100 Pin QFP package and bare chip available LCD Controller /Driver 1 /10 V1.1 GSM793E Syntek Semiconductor Co., Ltd. GSM793E FUNCTIONAL BLOCK S1 ...................S40 V1 V2 V3 V4 S41… … … … S80 SEGMENT DRIVER SEGMENT DRIVER DATA LATCH(40BITs) DATA LATCH(40BITs) BIDIRECTIONAL SHIFTER(40BITs) M CL1 CL2 VDD VSS VEE BIDIRECTIONAL SHIFTER(40BITs) CONTOL DL1 SHL1 DR1 LCD Controller /Driver DL2 SHL2 DR2 2 /10 V1.1 GSM793E Syntek Semiconductor Co., Ltd. Pin Description : PIN NAME PURPOSE DESCRIPTION I/O VDD POWER for logic N/A VSS GROUND for logic N/A VEE LCD GND for LCD driving voltage N/A V1 V2 LCD output used as select voltage level I V3 V4 LCD output used as non select voltage level I S1-S40 segment LCD driver output for part 1 O SHL1 direction direction control for part 1 segments I DL1, DR1 data in /out If SHL1 = 1 then DL1=out, DR1=in I/O If SHL1 = 0 then DL1=in, DR1=out S41-S80 segment LCD driver output for part 2 O SHL2 direction direction control for part 2 segments I DL2, DR2 data in/out If SHL2 = 1 then DL2=out, DR2=in I/O If SHL2 = 0 then DL2=in, DR2=out M alternation Alternate the LCD driving waveform I CL1 latch clock latch the data after shift is completed I CL2 shift clock shift the data into the segments I LCD Controller /Driver 3 /10 V1.1 GSM793E Syntek Semiconductor Co., Ltd. PAD Arrangement 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 75 79 47 76 80 46 77 81 45 78 82 “GSM793E” Marking: Easy to find the PAD 44 21 83 (0,0) 20 43 13 84 12 42 11 85 10 41 9 86 7 8 Size: 3800x2600 um 2 Coordinate: center 15 16 17 18 19 Min. PAD Pitch: 120um 14 22 23 24 25 26 27 28 29 GSM793E 30 31 32 33 34 35 36 37 40 6 87 5 39 Circle here to find the first PAD 4 88 3 38 2 89 90 91 92 93 94 95 96 1 V1.1 4 /10 LCD Controller /Driver GSM793E Syntek Semiconductor Co., Ltd. PAD NAMES AND COORDINATES Pa Pad d Nam No e . 1 S42 2 S43 3 S44 4 S45 5 S46 6 S47 7 S48 8 S49 9 S50 10 S51 11 S52 12 S53 13 S54 14 S55 15 S56 16 S57 17 S58 18 S59 19 S60 20 S61 21 S62 22 S63 23 S64 24 S65 25 S66 26 S67 27 S68 28 S69 29 S70 30 S71 31 S72 32 S73 X -1760 -1630 -1500 -1380 -1260 -1140 -1020 -900 -780 -660 -540 -420 -300 -180 -60 60 180 300 420 540 660 780 900 1020 1140 1260 1380 1500 1630 1760 1760 1760 Y -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1030 -900 LCD Controller /Driver 64 Pa Pad d Name No . 33 S74 34 S75 35 S76 36 S77 37 S78 38 S79 39 S80 40 S40 41 S39 42 S38 43 S37 44 S36 45 S35 46 S34 47 S33 48 S32 49 S31 50 S30 51 S29 52 S28 53 S27 54 S26 55 S25 56 S24 57 S23 58 S22 59 S21 60 S20 61 S19 62 S18 63 S17 X 1760 1760 1760 1760 1760 1760 1760 1760 1760 1760 1760 1760 1760 1760 1760 1760 1760 1630 1500 1380 1260 1140 1020 900 780 660 540 420 300 180 60 5 /10 S16 -60 1160 Y -780 -660 -540 -420 -300 -180 -60 60 180 300 420 540 660 780 900 1030 1160 1160 1160 1160 1160 1160 1160 1160 1160 1160 1160 1160 1160 1160 1160 Pa d No . 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 Pad Nam e S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 VEE V1 V2 V3 V4 VSS CL1 SHL1 SHL2 VDD CL2 DL1 DR1 DL2 X Y -180 -300 -420 -540 -660 -780 -900 -1020 -1140 -1260 -1380 -1500 -1630 -1760 -1760 -1760 -1760 -1760 -1760 -1760 -1760 -1760 -1760 -1760 -1760 -1760 -1760 -1760 -1760 1160 1160 1160 1160 1160 1160 1160 1160 1160 1160 1160 1160 1160 1160 1030 900 780 660 540 420 300 180 60 -60 -180 -300 -420 -540 -660 V1.1 GSM793E Syntek Semiconductor Co., Ltd. 94 95 96 DR2 M S41 -1760 -780 -1760 -900 -1760 -1030 LCD Controller /Driver 6 /10 V1.1 GSM793E Syntek Semiconductor Co., Ltd. Functional Description : Clock The CL1 is the clock to latch data on the falling edge. It latches the data input from the bidirectional shift register at the falling edge of CL1 and transfers its outputs to the LCD driver circuit. The CL2 is the clock to shift data on the falling edge. It shifts the serial data at the falling of CL2 and transfers the output of each bit of the register to the latch circuit. Shift Registers And Data I/O The GSM793E supplies two sets of 40-bit shift register, which controls the shift direction by SHL1 & SHL2. The SHL1 controls the 1st 40-bit shift register, and SHL2 controls the 2nd 40-bit shift register. When SHL1 is connected to VDD, the 1st shift direction is from S40 to S1; when SHL1 is connected to VSS, the shift direction changes from S1 to S40. When SHL2 is connected to VDD, the 2nd shift direction is from S80 to S41; when SHL2 is connected to VSS, the shift direction changes from S41 to S80. The DL1, DR1, DL2, DR2 are data input or output option function. Shift Direction of Channel 1 SHL1 Shift Direction DL1 DR1 0 S1 à S40 IN OUT 1 S40 à S1 OUT IN Shift Direction of Channel 2 SHL2 Shift Direction DL2 DR2 0 S41 à S80 IN OUT 1 S80 à S41 OUT IN LCD Controller /Driver 7 /10 V1.1 GSM793E Syntek Semiconductor Co., Ltd. LCD Output Waveforms : Output of LATCH (DATA) M V2 V2 V4 Output (S1 ~ S80) V4 V3 V3 V1 V1 Timing Characteristics : VIH TWCKL CL2 VIL TWCKH TF TR TDH TSU Data in (DL1, DL2) (DR1, DR2) TD Data out (DL1, DL2) (DR1, DR2) VOH TSL VOL TLS TLS CL1 TR TWCKH TSU M LCD Controller /Driver 8 /10 V1.1 GSM793E Syntek Semiconductor Co., Ltd. D.C Characteristics: Symbol Parameter Test Condition Min. Typ. Max. Unit Applicable pin VDD Operating Voltage - 2.7 - 5.5 V - VLCD Driver Supply Voltage VDD-VEE 3 - 11 V - VIH Input High Voltage - 0.7VDD - VDD V CL1,CL2,M,SHL1,SHL2 VIL Input Low Voltage - 0 - 0.3VDD V DL1,DL2,DR1,DR2 ILKG Input Leakage Current VIN = 0 ~ VDD -5 - 5 uA VOH Output High Voltage I OH = -0.4mA VDD-0.4 - - V DL1,DL2,DR1,DR2 VOL Output Low Voltage I OL = +0.4mA - - 0.4 V V1~V4, S1~S80 IDD Operating Current FCL2 = 400KHZ - 100 300 uA VDD,VEE IV Leakage Current VIN = VDD ~ VEE -10 - 10 uA V1 ~ V4 A.C Characteristics : Symbol Parameter Test Condition Min. Max. Unit Applicable pin FCL Data Shift Frequency - - 400 KHZ CL2 TWCKH Clock High Level Width - 800 - ns CL1,CL2 TWCKL Clock Low Level Width - 800 - ns CL2 TSL Clock Set-up Time CL2 à CL1 500 - ns CL1,CL2 TLS Clock Set-up Time CL1 à CL2 500 - ns CL1,CL2 TR/TF Clock Rise/Fall Time - - 200 ns CL1,CL2 TSU Data Set-up Time - 300 - ns DL1,DL2,DR1,DR2 TDH Data Hold Time - 300 - ns DL1,DL2,DR1,DR2 TD Data Delay Time CL = 15 P F - 500 ns DL1,DL2,DR1,DR2 Maximum Absolute Ratings : Symbol Parameters Min. Max. Unit VDD Supply Voltage -0.3 7 V T OPR Operating Temperature -20 75 0 C 125 0 C T STG Storage Temperature LCD Controller /Driver -55 9 /10 V1.1 GSM793E Syntek Semiconductor Co., Ltd. Application Circuit : (2Line x 40Word) SEG140 D Vdd GND CL2 CL1 M V1 V2 V3 V4 V5 S1-S80 GSM793E DR2 DL2 DR1 CL1 CL2 M Reg. Dot Matrix LCD Panel DL1 VDD SHL1 SHL2 GND VEE Reg. V1 V2 V3 V4 Reg. Vdd(+5V/+3V ) Reg. DL1 VDD SHL1 SHL2 GND VEE S1-S80 GSM793E Reg. V1 V2 V3 V4 Reg. DR2 DL2 DR1 CL1 CL2 M -V or GND V1.1 10 /10 LCD Controller /Driver COM116 GSM7980 DB0-DB7 To MPU Note: R= 2.2K ~ 10K, VR= 1K~30K