HD74LV2G125A Dual Bus Buffer with 3–state Output REJ03D0099–0500Z (Previous ADE-205-347D (Z)) Rev.5.00 Sep.30.2003 Description The HD74LV2G125A has dual bus buffer with 3–state output in a 8 pin package. Output is disabled when the associated output enable (OE) input is high. To ensure the high impedance state during power up or power down, OE should be connected to VCC through a pull-down resistor; the minimum value of the resistor is determined by the current souring capability of the driver. Low voltage and high-speed operation is suitable for the battery powered products (e.g., notebook computers), and the low power consumption extends the battery life. Features • The basic gate function is lined up as Renesas uni logic series. • Supplied on emboss taping for high-speed automatic mounting. • Electrical characteristics equivalent to the HD74LV125A Supply voltage range : 1.65 to 5.5 V Operating temperature range : –40 to +85°C • All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VO (Max.) = 5.5 V (@VCC = 0 V, Output : Z) • Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V) • All the logical input has hysteresis voltage for the slow transition. • Ordering Information Part Name Package Type HD74LV2G125AUSE SSOP-8 pin Rev.5.00, Sep.30.2003, page 1 of 9 Package Code Package Abbreviation Taping Abbreviation (Quantity) TTP-8DBV US E (3,000 pcs/reel) HD74LV2G125A Outline and Article Indication • HD74LV2G125A Index band Lot No. Y M W L 2 5 SSOP-8 Marking Function Table Inputs Output Y OE A L H H L L L H X Z H : High level L : Low level X : Immaterial Z : High impedance Rev.5.00, Sep.30.2003, page 2 of 9 Y : Year code (the last digit of year) M : Month code W : Week code HD74LV2G125A Pin Arrangement OE1 1 8 VCC A1 2 7 OE2 Y2 3 6 Y1 GND 4 5 A2 (Top view) Absolute Maximum Ratings Item Supply voltage range Input voltage range *1 Output voltage range *1, 2 Symbol Ratings Unit VCC –0.5 to 7.0 V VI –0.5 to 7.0 V VO –0.5 to VCC + 0.5 V –0.5 to 7.0 Test Conditions Output : H or L VCC : OFF or output : Z Input clamp current IIK –20 mA VI < 0 Output clamp current IOK ±50 mA VO < 0 or VO > VCC Continuous output current IO ±25 mA VO = 0 to VCC Continuous current through VCC or GND ICC or IGND ±50 mA Maximum power dissipation *3 at Ta = 25°C (in still air) PT 200 mW Storage temperature Tstg –65 to 150 °C Notes: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore no two of which may be realized at the same time. 1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The maximum package power dissipation was calculated using a junction temperature of 150°C. Rev.5.00, Sep.30.2003, page 3 of 9 HD74LV2G125A Recommended Operating Conditions Item Symbol Min Max Unit Supply voltage range VCC 1.65 5.5 V Input voltage range VI 0 5.5 V Output voltage range VO 0 VCC V 0 5.5 — 1 — 2 VCC = 2.3 to 2.7 V — 6 VCC = 3.0 to 3.6 V — 12 VCC = 4.5 to 5.5 V — –1 VCC = 1.65 to 1.95 V — –2 VCC = 2.3 to 2.7 V — –6 VCC = 3.0 to 3.6 V Output current IOL IOH Input transition rise or fall rate ∆t / ∆v Operating free-air temperature Ta Output : Z mA VCC = 1.65 to 1.95 V — –12 0 300 0 200 VCC = 2.3 to 2.7 V 0 100 VCC = 3.0 to 3.6 V 0 20 VCC = 4.5 to 5.5 V –40 85 Note: Unused or floating inputs must be held high or low. Rev.5.00, Sep.30.2003, page 4 of 9 Conditions VCC = 4.5 to 5.5 V ns / V °C VCC = 1.65 to 1.95 V HD74LV2G125A Electrical Characteristic • Ta = –40 to 85°C Item Symbol VCC (V) * Input voltage VIH Min Typ 1.65 to 1.95 VCC×0.75 — Max Unit — V Test condition 2.3 to 2.7 VCC×0.7 — — 3.0 to 3.6 VCC×0.7 — — 4.5 to 5.5 VCC×0.7 — — 1.65 to 1.95 — — VCC×0.25 2.3 to 2.7 — — VCC×0.3 3.0 to 3.6 — — VCC×0.3 4.5 to 5.5 — — VCC×0.3 1.8 — 0.25 — 2.5 — 0.30 — 3.3 — 0.35 — 5.0 — 0.45 — Min to Max VCC–0.1 — — 1.65 1.4 — — IOH = –1 mA 2.3 2.0 — — IOH = –2 mA 3.0 2.48 — — IOH = –6 mA 4.5 3.8 — — IOH = –12 mA Min to Max — — 0.1 IOL = 50 µA 1.65 — — 0.3 IOL = 1 mA 2.3 — — 0.4 IOL = 2 mA 3.0 — — 0.44 IOL = 6 mA 4.5 — — 0.55 IOL = 12 mA 0 to 5.5 — — ±1 µA VIN = 5.5 V or GND Off state output current IOZ Min to Max — — ±5 µA VO = 5.5 V or GND Quiescent supply current 5.5 — — 10 µA VIN = VCC or GND, IO = 0 Output leakage current IOFF 0 — — 5 µA VIN or VO = 0 to 5.5 V Input capacitance 3.3 — 3.0 — pF VIN = VCC or GND VIL Hysteresis voltage Output voltage VH VOH VOL Input current IIN ICC CIN V VT+ – VT– V IOH = –50 µA Note: For conditions shown as Min or Max, use the appropriate values under recommended operating conditions. Rev.5.00, Sep.30.2003, page 5 of 9 HD74LV2G125A Switching Characteristics • VCC = 1.8 ± 0.15 V Item Symbol Ta = 25°C Ta = –40 to 85°C Min Typ Max Min Max Propagation delay time tPLH tPHL — 13.5 23.5 1.0 26.0 — 19.0 33.0 1.0 36.0 Enable time tZH tZL — 13.7 26.5 1.0 29.0 — 20.5 36.0 1.0 38.0 tHZ tLZ — 8.3 20.0 1.0 22.5 — 13.0 29.5 1.0 32.0 Disable time Unit Test FROM Conditions (Input) ns CL = 15 pF TO (Output) A Y OE Y OE Y CL = 50 pF ns CL = 15 pF CL = 50 pF ns CL = 15 pF CL = 50 pF • VCC = 2.5 ± 0.2 V Item Symbol Ta = 25°C Ta = –40 to 85°C Min Typ Max Min Max Propagation delay time tPLH tPHL — 6.8 13.0 1.0 15.5 — 8.7 16.5 1.0 18.5 Enable time tZH tZL — 7.0 13.0 1.0 15.5 — 8.8 16.5 1.0 18.5 tHZ tLZ — 5.1 14.7 1.0 17.0 — 7.3 18.2 1.0 20.5 Disable time Unit Test FROM Conditions (Input) TO (Output) ns A Y OE Y OE Y CL = 15 pF CL = 50 pF ns CL = 15 pF CL = 50 pF ns CL = 15 pF CL = 50 pF • VCC = 3.3 ± 0.3 V Item Symbol Ta = 25°C Ta = –40 to 85°C Min Typ Max Min Max Propagation delay time tPLH tPHL — 4.8 8.0 1.0 9.5 — 6.1 11.5 1.0 13.0 Enable time tZH tZL — 4.8 8.0 1.0 9.5 — 6.2 11.5 1.0 13.0 tHZ tLZ — 4.1 9.7 1.0 11.5 — 5.5 13.2 1.0 15.0 Disable time Rev.5.00, Sep.30.2003, page 6 of 9 Unit Test FROM Conditions (Input) TO (Output) ns A Y OE Y OE Y CL = 15 pF CL = 50 pF ns CL = 15 pF CL = 50 pF ns CL = 15 pF CL = 50 pF HD74LV2G125A Switching Characteristics (cont) • VCC = 5.0 ± 0.5 V Item Symbol Ta = 25°C Ta = –40 to 85°C Min Typ Max Min Max Propagation delay time tPLH tPHL — 3.4 5.5 1.0 6.5 — 4.3 7.5 1.0 8.5 Enable time tZH tZL — 3.4 5.1 1.0 6.0 — 4.4 7.1 1.0 8.0 tHZ tLZ — 3.2 6.8 1.0 8.0 — 4.0 8.8 1.0 10.0 Disable time Unit Test FROM Conditions (Input) CL = 15 pF ns TO (Output) A Y OE Y OE Y CL = 50 pF CL = 15 pF ns CL = 50 pF CL = 15 pF ns CL = 50 pF Operating Characteristics • CL = 50 pF Item Symbol Power dissipation capacitance VCC (V) Ta = 25°C CPD Min Typ Max 3.3 — 10.5 — 5.0 — 11.5 — Unit Test Conditions pF f = 10 MHz Test Circuit VCC Pulse Generator Z OUT = 50 Ω See Function Table Input VCC Output 1k Ω S1 CL = 15 or 50 pF TEST t PLH / t PHL t ZH/ t HZ t ZL / t LZ Note: 1. C L includes probe and jig capacitance. Rev.5.00, Sep.30.2003, page 7 of 9 OPEN See under table GND *1 S1 OPEN GND VCC HD74LV2G125A • Waveforms – 1 tr tf VCC 90 % 50% 90 % 50% Input A 10 % 10 % GND t PHL t PLH VOH Output Y 50% 50% VOL • Waveforms – 2 Input OE tf tr 90 % 50% VCC 90 % 50% 10 % t ZL 10 % GND t LZ VCC 50% Waveform – A t ZH Waveform – B VOL + 0.3 V t HZ 50% VOH – 0.3 V VOL VOH GND Notes: 1. Input waveform : PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. 2. Waveform – A is for an output with internal conditions such that the output is low except when disabled by the output control. 3. Waveform – B is for an output with internal conditions such that the output is high except when disabled by the output control. 4. The output are measured one at a time with one transition per measurement. Rev.5.00, Sep.30.2003, page 8 of 9 HD74LV2G125A Package Dimensions 2.0 ± 0.2 1.5 ± 0.2 + 0.1 (0.17) 8 − 0.2 − 0.05 Package Code JEDEC JEITA Mass (reference value) Rev.5.00, Sep.30.2003, page 9 of 9 + 0.1 0.13 − 0.05 0 − 0.1 0.7 ± 0.1 (0.4) 2.3 ± 0.1 (0.5) (0.5) (0.5) 3.1 ± 0.3 (0.4) Unit: mm TTP–8DBV 0.010 g Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. 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