IS61NLP6432A IS61NLP6436A/IS61NVP6436A IS61NLP12818A/IS61NVP12818A 64K x 32, 64K x 36, and 128K x 18 2Mb, PIPELINE 'NO WAIT' STATE BUS SRAM PRELIMINARY INFORMATION SEPTEMBER 2005 FEATURES DESCRIPTION • 100 percent bus utilization The 2 Meg 'NLP/NVP' product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for networking and communications applications. They are organized as 64K words by 32 bits, 64K words by 36 bits, and 128K words by 18 bits, fabricated with ISSI's advanced CMOS technology. • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control using MODE input • Three chip enables for simple depth expansion and address pipelining • Power Down mode • Common data inputs and data outputs • CKE pin to enable clock and suspend operation • JEDEC 100-pin TQFP package • Power supply: NVP: Vdd 2.5V (± 5%), Vddq 2.5V (± 5%) NLP: Vdd 3.3V (± 5%), Vddq 3.3V/2.5V (± 5%) • Industrial temperature available • Lead-free available Incorporating a 'no wait' state feature, wait cycles are eliminated when the bus switches from read to write, or write to read. This device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers are controlled by a positive-edge-triggered single clock input. Operations may be suspended and all synchronous inputs ignored when Clock Enable, CKE is HIGH. In this state the internal device will hold their previous values. All Read, Write and Deselect cycles are initiated by the ADV input. When the ADV is HIGH the internal burst counter is incremented. New external addresses can be loaded when ADV is LOW. Write cycles are internally self-timed and are initiated by the rising edge of the clock inputs and when WE is LOW. Separate byte enables allow individual bytes to be written. A burst mode pin (MODE) defines the order of the burst sequence. When tied HIGH, the interleaved burst sequence is selected. When tied LOW, the linear burst sequence is selected. FAST ACCESS TIME SymbolParameter tkq Clock Access Time tkc Cycle Time Frequency -250 2.6 4 250 -200 Units 3.1 ns 5 ns 200 MHz Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-47741 Rev. 00A 08/31/05 IS61NLP6432A IS61NLP6436A/IS61NVP6436A IS61NLP12818A/IS61NVP12818A BLOCK DIAGRAM x 32/x 36: A [0:15] or x 18: A [0:16] ADDRESS REGISTER MODE A0-A1 CLK CONTROL LOGIC K CKE 64Kx32; 64Kx36; 128Kx18 MEMORY ARRAY A2-A15 or A2-A16 WRITE ADDRESS REGISTER BURST ADDRESS COUNTER A'0-A'1 WRITE ADDRESS REGISTER K DATA-IN REGISTER K DATA-IN REGISTER CE CE2 CE2 ADV WE BWŸX } CONTROL REGISTER K CONTROL LOGIC (X=a,b,c,d or a,b) OUTPUT REGISTER BUFFER OE ZZ 32, 36 or 18 DQx/DQPx 2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. 00A 08/31/05 IS61NLP6432A IS61NLP6436A/IS61NVP6436A IS61NLP12818A/IS61NVP12818A PIN CONFIGURATION VDDQ DQb DQc DQb Vss NC VDD ZZ DQc NC VDD DQa DQd DQa DQd VDDQ VDDQ Vss NC Vss DQa Vss DQd DQa DQd DQa DQa Vss DQd DQd Vss VDDQ VDDQ DQa DQa DQPa DQd DQd NC 64K x 36 NC OE ADV NC CKE CLK WE CE2 VDD Vss BWa BWc BWb BWd CE2 CE A A NC DQb DQb VDDQ Vss DQb DQb DQb DQb Vss VDDQ DQb DQb Vss NC VDD ZZ DQa DQa VDDQ Vss DQa DQa DQa DQa Vss VDDQ DQa DQa NC NC VDDQ A Vss A Vss A DQc A DQc DQb A DQb NC A DQc DQc NC DQb DQb VDD Vss NC NC Vss Vss VDDQ A1 A0 VDDQ A A NC OE ADV NC CKE CLK WE CE2 VDD Vss BWa BWc BWb BWd CE2 CE A A DQc A MODE DQd DQd DQPd DQb A VDDQ DQc A DQd DQd Vss DQb 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A DQd NC MODE Vss DQd DQPb NC VDDQ A DQd A DQd A NC Vss A DQc NC VDD A DQc NC A VDDQ NC Vss VDD DQc Vss DQc NC NC DQc DQc A1 A0 Vss A VDDQ A DQc A DQc 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A DQPc A A 100-Pin TQFP 64K x 32 PIN DESCRIPTIONS A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. A Synchronous Address Inputs CLK Synchronous Clock ADV Synchronous Burst Address Advance BWa-BWd Synchronous Byte Write Enable WE Write Enable CKE Clock Enable Vss Ground for Core NC Not Connected CE, CE2, CE2 Synchronous Chip Enable OE Output Enable DQa-DQd Synchronous Data Input/Output DQPa-DQPd Parity Data I/O MODE Burst Sequence Selection Vdd +3.3V/2.5V Power Supply Vss Ground for output Buffer Vddq Isolated Output Buffer Supply: +3.3V/2.5V ZZ Snooze Enable Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-47743 Rev. 00A 08/31/05 IS61NLP6432A IS61NLP6436A/IS61NVP6436A IS61NLP12818A/IS61NVP12818A PIN CONFIGURATION Vss DQb DQb DQPb NC Vss VDDQ MODE NC NC NC NC ADV NC OE CKE CLK WE CE2 VDD Vss BWa NC BWb NC CE2 CE A A A NC NC VDDQ Vss NC DQPa DQa DQa Vss VDDQ DQa DQa Vss NC VDD ZZ DQa DQa VDDQ Vss DQa DQa NC NC Vss VDDQ NC NC NC NC VDDQ A DQb A DQb A NC Vss A DQb NC VDD A DQb NC A VDDQ NC Vss VDD DQb Vss DQb NC NC NC NC A1 A0 Vss A VDDQ A NC A NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A NC A A 100-Pin TQFP 128K x 18 PIN DESCRIPTIONS A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. A Synchronous Address Inputs CLK Synchronous Clock ADV Synchronous Burst Address Advance BWa-BWd Synchronous Byte Write Enable WE Write Enable CKE Clock Enable Vss Ground for Core NC Not Connected 4 CE, CE2, CE2 Synchronous Chip Enable OE Output Enable DQa-DQd Synchronous Data Input/Output DQPa-DQPd Parity Data I/O MODE Burst Sequence Selection Vdd +3.3V/2.5V Power Supply Vss Ground for output Buffer Vddq Isolated Output Buffer Supply: +3.3V/2.5V ZZ Snooze Enable Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. 00A 08/31/05 IS61NLP6432A IS61NLP6436A/IS61NVP6436A IS61NLP12818A/IS61NVP12818A STATE DIAGRAM READ READ READ BURST WRITE BEGIN READ DS DS READ WRITE DESELECT BURST BURST READ BEGIN WRITE BURST DS BURST DS DS WRITE READ BURST WRITE WRITE WRITE BURST SYNCHRONOUS TRUTH TABLE(1) Address OperationUsed CECE2CE2 ADVWE BWx OE CKE CLK Not Selected N/A H X X L X X X L ↑ Not Selected N/A XLXLXXXL ↑ Not Selected N/A XXHLXXXL ↑ Not Selected Continue N/A X X X H X X X L ↑ Begin Burst Read External Address L H L L H X L L ↑ Continue Burst Read Next Address X X X H X X L L ↑ NOP/Dummy Read External Address LHLLHXHL ↑ Dummy Read Next Address X X X H X X H L ↑ Begin Burst Write External Address L H L L L L X L ↑ Continue Burst Write Next Address X X X H X L X L ↑ NOP/Write Abort N/A LHLLLHXL ↑ Write Abort Next Address X X X H X H X L ↑ Ignore Clock Current AddressXXXXXXXH ↑ Notes: 1. "X" means don't care. 2. The rising edge of clock is symbolized by ↑ 3. A continue deselect cycle can only be entered if a deselect cycle is executed first. 4. WE = L means Write operation in Write Truth Table. WE = H means Read operation in Write Truth Table. 5. Operation finally depends on status of asynchronous pins (ZZ and OE). Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-47745 Rev. 00A 08/31/05 IS61NLP6432A IS61NLP6436A/IS61NVP6436A IS61NLP12818A/IS61NVP12818A ASYNCHRONOUS TRUTH TABLE(1) OperationZZ OE I/O STATUS Sleep Mode H X High-Z Read LL DQ LH High-Z Write L X Din, High-Z Deselected LX High-Z Notes: 1. X means "Don't Care". 2. For write cycles following read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur. 3. Sleep Mode means power Sleep Mode where stand-by current does not depend on cycle time. 4. Deselected means power Sleep Mode where stand-by current depends on cycle time. WRITE TRUTH TABLE (x18) Operation READ WRITE BYTE a WRITE BYTE b WRITE ALL BYTEs WRITE ABORT/NOP Notes: WEBWaBWb HXX L L H L H L L L L L H H 1. X means "Don't Care". 2. All inputs in this table must beet setup and hold time around the rising edge of CLK. 6 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. 00A 08/31/05 IS61NLP6432A IS61NLP6436A/IS61NVP6436A IS61NLP12818A/IS61NVP12818A WRITE TRUTH TABLE (x32/x36) Operation WEBWaBWbBWcBWd READ HXXXX WRITE BYTE a L L H H H WRITE BYTE b LHLHH WRITE BYTE c LHHLH WRITE BYTE d L H H H L WRITE ALL BYTEs LLLLL WRITE ABORT/NOP LHHHH Notes: 1. X means "Don't Care". 2. All inputs in this table must beet setup and hold time around the rising edge of CLK. INTERLEAVED BURST ADDRESS TABLE (MODE = Vdd or NC) External Address 1st Burst Address 2nd Burst Address 3rd Burst Address A1 A0 A1 A0 A1 A0 A1 A0 00011011 01001110 10110001 11100100 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-47747 Rev. 00A 08/31/05 IS61NLP6432A IS61NLP6436A/IS61NVP6436A IS61NLP12818A/IS61NVP12818A LINEAR BURST ADDRESS TABLE (MODE = Vss) 0,0 A1', A0' = 1,1 0,1 1,0 ABSOLUTE MAXIMUM RATINGS(1) Symbol Tstg Pd Iout Vin, Vout Vin Parameter Value Storage Temperature –65 to +150 Power Dissipation 1.6 Output Current (per I/O) 100 Voltage Relative to Vss for I/O Pins –0.5 to Vddq + 0.3 Voltage Relative to Vss for –0.3 to 4.6 for Address and Control Inputs Unit °C W mA V V Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. This device contains circuitry that will ensure the output devices are in High-Z at power up. OPERATING RANGE (IS61NLPx) Range Commercial Industrial Ambient Temperature 0°C to +70°C -40°C to +85°C Vdd 3.3V ± 5% 3.3V ± 5% Vddq 3.3V / 2.5V ± 5% 3.3V / 2.5V ± 5% Vdd 2.5V ± 5% 2.5V ± 5% Vddq 2.5V ± 5% 2.5V ± 5% OPERATING RANGE (IS61NVPx) Range Commercial Industrial 8 Ambient Temperature 0°C to +70°C -40°C to +85°C Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. 00A 08/31/05 IS61NLP6432A IS61NLP6436A/IS61NVP6436A IS61NLP12818A/IS61NVP12818A DC ELECTRICAL CHARACTERISTICS (Over Operating Range) 3.3V2.5V Symbol Parameter Test Conditions Min.Max. Min.Max. Voh Output HIGH Voltage Ioh = –4.0 mA (3.3V) 2.4— 2.0— Ioh = –1.0 mA (2.5V) Vol Output LOW Voltage Iol = 8.0 mA (3.3V) —0.4 —0.4 Iol = 1.0 mA (2.5V) Vih Input HIGH Voltage 2.0 Vdd + 0.31.7 Vdd + 0.3 Vil Input LOW Voltage –0.30.8 –0.30.7 Ili Input Leakage Current Vss ≤ Vin ≤ Vdd(1) –55 –55 Ilo Output Leakage Current Vss ≤ Vout ≤ Vddq, OE = Vih –55 –55 Unit V V V V µA µA POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Test Conditions Temp. range Icc AC Operating Device Selected, Com. Supply Current OE = Vih, ZZ ≤ Vil, Ind. All Inputs ≤ 0.2V or ≥ Vdd – 0.2V, Cycle Time ≥ tkc min. Isb Standby Current Device Deselected, Com. TTL Input Vdd = Max., Ind. All Inputs ≤ Vil or ≥ Vih, ZZ ≤ Vil, f = Max. Isbi Standby Current Device Deselected, Com. CMOS Input Vdd = Max., Ind. Vin ≤ Vss + 0.2V or ≥Vdd – 0.2V typ.(2) f=0 Isb2 Sleep Mode ZZ>Vih Com. Ind. typ.(2) -250-200 MAXMAX x18 x32/x36 x18 x32/x36 225 225 200 200 250 250 210210 Unit mA 90 90 100 100 90 90 mA 100100 70 70 75 75 40 70 70 7575 40 30 30 35 35 20 30 35 mA 30 mA 35 20 Note: 1. MODE pin has an internal pullup and should be tied to Vdd or Vss. It exhibits ±100µA maximum leakage current when tied to ≤ Vss + 0.2V or ≥ Vdd – 0.2V. 2. Typical values are measured at Vdd = 3.3V, Ta = 25oC and not 100% tested. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-47749 Rev. 00A 08/31/05 IS61NLP6432A IS61NLP6436A/IS61NVP6436A IS61NLP12818A/IS61NVP12818A CAPACITANCE(1,2) Symbol Cin Cout Parameter Input Capacitance Input/Output Capacitance Conditions Vin = 0V Vout = 0V Max. Unit 6pF 8pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: Ta = 25°C, f = 1 MHz, Vdd = 3.3V. 3.3V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 1.5 ns 1.5V See Figures 1 and 2 3.3V I/O OUTPUT LOAD EQUIVALENT 317 Ω +3.3V Zo= 50Ω OUTPUT OUTPUT 50Ω 5 pF Including jig and scope 351 Ω 1.5V Figure 1 10 Figure 2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. 00A 08/31/05 IS61NLP6432A IS61NLP6436A/IS61NVP6436A IS61NLP12818A/IS61NVP12818A 2.5V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 2.5V 1.5 ns 1.25V See Figures 3 and 4 2.5V I/O OUTPUT LOAD EQUIVALENT 1,667 Ω +2.5V ZO = 50Ω OUTPUT OUTPUT 50Ω 5 pF Including jig and scope 1,538 Ω 1.25V Figure 3 Figure 4 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-477411 Rev. 00A 08/31/05 IS61NLP6432A IS61NLP6436A/IS61NVP6436A IS61NLP12818A/IS61NVP12818A READ/WRITE CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol fmax tkc tkh tkl tkq tkqx(2) tkqlz(2,3) tkqhz(2,3) toeq Parameter Clock Frequency Cycle Time Clock High Time Clock Low Time Clock Access Time Clock High to Output Invalid Clock High to Output Low-Z Clock High to Output High-Z Output Enable to Output Valid -250-200 Min. Max. Min.Max. — 250 — 200 4.0 — 5 — 1.7 — 2 — 1.7 — 2 — — 2.6 — 3.1 0.8 — 1.5 — 0.8 — 1 — — 2.6 — 3.0 — 2.8 — 3.1 Unit MHz ns ns ns ns ns ns ns ns toelz(2,3) toehz(2,3) tas tws tces tse tadvs tds tah the twh tceh tadvh tdh tpds tpus Notes: Output Enable to Output Low-Z Output Disable to Output High-Z Address Setup Time Read/Write Setup Time Chip Enable Setup Time Clock Enable Setup Time Address Advance Setup Time Data Setup Time Address Hold Time Clock Enable Hold Time Write Hold Time Chip Enable Hold Time Address Advance Hold Time Data Hold Time ZZ High to Power Down ZZ Low to Power Down 0 — 1.2 1.2 1.2 1.2 1.2 1.2 0.3 0.3 0.3 0.3 0.3 0.3 — — ns ns ns ns ns ns ns ns ns ns ns ns ns ns cyc cyc — 2.6 — — — — — — — — — — — — 2 2 0 — — 3.0 1.4 — 1.4 — 1.4 — 1.4 — 1.4 — 1.4 — 0.4— 0.4 — 0.4 — 0.4 — 0.4 — 0.4 — — 2 — 2 1. Configuration signal MODE is static and must not change during normal operation. 2. Guaranteed but not 100% tested. This parameter is periodically sampled. 3. Tested with load in Figure 2. 12 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. 00A 08/31/05 IS61NLP6432A IS61NLP6436A/IS61NVP6436A IS61NLP12818A/IS61NVP12818A SLEEP MODE ELECTRICAL CHARACTERISTICS Symbol Parameter Conditions Min. Max. Unit Isb2 Current during SLEEP MODE ZZ ≥ Vih 35 mA tpds ZZ active to input ignored 2 cycle tpus ZZ inactive to input sampled 2 cycle tzzi ZZ active to SLEEP current 2 cycle trzzi ZZ inactive to exit SLEEP current 0 ns SLEEP MODE TIMING CLK tPDS ZZ setup cycle tPUS ZZ recovery cycle ZZ tZZI Isupply ISB2 tRZZI All Inputs (except ZZ) Deselect or Read Only Deselect or Read Only Normal operation cycle Outputs (Q) High-Z Don't Care Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-477413 Rev. 00A 08/31/05 IS61NLP6432A IS61NLP6436A/IS61NVP6436A IS61NLP12818A/IS61NVP12818A READ CYCLE TIMING tKH tKL CLK tKC tADVS tADVH ADV tAS tAH Address A1 A3 A2 tWS tWH WRITE tSE tHE CKE tCES tCEH CE OE tOEQ tOEHZ Data Out Q1-1 tOEHZ tDS Q2-1 tKQ Q2-2 tKQHZ Q2-3 NOTES: WRITE = L means WE = L and BWx = L WE = L and BWX = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L 14 Q2-4 Q3-1 Q3-2 Q3-3 Q3-4 Don't Care Undefined Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. 00A 08/31/05 IS61NLP6432A IS61NLP6436A/IS61NVP6436A IS61NLP12818A/IS61NVP12818A WRITE CYCLE TIMING tKH tKL CLK tKC ADV Address A1 A3 A2 WRITE tSE tHE CKE CE OE tDS Data In D1-1 D2-1 D2-2 D2-3 D2-4 D3-1 tDH D3-2 D3-3 D3-4 tOEHZ Data Out Q0-3 Q0-4 NOTES: WRITE = L means WE = L and BWx = L WE = L and BWX = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L Don't Care Undefined Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-477415 Rev. 00A 08/31/05 IS61NLP6432A IS61NLP6436A/IS61NVP6436A IS61NLP12818A/IS61NVP12818A SINGLE READ/WRITE CYCLE TIMING tKH tKL CLK tSE tHE tKC CKE Address A1 A2 A3 A4 Q1 Q3 A5 A6 A7 A8 A9 WRITE CE ADV OE tOEQ Data Out tOELZ Q4 Q6 Q7 tDS tDH Data In D5 D2 NOTES: WRITE = L means WE = L and BWx = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L 16 Don't Care Undefined Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. 00A 08/31/05 IS61NLP6432A IS61NLP6436A/IS61NVP6436A IS61NLP12818A/IS61NVP12818A CKE OPERATION TIMING tKH tKL CLK tSE tHE tKC CKE Address A1 A2 A3 A4 A5 A6 WRITE CE ADV OE tKQ Data Out tKQLZ tKQHZ Q1 Q3 Q4 tDS tDH Data In D2 NOTES: WRITE = L means WE = L and BWx = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L Don't Care Undefined Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-477417 Rev. 00A 08/31/05 IS61NLP6432A IS61NLP6436A/IS61NVP6436A IS61NLP12818A/IS61NVP12818A CE OPERATION TIMING tKH tKL CLK tSE tHE tKC CKE Address A1 A2 A3 A4 A5 WRITE CE ADV OE tOEQ Data Out tOELZ tKQHZ Q1 tKQ tKQLZ Q2 Q4 tDS tDH Data In D3 NOTES: WRITE = L means WE = L and BWx = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L 18 D5 Don't Care Undefined Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. 00A 08/31/05 IS61NLP6432A IS61NLP6436A/IS61NVP6436A IS61NLP12818A/IS61NVP12818A ORDERING INFORMATION (Vdd = 3.3V/Vddq = 2.5V/3.3V) Commercial Range: 0°C to +70°C Access Time 250 200 250 200 250 200 Order Part Number 64Kx32 IS61NLP6432A-250TQ IS61NLP6432A-200TQ 64Kx36 IS61NLP6436A-250TQ IS61NLP6436A-200TQ 128Kx18 IS61NLP12818A-250TQ IS61NLP12818A-200TQ Package 100 TQFP 100 TQFP 100 TQFP 100 TQFP 100 TQFP 100 TQFP Industrial Range: -40°C to +85°C Access Time 250 200 200 250 200 250 200 200 Order Part Number 64Kx32 IS61NLP6432A-250TQI IS61NLP6432A-200TQI IS61NLP6432A-200TQLI 64Kx36 IS61NLP6436A-250TQI IS61NLP6436A-200TQI 128Kx18 IS61NLP12818A-250TQI IS61NLP12818A-200TQI IS61NLP12818A-200TQLI Package 100 TQFP 100 TQFP 100 TQFP, Lead-free 100 TQFP 100 TQFP 100 TQFP 100 TQFP 100 TQFP, Lead-free Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-477419 Rev. 00A 08/31/05 IS61NLP6432A IS61NLP6436A/IS61NVP6436A IS61NLP12818A/IS61NVP12818A ORDERING INFORMATION (Vdd = 2.5V/Vddq = 2.5V) Commercial Range: 0°C to +70°C Access Time 250 200 250 200 Order Part Number 64Kx36 IS61NVP6436A-250TQ IS61NVP6436A-200TQ 128Kx18 IS61NVP12818A-250TQ IS61NVP12818A-200TQ Package 100 TQFP 100 TQFP 100 TQFP 100 TQFP Industrial Range: -40°C to +85°C Access Time 250 200 250 200 20 Order Part Number 64Kx36 IS61NVP6436A-250TQI IS61NVP6436A-200TQI 128Kx18 IS61NVP12818A-250TQI IS61NVP12818A-200TQI Package 100 TQFP 100 TQFP 100 TQFP 100 TQFP Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. 00A 08/31/05