IS61NLP25636A/IS61NVP25636A IS61NLP51218A

IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A 256K x 36 and 512K x 18
9Mb, PIPELINE 'NO WAIT' STATE BUS SRAM
AUGUST 2014
FEATURES
DESCRIPTION
• 100 percent bus utilization
The 9 Meg 'NLP/NVP' product family feature high-speed,
low-power synchronous static RAMs designed to provide
a burstable, high-performance, 'no wait' state, device for
networking and communications applications. They are
organized as 256K words by 36 bits and 512K words by 18
bits, fabricated with ISSI's advanced CMOS technology.
• No wait cycles between Read and Write
• Internal self-timed write cycle
• Individual Byte Write Control
• Single R/W (Read/Write) control pin
• Clock controlled, registered address, data and control
• Interleaved or linear burst sequence control using MODE input
• Three chip enables for simple depth expansion
and address pipelining
• Power Down mode
• Common data inputs and data outputs
• CKE pin to enable clock and suspend operation
• JEDEC 100-pin TQFP, 165-ball PBGA and
119-ball PBGA packages
• Power supply:
NVP: Vdd 2.5V (± 5%), Vddq 2.5V (± 5%)
NLP: Vdd 3.3V (± 5%), Vddq 3.3V/2.5V (± 5%)
• JTAG Boundary Scan for PBGA packages
• Industrial temperature available
• Lead-free available
Incorporating a 'no wait' state feature, wait cycles are
eliminated when the bus switches from read to write, or
write to read. This device integrates a 2-bit burst counter,
high-speed SRAM core, and high-drive capability outputs
into a single monolithic circuit.
All synchronous inputs pass through registers are controlled
by a positive-edge-triggered single clock input. Operations
may be suspended and all synchronous inputs ignored
when Clock Enable, CKE is HIGH. In this state the internal
device will hold their previous values.
All Read, Write and Deselect cycles are initiated by the ADV
input. When the ADV is HIGH the internal burst counter
is incremented. New external addresses can be loaded
when ADV is LOW.
Write cycles are internally self-timed and are initiated
by the rising edge of the clock inputs and when WE is
LOW. Separate byte enables allow individual bytes to be
written.
A burst mode pin (MODE) defines the order of the burst
sequence.When tied HIGH, the interleaved burst sequence
is selected. When tied LOW, the linear burst sequence is
selected.
FAST ACCESS TIME
SymbolParameter
tkq
Clock Access Time
tkc
Cycle Time
Frequency
-250
2.6
4
250
-200 Units
3.1
ns
5
ns
200
MHz
Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written
assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-47741
Rev. J
08/25/2014
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A BLOCK DIAGRAM
x 36: A [0:17] or
x 18: A [0:18]
ADDRESS
REGISTER
A2-A17 or A2-A18
MODE
A0-A1
CLK
CONTROL
LOGIC
K
CKE
WRITE
ADDRESS
REGISTER
256Kx36;
512Kx18
MEMORY ARRAY
BURST
ADDRESS
COUNTER
A'0-A'1
WRITE
ADDRESS
REGISTER
K
DATA-IN
REGISTER
K
DATA-IN
REGISTER
CE
CE2
CE2
ADV
WE
BWŸX
}
CONTROL
REGISTER
K
CONTROL
LOGIC
(X=a,b,c,d or a,b)
OUTPUT
REGISTER
BUFFER
OE
ZZ
36 or 18
DQx/DQPx
2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. J
08/25/2014
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A Bottom View
165-Ball, 13 mm x 15mm BGA
Bottom View
119-Ball, 14 mm x 22 mm BGA
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-47743
Rev. J
08/25/2014
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A Pin Configuration ­— 256K x 36, 165-Ball PBGA (Top View)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
1
NC
NC
DQPc
DQc
DQc
DQc
DQc
NC
DQd
DQd
DQd
DQd
DQPd
NC
MODE
2
A
A
NC
DQc
DQc
DQc
DQc
NC
DQd
DQd
DQd
DQd
NC
NC
NC
3
CE
CE2
Vddq
Vddq
Vddq
Vddq
Vddq
NC
Vddq
Vddq
Vddq
Vddq
Vddq
A
A
4
BWc
BWd
VSS
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
VSS
A
A
5
BWb
BWa
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDI
TMS
6
CE2
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
A1*
A0*
7
CKE
WE
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDO
TCK
8
ADV
OE
VSS
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
VSS
A
A
9
A
NC
Vddq
Vddq
Vddq
Vddq
Vddq
NC
Vddq
Vddq
Vddq
Vddq
Vddq
A
A
10
A
A
NC
DQb
DQb
DQb
DQb
NC
DQa
DQa
DQa
DQa
NC
A
A
11
NC
NC
DQPb
DQb
DQb
DQb
DQb
ZZ
DQa
DQa
DQa
DQa
DQPa
NC
A
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
A0, A1
ADV Pin Name
Address Inputs
Synchronous Burst Address Inputs
Synchronous Burst Address Advance/
Load
WE
Synchronous Read/Write Control
Input
CLK Synchronous Clock
CKE
Clock Enable
CE, CE2, CE2 Synchronous Chip Enable
BWx (x=a-d) Synchronous Byte Write Inputs
OE
Output Enable
ZZ
Power Sleep Mode 4
MODE TCK, TDI
TDO, TMS
VDD
NC
DQx
DQPx VDDQ
Vss
Burst Sequence Selection
JTAG Pins
3.3V/2.5V Power Supply
No Connect
Data Inputs/Outputs
Parity Data I/O
Isolated output Power Supply 3.3V/2.5V
Ground
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. J
08/25/2014
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A 119-PIN PBGA PACKAGE CONFIGURATION
256K x 36 (TOP VIEW)
1
2
3
4
5
6
7
A
VDDQ
A
A
NC
A
A
VDDQ
B
NC
CE2
A
ADV
A
CE2
NC
C
NC
A
A
VDD
A
A
NC
D
DQc
DQPc
VSS
NC
Vss
DQPb
DQb
E
DQc
DQc
VSS
CE
Vss
DQb
DQb
F
VDDQ
DQc
VSS
OE
Vss
DQb
VDDQ
G
DQc
DQc
BWc
A
BWb
DQb
DQb
H
DQc
DQc
VSS
WE
Vss
DQb
DQb
J
VDDQ
VDD
NC
VDD
NC
VDD
VDDQ
K
DQd
DQd
VSS
CLK
Vss
DQa
DQa
L
DQd
DQd
BWd
NC
BWa
DQa
DQa
M
VDDQ
DQd
VSS
CKE
Vss
DQa
VDDQ
N
DQd
DQd
VSS
A 1*
Vss
DQa
DQa
P
DQd
DQPd
VSS
A0*
Vss
DQPa
DQa
R
NC
A
MODE
VDD
NC
A
NC
T
NC
NC
A
A
A
NC
ZZ
U
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
Note: A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
A0, A1
ADV Pin Name
Address Inputs
Synchronous Burst Address Inputs
Synchronous Burst Address Advance/
Load
WE
Synchronous Read/Write Control Input
CLK Synchronous Clock
CKE
Clock Enable
CE
Synchronous Chip Select
CE2
Synchronous Chip Select
CE2
Synchronous Chip Select
BWx (x=a-d) Synchronous Byte Write Inputs
OE
ZZ
MODE
TCK, TDO
TMS, TDI
Vdd
Vss
NC
DQa-DQd
DQPa-Pd
Vddq
Output Enable
Power Sleep Mode Burst Sequence Selection
JTAG Pins
Power Supply
Ground
No Connect
Data Inputs/Outputs
Parity Data I/O
Output Power Supply
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-47745
Rev. J
08/25/2014
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A 165-PIN PBGA PACKAGE CONFIGURATION
512K x 18 (TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
A
NC
A
BWb
NC
CE2
CKE
ADV
B
NC
A
CE
CE2
A
NC
A
A
C
NC
NC
VDDQ
NC
Vss
BWa
Vss
CLK
Vss
WE
Vss
D
NC
DQb
VDDQ
VDD
Vss
Vss
Vss
OE
Vss
VDD
A
VDDQ
NC
NC
DQPa
VDDQ
NC
DQa
E
NC
DQb
VDDQ
VDD
Vss
Vss
Vss
VDD
VDDQ
NC
DQa
F
NC
DQb
VDDQ
VDD
Vss
Vss
Vss
VDD
VDDQ
NC
DQa
G
NC
DQb
VDDQ
Vss
H
NC
NC
NC
VDD
VDD
Vss
Vss
Vss
Vss
VDD
VDD
VDDQ
NC
DQa
J
DQb
NC
VDDQ
VDD
Vss
Vss
NC
NC
ZZ
Vss
Vss
VDD
VDDQ
DQa
NC
K
DQb
NC
VDDQ
VDD
Vss
Vss
Vss
VDD
VDDQ
DQa
VDD
Vss
Vss
VDD
VDDQ
DQa
VDDQ
VDD
Vss
Vss
Vss
NC
NC
L
DQb
NC
VDDQ
M
DQb
NC
Vss
VDD
VDDQ
DQa
NC
N
DQPb
NC
Vss
A
NC
TDI
NC
NC
Vss
NC
TDO
A
A
NC
NC
A
A
TMS
A1*
A0*
VDDQ
A
NC
NC
VDDQ
A
P
NC
R
MODE
TCK
A
A
A
A
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
A0, A1
ADV Pin Name
Address Inputs
Synchronous Burst Address Inputs
Synchronous Burst Address Advance/
Load
WE
Synchronous Read/Write Control
Input
CLK Synchronous Clock
CKE
Clock Enable
CE, CE2, CE2 Synchronous Chip Enable
BWx (x=a,b) Synchronous Byte Write Inputs
OE
Output Enable
ZZ
Power Sleep Mode 6
MODE TCK, TDI
TDO, TMS
VDD
NC
DQx
DQPx VDDQ
Vss
Burst Sequence Selection
JTAG Pins
3.3V/2.5V Power Supply
No Connect
Data Inputs/Outputs
Parity Data I/O
Isolated output Power Supply 3.3V/2.5V
Ground
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. J
08/25/2014
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A 119-PIN PBGA PACKAGE CONFIGURATION
512K x 18 (TOP VIEW)
1
2
3
4
5
6
7
A
VDDQ
A
A
NC
A
A
VDDQ
B
NC
CE2
A
ADV
A
CE2
NC
C
NC
A
A
VDD
A
A
NC
D
DQb
NC
VSS
NC
Vss
DQPa
NC
E
DQb
VSS
CE
Vss
NC
DQa
F
NC
VDDQ
NC
VSS
OE
Vss
DQa
VDDQ
G
NC
DQb
BWb
A
NC
NC
DQa
H
DQb
NC
WE
Vss
DQa
NC
J
VDDQ
VDD
VSS
NC
VDD
NC
VDD
VDDQ
K
NC
DQb
VSS
CLK
Vss
NC
DQa
L
DQb
NC
NC
NC
BWa
DQa
NC
M
VDDQ
DQb
VSS
CKE
Vss
NC
VDDQ
N
DQb
NC
VSS
A 1*
Vss
DQa
NC
P
NC
DQPb
VSS
A0*
Vss
NC
DQa
R
NC
A
MODE
VDD
NC
A
NC
T
NC
A
A
NC
A
A
ZZ
U
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
Note: A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
A0, A1
ADV WE
CLK CKE
CE
CE2
CE2
BWx (x=a,b)
Pin Name
Address Inputs
Synchronous Burst Address Inputs
Synchronous Burst Address Advance/
Load
Synchronous Read/Write Control
Input
Synchronous Clock
Clock Enable
Synchronous Chip Select
Synchronous Chip Select
Synchronous Chip Select
Synchronous Byte Write Inputs
OE
ZZ
MODE
TCK, TDO
TMS, TDI
Vdd
Vss
NC
DQa-DQb
DQPa-Pb
Vddq
Output Enable
Power Sleep Mode Burst Sequence Selection
JTAG Pins
Power Supply
Ground
No Connect
Data Inputs/Outputs
Parity Data I/O
Output Power Supply
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-47747
Rev. J
08/25/2014
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A PIN CONFIGURATION
DQa
DQb
DQa
DQb
VDDQ
VDDQ
Vss
NC
Vss
DQa
Vss
DQb
DQa
DQb
DQa
DQa
Vss
DQPb
NC
VDDQ
VDDQ
DQa
DQa
DQPa
NC
NC
NC
Vss
A
ADV
NC
OE
CKE
CLK
WE
CE2
VDD
Vss
BWa
NC
BWb
NC
CE2
CE
A
A
A
NC
NC
VDDQ
Vss
NC
DQPa
DQa
DQa
Vss
VDDQ
DQa
DQa
Vss
NC
VDD
ZZ
DQa
DQa
VDDQ
Vss
DQa
DQa
NC
NC
Vss
VDDQ
NC
NC
NC
A
A
DQb
NC
VDD
A
DQb
Vss
NC
VDD
ZZ
A
DQb
A
VDDQ
DQb
A
VDDQ
NC
A
Vss
NC
DQb
VDD
Vss
DQb
Vss
DQb
NC
NC
NC
NC
DQb
Vss
A1
A0
MODE
DQd
DQd
DQPd
DQb
DQb
VDDQ
A
VDDQ
Vss
NC
A
DQd
DQd
Vss
VDDQ
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A
DQd
DQb
NC
A
Vss
DQd
DQb
MODE
VDDQ
DQPb
A
A
DQd
A
DQd
A
NC
Vss
A
DQc
NC
VDD
A
DQc
NC
A
VDDQ
NC
Vss
Vss
DQc
VDD
DQc
NC
NC
DQc
DQc
A1
A0
Vss
A
VDDQ
A
DQc
A
DQc
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A
DQPc
A
A
A
A
A
OE
ADV
NC
CKE
CLK
WE
CE2
VDD
Vss
BWa
BWc
BWb
BWd
CE2
CE
A
A
100-Pin TQFP
512K x 18
256K x 36
PIN DESCRIPTIONS
A0, A1
A
CLK ADV BWa-BWd
WE
CKE
Vss
NC
8
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
Synchronous Address Inputs
Synchronous Clock
Synchronous Burst Address Advance
Synchronous Byte Write Enable
Write Enable
Clock Enable
Ground for Core
Not Connected
CE, CE2, CE2 Synchronous Chip Enable
OE Output Enable
DQa-DQd
Synchronous Data Input/Output
DQPa-DQPd Parity Data I/O
MODE Burst Sequence Selection
Vdd
+3.3V/2.5V Power Supply
Vss
Ground for output Buffer
Vddq
Isolated Output Buffer Supply: +3.3V/2.5V
ZZ Snooze Enable
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. J
08/25/2014
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A STATE DIAGRAM
READ
READ
READ
BURST
WRITE
BEGIN
READ
DS
DS
READ
WRITE
DESELECT
BURST
BURST
READ
BEGIN
WRITE
BURST
DS
BURST
DS
DS
WRITE
READ
BURST
WRITE
WRITE
WRITE
BURST
SYNCHRONOUS TRUTH TABLE(1)
Address
OperationUsed
CECE2CE2
Not Selected N/A
H
X
X
Not Selected
N/A
X
L
X
Not Selected
N/A
X
X
H
Not Selected Continue
N/A
X
X
X
Begin Burst Read
External Address
L
H
L
Continue Burst Read
Next Address
X
X
X
NOP/Dummy Read
External Address
L
H
L
Dummy Read
Next Address
X
X
X
Begin Burst Write
External Address
L
H
L
Continue Burst Write
Next Address
X
X
X
NOP/Write Abort
N/A
L
H
L
Write Abort
Next Address
X
X
X
Ignore Clock
Current Address
X
X
X
Notes:
ADVWE
L
X
L
X
L
X
H
X
L
H
H
X
L
H
H
X
L
L
H
X
L
L
H
X
X
X
BWx
X
X
X
X
X
X
X
X
L
L
H
H
X
OE
X
X
X
X
L
L
H
H
X
X
X
X
X
CKE
L
L
L
L
L
L
L
L
L
L
L
L
H
CLK
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
1. "X" means don't care.
2. The rising edge of clock is symbolized by ↑
3. A continue deselect cycle can only be entered if a deselect cycle is executed first.
4. WE = L means Write operation in Write Truth Table.
WE = H means Read operation in Write Truth Table.
5. Operation finally depends on status of asynchronous pins (ZZ and OE).
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-47749
Rev. J
08/25/2014
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A ASYNCHRONOUS TRUTH TABLE(1)
OperationZZ
OE
Sleep Mode
H
X
Read
L
L
L
H
Write
L
X
Deselected
L
X
Notes:
I/O STATUS
High-Z
DQ
High-Z
Din, High-Z
High-Z
1. X means "Don't Care".
2. For write cycles following read cycles, the output buffers must be disabled with OE, otherwise data
bus contention will occur.
3. Sleep Mode means power Sleep Mode where stand-by current does not depend on cycle time.
4. Deselected means power Sleep Mode where stand-by current depends on cycle time.
WRITE TRUTH TABLE (x18)
Operation
READ
WRITE BYTE a
WRITE BYTE b
WRITE ALL BYTEs
WRITE ABORT/NOP
Notes:
WEBWaBWb
H
X
X
L
L
H
L
H
L
L
L
L
L
H
H
1. X means "Don't Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK.
10
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. J
08/25/2014
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A WRITE TRUTH TABLE (x36)
Operation
READ
WRITE BYTE a
WRITE BYTE b
WRITE BYTE c
WRITE BYTE d
WRITE ALL BYTEs
WRITE ABORT/NOP
Notes:
WEBWaBWbBWcBWd
H
X
X
X
X
L
L
H
H
H
L
H
L
H
H
L
H
H
L
H
L
H
H
H
L
L
L
L
L
L
L
H
H
H
H
1. X means "Don't Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK.
INTERLEAVED BURST ADDRESS TABLE (MODE = Vdd or NC)
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A1 A0
A1 A0
A1 A0
A1 A0
00011011
01001110
10110001
11100100
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Rev. J
08/25/2014
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A LINEAR BURST ADDRESS TABLE (MODE = Vss) 0,0
A1', A0' = 1,1
0,1
1,0
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Tstg
Pd
Iout
Vin, Vout
Vin
Parameter
Value
Storage Temperature
–65 to +150
Power Dissipation
1.6
Output Current (per I/O)
100
Voltage Relative to Vss for I/O Pins
–0.5 to Vddq + 0.3
Voltage Relative to Vss for –0.3 to 4.6
for Address and Control Inputs
Unit
°C
W
mA
V
V
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
OPERATING RANGE (IS61NLPx)
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
-40°C to +85°C
Vdd
3.3V ± 5%
3.3V ± 5%
Vddq
3.3V / 2.5V ± 5%
3.3V / 2.5V ± 5%
Vdd
2.5V ± 5%
2.5V ± 5%
Vddq
2.5V ± 5%
2.5V ± 5%
OPERATING RANGE (IS61NVPx)
Range
Commercial
Industrial
12
Ambient Temperature
0°C to +70°C
-40°C to +85°C
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Rev. J
08/25/2014
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol
Parameter
Voh
Output HIGH Voltage
Vol
Output LOW Voltage
Vih
Input HIGH Voltage Vil
Input LOW Voltage
Ili
Input Leakage Current
Ilo
Output Leakage Current
3.3V2.5V
Test Conditions
Min.Max. Min.Max.
Ioh = –4.0 mA (3.3V)
2.4
—
2.0
—
Ioh = –1.0 mA (2.5V)
Iol = 8.0 mA (3.3V)
—
0.4
—
0.4
Iol = 1.0 mA (2.5V)
2.0
Vdd + 0.31.7
Vdd + 0.3
–0.3
0.8
–0.3
0.7
(1)
Vss ≤ Vin ≤ Vdd –5
5
–5
5
Vss ≤ Vout ≤ Vddq, OE = Vih
–5
5
–5
5
Unit
V
V
V
V
µA
µA
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter
Test Conditions
Temp. range Icc
AC Operating
Device Selected, Com.
Supply Current
OE = Vih, ZZ ≤ Vil, Ind.
All Inputs ≤ 0.2V or ≥ Vdd – 0.2V,
Cycle Time ≥ tkc min.
Isb
Standby Current
Device Deselected, Com.
TTL Input
Vdd = Max.,
Ind.
All Inputs ≤ Vil or ≥ Vih,
ZZ ≤ Vil, f = Max.
Isbi
Standby Current
Device Deselected,
Com.
CMOS Input
Vdd = Max.,
Ind.
Vin ≤ Vss + 0.2V or ≥Vdd – 0.2V
f=0
Isb2
Sleep Mode
ZZ>Vih Com.
Ind.
-250-200
MAXMAX
x18
x36
x18 x36
280 280
270 270
300 300
280280
Unit
mA
100 100
100 100
100 100
mA
100100
70
70
80 80
70
70
8080
mA
45
50
45
50
mA
45
50
45
50
Note:
1. MODE pin has an internal pullup and should be tied to Vdd or Vss. It exhibits ±100µA maximum leakage current when tied to ≤
Vss + 0.2V or ≥ Vdd – 0.2V.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-477413
Rev. J
08/25/2014
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A CAPACITANCE(1,2)
Symbol
Cin
Cout
Parameter
Input Capacitance
Input/Output Capacitance
Conditions
Vin = 0V
Vout = 0V
Max.
6
8
Unit
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: Ta = 25°C, f = 1 MHz, Vdd = 3.3V.
3.3V I/O AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0V to 3.0V
1.5 ns
1.5V
See Figures 1 and 2
3.3V I/O OUTPUT LOAD EQUIVALENT
317 Ω
+3.3V
Zo= 50Ω
OUTPUT
OUTPUT
50Ω
5 pF
Including
jig and
scope
351 Ω
1.5V
Figure 1
14
Figure 2
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Rev. J
08/25/2014
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A 2.5V I/O AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0V to 2.5V
1.5 ns
1.25V
See Figures 3 and 4
2.5V I/O OUTPUT LOAD EQUIVALENT
1,667 Ω
+2.5V
ZO = 50Ω
OUTPUT
OUTPUT
50Ω
5 pF
Including
jig and
scope
1,538 Ω
1.25V
Figure 3
Figure 4
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Rev. J
08/25/2014
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A READ/WRITE CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Parameter
Clock Frequency
Cycle Time
Clock High Time
Clock Low Time
Clock Access Time Clock High to Output Invalid
Clock High to Output Low-Z
Clock High to Output High-Z Output Enable to Output Valid Output Enable to Output Low-Z
-250-200
Min. Max.
Min.Max.
—
250
— 200
4.0
—
5
—
1.7
—
2
—
1.7
—
2
—
—
2.6
— 3.1
0.8
—
1.5 —
0.8
—
1
—
—
2.6
— 3.1
—
2.6
— 3.1
0
—
0
—
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
Output Disable to Output High-Z Address Setup Time Read/Write Setup Time Chip Enable Setup Time Clock Enable Setup Time
Address Advance Setup Time Data Setup Time
Address Hold Time Clock Enable Hold Time
Write Hold Time Chip Enable Hold Time Address Advance Hold Time Data Hold Time
ZZ High to Power Down ZZ Low to Power Down —
1.2
1.2
1.2
1.2
1.2
1.2
0.3
0.3
0.3
0.3
0.3
0.3
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cyc
cyc
Symbol
fmax
tkc
tkh
tkl
tkq
tkqx(2)
tkqlz(2,3)
tkqhz(2,3)
toeq
toelz(2,3)
toehz(2,3)
tas
tws
tces
tse
tadvs
tds
tah
the
twh
tceh
tadvh
tdh
tpds
tpus
Notes:
2.6
—
—
—
—
—
—
—
—
—
—
—
—
2
2
— 3.0
1.4 —
1.4 —
1.4 —
1.4 —
1.4 —
1.4 —
0.4—
0.4 —
0.4 —
0.4 —
0.4 —
0.4 —
—
2
—
2
1. Configuration signal MODE is static and must not change during normal operation.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with load in Figure 2.
16
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Rev. J
08/25/2014
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A SLEEP MODE ELECTRICAL CHARACTERISTICS
Symbol Parameter
Conditions
Isb2
Current during SLEEP MODE
ZZ ≥ Vih
tpds
ZZ active to input ignored
tpus
ZZ inactive to input sampled
tzzi
ZZ active to SLEEP current
trzzi
ZZ inactive to exit SLEEP current
Min.
Max.
60
2
2
2
0
Unit
mA
cycle
cycle
cycle
ns
SLEEP MODE TIMING
CLK
tPDS
ZZ setup cycle
tPUS
ZZ recovery cycle
ZZ
tZZI
Isupply
ISB2
tRZZI
All Inputs
(except ZZ)
Deselect or Read Only
Deselect or Read Only
Normal
operation
cycle
Outputs
(Q)
High-Z
Don't Care
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Rev. J
08/25/2014
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A READ CYCLE TIMING
tKH tKL
CLK
tKC
tADVS tADVH
ADV
tAS tAH
Address
A2
A1
A3
tWS tWH
/WRITE
tSE tHE
/CKE
tCES tCEH
/CE
/OE
tOEQ
tOEHZ
Data Out
Q1-1
tOEHZ
tKQ
tKQX
Q2-1
Q2-2
tKQHZ
Q2-3
Q2-4
Q3-1
NOTES: /WRITE = L means /WE = L and /BW X =L
/CE = L means /CE1 = L, CE2 = H and /CE2 = L
/CE = H means /CE1 = H, or /CE1 = L and /CE2 = H, or /CE1 = L and CE2 = L
18
Q3-2
Q3-3
Q3-4
Don't Care
Undefined
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Rev. J
08/25/2014
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A WRITE CYCLE TIMING
tKH tKL
CLK
tKC
ADV
Address
A1
A3
A2
WRITE
tSE tHE
CKE
CE
OE
tDS
Data In
D1-1
D2-1
D2-2
D2-3
D2-4
D3-1
tDH
D3-2
D3-3
D3-4
tOEHZ
Data Out
Q0-3
Q0-4
NOTES: WRITE = L means WE = L and BWx = L
WE = L and BWX = L
CE = L means CE1 = L, CE2 = H and CE2 = L
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
Don't Care
Undefined
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Rev. J
08/25/2014
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A SINGLE READ/WRITE CYCLE TIMING
tKH
tKL
CLK
tSE tHE
tKC
CKE
Address
A1
A2
A3
A4
Q1
Q3
A5
A6
A7
A8
A9
WRITE
CE
ADV
OE
tOEQ
Data Out
tOELZ
Q4
Q6
Q7
tDS tDH
Data In
D5
D2
NOTES: WRITE = L means WE = L and BWx = L
CE = L means CE1 = L, CE2 = H and CE2 = L
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
20
Don't Care
Undefined
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Rev. J
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IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A CKE OPERATION TIMING
tKH
tKL
CLK
tSE tHE
tKC
CKE
Address
A1
A2
A3
A4
A5
A6
WRITE
CE
ADV
OE
tKQ
Data Out
tKQLZ
tKQHZ
Q1
Q3
Q4
tDS tDH
Data In
D2
NOTES: WRITE = L means WE = L and BWx = L
CE = L means CE1 = L, CE2 = H and CE2 = L
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
Don't Care
Undefined
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Rev. J
08/25/2014
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A CE OPERATION TIMING
tKH
tKL
CLK
tSE tHE
tKC
CKE
Address
A1
A2
A3
A4
A5
WRITE
CE
ADV
OE
tOEQ
Data Out
tOELZ
tKQHZ
Q1
tKQ
tKQLZ
Q2
Q4
tDS tDH
Data In
D3
NOTES: WRITE = L means WE = L and BWx = L
CE = L means CE1 = L, CE2 = H and CE2 = L
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
22
D5
Don't Care
Undefined
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Rev. J
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IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A IEEE 1149.1 Serial Boundary Scan (JTAG)
Test Access Port (TAP) - Test Clock
The IS61NLP and IS61NVP have a serial boundary scan
Test Access Port (TAP) in the PBGA package only. (Not
available in TQFP package.) This port operates in accordance with IEEE Standard 1149.1-1900, but does not
include all functions required for full 1149.1 compliance.
These functions from the IEEE specification are excluded
because they place added delay in the critical speed path
of the SRAM. The TAP controller operates in a manner that
does not conflict with the performance of other devices using 1149.1 fully compliant TAPs. The TAP operates using
JEDEC standard 2.5V I/O logic levels.
The test clock is only used with the TAP controller. All inputs
are captured on the rising edge of TCK and outputs are
driven from the falling edge of TCK.
Disabling the JTAG Feature
The SRAM can operate without using the JTAG feature.
To disable the TAP controller, TCK must be tied LOW
(Vss) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be disconnected. They may
alternately be connected to Vdd through a pull-up resistor.
TDO should be left disconnected. On power-up, the device
will start in a reset state which will not interfere with the
device operation.
Test Mode Select (TMS)
The TMS input is used to send commands to the TAP
controller and is sampled on the rising edge of TCK. This
pin may be left disconnected if the TAP is not used. The pin
is internally pulled up, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information to the
registers and can be connected to the input of any register. The register between TDI and TDO is chosen by the
instruction loaded into the TAP instruction register. For
information on instruction register loading, see the TAP
Controller State Diagram. TDI is internally pulled up and
can be disconnected if the TAP is unused in an application. TDI is connected to the Most Significant Bit (MSB)
on any register.
tap controller block diagram
0
Bypass Register
2
1
0
Instruction Register
TDI
Selection Circuitry
31 30 29
. . .
Selection Circuitry
2
1
0
2
1
0
TDO
Identification Register
x
. . . . .
Boundary Scan Register*
TCK
TMS
TAP CONTROLLER
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Rev. J
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IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A Test Data Out (TDO)
The TDO output pin is used to serially clock data-out from
the registers. The output is active depending on the current
state of the TAP state machine (see TAP Controller State
Diagram). The output changes on the falling edge of TCK
and TDO is connected to the Least Significant Bit (LSB)
of any register.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (Vdd) for five
rising edges of TCK. RESET may be performed while the
SRAM is operating and does not affect its operation. At
power-up, the TAP is internally reset to ensure that TDO
comes up in a high-Z state.
TAP Registers
Registers are connected between the TDI and TDO pins
and allow data to be scanned into and out of the SRAM
test circuitry. Only one register can be selected at a time
through the instruction registers. Data is serially loaded
into the TDI pin on the rising edge of TCK and output on
the TDO pin on the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed
between the TDI and TDO pins. (See TAP Controller Block
Diagram) At power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the
IDCODE instruction if the controller is placed in a reset
state as previously described.
When the TAP controller is in the CaptureIR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers,
it is sometimes advantageous to skip certain states. The
bypass register is a single-bit register that can be placed
between TDI and TDO pins. This allows data to be shifted
through the SRAM with minimal delay. The bypass register is set LOW (Vss) when the BYPASS instruction is
executed.
Boundary Scan Register
The boundary scan register is connected to all input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices. The x36 configuration has a 75-bit-long
register and the x18 configuration also has a 75-bit-long
register. The boundary scan register is loaded with the
contents of the RAM Input and Output ring when the TAP
controller is in the Capture-DR state and then placed between the TDI and TDO pins when the controller is moved
to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD
and SAMPLE-Z instructions can be used to capture the
contents of the Input and Output ring.
The Boundary Scan Order tables show the order in which
the bits are connected. Each bit corresponds to one of the
bumps on the SRAM package. The MSB of the register is
connected to TDI, and the LSB is connected to TDO.
Scan Register Sizes
Register Bit Size
Bit Size Name
(x18)(x36)
Instruction
33
Bypass
1
1
ID
3232
Boundary Scan
75
75
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit
code during the Capture-DR state when the IDCODE command is loaded to the instruction register. The IDCODE
is hardwired into the SRAM and can be shifted out when
the TAP controller is in the Shift-DR state. The ID register
has vendor code and other information described in the
Identification Register Definitions table.
Identification Register Definitions
Instruction Field
Description
Revision Number (31:28) Reserved for version number.
Device Depth (27:23)
Defines depth of SRAM. 256K or 512K
Device Width (22:18)
Defines width of the SRAM. x36 or x18
ISSI Device ID (17:12)
Reserved for future use.
ISSI JEDEC ID (11:1)
Allows unique identification of SRAM vendor.
ID Register Presence (0) Indicate the presence of an ID register.
24
256K x 36
512K x 18
xxxx
xxxx
00111
01000
00100
00011
xxxxx
xxxxx
00011010101 00011010101
1
1
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Rev. J
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IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A TAP Instruction Set
SAMPLE/PRELOAD
Eight instructions are possible with the three-bit instruction
register and all combinations are listed in the Instruction
Code table. Three instructions are listed as RESERVED
and should not be used and the other five instructions are
described below. The TAP controller used in this SRAM
is not fully compliant with the 1149.1 convention because
some mandatory instructions are not fully implemented.
The TAP controller cannot be used to load address, data or
control signals and cannot preload the Input or Output buffers. The SRAM does not implement the 1149.1 commands
EXTEST or INTEST or the PRELOAD portion of SAMPLE/
PRELOAD; instead it performs a capture of the Inputs and
Output ring when these instructions are executed. Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI
and TDO. During this state, instructions are shifted from
the instruction register through the TDI and TDO pins. To
execute an instruction once it is shifted in, the TAP controller must be moved into the Update-IR state.
SAMPLE/PRELOAD is a 1149.1 mandatory instruction.The
PRELOAD portion of this instruction is not implemented, so
the TAP controller is not fully 1149.1 compliant. When the
SAMPLE/PRELOAD instruction is loaded to the instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
It is important to realize that the TAP controller clock operates at a frequency up to 10 MHz, while the SRAM clock
runs more than an order of magnitude faster. Because of
the clock frequency differences, it is possible that during
the Capture-DR state, an input or output will under-go a
transition. The TAP may attempt a signal capture while in
transition (metastable state).The device will not be harmed,
but there is no guarantee of the value that will be captured
or repeatable results.
To guarantee that the boundary scan register will capture
the correct signal value, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture set-up
plus hold times (tcs and tch). To insure that the SRAM clock
input is captured correctly, designs need a way to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction.
If this is not an issue, it is possible to capture all other
signals and simply ignore the value of the CLK captured
in the boundary scan register.
Once the data is captured, it is possible to shift out the data
by putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
Note that since the PRELOAD part of the command is not
implemented, putting the TAP into the Update to the UpdateDR state while performing a SAMPLE/PRELOAD instruction
will have the same effect as the Pause-DR command.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with
all 0s. Because EXTEST is not implemented in the TAP
controller, this device is not 1149.1 standard compliant.
The TAP controller recognizes an all-0 instruction. When an
EXTEST instruction is loaded into the instruction register,
the SRAM responds as if a SAMPLE/PRELOAD instruction
has been loaded. There is a difference between the instructions, unlike the SAMPLE/PRELOAD instruction, EXTEST
places the SRAM outputs in a High-Z state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit
code to be loaded into the instruction register. It also places
the instruction register between the TDI and TDO pins
and allows the IDCODE to be shifted out of the device
when the TAP controller enters the Shift-DR state. The
IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a
test logic reset state.
Bypass
When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state,
the bypass register is placed between the TDI and TDO
pins. The advantage of the BYPASS instruction is that it
shortens the boundary scan path when multiple devices
are connected together on a board.
SAMPLE-Z
Reserved
The SAMPLE-Z instruction causes the boundary scan
register to be connected between the TDI and TDO pins
when the TAP controller is in a Shift-DR state. It also places
all SRAM outputs into a High-Z state.
These instructions are not implemented but are reserved
for future use. Do not use these instructions.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-477425
Rev. J
08/25/2014
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A Instruction Codes
Code InstructionDescription
000
EXTEST
Captures the Input/Output ring contents. Places the boundary scan register between the TDI and TDO. Forces all SRAM outputs to High-Z state. This
instruction is not 1149.1 compliant.
001
IDCODE
Loads the ID register with the vendor ID code and places the register between TDI
and TDO. This operation does not affect SRAM operation.
010
SAMPLE-Z
Captures the Input/Output contents. Places the boundary scan register between
TDI and TDO. Forces all SRAM output drivers to a High-Z state.
011
RESERVED
Do Not Use: This instruction is reserved for future use.
100
SAMPLE/PRELOAD
Captures the Input/Output ring contents. Places the boundary scan register
between TDI and TDO. Does not affect the SRAM operation. This instruction does not
implement 1149.1 preload function and is therefore not 1149.1 compliant.
101
RESERVED
Do Not Use: This instruction is reserved for future use. 110 RESERVED
Do Not Use: This instruction is reserved for future use.
111
BYPASS
Places the bypass register between TDI and TDO. This operation does not
affect SRAM operation.
TAP CONTROLLER STATE DIAGRAM
Test Logic Reset
1
0
Run Test/Idle
1
Select DR
0
0
1
1
1
Capture DR
0
Shift DR
1
Exit1 DR
0
Select IR
0
1
Exit1 IR
0
Pause DR
0
1
0
1
26
Exit2 DR
1
Update DR
0
Capture IR
0
Shift IR
1
0
Pause IR
1
0
1
1
0
1
0
Exit2 IR
1
Update IR
0
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. J
08/25/2014
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A TAP Electrical Characteristics Over the Operating Range(1,2)
Symbol
Voh1
Voh2
Vol1
Vol2
Vih
Vil
Ix
Notes:
Parameter
Test Conditions
Min.
Max.
Units
Output HIGH Voltage
Ioh = –2.0 mA
1.7
—
V
Output HIGH Voltage
Ioh = –100 µA
2.1
—
V
Output LOW Voltage
Iol = 2.0 mA—
0.7
V
Output LOW Voltage
Iol = 100 µA—
0.2
V
Input HIGH Voltage
1.7
Vdd +0.3
V
Input LOW Voltage
–0.3
0.7
V
Input Leakage Current
Vss ≤ V I ≤ Vddq
–10
10
µA
1. All Voltage referenced to Ground.
2. Overshoot: Vih (AC) ≤ Vdd +1.5V for t ≤ ttcyc/2,
Undershoot: Vil (AC) ≤ 0.5V for t ≤ ttcyc/2,
Power-up: Vih < 2.6V and Vdd < 2.4V and Vddq < 1.4V for t < 200 ms.
TAP AC ELECTRICAL CHARACTERISTICS(1,2) (Over Operating Range)
SymbolParameter Min.
Max.Unit
ttcyc
TCK Clock cycle time
100— ns
ftf
TCK Clock frequency—
10MHz
tth
TCK Clock HIGH
40—
ns
ttl
TCK Clock LOW
40
—ns
ttmss
TMS setup to TCK Clock Rise 10— ns
ttdis
TDI setup to TCK Clock Rise 10— ns
tcs
Capture setup to TCK Rise10— ns
ttmsh
TMS hold after TCK Clock Rise 10— ns
ttdih
TDI Hold after Clock Rise
10— ns
tch
Capture hold after Clock Rise 10— ns
ttdov
TCK LOW to TDO valid—
20
ns
ttdox
TCK LOW to TDO invalid
0— ns
Notes:
1. Both tcs and tch refer to the set-up and hold time requirements of latching data from the boundary scan register.
2. Test conditions are specified using the load in TAP AC test conditions. tr/tf = 1 ns.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-477427
Rev. J
08/25/2014
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A TAP AC TEST CONDITIONS (2.5V/3.3V)
TAP Output Load Equivalent
Input pulse levels
0 to 2.5V/0 to 3.0V
Input rise and fall times
1ns
Input timing reference levels
1.25V/1.5V
Output reference levels
1.25V/1.5V
Test load termination supply voltage
1.25V/1.5V
Vtrig
1.25V/1.5V
50Ω
Vtrig
TDO
Z0 = 50Ω
20 pF
GND
Tap timing
1
2
tTHTH
3
4
5
6
tTLTH
TCK
tTHTL
tMVTH tTHMX
TMS
tDVTH tTHDX
TDI
tTLOV
TDO
tTLOX
DON'T CARE
UNDEFINED
28
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. J
08/25/2014
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A 165 Pbga Boundary Scan Order (x 36)
SignalBump
Bit # Name ID
1
MODE 1R
2
NC
6N
3
NC
11P
4
A
8P
5
A
8R
6
A
9R
7
A
9P
8
A
10P
9
A
10R
10
A
11R
11
ZZ
11H
12
DQa 11N
13
DQa 11M
14
DQa 11L
15
DQa 11K
16
DQa 11J
17
DQa 10M
18
DQa 10L
19
DQa 10K
20
DQa 10J
Bit #
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
SignalBump
Name
ID
Bit #
DQb
11G
41
DQb
11F
42
DQb
11E
43
DQb
11D
44
DQb
10G
45
DQb
10F
46
DQb
10E
47
DQb
10D
48
DQb
11C
49
NC
11A
50
A
10A
51
A
10B
52
A
9A
53
NC
9B
54
ADV
8A
55
OE
8B
56
CKE
7A
57
WE
7B
58
CLK
6B
59
NC
11B
60
Signal Bump
Name
ID
NC
1A
CE2
6A
BWa
5B
BWb
5A
BWc
4A
BWd
4B
CE2
3B
CE
3A
A
2A
A
2B
NC
1B
DQc
1C
DQc
1D
DQc
1E
DQc
1F
DQc
1G
DQc
2D
DQc
2E
DQc
2F
DQc
2G
Bit #
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
SignalBump
Name
ID
DQd
1J
DQd
1K
DQd
1L
DQd
1M
DQd
2J
DQd
2K
DQd
2L
DQd
2M
DQd
1N
A
3P
A
3R
A
4R
A
4P
A1
6P
A0
6R
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-477429
Rev. J
08/25/2014
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A 119 bga Boundary Scan Order (x 36)
30
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. J
08/25/2014
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A 165 Pbga Boundary Scan Order (x 18)
SignalBump
Bit # Name ID
1
MODE 1R
2
NC
6N
3
NC
11P
4
A
8P
5
A
8R
6
A
9R
7
A
9P
8
A
10P
9
A
10R
10
A
11R
11
ZZ
11H
12
NC
11N
13
NC
11M
14
NC
11L
15
NC
11K
16
NC
11J
17
DQa 10M
18
DQa 10L
19
DQa 10K
20
DQa 10J
Bit #
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
SignalBump
Name
ID
Bit #
DQa
11G
41
DQa
11F
42
DQa
11E
43
DQa
11D
44
DQa
11C
45
NC
10F
46
NC
10E
47
NC
10D
48
NC
10G
49
A
11A
50
A
10A
51
A
10B
52
A
9A
53
NC
9B
54
ADV
8A
55
OE
8B
56
CKE
7A
57
WE
7B
58
CLK
6B
59
NC
11B
60
Signal Bump
Name
ID
NC
1A
CE2
6A
BWa
5B
NC
5A
BWb
4A
NC
4B
CE2
3B
CE
3A
A
2A
A
2B
NC
1B
NC
1C
NC
1D
NC
1E
NC
1F
NC
1G
DQb
2D
DQb
2E
DQb
2F
DQb
2G
Bit #
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
SignalBump
Name
ID
DQb
1J
DQb
1K
DQb
1L
DQb
1M
DQb
1N
NC
2K
NC
2L
NC
2M
NC
2J
A
3P
A
3R
A
4R
A
4P
A1
6P
A0
6R
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-477431
Rev. J
08/25/2014
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A 119 bga Boundary Scan Order (x 18)
32
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. J
08/25/2014
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A ORDERING INFORMATION (Vdd = 3.3V/Vddq = 2.5V/3.3V)
Commercial Range: 0°C to +70°C
Access Time
250
200
250
200
Order Part NumberPackage
256Kx36
IS61NLP25636A-250TQ
100 TQFP
IS61NLP25636A-250TQL 100 TQFP, Lead-free
IS61NLP25636A-250B3
165 PBGA IS61NLP25636A-250B2
119 PBGA
IS61NLP25636A-200TQ
100 TQFP
IS61NLP25636A-200TQL 100 TQFP, Lead-free
IS61NLP25636A-200B3
165 PBGA IS61NLP25636A-200B2
119 PBGA
512Kx18
IS61NLP51218A-250TQ
100 TQFP
IS61NLP51218A-250B3
165 PBGA IS61NLP51218A-250B2
119 PBGA
IS61NLP51218A-200TQ
100 TQFP
IS61NLP51218A-200B3
165 PBGA IS61NLP51218A-200B2
119 PBGA
Industrial Range: -40°C to +85°C
Access Time
Order Part Number
256Kx36
250
IS61NLP25636A-250TQI
IS61NLP25636A-250B3I
IS61NLP25636A-250B2I
200
IS61NLP25636A-200TQI
IS61NLP25636A-200TQLI
IS61NLP25636A-200B3I
IS61NLP25636A-200B3LI
IS61NLP25636A-200B2I
IS61NLP25636A-200B2LI
512Kx18
Package
100 TQFP
165 PBGA
119 PBGA
100 TQFP
100 TQFP, Lead-free
165 PBGA
119 PBGA
250
200
IS61NLP51218A-250TQI
IS61NLP51218A-250B3I
IS61NLP51218A-250B2I
IS61NLP51218A-200TQI
IS61NLP51218A-200TQLI
IS61NLP51218A-200B3I
IS61NLP51218A-200B2I
100 TQFP
165 PBGA
119 PBGA
100 TQFP
100 TQFP, Lead-free
165 PBGA
165 PBGA, Lead-free
119 PBGA
119 PBGA, Lead-free
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-477433
Rev. J
08/25/2014
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A ORDERING INFORMATION (Vdd = 2.5V/Vddq = 2.5V)
Commercial Range: 0°C to +70°C
Access Time
250
200
250
200
Order Part NumberPackage
256Kx36
IS61NVP25636A-250TQ
100 TQFP
IS61NVP25636A-250B3
165 PBGA
IS61NVP25636A-250B2
119 PBGA
IS61NVP25636A-200TQ
100 TQFP
IS61NVP25636A-200B3
165 PBGA
IS61NVP25636A-200B2
119 PBGA
512Kx18
IS61NVP51218A-250TQ
100 TQFP
IS61NVP51218A-250B3
165 PBGA
IS61NVP51218A-250B2
119 PBGA
IS61NVP51218A-200TQ
100 TQFP
IS61NVP51218A-200B3
165 PBGA
IS61NVP51218A-200B2
119 PBGA
Industrial Range: -40°C to +85°C
Access Time
Order Part Number
256Kx36
250
IS61NVP25636A-250TQI
IS61NVP25636A-250B3I
IS61NVP25636A-250B2I
200
IS61NVP25636A-200TQI
IS61NVP25636A-200TQLI
IS61NVP25636A-200B3I
IS61NVP25636A-200B3LI
IS61NVP25636A-200B2I
512Kx18
250
IS61NVP51218A-250TQI
IS61NVP51218A-250B3I
IS61NVP51218A-250B2I
200
IS61NVP51218A-200TQI
IS61NVP51218A-200B3I
IS61NVP51218A-200B2I
34
Package
100 TQFP
165 PBGA 119 PBGA
100 TQFP 100 TQFP, Leadfree
165 PBGA 165 PBGA, Leadfree
119 PBGA
100 TQFP
165 PBGA 119 PBGA
100 TQFP
165 PBGA 119 PBGA
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. J
08/25/2014
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-477435
Rev. J
08/25/2014
36
1. CONTROLLING DIMENSION : MM .
2. Reference document : JEDEC MS-028
NOTE :
Package Outline
10/02/2008
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. J
08/25/2014
Package Outline
1. CONTROLLING DIMENSION : MM .
NOTE :
08/28/2008
IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-477437
Rev. J
08/25/2014