IS62WV12816DALL/DBLL IS65WV12816DALL/DBLL

IS62WV12816DALL/DBLL
IS65WV12816DALL/DBLL
JUNE 2013
128K x 16 LOW VOLTAGE,
ULTRA LOW POWER CMOS STATIC RAM FEATURES
•
•
•
•
•
•
•
•
•
•
High-speed access time: 35ns, 45ns, 55ns
CMOS low power operation
– 36 mW (typical) operating
– 9 µW (typical) CMOS standby
TTL compatible interface levels
Single power supply – 1.8V ± 10% Vdd (IS62/65WV12816DALL)
– 2.5V--3.6V Vdd (IS62/65WV12816DBLL)
Fully static operation: no clock or refresh
required
Three state outputs
Data control for upper and lower bytes
Industrial and Autotmovie temperature support
2CS Option Available
Lead-free available
FUNCTIONAL BLOCK DIAGRAM
A0-A16
DESCRIPTION
The ISSI IS62/65WV12816DALL/DBLL are high-speed,
2M bit static RAMs organized as 128K words by 16
bits. It is fabricated using ISSI's high-performance
CMOS technology. This highly reliable process coupled
with innovative circuit design techniques, yields highperformance and low power consumption devices.
When CS1 is HIGH (deselected) or when CS2 is low
(deselected) or when CS1 is low, CS2 is high and both
LB and UB are HIGH, the device assumes a standby mode
at which the power dissipation can be reduced down with
CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs. The active LOW Write Enable
(WE) controls both writing and reading of the memory. A
data byte allows Upper Byte (UB) and Lower Byte (LB)
access.
The IS62/65WV12816DALL/DBLL are packaged in the
JEDEC standard 48-pin mini BGA (6mm x 8mm) and 44Pin TSOP (TYPE II).
DECODER
128K x 16
MEMORY ARRAY
I/O
DATA
CIRCUIT
COLUMN I/O
VDD
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
CS2
CS1
OE
WE
UB
LB
CONTROL
CIRCUIT
Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C
05/29/2013
1
IS62WV12816DALL/DBLL, IS65WV12816DALL/DBLL
PIN CONFIGURATIONS
48-Pin mini BGA (6mm x 8mm)
2 CS Option (Package Code B2)
48-Pin mini BGA (6mm x 8mm)
(Package Code B)
1
2
3
4
5
6
1
2
3
4
5
6
A
LB
OE
A0
A1
A2
N/C
A
LB
OE
A0
A1
A2
CS2
B
I/O8
UB
A3
A4
CSI
C
I/O9
I/O10
A5
A6
I/O1
I/O0
B
I/O8
UB
A3
A4
CS1
I/O0
I/O2
C
I/O9
I/O10
A5
A6
I/O1
I/O2
D
GND
I/O11
NC
A7
I/O3
VDD
D
GND
I/O11
NC
A7
I/O3
VDD
E
VDD
I/O12
NC
A16
I/O4
GND
E
VDD
I/O12
NC
A16
I/O4
GND
F
I/O14
I/O13
A14
A15
I/O5
I/O6
F
I/O14
I/O13
A14
A15
I/O5
I/O6
G
I/O15
NC
A12
A13
WE
I/O7
G
I/O15
NC
A12
A13
WE
I/O7
H
NC
A8
A9
A10
A11
NC
H
NC
A8
A9
A10
A11
NC
44-Pin mini TSOP (Type II)
(Package Code T)
A4
A3
A2
A1
A0
CS1
I/O0
I/O1
I/O2
I/O3
VDD
GND
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
PIN DESCRIPTIONS
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
VDD
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
A0-A16 Address Inputs
I/O0-I/O15
Data Inputs/Outputs
CS1, CS2 Chip Enable Input
OE Output Enable Input
WE Write Enable Input
LB
Lower-byte Control (I/O0-I/O7)
UB
Upper-byte Control (I/O8-I/O15)
NC
No Connection
Power
Vdd
GND
Ground
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
05/29/2013
IS62WV12816DALL/DBLL, IS65WV12816DALL/DBLL
TRUTH TABLE
I/O PIN
Mode
WE CS1 CS2 OE
LB
UB
I/O0-I/O7
I/O8-I/O15
Not Selected
X
H
X
X
X
X
High-Z
High-Z
X
X
L
X
X
X
High-Z
High-Z
X
X
X
X
H
H
High-Z
High-Z
Output Disabled
H
L
H
H
L
X
High-Z
High-Z
H
L
H
H
X
L
High-Z
High-Z
Read
H
L
H
L
L
H
Dout
High-Z
H
L
H
L
H
L
High-Z
Dout
H
L
H
L
L
LDoutDout
Write
L
L
H
X
L
H
Din
High-Z
L
L
H
X
H
L
High-Z
Din
L
L
H
X
L
LDinDin
Vdd Current
Isb1, Isb2
Isb1, Isb2
Isb1, Isb2
Icc
Icc
Icc
Icc
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Vterm
Tstg
Pt
Parameter
Terminal Voltage with Respect to GND
Storage Temperature
Power Dissipation
Value
–0.2 to Vdd+0.3
–65 to +150
1.0
Unit
V
°C
W
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
OPERATING RANGE (Vdd)
Range
Commercial
Industrial
Automotive
Ambient Temperature
0°C to +70°C
–40°C to +85°C
IS62WV12816DALL
1.8V ± 10%
1.8V ± 10%
IS62WV12816DBLL
2.5V - 3.6V
2.5V - 3.6V
IS65WV12816DALL
IS65WV12816DBLL
-40°C to +125°C
1.8V ± 10%
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
05/29/2013
2.5V - 3.6V
3
IS62WV12816DALL/DBLL, IS65WV12816DALL/DBLL
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
Test Conditions
Vdd
Voh
Output HIGH Voltage
Ioh = -0.1 mA
1.8V ± 10%
Ioh = -1 mA
2.5-3.6V
Vol
Output LOW Voltage
Iol = 0.1 mA
1.8V ± 10%
Iol = 1.0 mA
2.5-3.6V
Vih
Input HIGH Voltage
1.8V ± 10%
2.5-3.6V
Vil
Input LOW Voltage
1.8V ± 10%
2.5-3.6V
Ili
Input Leakage
GND ≤ Vin ≤ Vdd
Ilo
Output Leakage
GND ≤ Vout ≤ Vdd, Outputs Disabled
Min.
1.4
2.2
—
—
1.4
2.2
–0.2
–0.2
–1
–1
Max.
—
—
0.2
0.4
Vdd + 0.2
Vdd + 0.3
0.4
0.6
1
1
Unit
V
V
V
V
V
V
V
V
µA
µA
Notes:
For IS62/65WV12816DALL:
Vil (min.) = -1.0V AC (pluse width < 10ns). Not 100% tested.
Vih (max.) = Vdd + 1.0V AC; (pluse width < 10ns). Not 100% tested.
For IS62/65WV12816DBLL:
Vil (min.) = -2.0V AC (pluse width < 10ns). Not 100% tested.
Vih (max.) = Vdd + 2.0V AC; (pluse width < 10ns). Not 100% tested.
CAPACITANCE(1)
Symbol
Cin
Cout
Parameter
Input Capacitance
Input/Output Capacitance
Conditions
Vin = 0V
Vout = 0V
Max.
8
10
Unit
pF
pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
4
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
05/29/2013
IS62WV12816DALL/DBLL, IS65WV12816DALL/DBLL
IS62/65WV12816DALL, POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter
Test Conditions
Icc
Vdd Dynamic Operating Vdd = Max.,
Com.
Supply Current
Iout = 0 mA, f = fmax
Ind.
Auto.
Icc1
Operating Supply
Vdd = Max.,
Com.
Current
Iout = 0 mA, f = 0
Ind.
Auto.
Isb1
TTL Standby Current
CS2 = VIL
(TTL Inputs)
Isb2
CMOS Standby
Current (CMOS Inputs)
f = 0Hz
(1) 0V < CS2 < 0.2V
OR
(2) CS1 > VDD - 0.2V,
CS2 > VDD - 0.2V
OR
( 3) LB and UB > VDD- 0.2V
CS1 < 0.2V,
CS2 > VDD - 0.2V,
Unit
mA
mA
0.3
mA
0.3
0.5
4
µA
6
15
f= 0Hz
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
05/29/2013
Com.
Ind.
Auto.
Com.
Ind.
Auto.
Max.
55
15
20
25
3
3
4
5
IS62WV12816DALL/DBLL, IS65WV12816DALL/DBLL
IS62/65WV12816DBLL, POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter
Test Conditions
Icc
Vdd Dynamic Operating Vdd = Max.,
Com.
Supply Current
Iout = 0 mA, f = fmax
Ind.
Auto.
typ.(2)
Icc1
Operating Supply
Vdd = Max.,
Com.
Current
Iout = 0 mA, f = 0
Ind.
Auto.
Isb1
TTL Standby Current
CS2 = VIL
Com.
(TTL Inputs)
f = 0Hz
Ind.
Auto.
Isb2
CMOS Standby
(1) 0V < CS2 < 0.2V Com.
Current (CMOS Inputs) OR
Ind.
(2) CS1 > VDD - 0.2V,
Auto.
CS2 > VDD - 0.2V
typ.(2)
OR
(3) LB and UB > VDD- 0.2V
CS1 < 0.2V,
CS2 > VDD - 0.2V
f= 0Hz
Max
35
22
23
35
15
3
3
4
0.2
0.2
0.3
5
7
25
2
Max.
45
20
21
30
12
3
3
4
0.2
0.2
0.3
5
7
25
2
Max.
55
18
19
25
10
3
3
4
0.2
0.2
0.3
5
7 25
2
Unit
mA
mA
mA
µA
Note:
1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at Vdd = 3.0V, Ta = 25oC and not 100% tested.
6
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
05/29/2013
IS62WV12816DALL/DBLL, IS65WV12816DALL/DBLL
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
R1(Ω)
R2(Ω)
Vref
IS62/65WV12816DALL
(Unit)
0.4V to Vdd-0.2V
1V/1ns
Vref
See Figures 1 and 2
1.8V ± 10% 3070
3150
2.5V - 3.6V
3070
3150
0.9V
1.8V
1.5V
2.8V
Vtm
IS62/65WV12816DBLL
(Unit)
0.4V to Vdd-0.3V
1V/1ns
Vref
See Figures 1 and 2
AC TEST LOADS
R1
R1
VTM
VTM
OUTPUT
OUTPUT
30 pF
Including
jig and
scope
R2
Figure 1
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
05/29/2013
5 pF
Including
jig and
scope
R2
Figure 2
7
IS62WV12816DALL/DBLL, IS65WV12816DALL/DBLL
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol
trc
taa
toha
tacs1/tacs2
tdoe
thzoe(2)
tlzoe(2)
thzcs1/thzcs2(2)
tlzcs1/tlzcs2(2)
tba
thzb
tlzb
Parameter
Read Cycle Time
Address Access Time
Output Hold Time
CS1/CS2 Access Time
OE Access Time
OE to High-Z Output
OE to Low-Z Output
CS1/CS2 to High-Z Output
CS1/CS2 to Low-Z Output
LB, UB Access Time
LB, UB to High-Z Output
LB, UB to Low-Z Output
35 ns
Min.
Max.
35
—
—
35
10
—
—
35
—
15
—
10
5
—
0
10
10
—
—
35
0
0
10
—
45 ns
Min.
Max.
45
—
—
45
10
—
—
45
—
20
—
15
5
—
0
15
10
—
—
45
0
0
15
—
55 ns
Min.
Max.
55
—
—
55
10
—
—
55
—
25
—
20
5
—
0
20
10
—
—
55
0
0
20
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Test conditions and output loading conditions are specified in the AC Test Conditions and AC Test Loads (Figure 1).
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
8
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
05/29/2013
IS62WV12816DALL/DBLL, IS65WV12816DALL/DBLL
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CS1 = OE = Vil, CS2 = WE = Vih, UB or LB = Vil)
tRC
ADDRESS
tAA
tOHA
tOHA
DOUT
DATA VALID
PREVIOUS DATA VALID
AC WAVEFORMS
READ CYCLE NO. 2(1,3) (CS1, CS2, OE, AND UB/LB Controlled)
tRC
ADDRESS
tAA
tOHA
OE
tDOE
CS1
tHZOE
tLZOE
tACE1/tACE2
CS2
tLZCE1/
tLZCE2
tHZCS1/
tHZCS2
LB, UB
tLZB
DOUT
tBA
HIGH-Z
tHZB
DATA VALID
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CS1, UB, or LB = Vil. CS2=WE=Vih.
3. Address is valid prior to or coincident with CS1 LOW transition.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
05/29/2013
9
IS62WV12816DALL/DBLL, IS65WV12816DALL/DBLL
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
35 ns
Symbol
Parameter Min. Max. twc
Write Cycle Time
35
—
tscs1/tscs2 CS1/CS2 to Write End
25
—
taw
Address Setup Time to Write End 25
—
tha
Address Hold from Write End
0
—
tsa
Address Setup Time
0
—
tpwb
LB, UB Valid to End of Write
30
—
tpwe
WE Pulse Width
30
—
tsd
Data Setup to Write End
15
—
thd
Data Hold from Write End
0
—
(3)
thzwe WE LOW to High-Z Output
—
20
tlzwe(3)
WE HIGH to Low-Z Output
5
—
45 ns
55 ns
Min. Max. Min. Max. Unit
45 —
55
—
ns
35
—
45
—
ns
35
—
45
—
ns
0
—
0
—
ns
0
—
0
—
ns
35
—
45
—
ns
35
—
40
—
ns
20
—
25
—
ns
0
—
0
—
­ns
—
20
—
20
ns
5
—
5
—
ns
Notes:
1. Test conditions and output loading conditions are specified in the AC Test Conditions and AC Test Loads (Figure 1).
2. The internal write time is defined by the overlap of CS1 LOW, CS2 HIGH and UB or LB, and WE LOW. All signals must be in
valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are
referenced to the rising or falling edge of the signal that terminates the write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
10
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
05/29/2013
IS62WV12816DALL/DBLL, IS65WV12816DALL/DBLL
AC WAVEFORMS
WRITE CYCLE NO. 1(1,2) (CS1 Controlled, OE = HIGH or LOW)
tWC
ADDRESS
tHA
tSCS1
CS1
tSCS2
CS2
tAW
tPWE
WE
tPWB
LB, UB
tSA
DOUT
tHZWE
DATA UNDEFINED
tLZWE
HIGH-Z
tSD
DIN
tHD
DATA-IN VALID
Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CS1 , CS2 and WE inputs and at
least one of the LB and UB inputs being in the LOW state.
2. WRITE = (CS1) [ (LB) = (UB) ] (WE).
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
05/29/2013
11
IS62WV12816DALL/DBLL, IS65WV12816DALL/DBLL
AC WAVEFORMS
WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle)
tWC
ADDRESS
OE
tHA
tSCS1
CS1
tSCS2
CS2
tAW
t PWE
WE
LB, UB
tSA
DOUT
DATA UNDEFINED
tHZWE
tLZWE
HIGH-Z
tSD
DIN
12
tHD
DATA-IN VALID
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
05/29/2013
IS62WV12816DALL/DBLL, IS65WV12816DALL/DBLL
AC WAVEFORMS
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
tWC
ADDRESS
OE
tHA
tSCS1
CS1
tSCS2
CS2
tAW
t PWE
WE
LB, UB
tSA
DOUT
tHZWE
DATA UNDEFINED
tLZWE
HIGH-Z
tSD
DIN
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
05/29/2013
tHD
DATA-IN VALID
13
IS62WV12816DALL/DBLL, IS65WV12816DALL/DBLL
AC WAVEFORMS
WRITE CYCLE NO. 4 (UB/LB Controlled)
t WC
ADDRESS
t WC
ADDRESS 1
ADDRESS 2
OE
t SA
CS1
LOW
CS2
HIGH
t HA
t SA
WE
UB, LB
t HA
t PBW
t PBW
WORD 1
WORD 2
t HZWE
DOUT
t LZWE
HIGH-Z
DATA UNDEFINED
t HD
t SD
DIN
DATAIN
VALID
t HD
t SD
DATAIN
VALID
UB_CSWR4.eps
14
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
05/29/2013
IS62WV12816DALL/DBLL, IS65WV12816DALL/DBLL
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol
Vdr
Idr
tsdr
trdr
Parameter
Vdd for Data Retention
Data Retention Current
Data Retention Setup Time
Recovery Time
Test Condition
Min.
Max.
See Data Retention Waveform
1.5
3.6
Vdd = Vdr(min),
Com.
—
4
(1) 0V < CS2 < 0.2V, or Ind.
—
6
(2) CS1 ≥ Vdd – 0.2V, CS2 > Vdd - 0.2V or
Auto.
—
20
(3) LB and UB > Vdd -0.2V, CS1 < 0.2V, CS2 > Vdd - 0.2V typ.(2) 2
See Data Retention Waveform
0
—
ns
See Data Retention Waveform
trc
—
ns
Unit
V
µA
µA
µA
µA
Note:
1. Typical values are measured at Vdd = Vdr(min), Ta = 25oC and not 100% tested.
DATA RETENTION WAVEFORM (CS2 Controlled)
Data Retention Mode
VDD
CS2
tSDR
tRDR
VDR
CS2 ≤ 0.2V
GND
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Rev. C
05/29/2013
15
IS62WV12816DALL/DBLL, IS65WV12816DALL/DBLL
DATA RETENTION WAVEFORM (CS1Controlled)
Data Retention Mode
tSDR
tRDR
VDD
VDR
CS1 ≥ VDD - 0.2V
CS1
GND
Note:
1. CS2 must satisfy either CS2 > Vcc -0.2V or CS2 < 0.2V
DATA RETENTION WAVEFORM (UBand LB Controlled)
tSDR
Data Retention Mode
tRDR
VDD
VDR
UB / LB
GND
UB and LB > VDD - 0.2V
Note:
1. CS2 must satisfy either CS2 > Vcc -0.2V or CS2 < 0.2V
2. CS1 must satisfy either CS1 > Vcc -0.2V or CS1 < 0.2V
16
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Rev. C
05/29/2013
IS62WV12816DALL/DBLL, IS65WV12816DALL/DBLL
ORDERING INFORMATION: IS62WV12816DALL (1.65V - 2.2V)
Industrial Range: –40°C to +85°C
Speed (ns)
55
Order Part No.
Package
IS62WV12816DALL-55TI TSOP (Type II)
IS62WV12816DALL-55BI mini BGA (6mm x 8mm)
IS62WV12816DALL-55BLI mini BGA (6mm x 8mm), Lead-free
IS62WV12816DALL-55B2I mini BGA (6mm x 8mm), 2 CS Option
ORDERING INFORMATION: IS62WV12816DBLL (2.5V - 3.6V)
Industrial Range: –40°C to +85°C
Speed (ns)
35
45
55
Order Part No.
IS62WV12816DBLL-35TLI
IS62WV12816DBLL-35BLI
IS62WV12816DBLL-35B2LI
IS62WV12816DBLL-45TLI
IS62WV12816DBLL-45BLI
IS62WV12816DBLL-45B2LI
IS62WV12816DBLL-55TI
IS62WV12816DBLL-55TLI
IS62WV12816DBLL-55BI
IS62WV12816DBLL-55BLI
IS62WV12816DBLL-55B2I
IS62WV12816DBLL-55B2LI
Package
TSOP (Type II), Lead-free mini BGA (6mm x 8mm), Lead-free mini BGA (6mm x 8mm), 2 CS Option, Lead-free
TSOP (Type II), Lead-free mini BGA (6mm x 8mm), Lead-free mini BGA (6mm x 8mm), 2 CS Option, Lead-free
TSOP (Type II)
TSOP (Type II), Lead-free
mini BGA (6mm x 8mm)
mini BGA (6mm x 8mm), Lead-free
mini BGA (6mm x 8mm), 2 CS Option
mini BGA (6mm x 8mm), 2 CS Option, Lead-free
ORDERING INFORMATION: IS65WV12816DBLL (2.5V - 3.6V)
Automotive Range (A3): –40°C to +125°C
Speed (ns)
45
Order Part No. Package
IS65WV12816DBLL-45CTLA3 TSOP (Type II), Lead-free, Copper Leadframe
IS65WV12816DBLL-45BLA3 mini BGA (6mm x 8mm), Lead-free
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
05/29/2013
17
18
08/12/2008
Package Outline
1. CONTROLLING DIMENSION : MM .
2. Reference document : JEDEC MO-207
NOTE :
IS62WV12816DALL/DBLL, IS65WV12816DALL/DBLL
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
05/29/2013
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
05/29/2013
Package Outline
06/04/2008
3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION.
2. DIMENSION D AND E1 DO NOT INCLUDE MOLD PROTRUSION.
1. CONTROLLING DIMENSION : MM
NOTE :
IS62WV12816DALL/DBLL, IS65WV12816DALL/DBLL
19