LS7060C LS7061C

LSI/CSI
UL
LS7060C
LS7061C
®
LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747
(631) 271-0400 FAX (631) 271-0405
A3800
32 BIT BINARY UP COUNTER
WITH BYTE MULTIPLEXED THREE-STATE OUTPUTS
ADVANCE INFORMATION
DESCRIPTION:
The LS7060C/LS7061C are CMOS Silicon Gate, 32 bit Up
Counters. The ICs include latches, multiplexer, byte output sequencer, eight three-state binary data output drivers and output
cascading logic.
November 2002
PIN ASSIGNMENT - TOP VIEW
18 V DD (+V)
COUNT
1
ALT COUNT
2
B3 OUT
3
B2 OUT
4
B1 OUT
5
B0 OUT
6
13 TEST COUNT
RESET
7
12 SCAN RESET/LOAD
8
11 ENABLE
9
10 SCAN
CASCADE EN OUT
V SS (-V)
LSI
FEATURES:
• DC to 50MHz Count Frequency
• Byte Multiplexer
• DC to 10MHz Byte Output Scan Frequency
• +4.75V to +5.25V Operation (VDD - VSS)
• Three-State Data Outputs; Bus, TTL and CMOS Compatible
• Inputs TTL and CMOS Compatible
• Unique Cascade Feature Allows Multiplexing of
Successive Bytes of Data in Sequence in Multiple
Counter Systems
• Low Power Dissipation
• LS7060C (DIP); LS7060C-S (SOIC) - See Figure 1
• LS7061C (DIP); LS7061C-S (SOIC) - See Figure 2
17 B4 OUT
16 B5 OUT
15 B6 OUT
LS7060C
14 B7 OUT
FIGURE 1
DESCRIPTION OF OPERATION:
PIN ASSIGNMENT - TOP VIEW
COUNT, ALT COUNT (LS7060C)
Input count pulses to the 32 bit counter may be applied through
either of these two inputs. The ALT COUNT input circuitry contains a Schmitt trigger network which allows proper counting with
"infinitely" long clock edges. A high applied to either of these two
inputs inhibits counting.
COUNT (LS7061C)
Input count pulses to the 32 bit counter may be applied through
this input. This input is the most significant bit of the external data
byte.
RESET
All 32 counter bits are reset to zero when RESET is brought low
for a minimum of 20ns. RESET must be high for a minimum of
10ns before next valid count can be recorded.
TEST COUNT
Count pulses may be applied to the last 16 bits of the binary
counter through this input, as long as Bit 16 of the counter is a
low. The counter advances on the negative transition of these
pulses. This input is intended to be used for test purposes.
NOTE: LS7060C and LS7061C can directly replace LS7060 and
LS7061 in all existing applications.
7060C/61C-110702-1
V DD (+V)
1
LSI
32 BIT BINARY UP COUNTER - LS7060C (LS7061C)
The 32 bit static ripple through counter increments on the negative edge of the input count pulse. Maximum ripple time is 20ns
transition count of 32 ones to 32 zeros.
Guaranteed count frequency is DC to 50MHz.
See Figure 9A (9B) for Block Diagram.
24
B4 OUT
(COUNT) B7 IN
2
23
B5 OUT
B3 OUT
3
22
B0 IN
B6 IN
4
21
B1 IN
B2 OUT
5
20
B6 OUT
B5 IN
6
19
B2 IN
B7 OUT
LS7061C
B1 OUT
7
18
B4 IN
8
17
B3 IN
B0 OUT
9
16
TEST COUNT
RESET
10
15
SCAN RESET/LOAD
CASCADE ENABLE OUT 11
14
ENABLE
13
SCAN
Vss (-V)
12
FIGURE 2
LATCHES
32 bits of latch are provided for storage of counter data for the
LS7060C. 40 bits of latch are provided for the LS7061C of which
eight are for storage of a high speed external prescaling counter
and the remaining 32 are for the contents of the chip counter
data. All latches are loaded when the LOAD input is brought low
for a minimum of 10ns and kept low until a minimum of 20ns has
elapsed from previous negative edge of count pulse (ripple time).
Storage of valid data occurs when LOAD is brought high for a
minimum of 20ns before next negative edge of count pulse or
RESET.
ENABLE
When this input is high, the scan counter and the Data Outputs are
disabled. When ENABLE is low, the scan counter and Data Outputs
are enabled for normal operation. Transition of this input should
only be made while the SCAN input is in a low state in order to prevent false clocking of the scan counter.
SCAN COUNTER AND DECODER
The scan counter is reset to the least significant byte position
(State 1) when SCAN RESET input is brought low for a minimum of 10ns. The scan counter is enabled for counting as long
as the ENABLE input is held low. The counter advances to the
next significant byte position on each negative transition of the
SCAN pulse. When the scan counter advances to State 5 for
the LS7060C or Stage 6 for the LS7061C it disables the Output
Drivers and stops in that state until SCAN RESET is again
brought low.
CASCADE ENABLE
This output is normally high. It transitions low and stays low when
the scan counter advances to State 5 for LS7060C and State 6 for
LS7061C. In a multiple counter system this output is connected to
the ENABLE input of the next counter in the cascade string. The
SCAN input and SCAN RESET/LOAD input are carried to all the
counters in the "Cascade". Counter 1 then presents its bytes of data
to the Output Bus on each positive transition of the SCAN pulse as
previously discussed. When State 5 for LS7060C or State 6 for
LS7061C of Counter 1 is achieved, Counter 2 presents its data to
the Output Bus. This sequence continues until all counters in the
cascade have been addressed. See Figure 5 for an illustration of a
3 device cascade design. This output is TTL and CMOS
compatible.
SCAN
When the scan counter is enabled, each negative transition of
this input advances the scan counter to its next state. When
SCAN is low the Data Outputs are disabled. When SCAN is
brought high the Data Outputs are enabled and present the
latched counter data corresponding to the present state of the
scan counter. Therefore, in microprocessor applications, the
Data Output Bus may be utilized for other activities while new
data is propagating to the outputs. This positive SCAN pulse
can be viewed as a "Place the next byte on my bus" instruction
from the microprocessor. Minimum positive and negative pulse
widths of 10ns for the SCAN signal are required for scan
counter operation.
THREE-STATE DATA OUTPUT DRIVERS
The eight Data Output Drivers are disabled when either ENABLE
input is high, the scan counter is in State 5 for LS7060C and State 6
for LS7061C, or the SCAN input is low. The Output Drivers are TTL
and Bus compatible.
SCAN RESET/LOAD
When this input is brought low for a minimum of 10ns, the scan
counter is reset to State 1, the least significant byte position,
and the latches are simultaneously loaded with new count
information.
ABSOLUTE MAXIMUM RATINGS:
PARAMETER
StorageTemperature
Operating Temperature
Voltage (any pin to VSS)
POWER-ON-RESET
Upon the application of power to the IC, the counters and latches
are set to Logic 0 and the scan counter is set to State 1.
SYMBOL
TSTG
TA
VIN
VALUE
-55 to +150
0 to +70
+10 to -0.3
UNIT
°C
°C
V
DC ELECTRICAL CHARACTERISTICS:
(VDD = +5V ± 5%, VSS = 0V, TA = 0˚C to +70˚C unless otherwise noted.)
PARAMETER
Quiescent Power Supply
Current
Power Supply Current
SYMBOL
IDD
MIN
-
MAX
0.5
UNIT
mA
IDD
-
4
mA
Power Supply Current
IDD
-
8
mA
Input High Voltage
Input Low Voltage
VIH
VIL
+3.5
0
VDD
+0.6
V
V
CONDITIONS
VDD = Max, Outputs No Load,
Ø Frequency
15 MHz Operating Frequency
VDD = Max, Outputs No Load
At Maximum Operating Frequency
VDD = Max, Outputs No Load
-
Output High Voltage
CASCADE ENABLE
B0 - B7
VOH
VOH
+2.4
+2.4
-
V
V
IO = -6mA, VDD = Min
IO = -33mA, VDD = Min
Output Low Voltage
CASCADE ENABLE
B0 - B7
VOL
VOL
-
+0.4
+0.4
V
V
IO = 3mA, VDD = Min
IO = 10mA, VDD = Min
Isource
IOL
-34
-36
-38
25
20
10
-
10
mA
mA
mA
mA
mA
mA
nA
VO = +1.2V, VDD = Min
VO = +0.8V, VDD = Min
VO = +0.4V, VDD = Min
VO = +1.2V, VDD = Min
VO = +0.8V, VDD = Min
VO = +0.4V, VDD = Min
VO = +0.4V to +2.4V, VDD = Min
CIN
COUT
-
6
12
pF
pF
TA = 25˚C, f = 1MHz
TA = 25˚C, f = 1MHz
ILI
-
10
nA
VDD = Max
Output Source Current
B0 - B7 Outputs
Output Sink Current
B0 - B7 Outputs
Output Leakage Current
B0 - B7 (Off State)
Input Capacitance
Output Capacitance
Input Leakage Current
ENABLE, RESET, SCAN
7060C/61C-110702-2
Isink
INPUT CURRENT
*SCAN RESET/LOAD
**All Count inputs
SYMBOL
MIN
MAX
UNIT
IIH
IIL
IIH
IIL
-
-3.5
-5
5
1
µA
µA
µA
µA
CONDITIONS
VDD = Max, VIH = +3.5V
VDD = Max, VIL = 0V
VDD = Max, VIH = +3.5V
VDD = Max, VIL = 0.35V
*Input has internal pull-up resistor to VDD
** Inputs have internal pull-down resistor to VSS
DYNAMIC ELECTRICAL CHARACTERISTICS:
(VDD = +5V ± 5%, VSS = 0V, TA = 0˚C to +70˚C unless otherwise noted.)
PARAMETER
Count Frequency
(All Count inputs)
Count Pulse Width
(All Count Inputs)
SYMBOL
fc
MIN
DC
MAX
50
UNIT
MHz
tCPW
10
-
ns
Measured at 50% point,
Max tr, tf = 1ns
Count Ripple Time
tCR
-
20
ns
Transition from 32 ones to 32 zeros
from negative edge of count pulse
Reset Pulse Width
(All Counter Stages
Fully Reset)
tRPW
20
-
ns
Measured at 50% point
Max tr, tf = 10ns
tRR
-
10
ns
Measured from RESET signal at VIH
SCAN Frequency
SCAN Pulse Width
fSC
tSCPW
50
10
-
MHz
ns
SCAN RESET/LOAD
Pulse Width
(All latches loaded and
Scan Counter Reset to
Least Significant Byte)
tRSCPW
10
-
ns
SCAN RESET/LOAD
Removal Time
(Reset Removed from
Scan Counter; Load
Command Removed
From Latches)
tRSCR
-
10
ns
Measured from
SCAN RESET/LOAD at VIH
Output Disable
Delay Time
(B0 - B7)
tDOD
-
5
ns
Transition to Output High
Impedance State Measured
From Scan at VIL or
ENABLE at VIH
Output ENABLE
Delay Time
(B0 - B7)
tDOE
-
5
ns
Transition to Valid On State
Measured from Scan at VIH
and ENABLE at VIL; Delay to
Valid Data Levels for COL = 10pF
and one TTL Load or Valid Data
Currents for High Capacitance Loads
Output Delay Time
CASCADE ENABLE
tDCE
-
10
ns
Negative Transition from Scan at VIL
and ST5 of Scan Counter or Positive
Transition From SCAN RESET/LOAD at
VIL to Valid Data Levels for COL = 12pF
and one TTL Load
RESET Removal Time
(Reset Removed From
All Counter Stages)
7060C/61C-121901-3
CONDITIONS
-
Measured at 50% point
Max tr, tf = 10ns
Measured at 50% point
Max tr, tf = 5ns
tRSCPW
SCAN RESET
ENABLE
tRSCR
SCAN
tSCPW tSCPW
ST1 (int.)
ST2 (int.)
ST3 (int.)
ST4 (int.)
ST5 (int.)
ENABLE (int.)
t DCE
t DCE
CASCADE ENABLE
t DOD
t DOE
DATA OUTPUTS
valid
LSB
valid
LSB+1
valid
LSB +2
valid
MSB
FIGURE 3A. SCAN COUNTER & DECODER OUTPUTS TIMING DIAGRAM FOR LS7060C
tRSCPW
SCAN RESET
ENABLE
tRSCR
SCAN
tSCPW
tSCPW
ST1 (int.)
ST2 (int.)
ST3 (int.)
ST4 (int.)
ST5 (int.)
ST6 (int.)
ENABLE (int.)
t DCE
CASCADE ENABLE
DATA OUTPUTS
t DCE
t DOD
t DOE
valid
LSB
valid
LSB+1
valid
LSB +2
valid
valid
LSB+3
MSB
FIGURE 3B. SCAN COUNTER & DECODER OUTPUTS TIMING DIAGRAM FOR LS7061C.
7060C/62C-121801-4
tRPW
tRPW
RESET
tRR + tCPW
t RSCR
t RR+tCPW
COUNT
tCPW
tCR
t CPW
LOAD
tRSCPW
FIGURE 4. COUNTER TIMING DIAGRAM
OUTPUT DATA BUS
A
B
CE
EN SC RESET SC
C
CE
EN SC RESET SC
CE
EN SC RESET SC
END OF SCAN
ENABLE
SCAN RESET
SCAN
FIGURE 5.
ILLUSTRATION OF A 3 DEVICE CASCADE
SCAN RESET
ENABLE
SCAN
CASCADE ENABLE A
CASCADE ENABLE B
CASCADE ENABLE C
(END OF SCAN)
DATA BYTE ON BUS
PACKAGE
1
2
3
A
4
5
1
2
3
B
4
5
1
2
3
C
FIGURE 6. TIMING DIAGRAM FOR THE 3 DEVICE CASCADE
7060C/61C-121901-5
4
5
METHOD 1
METHOD 2
INHIBIT
INHIBIT
S
Q
TO
COUNT INPUT
R
D
PR
Q
TO COUNT
INPUT
C
COUNT
PULSES
(Same as input to Alt Count)
COUNT
PULSES
(Same as input to Alt Count)
FIGURE 7. SYNCHRONIZING INHIBIT WITH COUNT PULSES
FIGURE 8. APPLICATION EXAMPLE: HIGH SPEED DIFFERENTIAL ENERGY ANALYZER
LS7061C
D E TE CTOR
VOLTAGE
DISCRIMINATORS
PRESCALERS
SCAN
EN
RADIATION
PULSE
Pulse voltage
proportional
to energy of
radiation
CE
B
U
S
PROCESSOR
EN
CE
EN
CE
CASCADE ENABLE
NOTE : The processor subtracts counts from successive counters to determine the differential energy spectrum
The information included herein is believed to be
accurate and reliable. However, LSI Computer Systems,
Inc. assumes no responsibilities for inaccuracies, nor for
any infringements of patent rights of others which may
result from its use.
7060C/61C-121801-6
FIGURE 9A.
LS7060C BLOCK DIAGRAM
DATA OUT
CASCADE ENABLE
8
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
V DD
18
+V
V SS
9
-V
ENABLE
SCAN
10
SCAN RESET/LOAD
12
6
ST1
ENABLE
3
17 16 15
14
THREE STATE
OUTPUT DRIVERS
EN
8 BITS
ST3
ST2
4
ST5
5 STATE
STATIC SCAN COUNTER AND
CSC
DECODER
(STOPS IN STATE 5 UNTIL SCAN RESET
R SC CAUSES RESET TO STATE ONE)
11
5
ST4
8 BIT MUX BUS
G
LOAD
MUX
GATE
8 BIT LATCH
B0
COUNT
B0
8 BIT BINARY
COUNTER
C
G
8 BIT LATCH
LOAD
B7
1
MUX
GATE
G
LOAD
B7
C
8 BIT LATCH
LOAD
B7
B0
8 BIT BINARY
COUNTER
C
R
MUX
GATE
G
8 BIT LATCH
B0
8 BIT BINARY
COUNTER
R
MUX
GATE
B7
8 BIT BINARY
COUNTER
C
R
R
2
ALT COUNT
7
RESET
13
TEST COUNT
FIGURE 9B.
LS7061C BLOCK DIAGRAM
DATA OUT
CASCADE ENABLE
LSB
MSB
11
B0 B1 B2 B3 B4 B5 B6 B7
V DD
1
+V
V SS
12
-V
ENABLE
SCAN
9
6 STATE
STATIC SCAN COUNTER AND
DECODER
C SC
(STOPS IN STATE 6 UNTIL SCAN RESET
R SC CAUSES RESET TO STATE ONE)
14
13
SCAN RESET/LOAD
15
ST2
ST1
ST3
ST4
7
5
3
24
23 20 18
ST6
ENABLE
THREE STATE
EN OUTPUT DRIVERS
8 BITS
ST5
8 BIT MUX BUS
MUX
GATE
G
G
8 BIT LATCH LOAD
LOAD
B0
MUX
GATE
G
8 BIT LATCH
B7
8 BIT BINARY
COUNTER
C
R
LOAD
MUX
GATE
G
8 BIT LATCH
B0
B7
8 BIT BINARY
COUNTER
C
R
LOAD
MUX
GATE
G
8 BIT LATCH
B7
B0
8 BIT BINARY
COUNTER
C
R
LOAD
B0
19
8 BIT BINARY
COUNTER
C
R
21
B1
B2
17
B3
B4
RESET
4
8
6
B5
DATA IN
B6
16
2
B7
(COUNT)
TEST COUNT
8 BIT LATCH
B7
B0
10
22
MUX
GATE