The comparison of MX25L6435E and MX25L6436E

APPLICATION NOTE
Macronix MX25L6435E and MX25L6436E
Serial Flash Comparison
1. Introduction
This application note compares the MX25L6435E and MX25L6436E 64Mb 3V serial NOR flash.
The document does not provide detailed information on each individual device, but highlights the
similarities and differences between them. The comparison covers the general features, performance,
command sets and device ID.
In comparison with the MX25L6436E, the MX25L6435E supports new features, such as 2READ
mode (1-2-2, Single I/O Command input - Dual I/O Address input - Dual I/O Data output) and 4READ
mode (1-4-4, Single I/O Command input - Quad I/O Address input - Quad I/O Data output).
MX25L6435E supports a new TB (Top/Bottom) bit function, which enables Block Protection beginning
at either the top or bottom of the memory array.
The MX25L6435E also has a HOLD pin added and is available in not only the 8-SOP and 16-SOP
packages, but comes in a smaller 8-WSON package and a 24-TFBGA package as well.
The information provided in this document is based on datasheets listed in Section 8.
Newer versions of the datasheets may override the contents of this document.
Please refer to the contents and comparison tables below for more details.
P/N: AN183
1
REV. 1, SEP. 13, 2012
APPLICATION NOTE
2. General Features
The MX25L6435E has a new TB (Top/Bottom) bit located in Configuration Register Bit 3. By
controlling the T/B bit, memory blocks can be selected for protection beginning at either the top or
bottom of the memory array.
The MX25L6435E supports two additional read modes: 2READ mode and 4READ mode. The
MX25L6435E has the same or improved performance in all read modes.
The MX25L6435E also has a HOLD pin added and is available in not only the 8-SOP and 16-SOP
packages, but comes in a smaller 8-WSON and 24-TFBGA packages as well.
These features are summarized in Table 2-1.
Table 2-1: Feature Comparison
Feature
MX25L6435E
MX25L6436E
Voltage
2.7~3.6 V
2.7~3.6 V
Interface
x1, x2, x4
x1, x2, x4
Packages
16-SOP (300mil)
8-SOP (209mil)
8-WSON (6x5mm)
24-TFBGA (6x8mm)
16-SOP (300mil)
8-SOP (209mil)
8-WSON (8x6mm)
-40°C ~ +85°C
-40°C ~ +85°C
4KB / 32KB or 64KB
4KB / 32KB or 64KB
Fast Read (1-1-1)
104MHz
104MHz
Normal Read
50MHz
50MHz
DREAD (1-1-2)
(Dual Output)
86MHz
70MHz
QREAD (1-1-4)
(Quad Output)
86MHz
75MHz
2READ(1-2-2)
86MHz
--
4READ(1-4-4)
Up to 104MHz
--
104MHz
20MHz
Yes. for 4READ mode only
--
Yes
Yes
4Kbits
4Kbits
BP3~BP0
BP3~BP0
T/B (Top/Bottom)bit
Yes
--
Individual Protection
Individual Sector/Block Protect
Individual Sector/Block Protect
HOLD#
Yes
--
SFDP
Yes
Yes
Operating Temperature Range
Sector / Block
Clock Rate
(max.)
4PP
Configurable Dummy Cycle
Continuous Program (CP) Mode
Secured OTP
Data Protection
P/N: AN183
Block Protection
2
REV. 1, SEP. 13, 2012
APPLICATION NOTE
3. Performance
Both devices have similar power and timing as shown in Table 3-1.
Table 3-1: Performance Comparison
Parameter
Symbol
MX25L6435E
MX25L6436E
tCH
104MHz: 4.5ns
50MHz: 9ns
104MHz: 4.5ns
50MHz: 9ns
tCL
104MHz: 4.5ns
50MHz: 9ns
104MHz: 4.5ns
50MHz: 9ns
Byte
12us(typ.) ; 300us(max.)
9us(typ.) ; 300us(max.)
Page
1.4ms(typ.) ; 5ms(max.)
1.4ms(typ.) ; 5ms(max.)
Sector
60ms(typ.) ; 300ms(max.)
60ms(typ.) ; 300ms(max.)
Block
32KB:0.5s(typ.); 2s(max.)
64KB:0.7s(typ.); 2s(max.)
32KB:0.5s(typ.); 2s(max.)
64KB:0.7s(typ.); 2s(max.)
Chip
50s (typ.) / 80s(max.)
50s (typ.) / 80s(max.)
Clock High/Low Time
Program Time
Erase Time
CS# Active Setup Time
tSLCH
4ns(min.)
5ns(min.)
CS# Not Active Setup Time
tSHCH
4ns(min.)
5ns(min.)
CS# Active Hold Time
tCHSH
4ns(min.)
5ns(min.)
CS# Not Active Hold Time
tCHSL
4ns(min.)
5ns(min.)
CS# Deselect Time
tSHSL
Read=15ns(min.) ;
Write=50ns(min.)
Read=15ns(min.) ;
Write=50ns(min.)
VCC Standby
ISB1
80uA(max.)
50uA(max.)
Deep Power Down
ISB2
40uA(max.)
20uA(max.)
35mA (104MHz, 4 I/O)
25mA (86MHz, 4 I/O)
19mA (104MHz, 1 I/O)
20mA (86MHz, 2 I/O)
10mA (33MHz, 1 I/O)
22mA (75MHz, 4 I/O)
19mA (104MHz, 1 1/O)
17mA (70MHz, 2 I/O)
10mA (33MHz, 1 I/O)
VCC Read Current
ICC1
P/N: AN183
VCC Program Current
ICC2
25mA
25mA
VCC WRSR Current
ICC3
20mA
20mA
VCC Sector Erase Current
ICC4
25mA
25mA
VCC Chip Erase Current
ICC5
25mA
20mA
3
REV. 1, SEP. 13, 2012
APPLICATION NOTE
4. Package and Pin-out Comparison
Figure 4-1 shows the common packages and the pin-out assignments for the two devices. With
the exception of the added HOLD# pin function on the MX25L6435E, both devices have the same
footprint and pinout. When migrating from the 36E to the 35E, if the HOLD#/SIO3 pin is currently N/C
(not connected) it can be left unconnected as the HOLD# pin is internal pull high.
Figure 4-1: Packages and Pin-outs
16-PIN SOP (300mil)
MX25L6435E
HOLD#/SIO3
VCC
NC
NC
NC
NC
CS#
SO/SIO1
MX25L6436E
NC/SIO3
VCC
NC
NC
NC
NC
CS#
SO/SIO1
MX25L6435E
CS#
SO/SIO1
WP#/SIO2
GND
MX25L6436E
CS#
SO/SIO1
WP#/SIO2
GND
MX25L6435E
CS#
SO/SIO1
WP#/SIO2
GND
MX25L6436E
CS#
SO/SIO1
WP#/SIO2
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
MX25L6435E
SCLK
SI/SIO0
NC
NC
NC
NC
GND
WP#/SIO2
MX25L6436E
SCLK
SI/SIO0
NC
NC
NC
NC
GND
WP#/SIO2
MX25L6435E
VCC
HOLD#/SIO3
SCLK
SI/SIO0
MX25L6436E
VCC
NC/SIO3
SCLK
SI/SIO0
MX25L6435E
VCC
HOLD#/SIO3
SCLK
SI/SIO0
MX25L6436E
VCC
NC/SIO3
SCLK
SI/SIO0
8-PIN SOP (200mil)
1
2
3
4
8
7
6
5
8-WSON
1
2
3
4
8
7
6
5
24-Ball TFBGA (6x8 mm) (MX25L6435E only)
4
NC
VCC
WP#/SIO2 HOLD#/SIO3
NC
NC
NC
GND
NC
SI/SIO0
NC
NC
NC
SCLK
CS#
SO/SIO1
NC
NC
NC
NC
NC
NC
NC
NC
A
B
C
D
E
3
2
1
P/N: AN183
4
F
REV. 1, SEP. 13, 2012
APPLICATION NOTE
5. Command Set Comparison
Table 5-1 shows that the command set remain the same with the exception of the additional 2READ
and 4READ (BBh and EBh, added to the 35E). The MX25L6435E does not have the Clear Security
Register Fail Flags command (30h) to clear the E_FAIL or P_FAIL flags as the MX25L6436E does.
The MX25L6435E clears these flags automatically at the beginning of the next command sequence.
Table 5-1: Command Set Comparison
Command
Write
Read
Erase
Program
Security Register
Secured OTP
SO output
Deep Power Down
Block Lock
Clear SR
Block Protect Read
P/N: AN183
WREN
WRDI
WRSR
RDID
RDSR
READ
RDSFDP
Fast Read
2READ
4READ
DREAD
QREAD
RES
REMS
REMS2
REMS4
SE
BE
BE32K
CE
4PP
PP
CP
RDSCUR
WRSCUR
ENSO
EXSO
ESRY
DSRY
DP
RDP
SBLK
SBULK
GBLK
GBULK
CLSR
RDBLOCK
5
MX25L6435E
MX25L6436E
06h
04h
01h
9Fh
05h
03h
5A
0Bh
BBh
EBh
3Bh
6Bh
Abh
90h
EFh
DFh
20h
D8h
52h
60h or C7h
38h
02h
ADh
2Bh
2Fh
B1h
C1h
70h
80h
B9h
ABh
36h
39h
7Eh
98h
-3Ch
06h
04h
01h
9Fh
05h
03h
5A
0Bh
--38h
6Bh
Abh
90h
EFh
DFh
20h
D8h
52h
60h or C7h
38h
02h
ADh
2Bh
2Fh
B1h
C1h
70h
80h
B9h
ABh
36h
39h
7Eh
98h
30h
3Ch
REV. 1, SEP. 13, 2012
APPLICATION NOTE
6. Device ID Code Comparison
Table 6-1 shows that the Manufacturer and Device IDs have not changed.
Table 6-1: ID Code Comparison
Command Type
RDID Command
MX25L6435E
M ID
Type
Density
M ID
Type
Density
C2
20
17
C2
20
17
RES Command
REMS
MX25L6436E
Electronic ID
Electronic ID
16
16
M ID
Device ID
M ID
Device ID
C2
16
C2
16
7. Summary
The MX25L6435E is backwards compatible with most of the common commands and features of
the MX25L6436E. Additionally, the supported package types have identical footprints and nearly
identical pin-out definitions.
8. References
Table 8-1 shows the datasheet versions used for comparison in this application note. For the most
current Macronix specification, please refer to the Macronix Website at http://www.macronix.com
Table 8-1: Datasheet Version
P/N: AN183
Datasheet
Location
Date Issued
Version
MX25L6435E
Macronix Website
Sep. 2012
1.0
MX25L6436E
Macronix Website
Apr. 2010
1.9
6
REV. 1, SEP. 13, 2012
APPLICATION NOTE
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P/N: AN183
7
REV. 1, SEP. 13, 2012