MX35LF1GE4AB MX35LF2GE4AB 3V, 1Gb/2G-bit Serial NAND Flash Memory MX35LFxGE4AB REV. 1.2, AUG. 19, 2015 P/N: PM2128 1 MX35LF1GE4AB MX35LF2GE4AB Contents 1. FEATURES..........................................................................................................................................5 2. GENERAL DESCRIPTIONS................................................................................................................6 Figure 1. Logic Diagram......................................................................................................................... 6 3. ORDERING INFORMATION................................................................................................................7 4. BALL ASSIGNMENT AND DESCRIPTIONS......................................................................................8 Figure 2. 16-SOP (300mil)..................................................................................................................... 8 5. PIN DESCRIPTIONS...........................................................................................................................8 Figure 3. 8-WSON (8x6mm) (1Gb only)................................................................................................ 8 6. DEVICE OPERATION..........................................................................................................................9 Figure 4. Serial Mode Supported........................................................................................................... 9 7. ADDRESS MAPPING........................................................................................................................10 8. COMMAND DESCRIPTION...............................................................................................................11 Table 1. Command Set..........................................................................................................................11 8-1. WRITE Operations................................................................................................................12 8-1-1. Write Enable ............................................................................................................................. 12 Figure 5. Write Enable (WREN) Sequence ......................................................................................... 12 8-1-2. Write Disable (04h)................................................................................................................... 12 Figure 6. Write Disable (WRDI) Sequence ........................................................................................ 12 8-2. Feature Operations...............................................................................................................13 8-2-1. GET Feature (0Fh) and SET Feature (1Fh)............................................................................. 13 Table 2-1. Feature Settings (For 2Gb)................................................................................................. 13 Table 2-2. Feature Settings (For 1Gb)................................................................................................. 13 Figure 7. GET FEATURE (0Fh) Timing................................................................................................ 13 Figure 8. SET FEATURE (1Fh) Timing................................................................................................ 14 8-3. READ Operations..................................................................................................................14 8-3-1. PAGE READ (13h)..................................................................................................................... 14 Table 3. Wrap Address bit Table (Only for 1Gb)................................................................................... 14 8-3-2. QE bit......................................................................................................................................... 14 Figure 9. PAGE READ (13h) Timing x1............................................................................................... 15 Figure 10. RANDOM DATA READ (03h or 0Bh) Timing...................................................................... 16 Figure 11. READ FROM CACHE x 2................................................................................................... 17 Figure 12. READ FROM CACHE x 4................................................................................................... 18 8-3-3. READ ID (9Fh)........................................................................................................................... 19 Table 4. READ ID Table....................................................................................................................... 19 Figure 13. READ ID (9Fh) Timing........................................................................................................ 19 REV. 1.2, AUG. 19, 2015 P/N: PM2128 2 MX35LF1GE4AB MX35LF2GE4AB 8-4. Parameter Page.....................................................................................................................20 Table 5. Parameter Page Data Structure............................................................................................. 21 8-5. UniqueID Page......................................................................................................................22 8-6. Internal ECC Status Read (For 1Gb only)...........................................................................23 Table 6-1. The ECCSR (Internal ECC Status Register) Bits................................................................ 23 Table 6-2. The Definition of Internal ECC Status................................................................................. 23 Figure 14. The Page Structure and Internal ECC Segments............................................................... 23 Figure 15. The Sequence of Internal ECC Status Read...................................................................... 24 8-7. Program Operations.............................................................................................................25 8-7-1. PAGE PROGRAM...................................................................................................................... 25 Figure 16. PROGRAM LOAD (02h) Timing.......................................................................................... 25 Figure 17. PROGRAM LOAD RANDOM DATA (84h) Timing............................................................... 26 8-7-2. QUAD IO PAGE PROGRAM...................................................................................................... 27 Figure 18. PROGRAM LOAD X4 (32h) Timing.................................................................................... 27 Figure 19. QUAD IO PROGRAM RANDOM INPUT (34h) Timing....................................................... 28 Figure 20. PROGRAM EXECUTE (10h) Timing.................................................................................. 29 9. BLOCK OPERATIONS......................................................................................................................30 9-1. Block Erase (D8h).................................................................................................................30 Figure 21. Block Erase (BE) Sequence .............................................................................................. 30 10. Feature Register.............................................................................................................................31 10-1. Block Protection Feature.....................................................................................................31 Table 7-1. Definition of Protection Bits (BPx) (For 2Gb)....................................................................... 32 Table 7-2. Definition of Protection Bits (For 1Gb)................................................................................. 32 10-2. Secure OTP (One-Time-Programmable) Feature...............................................................33 Table 8. Secure OTP States................................................................................................................. 33 10-3. Status Register.....................................................................................................................34 Table 9. Status Register Bit Descriptions............................................................................................. 34 11. SOFTWARE ALGORITHM...............................................................................................................35 11-1. Invalid Blocks (Bad Blocks) ................................................................................................35 Figure 22. Bad Blocks.......................................................................................................................... 35 Table 10. Valid Blocks.......................................................................................................................... 35 11-2. Bad Block Test Flow.............................................................................................................36 Figure 23. Bad Block Test Flow............................................................................................................ 36 11-3. Failure Phenomena for Read/Program/Erase Operations................................................36 Table 11. Failure Modes....................................................................................................................... 36 11-3-1. Internal ECC Enabled/Disabled ............................................................................................ 37 Table 12. The Distribution of ECC Segment and Spare Area.............................................................. 37 REV. 1.2, AUG. 19, 2015 P/N: PM2128 3 MX35LF1GE4AB MX35LF2GE4AB 12. DEVICE POWER-UP.......................................................................................................................38 12-1.Power-up...............................................................................................................................38 Figure 24. Power On Sequence .......................................................................................................... 38 13. PARAMETERS.................................................................................................................................39 13-1. ABSOLUTE MAXIMUM RATINGS........................................................................................39 Figure 25. Maximum Negative Overshoot Waveform.......................................................................... 39 Table 13. AC Testing Conditions.......................................................................................................... 39 Table 14. Capacitance......................................................................................................................... 39 Table 15. Operating Range.................................................................................................................. 39 Figure 26. Maximum Positive Overshoot Waveform............................................................................ 39 Table 16. DC Characteristics ............................................................................................................... 40 Table 17. General Timing Characteristics............................................................................................ 40 Table 18. PROGRAM/READ/ERASE Characteristics.......................................................................... 40 Figure 27. WP# Setup Timing and Hold Timing during SET FEATURE when BPRWD=1................... 41 Figure 28. Serial Input Timing.............................................................................................................. 41 Figure 29. Serial Output Timing........................................................................................................... 41 Figure 30. Hold Timing......................................................................................................................... 42 14. PACKAGE INFORMATION..............................................................................................................43 14-1. 8-WSON (8x6mm)..................................................................................................................43 14-2. 8-WSON (8x6mm), E.P. 3.4x4.3mm......................................................................................44 14-3. 16-SOP (300mil)....................................................................................................................45 15. REVISION HISTORY .......................................................................................................................46 REV. 1.2, AUG. 19, 2015 P/N: PM2128 4 MX35LF1GE4AB MX35LF2GE4AB 3V, 1Gb/2Gb Serial NAND Flash Memory 1. FEATURES • 1Gb/2Gb SLC NAND Flash • BP bits for block group protection • Low Power Dissipation - Max 30mA Active current (Read/Program/Erase) • Sleep Mode - 50uA (Max) standby current • High Reliability - Program / Erase Endurance: Typical 100K cycles (with internal 4-bit ECC per (512+16) Byte - Data Retention: 10 years • Wide Temperature Operating Range -40°C to +85°C • Package: 1) 8-WSON (8x6mm) for 1Gb 2)16-SOP (300mil) for 2Gb All packaged devices are RoHS Compliant and Halogen-free. - Bus: x4 - Page size: (2048+64) byte - Block size: (128K+4K) byte • Fast Read Access - Supports Random data read out by x1 x2 & x4 modes, (1-1-1,1-1-2, 1-1-4)Note 2 - Latency of array to register: 25usNote1 - Frequency: 104MHz • Page Program Operation - Page program time: 300us (typ)Note1 • Block Erase Operation - Block erase time: 1ms (typ.) • Single Voltage Operation: - VCC: 2.7 to 3.6V Note 1. Please refer to the tRD_ECC and tPROG_ECC specifications if internal ECC function is turned on. Note 2. Which indicates the number of I/O for command, address and data. REV. 1.2, AUG. 19, 2015 P/N: PM2128 5 MX35LF1GE4AB MX35LF2GE4AB 2. GENERAL DESCRIPTIONS The MX35LFxGE4AB is a 1Gb/2Gb SLC NAND Flash memory device with Serial interface. The memory array of this device adopted the same cell architecture as the parallel NAND, however implementing the industry standard serial interface. An internal 4-bit ECC logic is implemented in the chip, which is enabled by default. The internal ECC can be disabled or enabled again by command. When the internal 4-bit ECC logic is disabled, the host side needs to handle the 4-bit ECC by host micro controller. Figure 1. Logic Diagram SI/SIO0 CS# SCLK# 1Gb 2Gb SO/SIO1 WP#/SIO2 ECC Logic HOLD#/SIO3 REV. 1.2, AUG. 19, 2015 P/N: PM2128 6 MX35LF1GE4AB MX35LF2GE4AB 3. ORDERING INFORMATION Part Name Description Macronix NAND Flash devices are available in different configurations and densities. Verify valid part numbers by using Macronix’s product search at http://www.Macronix.com. Contact Macronix sales for devices not found. MX 35 L F 2G E4A B - M I XX RESERVE OPERATING TEMPERATURE: I: Industrial (-40°C to 85°C) PACKAGE TYPE: Z2: 8-WSON (8x6mm) Z4: 8-WSON (8x6mm, E.P.= 3.4x4.3mm) M: 16-SOP (300mil) Package: RoHS Compliant & Halogen-free GENERATION (Tech. Code): B OPTION CODE: E4A = Quad I/O (x4), Internal ECC default enabled, Mode A DENSITY: 1G= 1Gb bit 2G= 2Gb bit CLASSIFICATION: F = SLC + Large Block VOLTAGE: L = 2.7V to 3.6V TYPE: 35 = Serial NAND Flash BRAND: MX Part Number Density Organization VCC Range Package MX35LF2GE4AB-MI MX35LF1GE4AB-Z2I 2Gb 1Gb x4 x4 3V 3V MX35LF1GE4AB-Z4INote 1Gb x4 3V 16-SOP 8-WSON 8-WSON (E.P.=3.4x4.3mm) Temperature Grade Industrial Industrial Industrial Note: MX35LF1GE4AB-Z4I is highly recommended for 8-WSON package instead of MX35LF1GE4AB-Z2I. REV. 1.2, AUG. 19, 2015 P/N: PM2128 7 MX35LF1GE4AB MX35LF2GE4AB 4. BALL ASSIGNMENT AND DESCRIPTIONS Figure 3. 8-WSON (8x6mm) (1Gb only) Figure 2. 16-SOP (300mil) HOLD#/ SIO3 VCC DNU NC NC NC CS# SO/SIO1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 SCLK SI/SIO0 DNU NC NC NC GND WP#/SIO2 CS# SO/SIO1 WP#/SIO2 GND 1 2 3 4 8 7 6 5 VCC HOLD#/SIO3 SCLK SI/SIO0 5. PIN DESCRIPTIONS SYMBOL CS# SI/SIO0 SO/SIO1 SCLK WP#/SIO2 HOLD#/SIO3 VCC GND NC DNU DESCRIPTION Chip Select Serial Data Input (for 1 x I/O)/ Serial Data Input & Output (for 2xI/O or 4xI/O read mode) Serial Data Output (for 1 x I/O)/ Serial Data Input & Output (for 2xI/O or 4xI/O read mode) Clock Input Write protection: connect to GND or Serial Data Input & Output (for 4xI/O read mode) Hold or Serial Data Input & Output (for 4xI/O read mode) + 3V Power Supply Ground No Connection Do not use REV. 1.2, AUG. 19, 2015 P/N: PM2128 8 MX35LF1GE4AB MX35LF2GE4AB 6. DEVICE OPERATION 1. Before a command is issued, status register should be checked via get features operations to ensure device is ready for the intended operation. 2. When incorrect command is inputted to this device, this device becomes standby mode and keeps the standby mode until next CS# falling edge. In standby mode, SO pin of this device should be High-Z. 3. When correct command is inputted to this device, this device becomes active mode and keeps the active mode until next CS# rising edge. 4. Input data is latched on the rising edge of Serial Clock (SCLK) and data shifts out on the falling edge of SCLK. The difference of Serial mode 0 and mode 3 is shown as "Figure 4. Serial Mode Supported". 5. During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglected and not affect the current operation of Write Status Register, Program, Erase. Figure 4. Serial Mode Supported CPOL CPHA shift in (Serial mode 0) 0 0 SCLK (Serial mode 3) 1 1 SCLK SI shift out MSB SO MSB REV. 1.2, AUG. 19, 2015 P/N: PM2128 9 MX35LF1GE4AB MX35LF2GE4AB Macronix Confidential 7. ADDRESS MAPPING block# 2047Note1 Byte# 2111 Page# 63 block# 0 Block address Page# 0 Note2 2Gb: RA[16:6] 1Gb: RA[15:6] Page address RA[5:0] Byte# 0 Byte address CA[11:0] Note 1: 2047 for 2Gb, 1023 for 1Gb Note 2: RA[6] is for plane select, for 2Gb REV. 1.2, AUG. 19, 2015 P/N: PM2128 10 MX35LF1GE4AB MX35LF2GE4AB 8. COMMAND DESCRIPTION Table 1. Command Set Read/Write Array Commands Command Type Command Code Address Bytes Dummy Bytes Data Bytes Actions Command Type Command Code Address Bytes Dummy Bytes Data Bytes Actions Command Type Command Code Address Bytes Dummy Bytes Data Bytes Actions GET FEATURE SET FEATURE PAGE READ READ FROM CACHE READ FROM CACHE x2 0Fh 1Fh 13h 03h, 0Bh 3Bh 1 0 1 1 0 1 3 0 0 Get features Set features Array read 2 1 1 to 2112 Output cache data on SO 2 1 1 to 2112 Output cache data on SI and SO READ FROM CACHE x4 READ ID Internal ECC Status Read(Note) BLOCK ERASE PROGRAM EXECUTE PROGRAM LOAD 6Bh 9Fh 7Ch D8h 10h 02h 2 1 1 to 2112 Output cache data on SI, SO, WP#, HOLD# 0 1 2 0 1 1 3 0 0 Read device ID Internal ECC Status Output PROGRAM LOAD WRITE RANDOM DATA ENABLE 3 2 0 0 0 1 to 2112 Enter block/page Load program Block erase address, no data, data with cache execute reset first WRITE PROGRAM DISABLE LOAD x4 PROGRAM LOAD RANDOM DATA x4 RESET 84h 06h 04h 32h 34h FFh 2 0 1 to 2112 0 0 0 0 0 0 2 0 1 to 2112 Program Load operation with X4 data input 2 0 1 to 2112 0 0 0 Program Load random data operation with X4 data input Reset the device Load program data without cache reset Note: The 7Ch command is only for 1Gb. For the internal ECC status, which may also check by the Get feature command operation. REV. 1.2, AUG. 19, 2015 P/N: PM2128 11 MX35LF1GE4AB MX35LF2GE4AB 8-1.WRITE Operations 8-1-1.Write Enable The Write Enable (WREN, 06h) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like Page Program, Secure OTP program, Block Erase, which are intended to change the device content WEL bit should be set every time after the WREN instruction setting the WEL bit. The sequence of issuing WREN instruction is: CS# goes low→sending WREN instruction code→ CS# goes high. Figure 5. Write Enable (WREN) Sequence CS# Mode 3 0 1 2 3 4 5 6 7 SCLK Mode 0 Command SI 06h High-Z SO 8-1-2.Write Disable (04h) The Write Disable (WRDI, 04h) instruction is to reset Write Enable Latch (WEL) bit. The sequence of issuing WRDI instruction is: CS# goes low→sending WRDI instruction code→CS# goes high. It disables the following operations: • Block Erase • Secure OTP program • Page program Figure 6. Write Disable (WRDI) Sequence CS# Mode 3 0 1 2 3 4 5 6 7 SCLK Mode 0 Command SI 04h High-Z SO REV. 1.2, AUG. 19, 2015 P/N: PM2128 12 MX35LF1GE4AB MX35LF2GE4AB 8-2.Feature Operations 8-2-1.GET Feature (0Fh) and SET Feature (1Fh) By issuing a one byte address into the feature address, the device may then decide if it's a feature read or feature modification. (0Fh) is for the "GET FEATURE"; (1Fh) is for the "SET FEATURE". The RESET command (FFh) will not clear the previous feature setting, the feature setting data bits remain until the power is being cycled or modified by the settings in the table below. The RESET command (FFh) will not affect the GET Feature command. Table 2-1. Feature Settings (For 2Gb) Register Address bit7 Secure OTP B0h Status C0h Secure OTP Protect Reserved Block Protection A0h BPRWD1 bit6 Secure OTP Enable Reserved Reserved Data Bits bit4 bit3 bit5 bit2 bit1 bit0 Reserved ECC enabled Reserved Reserved Reserved QE ECC_S1 ECC_S0 P_Fail E_Fail WEL OIP BP2 BP1 BP0 Reserved Reserved Reserved Note 1: If BPRWD is enabled and WP# is LOW, then the block protection register cannot be changed. Table 2-2. Feature Settings (For 1Gb) Register Address Secure OTP B0h Status C0h Secure Secure OTP OTP Reserved Protect Enable Reserved Reserved ECC_S1 Block Protection A0h BPRWD1 bit7 bit6 Data Bits bit4 bit3 bit5 Reserved ECC enabled bit2 Reserved Reserved bit1 bit0 Reserved QE ECC_S0 P_Fail E_Fail WEL OIP BP1 BP0 Invert Complementary SP2 BP2 Note 1: If BPRWD is enabled and WP# is LOW, then the block protection register cannot be changed. Note 2: SP bit is for Solid-protection. Once the SP bit sets as 1, the rest of the protection bits (BPx bits, Invert bits, complementary bits) cannot be changed during the current power cycle. Figure 7. GET FEATURE (0Fh) Timing CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 3 2 1 0 16 17 18 19 20 21 22 23 2 1 0 SCLK Command (0Fh) SI Address 7 6 5 4 MSB Data SO High-Z 7 6 5 4 3 MSB Don’t Care REV. 1.2, AUG. 19, 2015 P/N: PM2128 13 MX35LF1GE4AB MX35LF2GE4AB Figure 8. SET FEATURE (1Fh) Timing CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCLK Command 7 (1Fh) SI Data Address 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 MSB MSB Don’t Care 8-3.READ Operations The device supports "Power-on Read" function, after power up, the device will automatically load the data of the 1st page of 1st block from array to cache. The host micro-controller may directly read the 1st page of 1st block data from the cache buffer. The data is also under the internal ECC protection. 8-3-1.PAGE READ (13h) The page read operation transfers data from array to cache by issuing the page read (13h)command followed by the 24-bit address (including the dummy/block/page address). The device will have a period of time (tRD) being busy after the CS# goes high. The 0Fh (GET FEATURE) may be used to poll the operation status. After read operation is completed, the RANDOM DATA READ (03H or 0Bh), Read from cache (x2) (3Bh), and Read from cache (x4) (6Bh) may be issued to fetch the data. Wrap Read Operation (Only for 1Gb) For 1Gb, there are four wrap address bits which define the four wrap length as below table. After the Read from cache command (03h, 0Bh, 3Bh, 6Bh), setting the wrap address bits, and followed by the 12-bit column address to define the starting address. The starting address for wrap read only can be 0 - 2112. The data will be output from the starting address, once it reaches the end of the boundary of wrap length, the data will be wrap around the beginning starting wrap address until CS# goes high. Table 3. Wrap Address bit Table (Only for 1Gb) Wrap [1] 0 0 1 1 Wrap [0] 0 1 0 1 Wrap Length (byte) 2112 2048 64 16 8-3-2.QE bit The Quad Enable (QE) bit, volatile bit, while it is "0" (factory default), it performs non-Quad and WP#, HOLD# are enabled. While QE is "1", it performs Quad I/O mode and WP#, HOLD# are disabled. In another word, if the system goes into four I/O mode (QE=1), the feature of Hardware Protection Mode(HPM) and HOLD will be disabled. Upon power cycle, the QE bit will go into the factory default setting "0". REV. 1.2, AUG. 19, 2015 P/N: PM2128 14 MX35LF1GE4AB MX35LF2GE4AB Figure 9. PAGE READ (13h) Timing x1 A CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 13 12 11 10 9 8 7 6 14 15 1 0 SCLK 24-bit Address Command SI 23 (13h) 22 21 20 19 18 17 16 15 14 High-Z SO A B CS# 23 24 25 26 27 28 29 30 0 31 1 2 3 4 5 6 7 8 9 10 11 12 13 SCLK 24-bit Address SI 8 7 6 5 4 3 t CS 2 1 Status register address (C0h) GET FEATURES (0Fh) 0 7 6 5 4 3 2 MSB Plane select for 2Gb SO High-Z B CS# 13 14 15 2 1 0 16 17 18 19 20 21 22 23 SCLK SI Status register data out SO 07 MSB 60 5 4 3 2 Status register data out 1 0 7 6 5 4 3 2 1 0 MSB Don’t Care REV. 1.2, AUG. 19, 2015 P/N: PM2128 15 MX35LF1GE4AB MX35LF2GE4AB Figure 10. RANDOM DATA READ (03h or 0Bh) Timing A CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 SCLK 3 Dummy bits Command (03 or 0Bh) SI 15 Wrap[1:0] for 1Gb High-Z SO 14 13 12-Bit Address 12 11 10 9 8 7 6 1 Dummy byte 5 4 3 2 1 7 0 6 MSB Plane select for 2Gb A CS# 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 16919... 16927 SCLK 1 Dummy byte SI 0 7 6 5 4 3 2 1 0 Data OUT 1 SO High-Z 7 6 5 4 3 MSB Data OUT 2112 2 1 0 7 6 5 4 3 2 1 0 MSB Don’t Care REV. 1.2, AUG. 19, 2015 P/N: PM2128 16 MX35LF1GE4AB MX35LF2GE4AB Figure 11. READ FROM CACHE x 2 A CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 SCLK 3 Dummy bits Command SI (3Bh) 15 Wrap[1:0] for 1Gb High-Z SO 14 13 1 Dummy byte 12-Bit Address 12 11 10 9 8 7 6 5 4 3 2 1 0 6 7 MSB Plane select for 2Gb A CS# 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 8479 8471... SCLK SI switches from input to output 1 Dummy byte SI SO 0 7 6 5 High-Z 4 3 2 1 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 Data OUT 2 Data OUT 1 Data OUT 2111 Data OUT 2112 REV. 1.2, AUG. 19, 2015 P/N: PM2128 17 MX35LF1GE4AB MX35LF2GE4AB Figure 12. READ FROM CACHE x 4 A CS# 0 1 2 3 5 4 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 SCLK 3 Dummy bits Command SI/ SIO0 15 (6Bh) SO/ SIO1 High-Z WP#/ SIO2 High-Z HOLD#/ SIO3 High-Z 14 Wrap[1:0] for 1Gb 13 1 Dummy byte 12-Bit Address 12 11 10 9 8 38 39 7 6 5 4 3 2 1 0 7 6 MSB Plane select for 2Gb A CS# 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 SCLK SI/ 0 SIO0 SI switches from input to output 1 Dummy byte 7 6 5 4 3 2 1 0 4 0 4 0 4 0 4 0 4 SO/ SIO1 High-Z 5 1 5 1 5 1 5 1 5 WP#/ SIO2 High-Z 6 2 6 2 6 2 6 2 6 HOLD#/ SIO3 High-Z 7 3 7 3 7 3 7 3 7 Byte 1 Byte 2 Byte 3 Byte 4 REV. 1.2, AUG. 19, 2015 P/N: PM2128 18 MX35LF1GE4AB MX35LF2GE4AB 8-3-3.READ ID (9Fh) The READ ID command is shown as the table below. Table 4. READ ID Table Byte Description I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Value Byte 0 Manufacturer ID (Macronix) 1 1 0 0 0 0 1 0 C2h Byte 1 Device ID (Serial NAND) 0 0 0 1 0 0 1 0 12h (1Gb) 0 0 1 0 0 0 1 0 22h (2Gb) Figure 13. READ ID (9Fh) Timing A CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 2 1 15 16 17 18 19 20 21 22 23 24 25 SCLK 1 Dummy byte Command SI 7 (9Fh) 6 5 4 3 0 Device Identification Manufacturer Identification (C2h) High-Z SO 7 6 5 4 3 2 1 0 7 6 MSB A CS# 23 24 25 26 27 28 29 30 31 SCLK SI Device Identification SO 7 6 5 4 3 2 1 0 MSB Don’t Care REV. 1.2, AUG. 19, 2015 P/N: PM2128 19 MX35LF1GE4AB MX35LF2GE4AB 8-4.Parameter Page The parameter page is accessed by the following command flows: Issue 1Fh (SET FEATURE) command with Secure OTP enable and ECC disabled (B0h for address & 40h for data) → Issue 13h (PAGE READ) with 01h address, issue 0Fh (GET FEATURE) with C0h feature address to poll the status of read completion. → Issue 03h (READ FROM CACHE) with address A[11:0]=000h and read data → Issue 1Fh (SET FEATURE) with feature address B0h to disable Secure OTP feature (data byte = 10h or 00h) [exit parameter page read]. REV. 1.2, AUG. 19, 2015 P/N: PM2128 20 MX35LF1GE4AB MX35LF2GE4AB Table 5. Parameter Page Data Structure Byte 0–3 4–5 6–7 8–9 10–31 32–43 44–63 64 65–66 67–79 80–83 84–85 86–89 90–91 92–95 96–99 100 101 102 Description Parameter page signature Revision number Features supported (N/A) Optional commands supported Value 4Fh, 4Eh, 46h, 49h 00h, 00h 00h, 00h 06h, 00h 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, Reserved 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h 4Dh,41h,43h,52h,4Fh,4Eh,49h,58h,20h, Device manufacturer 20h,20h,20h 4Dh, 58h, 33h, 35h, 4Ch, 46h, 31h, 47h, MX35LF1GE4AB 45h, 34h, 41h, 42h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h Device model 4Dh, 58h, 33h, 35h, 4Ch, 46h, 32h, 47h, MX35LF2GE4AB 45h, 34h, 41h, 42h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h Manufacturer ID C2h Date code 00h, 00h 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, Reserved 00h, 00h, 00h, 00h, 00h Number of data bytes per page 00h, 08h, 00h, 00h Number of spare bytes per page 40h, 00h Number of data bytes per partial page 00h, 02h, 00h, 00h Number of spare bytes per partial page 10h, 00h Number of pages per block 40h, 00h, 00h, 00h 1Gb 00h, 04h, 00h, 00h Number of blocks per unit 2Gb Number of logical units Number of address cycles (N/A) Number of bits per cell 1Gb 2Gb 103–104 Bad blocks maximum per unit 105–106 107 108–109 110 111 112 113 114 00h, 08h, 00h, 00h 01h 00h 01h Block endurance Guaranteed valid blocks at beginning of target Block endurance for guaranteed valid blocks Number of programs per page Partial programming attributes Number of ECC bits Number of interleaved address bits (N/A) Interleaved operation attributes (N/A) 115–127 Reserved 128 I/O pin capacitance 129–130 Timing mode support (N/A) 14h, 00h 28h, 00h 01h, 05h 01h 00h, 00h 04h 00h 00h 00h 00h 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h 0Ah 00h, 00h REV. 1.2, AUG. 19, 2015 P/N: PM2128 21 MX35LF1GE4AB MX35LF2GE4AB Byte 131–132 133–134 135–136 137–138 139–140 Description Program cache timing (N/A) tPROG maximum page program time BE maximum block erase time tRD_ECC maximum page read time tCCS minimum (N/A) 141–163 Reserved 164–165 Vendor-specific revision number Value 600us 3500us 70us 00h, 00h 58h, 02h ACh, 0Dh 46h, 00h 00h, 00h 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h Vendor specific 00h, 00h 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h 254–255 Integrity CRC Set at test (Note 2) 256–511 512–767 768+ Value of bytes 0–255 Value of bytes 0–255 Additional redundant parameter pages 166–253 Notes: 1. h = hexadecimal. 2. The Integrity CRC (Cycling Redundancy Check) field is used to verify that the contents of the parameters page were transferred correctly to the host. Please refer to ONFI 1.0 specifications for details. The CRC shall be calculated using the following 16-bit generator polynomial: G(X) = X16 + X15 +X2 + 1 8-5.UniqueID Page The UniqueID page is accessed by the following command flows: Issue 1Fh (SET FEATURE) command with Secure OTP enable and ECC disabled (B0h for address & 40h for data) → Issue 13h (PAGE READ) with 00h address, issue 0Fh (GET FEATURE) with C0h feature address to poll the status of read completion → Issue 03h (READ FROM CACHE) with address A[11:0]=000h and read data → Issue 1Fh (SET FEATURE) with feature address B0h to disable Secure OTP function (data byte =10h or 00h) [exit unique ID read] UniqueID data: 16x32byte of UniqueID data. On each 32byte, the first 16byte and following 16byte should be XOR to be FFh. REV. 1.2, AUG. 19, 2015 P/N: PM2128 22 MX35LF1GE4AB MX35LF2GE4AB 8-6.Internal ECC Status Read (For 1Gb only) Besides the Get Feature( with feature address of C0h) may collect the internal ECC status; the 7Ch command may read out more status of internal ECC, such as 1-bit error, 2-bit error, 3-bit error, or 4-bit error by ECCSR[3:0] which Get Feature (with C0h address) cannot distinguish it. Please refer to the "Table 6-1. The ECCSR (Internal ECC Status Register) Bits" & "Table 6-2. The Definition of Internal ECC Status" about the ECCSR definition. The ECC Status Register reports the highest bit error correction among the four segments of a page. For example, if Segment 1 had a 1-bit error corrected, Segment 2 had no bit error, Segment 3 had a 2-bit error corrected, and Segment 4 had no bit error, then the ECC register would report that a 2-bit error was corrected. The register is updated after the completion of the Page Read Command (13h) The Reset Command (FFh) will clear the register to 00h. Table 6-1. The ECCSR (Internal ECC Status Register) Bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Reserved Reserved Reserved Reserved ECCSR[3] ECCSR[2] ECCSR[1] ECCSR[0] Table 6-2. The Definition of Internal ECC Status ECCSR[3:0] ECC Status 0000 No bit error 0001 1-bit error corrected 0010 2-bit error corrected 0011 3-bit error corrected 0100 4-bit error corrected 1111 Uncorrectable Each Page has four 528-Byte ECC segments and each 528-Byte segment consists of 512 Bytes from the Data Area and its associated 16 Bytes from the Spare Area. Figure 14. The Page Structure and Internal ECC Segments 2112-Byte Page Segment 1 512 Bytes Segment 2 512 Bytes Segment 3 512 Bytes Segment 4 512 Bytes Segment 1 Segment 2 16 Bytes 16 Bytes 2048-Byte Data Area Segment 3 16 Bytes Segment 4 16 Bytes 64-Byte Spare Area Operation sequence: Command (7Ch)→Dummy Byte (xxh) →Read ECC Status Register REV. 1.2, AUG. 19, 2015 P/N: PM2128 23 MX35LF1GE4AB MX35LF2GE4AB Figure 15. The Sequence of Internal ECC Status Read CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 2 1 0 16 17 18 7 6 5 19 20 21 22 23 2 1 0 SCLK Command SI 1 dummy byte 7 (7Ch) 6 5 4 3 ECC Status SO High-Z 4 3 REV. 1.2, AUG. 19, 2015 P/N: PM2128 24 MX35LF1GE4AB MX35LF2GE4AB 8-7.Program Operations 8-7-1.PAGE PROGRAM With following operation sequences, the PAGE PROGRAM operation programs the page from byte 1 to byte 2112. WRITE ENABLE (06h) → PROGRAM LOAD (02h) → PROGRAM LOAD RANDOM DATA (84h) if needed → PROGRAM EXECUTE (10h) → GET FEATUR from command to read status (0Fh). WEL bit is set with the WRITE ENABLE (06h) issued. The program operation will be ignored if 06h command not issued. In a single page, four partial page programs are allowed. Exceeded bytes (Page address is larger than 2112) for "PROGRAM LOAD" or "PROGRAM LOAD RANDOM DATA", the exceeding bytes will be ignored. When CS goes high, the "PROGRAM LOAD" or "PROGRAM LOAD RANDOM DATA" operation" terminates. Please note the figure below for PROGRAM LOAD. After PROGRAM LOAD is done, the programming of data should be as following steps: issue 10h (PROGRAM EXECUTE) with 1byte command code, 24 bits address → code programming to memory and busy for tPROG → Program complete. During programming, status to be polled by the status register. Operation shows in the Figure below. Figure 16. PROGRAM LOAD (02h) Timing A CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 0 7 25 SCLK 3 Dummy bits Command SI 15 (02h) 14 12-Bit Address 13 12 11 10 9 8 7 6 5 Data byte 1 4 3 2 1 6 MSB Plane select for 2Gb A CS# 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 16912… 16919 SCLK Data byte 1 SI 7 6 5 4 3 Data byte 2 2 1 0 7 6 5 4 3 Data byte 2112 2 1 0 7 6 5 4 3 2 1 0 Don’t Care REV. 1.2, AUG. 19, 2015 P/N: PM2128 25 MX35LF1GE4AB MX35LF2GE4AB Figure 17. PROGRAM LOAD RANDOM DATA (84h) Timing A CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 SCLK 3 Dummy bits Command (84h) SI 15 14 Data byte 1 12-Bit Address 13 12 11 10 9 8 37 38 39 7 6 5 4 3 2 1 0 7 6 MSB Plane select for 2Gb A CS# 23 24 25 26 27 28 29 30 31 32 33 34 35 36 16912… 16919 SCLK Data byte 1 SI 7 6 5 4 3 Data byte 2112 Data byte 2 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Don’t Care REV. 1.2, AUG. 19, 2015 P/N: PM2128 26 MX35LF1GE4AB MX35LF2GE4AB 8-7-2.QUAD IO PAGE PROGRAM QUAD IO PAGE PROGRAM conducts the 2Kbyte program with 4 I/O mode. The steps are: WRITE ENABLE (06h) → PROGRAM LOAD X4 (32h) → PROGRAM LOAD RANDOM DATA (34h) if needed → PROGRAM EXECUTE (10h) → Poll status by issuing GET FEATURE (0Fh). Figure 18. PROGRAM LOAD X4 (32h) Timing A CS# 0 1 2 3 4 5 6 7 8 9 10 11 20 21 22 23 24 25 26 27 28 29 30 31 SCLK 3 Dummy bits Command SI SIO0 12-Bit Address 4 0 4 0 4 0 4 0 5 1 5 1 5 1 5 1 WP# SIO2 6 2 6 2 6 2 6 2 HOLD# SIO3 7 3 7 3 7 3 7 3 (32h) 15 14 13 11 Byte 2 Byte 1 12 3 2 1 0 MSB Plane select for 2Gb SO SIO1 A CS# 31 32 33 34 35 36 37 38 39 40 41 42 43 SCLK 44 45 46 47 Byte 1111 Byte 1112 SI SIO0 Byte 11 Byte 12 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 SO SIO1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 WP# SIO2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 HOLD# SIO3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 Don’t Care REV. 1.2, AUG. 19, 2015 P/N: PM2128 27 MX35LF1GE4AB MX35LF2GE4AB Figure 19. QUAD IO PROGRAM RANDOM INPUT (34h) Timing A CS# 0 1 2 3 4 5 6 7 8 9 10 11 20 21 22 23 24 25 26 27 28 29 30 31 SCLK 3 Dummy bits Command SI SIO0 (34h) 15 14 12-Bit Address 13 11 12 3 2 1 MSB Plane select for 2Gb SO SIO1 Byte 2 Byte 1 0 4 0 4 0 4 0 4 0 5 1 5 1 5 1 5 1 WP# SIO2 6 2 6 2 6 2 6 2 HOLD# SIO3 7 3 7 3 7 3 7 3 A CS# 31 32 33 34 35 36 37 38 39 40 41 42 43 SCLK 44 45 46 47 Byte 1111 Byte 1112 SI SIO0 Byte 11 Byte 12 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 SO SIO1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 WP# SIO2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 HOLD# SIO3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 Don’t Care REV. 1.2, AUG. 19, 2015 P/N: PM2128 28 MX35LF1GE4AB MX35LF2GE4AB Figure 20. PROGRAM EXECUTE (10h) Timing A CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 7 6 SCLK 24-Bit Address Command (10h) SI 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 High-Z SO B A CS# 23 24 25 26 27 28 29 30 0 31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK 24-Bit Address SI 7 6 5 4 3 Status register address (C0h) Get Feature 2 1 0 (0Fh) 7 Plane select for 2Gb High-Z SO 6 5 4 3 2 1 0 MSB B CS# 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 1 0 SCLK Status register Address SI 2 1 0 Status register data out SO High-Z 7 6 5 4 3 2 1 Status register data out 0 7 MSB 6 5 4 3 2 MSB Don’t Care REV. 1.2, AUG. 19, 2015 P/N: PM2128 29 MX35LF1GE4AB MX35LF2GE4AB 9. BLOCK OPERATIONS 9-1.Block Erase (D8h) The Block Erase (D8h) instruction is for erasing the data of the chosen block to be "1". The instruction is used for a block of 128K-byte erase operation. A Write Enable (WREN) instruction be executed to set the Write Enable Latch (WEL) bit before sending the Block Erase (D8h). Any address of the block is a valid address for Block Erase (D8h) instruction. The CS# must go high exactly at the byte boundary (the least significant bit of address byte been latched-in); otherwise, the instruction will be rejected and not executed. Finally, a Get Feature(0Fh) instruction to check the status is necessary. The sequence of issuing Block Erase instruction is: CS# goes low→ sending Block Erase instruction code→ 24-bit address on SI→CS# goes high. The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Get Feature (0Fh) instruction with Address (C0h) may check the status of the operation during the Block Erase cycle is in progress (please refer to the Get Feature waveform and table of Feature Setting). The OIP bit is "1" during the tBE timing, and is cleared to "0" when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. Figure 21. Block Erase (BE) Sequence CS# Mode 3 0 1 2 3 4 5 6 7 8 9 29 30 31 SCLK Mode 0 SI Command 24-Bit Address(Note) D8h A23 A22 A2 A1 A0 MSB Note: The 24-bit Address includes: 17-bit row address and 7-bit dummy (for 2Gb), or 16-bit row address and 8-bit dummy (for 1Gb). REV. 1.2, AUG. 19, 2015 P/N: PM2128 30 MX35LF1GE4AB MX35LF2GE4AB 10. Feature Register Feature register defines various register's definitions (Block Protection, Secure OTP, Status register). The definition of each register is defined in "Table 7-1. Definition of Protection Bits (BPx) (For 2Gb)" and "Table 7-2. Definition of Protection Bits (For 1Gb)": 10-1.Block Protection Feature The Block Protection feature includes three block protection bits (BPx), Block Protection Register Write Disable (BPRWD). For 1Gb, there are three more feature bits, including Inverse bit (INVERT), complement bit (CMPLEMENTARY) and Solid Protection Bit (SP). Soft Protection Mode (SPM) The SPM uses the BPx bits, INVERT, and COMPLEMENTARY bits to allow part of memory to be protected as read only. The protected area definition is shown as "Table 7-1. Definition of Protection Bits (BPx) (For 2Gb)" and "Table 7-2. Definition of Protection Bits (For 1Gb)", the protected areas are more flexible which may protect various area by setting value of BP0-BP3 bits. These are volatile bits and can be modified by set feature command. Note: INVERT, and COMPLEMENTARY bits are for 1Gb only. After power-up, the chip is in protection state, that is, the feature bits BPx is 1, all other bits (BPRWD, INVERT, COMPLEMENTARY and SP) are 0. The Set feature instruction (1Fh) with feature address (A0h) may change the value of the block protection bits and un-protect whole chip or a certain area for further program/erase operation. For example, after the power-on, the whole chip is protected from program/erase operation, the top 1/64 area may be un-protected by using the Set feature instruction (1Fh) with the feature address (A0h) to change the values of BP2 and BP1 from "1" to "0" as "Table 7-1. Definition of Protection Bits (BPx) (For 2Gb)" and "Table 7-2. Definition of Protection Bits (For 1Gb)" of "Block protection register bits". Hardware Protection Mode (HPM) & Solid Protection Mode (SDPM) Under the Hardware Protection mode and Solid Protection Mode, the (BPx, INVERT, COMPLEMENTART) bits can not be changed. Hardware Protection Mode: The device enters HPM if BPRWD bits is set to 1 and WP#/SIO2 is driven to 0. Note 1: The 1Gb HPM also requires SP bit to be 0 state (SP bit is for 1Gb only). Note 2: The Quad mode is not supported in HPM. Solid Protection Mode: If SP bit is set to 1, the device enters SDPM (Only for 1Gb). After that, the selected block is solid protected and can not be un-protected until next power cycle. REV. 1.2, AUG. 19, 2015 P/N: PM2128 31 MX35LF1GE4AB MX35LF2GE4AB Table 7-1. Definition of Protection Bits (BPx) (For 2Gb) Block Protection Register Bits Protected Area BP2 BP1 BP0 0 0 0 None - all unprotected 0 0 1 Top 1/64 protected 0 1 0 Top 1/32 protected 0 1 1 Top 1/16 protected 1 0 0 Top 1/8 protected 1 0 1 Top 1/4 protected 1 1 0 Top 1/2 protected 1 1 1 All protected (default) Note: Block #0 is at bottom portion. Table 7-2. Definition of Protection Bits (For 1Gb) BP2 BP1 BP0 Invert Complementary 0 0 0 0 1 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 1 1 0 0 1 0 1 1 0 0 1 0 1 1 0 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 x 0 0 0 0 0 0 x 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 x 0 0 0 0 0 0 x 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 Protection Area all unlocked upper 1/64 locked upper 1/32 locked upper 1/16 locked upper 1/8 locked upper 1/4 locked upper 1/2 locked all locked (default) lower 1/64 locked lower 1/32 locked lower 1/16 locked lower 1/8 locked lower 1/4 locked lower 1/2 locked lower 63/64 locked lower 31/32 locked lower 15/16 locked lower 7/8 locked lower 3/4 locked block 0 upper 63/64 locked upper 31/32 locked upper 15/16 locked upper 7/8 locked upper 3/4 locked block0 Note: Block #0 is at lower portion. REV. 1.2, AUG. 19, 2015 P/N: PM2128 32 MX35LF1GE4AB MX35LF2GE4AB 10-2.Secure OTP (One-Time-Programmable) Feature There is an Secure OTP area which has 30 full pages (30 x 2112-byte) from page 02h to page 1Fh guarantee to be good for system device serial number storage or other fixed code storage. The Secure OTP area is a non-erasable and one-time-programmable area, which is default to “1” and allows partial page program to be “0”, once the Secure OTP protection mode is set, the Secure OTP area becomes read-only and cannot be programmed again. The Secure OTP operation is operated by the Set Feature instruction with feature address (B0h) to access the Secure OTP operation mode and Secure OTP protection mode. To check the NAND device is ready or busy in the Secure OTP operation mode, the status register bit 0 (OIP bit) may report the status by Get Feature command operation. To exit the Secure OTP operation or protect mode, it can be done by writing "0" to both Bit7 (Secure OTP protect bit) and bit6 (Secure OTP enable bit) for returning to the normal operation. Secure OTP Read 1. Issuing the Set Feature instruction (1Fh) 2. Sending the Feature address (B0h) and set the "Secure OTP Enabled Bit" as "1". 3. Issuing normal Page Read command (13h) Secure OTP Program (if the "Secure OTP Protection Bit" is "0") for 1. 2. 3. 4. Issuing the Set Feature instruction (1Fh) Sending the Feature address (B0h) and set the "Secure OTP Enabled Bit" as "1". Issuing Page Program command (02h) Issuing program execute command (10h) Secure OTP Protection 1. Issuing the Set Feature instruction (1Fh) 2. Sending the Feature address (B0h) and set both the "Secure OTP Protection Bit" and "Secure OTP Enabled Bit" as "1". 3. Issuing program execute command (10h) Table 8. Secure OTP States Secure OTP Protection BitNote1 Secure OTP Enabled Bit 0 0 Normal operation 0 1 Access the Secure OTP for reading or programming 1 0 Not applicable 1 1 Secure OTP Protection by using the Program Execution command (10h)Note2 State Note 1. OTP protection bit is non-volatile. Note 2. Once the "Secure OTP Protection Bit" and "Secure OTP Enabled Bit" are set as "1", the secure OTP becomes read only. REV. 1.2, AUG. 19, 2015 P/N: PM2128 33 MX35LF1GE4AB MX35LF2GE4AB 10-3.Status Register The MX35LFxGE4AB provides a status register that outputs the device status by writing a Get Feature command (0Fh) with the feature address (C0h), and then the IO pins output the status. The Get Feature (0Fh) command with the feature address(C0h) will keep the device at the status read mode unless next valid command is issued. The resulting information is outlined in the table below. Table 9. Status Register Bit Descriptions SR Bit Bit Name SR[0] (OIP) Operation in progress SR[1] (WEL) Write enable latch SR[2] (ERS_Fail) Erase fail SR[3] (PGM_Fail) Program fail Description The bit value indicates whether the device is busy in operations of read/ program execute/ erase/ reset command. 1: Busy, 0: Ready The bit value indicates whether the device is set to internal write enable latch. When WEL bit sets to 1, which means the internal write enable latch is set, and then the device can accept program/ erase/write status register instruction. 1: write enable, 0: not write enable The bit value will be cleared (as "0") by issuing Write Disable command(04h). The bit value shows the status of erase failure or if host erase any invalid address or protected area (including protected blocks or protected Secure OTP area). 0: Passed, 1: Failed The bit value will be cleared (as "0") by RESET command or at the beginning of the block erase command operation. The bit value shows the status of program failure or if host program any invalid address or protected area (including protected blocks or protected Secure OTP area). 0: Passed, 1: Failed The bit value will be cleared (as "0") by RESET command or during the program execute command operation. The bit shows the status of ECC as below: 00b = 0 bit error 01b = 1 to 4 bits error corrected. 10b = More than 4-bit error not corrected. SR[5:4] (ECC_S1, ECC_S0) ECC Status 11b = Reserved The value of ECC_Sx (S1:S0) bits will be clear as "00b" by Reset command or at the start of the Read operation. After a valid Read operation completion, the bit will be updated to reflect the ECC status of the current valid Read operation. The ECC_Sx (S1:S0) value reflects the ECC status of the content of the page 0 of block 0 after a power-on reset. If the internal ECC is disabled by the Set feature command, the ECC_ Sx(S1:S0) are invalid. SR[6:7] Reserved REV. 1.2, AUG. 19, 2015 P/N: PM2128 34 MX35LF1GE4AB MX35LF2GE4AB 11. SOFTWARE ALGORITHM 11-1. Invalid Blocks (Bad Blocks) The bad blocks are included in the device while it gets shipped. During the time of using the device, the additional bad blocks might be increasing; therefore, it is necessary to check the bad block marks and avoid using the bad blocks. Furthermore, please read out the bad block information before any erase operation since the bad block marks may be cleared by any erase operation. Figure 22. Bad Blocks Bad Block Bad Block While the device is shipped, the value of all data bytes of the good blocks are FFh. The 1st byte of the 1st and 2nd page in the spare area for bad block will be 00h. The erase operation at the bad blocks is not recommended. After the device is installed in the system, the bad block checking is recommended. "Figure 23. Bad Block Test Flow" shows the brief test flow by the system software managing the bad blocks while the bad blocks were found. When a block gets damaged, it should not be used any more. Due to the blocks are isolated from bit-line by the selected gate, the performance of good blocks will not be impacted by bad ones. Table 10. Valid Blocks Density Min. Typ. Max. Unit Valid (Good) 1Gb 1004 1024 Block Block Number 2Gb 2008 2048 Block Remark Block 0 is guaranteed to be good (with ECC). REV. 1.2, AUG. 19, 2015 P/N: PM2128 35 MX35LF1GE4AB MX35LF2GE4AB 11-2. Bad Block Test Flow Although the initial bad blocks are marked by the flash vendor, they could be inadvertently erased and destroyed by a user that does not pay attention to them. To prevent this from occurring, it is necessary to always know where any bad blocks are located. Continually checking for bad block markers during normal use would be very time consuming, so it is highly recommended to initially locate all bad blocks and build a bad block table and reference it during normal NAND flash use. This will prevent having the initial bad block markers erased by an unexpected program or erase operation. Failure to keep track of bad blocks can be fatal for the application. For example, if boot code is programmed into a bad block, a boot up failure may occur. "Figure 23. Bad Block Test Flow" shows the recommended flow for creating a bad block table. Figure 23. Bad Block Test Flow Start Block No. = 0 Yes (Note1) Read 00h Check Create (or Update) Bad Block Table No Block No. = 1023 Block No. = Block No. + 1 (Note2) No Yes End Note 1: Read 00h check is at the 1st byte of the 1st and 2nd pages of the block spare area. Note 2: The Block No. = 1023 for 1Gb, 2047 for 2Gb. 11-3. Failure Phenomena for Read/Program/Erase Operations The device may fail during a Read, Program or Erase operation. The following possible failure modes should be considered when implementing a highly reliable system: Table 11. Failure Modes Failure Mode Detection and Countermeasure Sequence Erase Failure Status Read after Erase Block Replacement Programming Failure Status Read after Program Block Replacement Read Failure (Note) Read Failure ECC Note: If the internal ECC is enabled, the internal ECC will handle the Read failure. REV. 1.2, AUG. 19, 2015 P/N: PM2128 36 MX35LF1GE4AB MX35LF2GE4AB 11-3-1. Internal ECC Enabled/Disabled The internal ECC logic may detect 5-bit error and correct 4-bit error. The default state of the internal ECC is enabled. To enable/disable the internal ECC, it is operated by the Set Feature operation to enable internal ECC or disable the internal ECC, and then check the internal ECC state by Get Feature operation. The internal ECC is enabled by using Set Feature command (1Fh) and followed by feature address (B0h) and then set Bit4( ECC enabled) as "1". To disable the internal ECC can be done by using the Set Feature command (1Fh) and followed by the feature address (B0h) and then set Bit4( ECC enabled) as "0". When the internal ECC is enabled, after the data transfer time (tRD_ECC) is completed, a Status Read operation is required to check any uncorrectable read error happened. Please refer to "Table 9. Status Register Bit Descriptions". The constraint of the internal ECC enabled operation: • The ECC protection coverage: please refer to "Table 12. The Distribution of ECC Segment and Spare Area". Only the grey areas are under internal ECC protection when the internal ECC is enabled. • The number of partial-page program is not 4 in an ECC segment, the user need to program the main area (512B)+Metadata1(4B) at one program time, so the ECC parity code can be calculated properly and stored in the additional hidden spare area. Table 12. The Distribution of ECC Segment and Spare Area Area Main Area (0) Main Area (1) Main Area (2) Main Area (3) Spare(0) R1 M2 M1 Spare(1) R2 R1 M2 M1 Spare(2) R2 R1 M2 M1 Spare(3) R2 R1 M2 M1 R2 Addr. 000h 200h 400h 600h 800h 802h 804h 808h 810h 812h 814h 818h 820h 822h 824h 828h 830h 832h 834h 838h (Start) Addr. 1FFh 3FFh 5FFh 7FFh 801h 803h 807h 80Fh 811h 813h 817h 81Fh 821h 823h 827h 82Fh 831h 833h 837h 83Fh (End) Size 512(B) 512(B) 512(B) 512(B) 2(B) 2(B) 4(B) 8(B) 2(B) 2(B) 4(B) 8(B) 2(B) 2(B) 4(B) 8(B) 2(B) 2(B) 4(B) 8(B) Notes: R1/R2: Reserved M2: Metadata 2 M1: Metadata 1 Grey area: Under ECC protection REV. 1.2, AUG. 19, 2015 P/N: PM2128 37 MX35LF1GE4AB MX35LF2GE4AB 12. DEVICE POWER-UP 12-1.Power-up After the Chip reaches the power on level, the internal power on reset sequence will be triggered. During the internal power on reset period, no any external command is accepted. The device can be fully accessible when VCC reaches the power-on level and wait 1ms. During the power on and power off sequence, it is necessary to keep the WP# = Low for internal data protection. Figure 24. Power On Sequence Vcc Chip Selection is Not Allowed Vcc=2.5V 1ms Device is fully accessible Time REV. 1.2, AUG. 19, 2015 P/N: PM2128 38 MX35LF1GE4AB MX35LF2GE4AB 13. PARAMETERS 13-1.ABSOLUTE MAXIMUM RATINGS Temperature under Bias -50°C to +125°C Storage temperature -65°C to +150°C All input voltages with respect to ground (Note 2) -0.6V to 4.6V VCC supply voltage with respect to ground (Note 2) -0.6V to 4.6V ESD protection >2000V Notes: 1. The reliability of device may be impaired by exposing to extreme maximum rating conditions for long range of time. 2. Permanent damage may be caused by the stresses higher than the "Absolute Maximum Ratings" listed. 3. During voltage transitions, all pins may overshoot Vss to -2.0V and Vcc to +2.0V for periods up to 20ns, please refer to "Figure 25. Maximum Negative Overshoot Waveform" and "Figure 26. Maximum Positive Overshoot Waveform". Figure 25. Maximum Negative Overshoot Waveform 20ns Figure 26. Maximum Positive Overshoot Waveform 20ns 20ns Vss Vcc + 2.0V Vss-2.0V Vcc 20ns 20ns 20ns Table 13. AC Testing Conditions Testing Conditions Value Unit 0 to VCC V Output load capacitance 1TTL+CL(30) pF Input rising & falling time 5 ns Input timing measurement reference levels VCC/2 V Output timing measurement reference levels VCC/2 V Input pulse level Table 14. Capacitance TA = +25°C, F = 1 MHz Symbol Parameter CIN Input capacitance COUT Output capacitance Min. Typ. Max. Units Conditions 8 pF VOUT = 0V 6 pF VIN = 0V Note: CIN/COUT=10pF/10pF for 2Gb Table 15. Operating Range Temperature VCC Tolerance -40°C to + 85°C +3.3V 2.7 - 3.6V REV. 1.2, AUG. 19, 2015 P/N: PM2128 39 MX35LF1GE4AB MX35LF2GE4AB Table 16. DC Characteristics Symbol Max. Unit ILI Input leakage current Parameter Min. Typical +/- 10 uA VIN= 0 to VCC Max. Test Conditions ILO Output leakage current +/- 10 uA VOUT= 0 to VCC Max. ISB VCC standby current (CMOS) ICC1 ICC2 VCC active current (Sequential Read) VCC active current (Program) ICC3 VCC active current (Erase) VIL Input low level -0.3 VIH Input high level 0.8VCC VCC + 0.3 V VOL Outout low voltage 0.2 V IOL= -1mA VOH Outout high voltage V IOH= -20uA 15 50 uA VIN=VCC or GND, CS#=VCC 20Note 30 mA f=104MHz 20Note 30 mA 30 mA 0.2VCC V 15 VCC-0.2 Note: ICC1/ICC2 typical value is 15mA for 1Gb. Table 17. General Timing Characteristics Symbol Parameter fC tCHHH tCHHL tCS tCHSH tSLCH tSHCH tCHSL tDIS tHC tHD tHDDAT tHO tHZ tLZ tSUDAT tV tWH tWL tWPH tWPS Clock Frequency HOLD# high hold time relative to SCLK HOLD# low hold time relative to SCLK Command diselect time Chip select# hold time Chip select# setup time Chip select# non-active setup time Chip select# non-active hold time Output disable time Hold# non-active setup time relative to SCLK Hold# setup time relative to SCLK Data input hold time Output hold time Hold to output High-Z Hold to output low-Z Data input setup time Clock LOW to output Valid Clock HIGH time Clock LOW time WP# hold time WP# setup time Min. Max. Unit 5 5 100 5 5 5 5 5 5 3.5 1 3.5 4 4 100 20 104 - 20 15 15 8 - MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Min. Max. Unit 45 70 us 5/10/500 300 320 1 - 600 600 3.5 4 us us us ms cycle Table 18. PROGRAM/READ/ERASE Characteristics Symbol Parameter tRD Data transfer time from NAND Flash array to data register. tRD_ECC Data transfer time from NAND Flash array to data register with internal ECC enabled Device reset time (Read/ Program/ Erase) Page programming time Page programming time under internal ECC enabled Block Erase Time Number of partial-page programming operation supported tRST tPROG tPROG_ECC tERS NOPNote Note: - 25 us When internal ECC is enabled, the partial program cycle is limited to be one for each ECC unit, and do not exceed the four partial program cycles per page. REV. 1.2, AUG. 19, 2015 P/N: PM2128 40 MX35LF1GE4AB MX35LF2GE4AB Figure 27. WP# Setup Timing and Hold Timing during SET FEATURE when BPRWD=1 WP# tWPH tWPS CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 2 1 0 SCLK Data In FEATURE ADDRESS (A0h) SI 1Fh 7 6 5 4 3 2 1 0 MSB 7 6 5 4 3 MSB High-Z SO Figure 28. Serial Input Timing tCS CS# tCHSL tCHSH tSLCH tSHCH SCLK tSUDAT tCFT tCRT tHDDAT LSB MSB SI High-Z SO Figure 29. Serial Output Timing CS# tWH SCLK tV tHO tWL tV tHO LSB SO SI tDIS ADDR.LSB IN REV. 1.2, AUG. 19, 2015 P/N: PM2128 41 MX35LF1GE4AB MX35LF2GE4AB Figure 30. Hold Timing CS# tHD tHC tCHHL SCLK tCHHH tHZ tLZ SO HOLD# Note: SI is "don't care" during HOLD operation. REV. 1.2, AUG. 19, 2015 P/N: PM2128 42 MX35LF1GE4AB MX35LF2GE4AB 14. PACKAGE INFORMATION 14-1. 8-WSON (8x6mm) REV. 1.2, AUG. 19, 2015 P/N: PM2128 43 MX35LF1GE4AB MX35LF2GE4AB 14-2. 8-WSON (8x6mm), E.P. 3.4x4.3mm, Recommended for new design REV. 1.2, AUG. 19, 2015 P/N: PM2128 44 MX35LF1GE4AB MX35LF2GE4AB 14-3. 16-SOP (300mil) REV. 1.2, AUG. 19, 2015 P/N: PM2128 45 MX35LF1GE4AB MX35LF2GE4AB 15. REVISION HISTORY Rev. No. Descriptions 0.00 1. Initial Released PageDate All JUN/26/2014 0.01 1. Removed 16-SOP package for 1Gb 2. Typo correction for Table 11. The Distribution of ECC Segment and Spare Area P5, 7 P36 3. Modified Figure 2. 63-ball VFBGA. P8 JUL/09/2014 0.02 1. Corrected typo on Part Number P7 2. Revised the QE bit description - only POR (power-on reset) P15 will trigger the QE bit returning to default mode 3. Corrected typo on Unique ID address range from 0x00h/0x01h P21 to 00h/01h NOV/24/2014 0.03 JAN/09/2015 0.04 1. Revised the 4Gb Reset command will block the P14 Set feature command 2. Revised the clock rate of 4Gb READ ID as 80MHz max. P20,40 3. Revised the OTP program/ OTP protection flow of 4Gb P32 by adding to set BPx bits value as NOT all "1" first. 1. Separated the 4Gb from the original datasheet 2. Changed title from "Advanced Information" to "Preliminary". 3. Revised the bad block mark from non-FFh to 00h, and non-FFFFh to 0000h; also revised the page of bad block mark from 1st or 2nd page to 1st and 2nd page 4. Revised the note for DC Table (ICC1/ICC2, Typ.) 5. Supplement footnotes for Table 6-1, 6-2 & Table 7 ALL ALL P33/34 MAR/27/2015 P38 P30/31 1.0 1. Removed title from 1Gb as production specification ALL 2. Modified wording of "function" as "feature" P13,20 3. Added new command 7Ch function P11,23,24 4. Re-arranged the paragraph of feature register and parameter page P20-22 5. Corrected wording for Table 9. Status Register Bit DescriptionsP34 MAY/08/2015 1.1 JUL/01/2015 1. Removed "Preliminary" title for 2Gb 2. Specified read-out mode description 3. Corrected the R2 of spare as under internal ECC protection 4. Added overshoot/undershoot waveforms 5. Added note mark for NOP 6. Recovered the timing spec of Input rising & falling ALL P5 P37 P39 P40 P39 1.21. Added new package for 8-WSON (8x6mm) with E.P.= 3.4x4.3mmP7/44 2. Added Program/Erase endurance cycle and data rention specs P5 AUG/19/2015 REV. 1.2, AUG. 19, 2015 P/N: PM2128 46 MX35LF1GE4AB MX35LF2GE4AB Except for customized products which have been expressly identified in the applicable agreement, Macronix's products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only, and not for use in any applications which may, directly or indirectly, cause death, personal injury, or severe property damages. In the event Macronix products are used in contradicted to their target usage above, the buyer shall take any and all actions to ensure said Macronix's product qualified for its actual use in accordance with the applicable laws and regulations; and Macronix as well as it’s suppliers and/or distributors shall be released from any and all liability arisen therefrom. Copyright© Macronix International Co., Ltd. 2015. All rights reserved, including the trademarks and tradename thereof, such as Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, NBit, Nbit, NBiit, Macronix NBit, eLiteFlash, HybridNVM, HybridFlash, XtraROM, Phines, KH Logo, BE-SONOS, KSMC, Kingtech, MXSMIO, Macronix vEE, Macronix MAP, Rich Audio, Rich Book, Rich TV, and FitCAM. The names and brands of third party referred thereto (if any) are for identification purposes only. For the contact and order information, please visit Macronix’s Web site at: http://www.macronix.com MACRONIX INTERNATIONAL CO., LTD. http://www.macronix.com MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. REV. 1.2, AUG. 19, 2015 P/N: PM2128 47