I/O Flash USB 8-Bit MCU with SPI HT68FB540/HT68FB550/HT68FB560 Revision: V1.30 Date: ����������������� December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Table of Contents Features............................................................................................................. 6 CPU Features.......................................................................................................................... 6 Peripheral Features.................................................................................................................. 6 General Description.......................................................................................... 7 Selection Table.................................................................................................. 8 Block Diagram................................................................................................... 8 Pin Assignment................................................................................................. 9 Pin Description............................................................................................... 12 Absolute Maximum Ratings........................................................................... 18 D.C. Characteristics........................................................................................ 18 A.C. Characteristics........................................................................................ 20 LVD & LVR Electrical Characteristics........................................................... 21 Power on Reset (AC+DC) Electrical Characteristics................................... 21 System Architecture....................................................................................... 22 Clocking and Pipelining.......................................................................................................... 22 Program Counter.................................................................................................................... 23 Stack...................................................................................................................................... 24 Arithmetic and Logic Unit – ALU............................................................................................ 24 Flash Program Memory.................................................................................. 25 Structure................................................................................................................................. 25 Special Vectors...................................................................................................................... 25 Look-up Table......................................................................................................................... 26 Table Program Example......................................................................................................... 26 In System Programming – ISP............................................................................................... 27 Flash Memory Read/Write Page Size.................................................................................... 27 ISP Bootloader....................................................................................................................... 29 Flash Program Memory Registers......................................................................................... 29 In Application Program – IAP................................................................................................ 33 In Circuit Programming – ICP................................................................................................ 37 On-Chip Debug Support – OCDS.......................................................................................... 37 RAM Data Memory.......................................................................................... 38 Structure................................................................................................................................. 38 Special Function Register Description......................................................... 42 Indirect Addressing Registers – IAR0, IAR1.......................................................................... 42 Memory Pointers – MP0, MP1............................................................................................... 42 Bank Pointer – BP.................................................................................................................. 43 Accumulator – ACC................................................................................................................ 44 Program Counter Low Register – PCL................................................................................... 44 Rev. 1.30 2 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Look-up Table Registers – TBLP, TBHP, TBLH...................................................................... 44 Status Register – STATUS..................................................................................................... 45 Oscillator......................................................................................................... 46 Oscillator Overview................................................................................................................ 46 System Clock Configurations................................................................................................. 46 External Crystal Oscillator – HXT........................................................................................... 47 Internal PLL Frequency Generator......................................................................................... 48 Internal RC Oscillator – HIRC................................................................................................ 50 Internal 32kHz Oscillator – LIRC............................................................................................ 50 Supplementary Internal Clocks.............................................................................................. 50 Operating Modes and System Clocks.......................................................... 50 System Clocks....................................................................................................................... 51 System Operation Modes....................................................................................................... 51 Control Register..................................................................................................................... 53 Fast Wake-up......................................................................................................................... 54 Operating Mode Switching and Wake-up............................................................................... 55 Standby Current Considerations............................................................................................ 58 Wake-up................................................................................................................................. 59 Programming Considerations................................................................................................. 59 Watchdog Timer.............................................................................................. 60 Watchdog Timer Clock Source............................................................................................... 60 Watchdog Timer Control Register.......................................................................................... 60 Watchdog Timer Operation.................................................................................................... 61 Reset and Initialisation................................................................................... 62 Reset Overview...................................................................................................................... 62 Reset Functions..................................................................................................................... 63 Reset Initial Conditions.......................................................................................................... 67 Input/Output Ports.......................................................................................... 77 Pull-high Resistors................................................................................................................. 79 Port Wake-up......................................................................................................................... 81 Port A Wake-up Polarity Control Register ............................................................................. 82 I/O Port Control Registers...................................................................................................... 83 Port A , Port D Power Source Control Registers.................................................................... 84 I/O Pin Structures................................................................................................................... 86 Programming Considerations................................................................................................. 86 Timer Modules – TM....................................................................................... 87 Introduction............................................................................................................................ 87 TM Operation......................................................................................................................... 87 TM Clock Source.................................................................................................................... 88 TM Interrupts.......................................................................................................................... 88 TM External Pins.................................................................................................................... 88 TM Input/Output Pin Control Registers.................................................................................. 89 Programming Considerations................................................................................................. 92 Compact Type TM.................................................................................................................. 93 Rev. 1.30 3 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Compact TM Operation.......................................................................................................... 94 Compact Type TM Register Description................................................................................ 94 Compact Type TM Operating Modes..................................................................................... 98 Compare Match Output Mode................................................................................................ 98 Timer/Counter Mode............................................................................................................ 100 PWM Output Mode............................................................................................................... 101 Standard Type TM – STM............................................................................. 104 Standard TM Operation........................................................................................................ 104 Standard Type TM Register Description.............................................................................. 105 Standard Type TM Operating Modes....................................................................................112 Compare Output Mode..........................................................................................................112 Timer/Counter Mode.............................................................................................................113 Timer/Counter Mode.............................................................................................................114 PWM Output Mode................................................................................................................114 Single Pulse Mode................................................................................................................117 Capture Input Mode..............................................................................................................119 Serial Interface Module – SIM...................................................................... 121 SPI Interface........................................................................................................................ 121 SPI Interface Operation........................................................................................................ 121 SPI Registers....................................................................................................................... 122 SPI Communication............................................................................................................. 125 SPI Bus Enable/Disable....................................................................................................... 127 SPI Operation....................................................................................................................... 128 Error Detection..................................................................................................................... 129 I2C Interface......................................................................................................................... 129 I2C Bus Communication....................................................................................................... 134 I2C Bus Start Signal.............................................................................................................. 135 I2C Bus Slave Address......................................................................................................... 135 I2C Bus Read/Write Signal................................................................................................... 136 I2C Bus Slave Address Acknowledge Signal........................................................................ 136 I2C Bus Data and Acknowledge Signal................................................................................ 136 I2C Time Out Function.......................................................................................................... 138 Serial Interface – SPIA.................................................................................. 138 SPIA Interface Operation..................................................................................................... 139 SPIA Registers..................................................................................................................... 140 SPIA Communication................................................................................... 142 SPIA Bus Enable/Disable..................................................................................................... 144 SPIA Operation.................................................................................................................... 145 Error Detection..................................................................................................................... 146 Peripheral Clock Output............................................................................... 147 Peripheral Clock Operation.................................................................................................. 147 Rev. 1.30 4 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Interrupts....................................................................................................... 148 Interrupt Registers................................................................................................................ 148 Interrupt Operation............................................................................................................... 152 External Interrupt.................................................................................................................. 153 USB Interrupt....................................................................................................................... 154 Serial Interface Module Interrupts – SIM Interrupt............................................................... 154 Serial Peripheral Interface Interrupt – SPIA Interrupt........................................................... 154 LVD Interrupt........................................................................................................................ 154 Multi-function Interrupt......................................................................................................... 154 TM Interrupts........................................................................................................................ 155 Interrupt Wake-up Function.................................................................................................. 155 Programming Considerations............................................................................................... 155 Low Voltage Detector – LVD........................................................................ 156 LVD Register........................................................................................................................ 156 LVD Operation...................................................................................................................... 157 USB Interface................................................................................................ 157 Power Plane......................................................................................................................... 158 USB Suspend Wake-Up Remote Wake-Up......................................................................... 158 USB Interface Operation...................................................................................................... 159 USB Interface Registers....................................................................................................... 160 Configuration Options.................................................................................. 177 Application Circuits...................................................................................... 178 Instruction Set............................................................................................... 179 Introduction.......................................................................................................................... 179 Instruction Timing................................................................................................................. 179 Moving and Transferring Data.............................................................................................. 179 Arithmetic Operations........................................................................................................... 179 Logical and Rotate Operations............................................................................................. 180 Branches and Control Transfer............................................................................................ 180 Bit Operations...................................................................................................................... 180 Table Read Operations........................................................................................................ 180 Other Operations.................................................................................................................. 180 Instruction Set Summary...................................................................................................... 181 Instruction Definition.................................................................................... 183 Package Information.................................................................................... 192 20-pin SSOP (150mil) Outline Dimensions.......................................................................... 193 24-pin SSOP (150mil) Outline Dimensions.......................................................................... 194 28-pin SSOP (150mil) Outline Dimensions.......................................................................... 195 SAW Type 20-pin (4mm×4mm) QFN Outline Dimensions................................................... 196 48-pin LQFP (7mm×7mm) Outline Dimensions................................................................... 197 Rev. 1.30 5 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Features CPU Features • Operating voltage : ♦♦ VDD(MCU) – fSYS= 4MHz/6MHz: 2.2V~5.5V – fSYS= 12MHz: 2.7V~5.5V ♦♦ VDD(USB mode) – fSYS= 6MHz/12MHz: 3.3V~5.5V – fSYS= 16MHz: 4.5V~5.5V • Up to 0.25µs instruction cycle with 16MHz system clock at VDD= 5V • Power down and wake-up functions to reduce power consumption • Three oscillators: ♦♦ External Crystal - HXT ♦♦ Internal RC - HIRC ♦♦ Internal 32kHz RC - LIRC • Multi-mode operation: NORMAL, SLOW, IDLE and SLEEP • 2 Compact type 10-bit Timer Module - CTM • 1 Standard type 10-bit Timer Module - STM • 1 Standard type 16-bit Timer Module - STM • All instructions executed in one or two instruction cycles • Table read instructions • 62 powerful instructions • Up to 12-level subroutine nesting • Bit manipulation instruction Peripheral Features • Flash Program Memory: 4K×16~16K×16 • RAM Data Memory: 256×8~768×8 • USB 2.0 Full Speed compatible • Up to 8 endpoints supported including endpoint 0 • All endpoints except endpoint 0 can support interrupt and bulk transfer • All endpoints except endpoint 0 can be configured as 8, 16, 32, 64 bytes FIFO size • Endpoint 0 support control transfer • Endpoint 0 has 8 byte FIFO • Support 3.3V LDO and internal UDP 1.5K ohm pull-up resistor • Internal 12MHz RC OSC with 0.25% accuracy for all USB modes • Watchdog Timer function • Up to 37 bidirectional I/O lines • Dual pin-shared external interrupts • Multiple Timer Modules for time measurement, input capture, compare match output or PWM output or single pulse output function • Serial Interface Modules with Dual SPI and I2C interfaces • Single Serial SPI interface • Low voltage reset function Rev. 1.30 6 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI • Low voltage detect function • Wide range of available package types • Flash program memory can be re-programmed up to 1,000,000 times • Flash program memory data retenton > 10 years • Support In System Programming function - ISP General Description The HT68FB540, HT68FB550 and HT68FB560 are Flash Memory I/O with USB type 8-bit high performance RISC architecture microcontrollers, designed for applications that interface directly to which require an USB interface. Offering users the convenience of Flash Memory multiprogramming features, these devices also include a wide range of functions and features. Other memory includes an area of RAM Data Memory. Multiple and extremely flexible Timer Modules provide timing, pulse generation and PWM generation functions. Communication with the outside world is catered for by including fully integrated SPI, I2C and USB interface functions, three popular interfaces which provide designers with a means of easy communication with external peripheral hardware. Protective features such as an internal Watchdog Timer, Low Voltage Reset and Low Voltage Detector coupled with excellent noise immunity and ESD protection ensure that reliable operation is maintained in hostile electrical environments. The external interrupt can be triggered with falling edges or both falling and rising edges. A full choice of three oscillator functions are provided including two fully integrated system oscillators which requires no external components for their implementation. The ability to operate and switch dynamically between a range of operating modes using different clock sources gives users the ability to optimize microcontroller operation and minimize power consumption. The inclusion of flexible I/O programming features along with many other features ensure that the devices will find specific excellent use in a wide range of application possibilities such as motor driving, industrial control, consumer products, subsystem controllers, etc. The devices are fully supported by the Holtek range of fully functional development and programming tools, providing a means for fast and efficient product development cycles. Rev. 1.30 7 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Selection Table Most features are common to all devices, the main feature distinguishing them are Program Memory capacity, I/O count, stack capacity and package types. The following table summarises the main features of each device. Part No. VDD HT68FB540 2.2V~ 5.5V Program Data Memory Memory Ext. Interrupt 17 2 Timer Module SIM (SPI/I2C) SPI Stack Package √ √ 8 20QFN 20/24SSOP √ √ 8 24/28SSOP 48LQFP √ √ 12 24/28SSOP 48LQFP 10-bit CTM×2 4K×16 256×8 10-bit STM×1 16-bit STM×1 10-bit CTM×2 2.2V~ HT68FB550 5.5V 8K×16 2.2V~ 5.5V 16K×16 HT68FB560 I/O 512×8 25 10-bit STM×1 2 16-bit STM×1 10-bit CTM×2 768×8 37 10-bit STM×1 2 16-bit STM×1 Block Diagram Rev. 1.30 8 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Pin Assignment HT68FB540 PA5/SDIA/TP1_0 PA6/TCK0/SCKA PA7/INT0/SCSA PA4/SDOA/TP0_0 UDN/GPIO0 UDP/GPIO1 V33O UBUS/PE1/VDD HVDD PE� �0 19 18 17 16 15 1 14 � HT68FB540 13 3 20 QFN-A 1� 4 11 5 6 7 8 9 10 PA7/INT0/SCSA PA4/SDOA/TP0_0 UDN/GPIO0 UDP/GPIO1 V33O UBUS/PE1/VDD HVDD PE� PA3/TCK� PA�/TP3_1/OSC� PA1/TP�_1/OSC1 PA0/TCK1/OCDSDA PE0/VDDIO PB�/TCK3/SCK PB1/SDI/SCL PB0/SDO/SDA RES/OCDSCK VSS VSS RES/OCDSCK 1 � 3 4 5 6 7 8 9 10 �0 19 18 17 16 15 14 13 1� 11 PA6/TCK0/SCKA PA5/SDIA/TP1_0 PA3/TCK� PA�/TP3_1/OSC� PA1/TP�_1/OSC1 PA0/TCK1/OCDSDA PE0/VDDIO PB�/TCK3/SCK PB1/SDI/SCL PB0/SDO/SDA HT68FB540 20 SSOP-A PA4/SDOA/TP0_0 1 �4 PA7/INT0/SCSA PE0/VDDIO � �3 PA6/TCK0/SCKA UDN/GPIO0 3 �� UDP/GPIO1 V33O 4 �1 PA5/SDIA/TP1_0 PA3/TCK� 5 �0 PA�/TP3_1/OSC� UBUS/PE1/VDD 6 19 PA1/TP�_1/OSC1 HVDD 7 18 PA0/TCK1/OCDSDA PE� 8 17 PB5/PCK/TP3_0 VSS RES/OCDSCK 9 16 PB4/TP0_1 10 15 PB3/SCS/TP1_1 11 14 PB�/TCK3/SCK 1� 13 PB1/SDI/SCL PB0/SDO/SDA PB6/INT1/TP�_0 HT68FB540 24 SSOP-A Rev. 1.30 9 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI HT68FB550 PA6/TCK0/SCKA 1 �4 PA5/SDIA/TP1_0 PA7/INT0/SCSA � �3 PA4/SDOA/TP0_0 UDN/GPIO0 3 �� UDP/GPIO1 V33O 4 5 UBUS/PE1/VDD PA6/TCK0/SCKA PA7/INT0/SCSA 1 �8 � �7 PA4/SDOA/TP0_0 PA3/TCK� UDN/GPIO0 3 �6 PA3/TCK� �1 PA�/TP3_1/OSC� �5 PA�/TP3_1/OSC� PA1/TP�_1/OSC1 UDP/GPIO1 V33O 4 �0 5 �4 PA1/TP�_1/OSC1 6 19 PA0/TCK1/OCDSDA UBUS/PE1/VDD 6 �3 HVDD 7 18 HVDD 7 �� PA0/TCK1/OCDSDA PE0/VDDIO PE� 8 17 PE0/VDDIO PB6/INT1/TP�_0 PE� 8 �1 PD3 VSS 9 16 PB5/PCK/TP3_0 9 �0 15 PB4/TP0_1 PD� RES/OCDSCK 10 VSS 10 19 14 PB3/SCS/TP1_1 11 1� 13 PB�/TCK3/SCK PD0 18 PB6/INT1/TP�_0 PB0/SDO/SDA PB1/SDI/SCL 11 RES/OCDSCK PD1 PB0/SDO/SDA 1� 17 13 16 PB3/SCS/TP1_1 PB1/SDI/SCL 14 15 PB�/TCK3/SCK HT68FB550 24 SSOP-A PA5/SDIA/TP1_0 PB5/PCK/TP3_0 PB4/TP0_1 HT68FB550 28 SSOP-A PA3/TCK� PA4/SDOA/TP0_0 PA5/SDIA/TP1_0 PA6/TCK0/SCKA PA7/INT0/SCSA NC NC NC NC NC NC NC NC UDN/GPIO0 UDP/GPIO1 V33O UBUS/PE1/VDD HVDD PE� VSS RES/OCDSCK NC NC NC 48 47 46 45 44 43 4� 41 40 39 38 37 36 1 35 � 34 3 33 4 5 3� 31 6 HT68FB550 7 30 48 LQFP-A �9 8 �8 9 �7 10 �6 11 �5 1� 13 14 1516 17 18 19 �0 �1 �� �3 �4 PA�/TP3_1/OSC� PA1/TP�_1/OSC1 PA0/TCK1/OCDSDA PE0/VDDIO PD7 PD6 PD5 PD4 PD3 PD� NC PB6/INT1/TP�_0 PB5/PCK/TP3_0 NC NC NC NC PB4/TP0_1 PB3/SCS/TP1_1 PB�/TCK3/SCK PB1/SDI/SCL PB0/SDO/SDA PD1 PD0 Rev. 1.30 10 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI HT68FB560 PA6/TCK0/SCKA 1 �4 PA5/SDIA/TP1_0 PA6/TCK0/SCKA 1 �8 PA5/SDIA/TP1_0 PA7/INT0/SCSA � �3 PA4/SDOA/TP0_0 PA7/INT0/SCSA � �7 PA4/SDOA/TP0_0 UDN/GPIO0 3 �� PA3/TCK� UDN/GPIO0 3 �6 PA3/TCK� UDP/GPIO1 V33O 4 �1 PA�/TP3_1/OSC� 4 �5 PA�/TP3_1/OSC� 5 �0 PA1/TP�_1/OSC1 UDP/GPIO1 V33O 5 �4 PA1/TP�_1/OSC1 UBUS/PE1/VDD 6 19 6 �3 7 18 PA0/TCK1/OCDSDA PE0/VDDIO UBUS/PE1/VDD HVDD HVDD 7 �� PA0/TCK1/OCDSDA PE0/VDDIO PE� 8 17 PB6/INT1/TP�_0 PE� 8 �1 PD3 VSS 9 16 PB5/PCK/TP3_0 VSS 9 �0 PD� RES/OCDSCK 10 15 PB4/TP0_1 RES/OCDSCK 10 19 PB0/SDO/SDA PB1/SDI/SCL 11 14 PB3/SCS/TP1_1 PD0 11 18 PB6/INT1/TP�_0 1� 13 PB�/TCK3/SCK PD1 PB0/SDO/SDA 1� 17 13 16 PB3/SCS/TP1_1 PB1/SDI/SCL 14 15 PB�/TCK3/SCK HT68FB560 24 SSOP-A PB5/PCK/TP3_0 PB4/TP0_1 HT68FB560 28 SSOP-A PA3/TCK� PA4/SDOA/TP0_0 PA5/SDIA/TP1_0 PA6/TCK0/SCKA PA7/INT0/SCSA PC0 PC1 PC� PC3 PC4 PC5 PC6 PC7 UDN/GPIO0 UDP/GPIO1 V33O UBUS/PE1/VDD HVDD PE� VSS RES/OCDSCK PE3 PE4 PE5 48 47 46 45 44 43 4� 41 40 39 38 37 36 1 35 � 34 3 4 33 5 3� 31 6 HT68FB560 7 30 48 LQFP-A �9 8 �8 9 �7 10 �6 11 �5 1� 13 14 1516 17 18 19 �0 �1 �� �3 �4 PA�/TP3_1/OSC� PA1/TP�_1/OSC1 PA0/TCK1/OCDSDA PE0/VDDIO PD7 PD6 PD5 PD4 PD3 PD� PB7 PB6/INT1/TP�_0 PB5/PCK/TP3_0 NC NC NC NC PB4/TP0_1 PB3/SCS/TP1_1 PB�/TCK3/SCK PB1/SDI/SCL PB0/SDO/SDA PD1 PD0 Rev. 1.30 11 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Pin Description The pins on these devices can be referenced by their Port name, e.g. PA.0, PA.1 etc, which refer to the digital I/O function of the pins. However these Port pins are also shared with other function such as the Serial Port pins etc. The function of each pin is listed in the following table, however the details behind how each pin is configured is contained in other sections of the datasheet. HT68FB540 Pin Name PA0/TCK1/ OCDSDA PA1/TP2_1/ OSC1 PA2/TP3_1/ OSC2 PA3/TCK2 PA4/SDOA/ TP0_0 PA5/SDIA/ TP1_0 PA6/TCK0/ SCKA PA7/INT0/SCSA PB0/SDO/SDA PB1/SDI/SCL Rev. 1.30 Function OPT I/T PA0 PAPU PAWU ST TCK1 — ST O/T Description CMOS General purpose I/O. Register enabled pull-up and wake-up. — TM1 input OCDSDA — ST Debug Data I/O in On-Chip Debug Support mode for OCDS CMOS EV only PA1 PAPU PAWU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. TP2_1 TMPC1 ST CMOS TM2 I/O OSC1 — HXT PA2 PAPU PAWU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. TP3_1 TMPC1 ST CMOS TM3 I/O OSC2 — — PA3 PAPU PAWU ST TCK2 — ST PA4 PAPU PAWU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. — HXT HXT pin HXT pin CMOS General purpose I/O. Register enabled pull-up and wake-up. — TM2 input SDOA — — CMOS SPIA Data output TP0_0 TMPC0 ST CMOS TM0 I/O PA5 PAPU PAWU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. SDIA — ST TP1_0 TMPC0 ST CMOS TM1 I/O — PA6 PAPU PAWU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. TCK0 — ST SCKA — ST NMOS SPIA Serial Clock PA7 PAPU PAWU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. INT0 — ST SCSA — ST CMOS SPIA Slave select PB0 PXPU PXWU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. SDO — — CMOS SPI Data output SDA — ST NMOS I2C Data PB1 PXPU PXWU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. SDI — ST SCL — ST — — — SPIA Data input TM0 input External interrupt 0 SPI Data input NMOS I2C Clock 12 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Pin Name PB2/TCK3/SCK PB3/SCS/TP1_1 PB4/TP0_1 PB5/PCK/TP3_0 PB6/INT1/TP2_0 PE0/VDDIO VDD/PE1/UBUS PE2 RES/OCDSCK UDN/GPIO0 UDP/GPIO1 Function OPT I/T PB2 PXPU PXWU ST TCK3 TMPC1 ST SCK — ST CMOS SPI Serial Clock PB3 PXPU PXWU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. Description CMOS General purpose I/O. Register enabled pull-up and wake-up. — TM3 input SCS — ST CMOS SPI Slave select TP1_1 TMPC0 ST CMOS TM1 I/O PB4 PXPU PXWU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. TP0_1 TMPC0 ST CMOS TM0 I/O PB5 PXPU PXWU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. PCK — — CMOS Peripheral output clock TP3_0 TMPC1 ST CMOS TM3 I/O PB6 PXPU PXWU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. INT1 — ST TP2_0 TMPC1 ST CMOS TM2 I/O PE0 PXPU PXWU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. VDDIO — PWR — PA external power input VDD — PWR — Power supply — External interrupt 1 PE1 — ST — General purpose I/O, Input pin UBUS — PWR — USB SIE VDD PE2 PXPU PXWU ST RES — ST OCDSCK — ST CMOS General purpose I/O. Register enabled pull-up and wake-up. — Reset input — Debug clock input in On-Chip Debug Support mode for OCDS EV only UDN — ST CMOS USB UDN line GPIO0 — ST CMOS General purpose I/O UDP — ST CMOS USB UDP line CMOS General purpose I/O GPIO1 — ST VSS — PWR V33O V33O — — HVDD HVDD — PWR VSS O/T — Ground PWR 3.3V regulator output — HIRC oscillator Positive Power supply. Note: I/T: Input type O/T: Output type OPT: Optional by configuration option (CO) or register option PWR: Power CO: Configuration option ST: Schmitt Trigger input CMOS: CMOS output HXT: High frequency crystal oscillator Where devices exist in more than one package type the table reflects the situation for the package with the largest number of pins. For this reason not all pins described in the table may exist on all package types. Rev. 1.30 13 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI HT68FB550 Pin Name PA0/TCK1/ OCDSDA PA1/TP2_1/ OSC1 PA2/TP3_1/ OSC2 PA3/TCK2 PA4/SDOA/ TP0_0 PA5/SDIA/ TP1_0 PA6/TCK0/ SCKA PA7/INT0/ SCSA PB0/SDO/ SDA PB1/SDI/SCL PB2/TCK3/ SCK Rev. 1.30 Function OPT I/T PA0 PAPU PAWU ST TCK1 — ST O/T Description CMOS General purpose I/O. Register enabled pull-up and wake-up. — TM1 input OCDSDA — ST Debug Data I/O in On-Chip Debug Support mode for OCDS CMOS EV only PA1 PAPU PAWU ST CMOS General purpose I/O. Register enabled pull-up and wake-up TP2_1 TMPC1 ST CMOS TM2 I/O OSC1 — HXT PA2 PAPU PAWU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. TP3_1 TMPC1 ST CMOS TM3 I/O OSC2 — — PA3 PAPU PAWU ST TCK2 — ST PA4 PAPU PAWU ST — HXT HXT pin HXT pin CMOS General purpose I/O. Register enabled pull-up and wake-up. — TM2 input CMOS General purpose I/O. Register enabled pull-up and wake-up. SDOA — — CMOS SPIA Data output TP0_0 TMPC0 ST CMOS TM0 I/O PA5 PAPU PAWU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. SDIA — ST TP1_0 TMPC0 ST CMOS TM1 I/O PA6 PAPU PAWU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. TCK0 — ST SCKA — ST NMOS SPIA Serial Clock PA7 PAPU PAWU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. — — — SPIA Data input TM0 input INT0 — ST SCSA — ST CMOS SPIA Slave select External interrupt 0 PB0 PXPU PXWU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. SDO — — CMOS SPI Data output SDA — ST NMOS I2C Data PB1 PXPU PXWU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. SDI — ST SCL — ST NMOS I2C Clock PB2 PXPU PXWU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. TCK3 TMPC1 ST SCK — ST — — SPI Data input TM3 input CMOS SPI Serial Clock 14 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Pin Name PB3/SCS/ TP1_1 PB4/TP0_1 PB5/PCK/ TP3_0 PB6/ INT1/ TP2_0 PD0~PD7 PE0/VDDIO VDD/PE1/ UBUS PE2 RES/OCDSCK UDN/GPIO0 UDP/GPIO1 Function OPT I/T PB3 PXPU PXWU O/T ST CMOS General purpose I/O. Register enabled pull-up and wake-up. SCS — ST CMOS SPI Slave select TP1_1 TMPC0 ST CMOS TM1 I/O PB4 PXPU PXWU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. TP0_1 TMPC0 ST CMOS TM0 I/O PB5 PXPU PXWU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. PCK — — CMOS Peripheral output clock. TP3_0 TMPC1 ST CMOS TM3 I/O PB6 PXPU PXWU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. INT1 — ST TP2_0 TMPC1 ST CMOS TM2 I/O PD0~PD7 PXPU PXWU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. PE0 PXPU PXWU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. VDDIO — PWR — PA, PD4~PD7 external power input. VDD — PWR — Power supply PE1 — ST — General purpose I/O, Input pin UBUS — PWR — USB SIE VDD PE2 PXPU PXWU ST RES — ST OCDSCK — ST UDN — ST — Description External interrupt 1 CMOS General purpose I/O. Register enabled pull-up and wake-up. — Reset input — Debug clock input in On-Chip Debug Support mode for OCDS EV only CMOS USB UDN line. GPIO0 — ST CMOS General purpose I/O UDP — ST CMOS USB UDP line CMOS General purpose I/O GPIO1 — ST VSS VSS — PWR — V33O V33O — — PWR HVDD HVDD — PWR — Ground 3.3V regulator output HIRC oscillator Positive Power supply. Note: I/T: Input type O/T: Output type OPT: Optional by configuration option (CO) or register option PWR: Power CO: Configuration option ST: Schmitt Trigger input CMOS: CMOS output HXT: High frequency crystal oscillator Where devices exist in more than one package type the table reflects the situation for the package with the largest number of pins. For this reason not all pins described in the table may exist on all package types. Rev. 1.30 15 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI HT68FB560 Pin Name PA0/TCK1/ OCDSDA PA1/TP2_1/ OSC1 PA2/TP3_1/ OSC2 PA3/TCK2 PA4/SDOA/ TP0_0 PA5/SDIA/ TP1_0 PA6/TCK0/ SCKA PA7/INT0/ SCSA PB0/SDO/SDA PB1/SDI/SCL PB2/TCK3/ SCK Rev. 1.30 Function OPT I/T PA0 PAPU PAWU ST TCK1 — ST O/T Description CMOS General purpose I/O. Register enabled pull-up and wake-up. — TM1 input OCDSDA — ST Debug Data I/O in On-Chip Debug Support mode for OCDS CMOS EV only PA1 PAPU PAWU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. TP2_1 TMPC1 ST CMOS TM2 I/O OSC1 — HXT PA2 PAPU PAWU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. TP3_1 TMPC1 ST CMOS TM3 I/O OSC2 — — PA3 PAPU PAWU ST TCK2 — ST PA4 PAPU PAWU ST — HXT HXT pin HXT pin CMOS General purpose I/O. Register enabled pull-up and wake-up. — TM2 input CMOS General purpose I/O. Register enabled pull-up and wake-up. SDOA — — CMOS SPIA Data output TP0_0 TMPC0 ST CMOS TM0 I/O PA5 PAPU PAWU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. SDIA — ST TP1_0 TMPC0 ST CMOS TM1 I/O PA6 PAPU PAWU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. TCK0 — ST SCKA — ST NMOS SPIA Serial Clock PA7 PAPU PAWU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. — — — SPIA Data input TM0 input INT0 — ST SCSA — ST CMOS SPIA Slave select External interrupt 0 PB0 PXPU PXWU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. SDO — — CMOS SPI Data output SDA — ST NMOS I2C Data PB1 PXPU PXWU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. SDI — ST SCL — ST NMOS I2C Clock PB2 PXPU PXWU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. TCK3 TMPC1 ST SCK — ST — — SPI Data input TM3 input CMOS SPI Serial Clock 16 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Pin Name PB3/SCS/ TP1_1 PB4/TP0_1 PB5/PCK/ TP3_0 PB6/INT1/ TP2_0 Function OPT I/T PB3 PXPU PXWU O/T ST CMOS General purpose I/O. Register enabled pull-up and wake-up. SCS — ST CMOS SPI Slave select TP1_1 TMPC0 ST CMOS TM1 I/O PB4 PXPU PXWU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. TP0_1 TMPC0 ST CMOS TM0 I/O PB5 PXPU PXWU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. PCK — — CMOS Peripheral output clock TP3_0 TMPC1 ST CMOS TM3 I/O PB6 PXPU PXWU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. INT1 — ST TP2_0 TMPC1 ST CMOS TM2 I/O PB7 PXPU PXWU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. PC0~PC7 PC0~PC7 PXPU PXWU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. PD0~PD7 PD0~PD7 PXPU PXWU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. PE0 PXPU PXWU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. PB7 PE0/VDDIO VDD/PE1/ UBUS PE2~PE5 RES/OCDSCK UDN/GPIO0 — Description External interrupt 1 VDDIO — PWR — PA, PD4~PD7 external power input VDD — PWR — Power supply. PE1 — ST — General purpose I/O, Input pin UBUS — PWR — USB SIE VDD PE2~PE5 PXPU PXWU ST RES — ST — Reset input OCDSCK — ST — Debug clock input in On-Chip Debug Support mode for OCDS EV only CMOS General purpose I/O. Register enabled pull-up and wake-up. UDN — ST CMOS USB UDN line GPIO0 — ST CMOS General purpose I/O. UDP — ST CMOS USB UDP line GPIO1 — ST CMOS General purpose I/O. VSS VSS — PWR — V33O V33O — — PWR HVDD HVDD — PWR — UDP/GPIO1 Ground 3.3V regulator output HIRC oscillator Positive Power supply. Note: I/T: Input type O/T: Output type OPT: Optional by configuration option (CO) or register option PWR: Power CO: Configuration option ST: Schmitt Trigger input CMOS: CMOS output HXT: High frequency crystal oscillator Where devices exist in more than one package type the table reflects the situation for the package with the largest number of pins. For this reason not all pins described in the table may exist on all package types. Rev. 1.30 17 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Absolute Maximum Ratings Supply Voltage ......................... VSS-0.3V to VSS +6.0V Storage Temperature ........................... -50°C to 125°C Input Voltage ............................VSS-0.3V to VDD +0.3V Operating Temperature ......................... -40°C to 85°C IOL Total..............................................................150mA IOH Total............................................................ -100mA Total Power Dissipation������������������������������������500mV Note: These are stress ratings only. Stresses exceeding the range specified under "Absolute Maximum Ratings" may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. D.C. Characteristics Ta= 25°C Symbol VDD1 VDD2 Parameter Operating Voltage (Crystal OSC) Operating Voltage (High Frequency Internal RC OSC) Test Conditions Min. Typ. Max. Unit fSYS=4MHz 2.2 — 5.5 V fSYS=6MHz 2.2 — 5.5 V fSYS=8MHz 2.2 — 5.5 V fSYS=12MHz 2.7 — 5.5 V fSYS=16MHz 4.5 — 5.5 V — fSYS=12MHz 2.7 — 5.5 V 3V No load, fH=4MHz, WDT enable — 0.8 1.5 mA — 1.8 4.0 mA No load, fH=6MHz, WDT enable — 1.0 2.0 mA — 2.5 5.0 mA No load, fH=8MHz, WDT enable — 1.3 3.0 mA — 3.0 5.5 mA — 2.0 4.0 mA — 4.0 7.0 mA — 2.0 4.0 mA — 4.0 7.0 mA No load, ADC off, fLIRC=32kHz, WDT enable, LVR enable — 40 80 μA — 70 150 μA No load, fH=12MHz, WDT enable, USB enable, PLL on, V33O on — 5.5 10.0 mA — 5V 3V IDD1 Operating Current (Crystal OSC, fSYS=fH, fS=fLIRC) 5V 3V 5V 3V 5V Operating Current (HIRC OSC, fSYS=fH, fS=fLIRC) 3V IDD3 Operating Current (LIRC OSC, fSYS=fL=fLIRC, fS=fLIRC) 3V IDD4 Operating Current (HIRC OSC, fSYS=fH, fS=fLIRC) 3V IDD2 IDD5 Rev. 1.30 Operating Current (Crystal OSC, fSYS=fH, fS=fLIRC) Conditions VDD 5V 5V 5V No load, fH=12MHz, WDT enable No load, fH=12MHz, WDT enable — 11 16 mA 5V No load, fH=6MHz, WDT enable, USB enable, PLL on, V33O on — 10 15 mA 5V No load, fH=12MHz, WDT enable, USB enable, PLL on, V33O on — 11 16 mA 5V No load, fH=16MHz, WDT enable, USB enable, PLL on, V33O on — 12 17 mA 18 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Symbol Parameter Test Conditions Min. Typ. Max. Unit — 0.8 1.5 mA — 1.5 3.0 mA No load, system HALT, WDT enable, oscillator off (FSYSON=0) — 1.5 3.0 μA — 3.0 6.0 μA No load, system HALT, WDT enable — 1.5 3.0 μA — 3.0 6.0 μA No load, system HALT, WDT disable — 0.1 1.0 μA — 0.3 2.0 μA Conditions VDD ISTB1 Standby Current (Idle 1) (Crystal or HIRC OSC, fSYS=fH, fS=fLIRC) ISTB2 Standby Current (Idle 0) (Crystal or HIRC OSC, fSYS=off, fS=fLIRC) 3V ISTB3 Standby Current (Idle 0) (LIRC OSC, fSYS=off, fS=fLIRC) 3V ISTB4 Standby Current (Sleep 0) (Crystal or HIRC OSC, fSYS=off, fS=fLIRC) 3V ISTB5 Standby Current (Sleep 0) (Crystal or HIRC OSC, fSYS=off, fS=fLIRC) — No load, system HALT, WDT disable, LVR enable and LVDEN=1 — 60 90 μA ISUS1 Suspend Current (Sleep 0) (Crystal or HIRC OSC, fSYS=off, fS=fLIRC) 5V No load, system HALT, WDT disable, USB transceiver, 3.3V Regulator on and clr suspend2 (UCC.4) — 360 420 μA ISUS2 Suspend Current (Sleep 0) (Crystal or HIRC OSC, fSYS=off, fS=fLIRC) 5V No load, system HALT, WDT disable, USB transceiver, 3.3V Regulator on and set suspend2 (UCC.4) — 240 320 μA VIL1 Input Low Voltage for I/O Ports, TCK and INT — — 0 — 0.2VDD V VIH1 Input High Voltage for I/O Ports, TCK and INT — — 0.8VDD — VDD V VIL2 Input Low Voltage (RES) — — 0 — 0.4VDD V VIH2 Input High Voltage (RES) — IOL I/O Port Sink Current IOH I/O Port, Source Current VV33O 3.3V Regulator Output RUDP Pull-high Resistance of UDP to V33O RPH Pull-high Resistance of I/O Ports RPL Pull-low Resistance of UBUS Pin Rev. 1.30 3V 5V 5V 5V 5V No load, system HALT, WDT enable, oscillator on (FSYSON=1) 0.9VDD — VDD V 3V — VOL=0.1VDD 4 8 — mA 5V VOL=0.1VDD 10 20 — mA 3V VOH=0.9VDD -2 -4 — mA 5V VOH=0.9VDD -5 -10 — mA 5V IV33O=70mA 3.0 3.3 3.6 V 3.3V — -5% 1.5 +5% kΩ 3V — 20 60 100 kΩ 5V — 10 30 50 kΩ 0.5 1 1.5 MΩ 5V SUSP2=1, RUBUS=0 19 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI A.C. Characteristics Ta= 25°C Symbol Parameter VDD Condition 2.2~5.5V 2.2~5.5V fSYS1 System Clock (Crystal OSC) 2.2~5.5V — 2.7~5.5V System Clock (HIRC OSC) System Clock (32K RC) Timer I/P Frequency (TMR) tTIMER tRES tINT VBG Turn on Stable Time TCKn Input Pin Minimum Pulse Width External Reset Minimum Low Pulse Width Interrupt Minimum Pulse Width System Start-up Timer Period (Wake-up from HALT, fSYS off at HALT state, Slow Mode → Normal Mode) tSST tRSTD Rev. 1.30 MHz 2 — 6 MHz 2 — 8 MHz 2 — 12 MHz — 16 MHz +3% MHz 3.0~5.5V Non-USB mode, Ta= -40~85°C -6% 12 +6% MHz 2.2~5.5V Non-USB mode, Ta=-40~85°C -10% 12 +10% MHz -0.25% 12 Ta= 25°C -10% 32 +10% 2.2~5.5V Ta= -40°C to 85°C -50% 32 +60% kHz 2 — 8 MHz 2 — 12 MHz 2 — 16 MHz 5V 2.7~5.5V — 4.5~5.5V tBGS Unit 4 12 2.2~5.5V fTIMER Max. — 2 3.3~5.5V USB mode fLIRC Typ. 2 -3% 4.5~5.5V 2.2~5.5V Non-USB mode, Ta=25°C fSYS2 Min. +0.25% MHz kHz — — 10 — — ms — — 0.3 — — μs — — 10 — — μs — — 10 — — μs — fSYS=HXT (Slow Mode → Normal Mode (HXT)) 1024 — — tSYS — fSYS=HXT (Wake-up from HALT, fSYS off at HALT state) 1024 — — tSYS — fSYS=HIRC 1024 — — tSYS — fSYS=LIRC 2 — — tSYS System Start-up Timer Period (Wake-up from HALT, fSYS on at HALT state) — — 2 — — tSYS System Start-up Timer Period (Reset) — — 1024 — — tSYS System Reset Delay Time (Power On Reset) — — 25 50 100 ms System Reset Delay Time (Any Reset except Power On Reset) — — 8.3 16.7 33.3 ms 20 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI LVD & LVR Electrical Characteristics Ta= 25°C Symbol Test Conditions Parameter VLVR2 Min. LVR Enable, 2.1V option VLVR1 VLVR3 Conditions VDD Low Voltage Reset Voltage — LVR Enable, 2.55V option LVR Enable, 3.15V option Typ. Max. 2.1 -5% ×Typ. 2.55 3.15 Unit V +5% ×Typ. V V VLVR4 LVR Enable, 3.8V option 3.8 V VLVD1 LVDEN=1, VLVD=2.0V 2.0 V VLVD2 LVDEN=1, VLVD=2.2V 2.2 V VLVD3 LVDEN=1, VLVD=2.4V 2.4 V VLVD4 VLVD5 Low Voltage Detector Voltage — LVDEN=1, VLVD=2.7V LVDEN=1, VLVD=3.0V -5% ×Typ. 2.7 3.0 +5% ×Typ. V V VLVD6 LVDEN=1, VLVD=3.3V 3.3 V VLVD7 LVDEN=1, VLVD=3.6V 3.6 V VLVD8 LVDEN=1, VLVD=4.0V 4.0 V 3V ILVD Additional Power Consumption if LVD/LVR is Used 5V tLVR Low Voltage Width to Reset — tLVD Low Voltage Width to Interrupt — tSRESET Software Reset Width to Reset — tLVDS LVDO Stable Time — — 30 45 μA — 60 90 μA — 120 240 480 μs — 20 45 90 μs — 45 90 120 μs 15 — — μs LVD disable → LVD enable (LVR enable) For LVR enable, LVD off → on Power on Reset (AC+DC) Electrical Characteristics Ta= 25°C Symbol VDD Condition Min. Typ. Max. Unit VPOR VDD Start Voltage to ensure Power-on Reset — — — — 100 mV RRVDD VDD Rise Rate to ensure Power-on Reset — — 0.035 — — V/ms tPOR Minimum Time for VDD Stays at VPOR to Ensure Power-on Reset — — 1 — — ms Parameter Rev. 1.30 21 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI System Architecture A key factor in the high-performance features of the Holtek range of microcontrollers is attributed to their internal system architecture. The range of devices take advantage of the usual features found within RISC microcontrollers providing increased speed of operation and enhanced performance. The pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. An 8-bit wide ALU is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the Accumulator and the ALU. Certain internal registers are implemented in the Data Memory and can be directly or indirectly addressed. The simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional I/O control system with maximum reliability and flexibility. This makes the device suitable for low-cost, high-volume production for controller applications. Clocking and Pipelining The main system clock, derived from either a HXT, HIRC or LIRC oscillator is subdivided into four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms one instruction cycle. Although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. The exception to this are instructions where the contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. For instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. An extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. System Clocking and Pipelining Rev. 1.30 22 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Instruction Fetching Program Counter During program execution, the Program Counter is used to keep track of the address of the next instruction to be executed. It is automatically incremented by one each time an instruction is executed except for instructions, such as "JMP" or "CALL" that demand a jump to a nonconsecutive Program Memory address. Only the lower 8 bits, known as the Program Counter Low Register, are directly addressable by the application program. When executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the Program Counter. For conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. Device Program Counter Program Counter High Byte HT68FB540 PC11~PC8 HT68FB550 PC12~PC8 HT68FB560 PC13~PC8 PCL Register PCL7~PCL0 Program Counter The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is available for program control and is a readable and writeable register. By transferring data directly into this register, a short program jump can be executed directly; however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, which is 256 locations. When such program jumps are executed it should also be noted that a dummy cycle will be inserted. Manipulating the PCL register may cause program branching, so an extra cycle is needed to pre-fetch. Rev. 1.30 23 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Stack This is a special part of the memory which is used to save the contents of the Program Counter only. The stack has multiple levels depending upon the device and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the Stack Pointer, and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the stack. If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack overflow. Precautions should be taken to avoid such cases which might cause unpredictable program branching. If the stack is overflow, the first Program Counter save in the stack will be lost. P ro g ra m T o p o f S ta c k S ta c k L e v e l 1 S ta c k L e v e l 2 S ta c k P o in te r B o tto m C o u n te r P ro g ra m M e m o ry S ta c k L e v e l 3 o f S ta c k S ta c k L e v e l N Device Stack Levels HT68FB540/HT68FB550 8 HT68FB560 12 Arithmetic and Logic Unit – ALU The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. As these ALU calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the following functions: • Arithmetic operations: ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, DAA • Logic operations: AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA • Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC • Increment and Decrement INCA, INC, DECA, DEC • Branch decision JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI Rev. 1.30 24 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Flash Program Memory The Program Memory is the location where the user code or program is stored. For this device series the Program Memory is Flash type, which means it can be programmed and re-programmed a large number of times, allowing the user the convenience of code modification on the same device. By using the appropriate programming tools, this Flash device offers users the flexibility to conveniently debug and develop their applications while also offering a means of field programming and updating. Structure The Program Memory has a capacity of 4Kx16 bits to 16Kx16 bits. The Program Memory is addressed by the Program Counter and also contains data, table information and interrupt entries. Table data, which can be setup in any location within the Program Memory, is addressed by a separate table pointer register. Device Capacity Banks HT68FB540 4K × 16 0 HT68FB550 8K × 16 0 HT68FB560 16K × 16 0,1 The HT68FB560 has its Program Memory divided into two Banks, Bank 0 and Bank 1. The required Bank is selected using Bit 5 of the BP Register. Special Vectors Within the Program Memory, certain locations are reserved for the reset and interrupts. The location 000H is reserved for use by the device reset for program initialisation. After a device reset is initiated, the program will jump to this location and begin execution. R e s e t R e s e t R e s e t 0 0 2 8 H In te rru p t V e c to r In te rru p t V e c to r In te rru p t V e c to r 0 F F F H 1 6 b its 1 6 b its 1 6 b its 0 0 0 0 H 0 0 0 4 H 1 F F F H 2 0 0 0 H B a n k 1 3 F F F H Program Memory Structure Rev. 1.30 25 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Look-up Table Any location within the Program Memory can be defined as a look-up table where programmers can store fixed data. To use the look-up table, the table pointer must first be setup by placing the address of the look up data to be retrieved in the table pointer register, TBLP and TBHP. These registers define the total address of the look-up table. After setting up the table pointer, the table data can be retrieved from the Program Memory using the "TABRD[m]" instructions, respectively. When the instruction is executed, the lower order table byte from the Program Memory will be transferred to the user defined Data Memory register [m] as specified in the instruction. The higher order table data byte from the Program Memory will be transferred to the TBLH special register. Any unused bits in this transferred higher order byte will be read as "0". The accompanying diagram illustrates the addressing data flow of the look-up table. T B L P R e g is te r A d d re s s T B H P R e g is te r D a ta 1 6 b its R e g is te r T B L H U s e r S e le c te d R e g is te r H ig h B y te L o w B y te Table Program Example The following example shows how the table pointer and table data is defined and retrieved from the microcontroller. This example uses raw table data located in the Program Memory which is stored there using the ORG statement. The value at this ORG statement is"1F00H" which refers to the start address of the last page within the 8K Program Memory of the HT68FB550. The table pointer is setup here to have an initial value of "06H". This will ensure that the first data read from the data table will be at the Program Memory address "1F06H" or 6 locations after the start of the last page. Note that the value for the table pointer is referenced to the first address of the present page if the "TABRD [m]" instruction is being used. The high byte of the table data which in this case is equal to zero will be transferred to the TBLH register automatically when the "TABRD [m]" instruction is executed. Because the TBLH register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and Interrupt Service Routine use table read instructions. If using the table read instructions, the Interrupt Service Routines may change the value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is recommended that simultaneous use of the table read instructions should be avoided. However, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. Note that all table related instructions require two instruction cycles to complete their operation. Rev. 1.30 26 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI In System Programming – ISP The provision of Flash type Program Memory provides the user with a means of convenient and easy upgrades and modifications to their programs on the same device. As an additional convenience, Holtek has provided a means of programming the microcontroller in-system using a two-line USB interface. This provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then programming or upgrading the program at a later stage. This enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device. The Program Memory can be programmed serially in-system using the USB interface, namely using the UDN and UDP pins. The power is supplied by the UBUS pin. The technical details regarding the in-system programming of the devices are beyond the scope of this document and will be supplied in supplementary literature. The Flash Program Memory Read/ Write function is implemented using a series of registers. Flash Memory Read/Write Page Size There are two page sizes, 32 words or 64 words, assigned for various Flash memory size. When the Flash memory, larger than 8K bytes, is selected, the 64 word page size is assigned per page and buffer. Otherwise, the page and buffer size are assigned as 32 words. The following diagram illustrates the Read/Write page and buffer assignment. The write buffer is controlled by the CLWB bit in the FRCR register. The CLWB bit can be set high to enable the Clear Write Buffer procedure, as the procedure is finished, this bit will be cleared to low by hardware. The Write Buffer is filled when the FWEN bit is set to high, when this bit is set high, the data in the Write buffer will be written to the Flash ROM, the FWT bit is used to indicate the writing procedure. Setting this bit high and check if the write procedure is finished, this bit will be cleared by hardware. The Read Byte can be assigned by the address. The FRDEN is used to enable the read function and the FRD is used to indicate the reading procedure. When the reading procedure is finished, this bit will be cleared by hardware. Rev. 1.30 Device Page Size (Words) Write Buffer (Words) HT68FB540 (4K×16) 32 32 HT68FB550 (8K×16) 32 32 HT68FB560 (16K×16) 64 64 27 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Flash Me�o�y W�ite Buffe� FARH FARL FD0H FD0L CLWB Write one word to FD0L/FD0H Flash Me�o�y FARH FARL FD0H FD0L Read one word to FD0L/FD0H Note:1. Writing a data into high byte, which means the H/L Data is written into Write Buffer, will cause the Flash memory address increased by one automatically and the new address will be loaded to the FARH and FARL registers. However, the user can also fill the new address by filling the data into FARH and FARL registers in the same page, then the data will be written into the corresponding address. 2. If the address already reached the boundary of the flash memory, such as 11111b of the 32 words or 111111b of the 64 words. At this moment, the address will not be increased and the address will stop at the last address of that page and the writing data is invalid. 3. At this point, the user has to set a new address again to fill a new data. 4. If the data is writing using the write buffer, the write buffer will be cleared by hardware automatically after the write procedure is ready in 2ms. 5. First time use the Write buffer or renew the data in the Write buffer, the user can use to Clear buffer bit (CLWB) to clear write buffer. Rev. 1.30 28 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI ISP Bootloader The devices provide the ISP Bootloader function to upgrade the software in the Flash memory. The user can select to use the ISP Bootloader application software provided by Holtek IDE tool or to create his own Bootloader software. When the Holtek Bootloader software is selected, that will occupy 0.5K words area in the Flash memory. The accopanying diagram illustrates the Flash memory structure with Holtek Bootloader software. HT68FB540 HT68FB550 Bootloade� 0D00H 0DFFH Bootloade� 0000H 0000H HT68FB560 Bootloade� 0000H Last Page Bank 0 1D00H 1DFFH Last Page 1FFFH Bank 1 3D00H 3DFFH Last Page Flash Program Memory Registers There are two address registers, four 16-bit data registers and two control register. The control register is located in Bank1 and the other registers are located in Bank0. Read and Write operations to the Flash memory are carried out in 16-bit data operations using the address and data registers and the control register. Several registers control the overall operation of the internal Flash Program Memory. The address registers are named FARL and FARH, the data registers are named FDnL and FDnH, and the control registers are named FCR and FRCR. As the FARL and FDnL registers are located in Bank 0, they can be directly accessed in the same was as any other Special Function Register. The FARH, FDnH, FCR and FRCR registers however, being located in Bank1, cannot be addressed directly and can only be read from or written to indirectly using the MP1 Memory Pointer and Indirect Addressing Register, IAR1. Rev. 1.30 29 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Program Memory Register List • HT68FB540 Bit Name FARL 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 FARH — — — — D11 D10 D9 D8 FD0L D7 D6 D5 D4 D3 D2 D1 D0 FD0H D15 D14 D13 D12 D11 D10 D9 D8 FD1L D7 D6 D5 D4 D3 D2 D1 D0 FD1H D15 D14 D13 D12 D11 D10 D9 D8 FD2L D7 D6 D5 D4 D3 D2 D1 D0 FD2H D15 D14 D13 D12 D11 D10 D9 D8 FD3L D7 D6 D5 D4 D3 D2 D1 D0 FD3H D15 D14 D13 D12 D11 D10 D9 D8 FCR CFWEN FMOD2 FMOD1 FMOD0 BWT FWT FRDEN FRD FRCR — — — FSWRST — — — CLWB 7 6 5 4 3 2 1 0 FARL D7 D6 D5 D4 D3 D2 D1 D0 FARH — — — D12 D11 D10 D9 D8 • HT68FB550 Bit Name FD0L D7 D6 D5 D4 D3 D2 D1 D0 FD0H D15 D14 D13 D12 D11 D10 D9 D8 FD1L D7 D6 D5 D4 D3 D2 D1 D0 FD1H D15 D14 D13 D12 D11 D10 D9 D8 FD2L D7 D6 D5 D4 D3 D2 D1 D0 FD2H D15 D14 D13 D12 D11 D10 D9 D8 FD3L D7 D6 D5 D4 D3 D2 D1 D0 FD3H D15 D14 D13 D12 D11 D10 D9 D8 FCR CFWEN FMOD2 FMOD1 FMOD0 BWT FWT FRDEN FRD FRCR — — — FSWRST — — — CLWB 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 D8 • HT68FB560 Name FARL Rev. 1.30 Bit FARH — — D13 D12 D11 D10 D9 FD0L D7 D6 D5 D4 D3 D2 D1 D0 FD0H D15 D14 D13 D12 D11 D10 D9 D8 FD1L D7 D6 D5 D4 D3 D2 D1 D0 FD1H D15 D14 D13 D12 D11 D10 D9 D8 FD2L D7 D6 D5 D4 D3 D2 D1 D0 FD2H D15 D14 D13 D12 D11 D10 D9 D8 FD3L D7 D6 D5 D4 D3 D2 D1 D0 FD3H D15 D14 D13 D12 D11 D10 D9 D8 FCR CFWEN FMOD2 FMOD1 FMOD0 BWT FWT FRDEN FRD FRCR — — — FSWRST — — —- CLWB 30 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI FARL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x "x" unknown Bit 7~0 D7~D0: Flash Program Memory address Flash Program Memory address bit 7~bit 0 FARH Register • HT68FB540 Bit 7 6 5 4 3 2 1 0 Name — — — — D11 D10 D9 D8 R/W — — — — R/W R/W R/W R/W POR — — — — x x x x "x" unknown Bit 7~4 Reserved, cannot be used Bit 3~0 D11~D8: Flash Program Memory address Flash Program Memory address bit 11~bit 8 • HT68FB550 Bit 7 6 5 4 3 2 1 0 Name — — — D12 D11 D10 D9 D8 R/W — — — R/W R/W R/W R/W R/W POR — — — x x x x x "x" unknown Bit 7~5 Reserved, cannot be used Bit 4~0 D12~D8: Flash Program Memory address Flash Program Memory address bit 12~bit 8 • HT68FB560 Bit 7 6 5 4 3 2 1 0 Name — — D13 D12 D11 D10 D9 D8 R/W — — R/W R/W R/W R/W R/W R/W POR — — x x x x x x "x" unknown Bit 7~6 Reserved, cannot be used Bit 5~0 Rev. 1.30 D13~D8: Flash Program Memory address Flash Program Memory address bit 13~bit 8 31 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI FCR Register Rev. 1.30 Bit 7 6 5 4 3 2 1 0 Name CFWEN FMOD2 FMOD1 FMOD0 BWT FWT FRDEN FRD R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 CFWEN: Flash ROM Write Enable bit, FWEN, control bit 0: disable 1: unimplemented This bit is used to control the FWEN bit enable or disable. When this bit is cleared to low by software, the Flash memory write enable control bit, FWEN will be cleared to low as well. It’s ineffective to set this bit to high. The user can check this bit to confirm the FWEN status. Bit 6~4 FMOD2~FMOD0: Flash Program memory, Configuration option memory operating mode control bits 000: write memory mode 001: page erase mode 010: reserved 011: read memory mode 100: reserved 101: reserved 110: FWEN (flash memory write enable) bit control mode 111: reserved Bit 3 BWT: Mode change control 0: mode change cycle has finished 1: activate a mode change cycle This bit will be automatically reset to zero by the hardware after the mode change cycle has finished. Bit 2 FWT: Flash memory Write Control 0: write cycle has finished 1: activate a write cycle This is the Flash memory Write Control Bit and when set high by the application program will activate a write cycle. This bit will be automatically reset to zero by the hardware after the write cycle has finished. Bit 1 FRDEN: Flash Memory Read Enable 0: disable 1: enable This is the Flash memory Read Enable Bit which must be set high before Flash memory read operations are carried out. Clearing this bit to zero will inhibit Flash memory read operations. Bit 0 FRD: Flash memory Read Control 0: read cycle has finished 1: activate a read cycle This is the Flash memory Read Control Bit and when set high by the application program will activate a read cycle. This bit will be automatically reset to zero by the hardware after the read cycle has finished. Setting this bit high will have no effect if the RDEN has not first been set high. Note: The FWT, FRDEN and FRD registers can not be set to "1" at the same time with a single instruction. 32 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI FRCR Register Bit 7 6 5 4 3 2 1 0 Name — — — FSWRST — — — CLWB R/W — — — R/W — — — R/W POR — — — 0 — — — 0 Bit 7~5 "—": unimplemented, read as "0" Bit 4 FSWRST: control bit Must be to 0 Bit 3~1 "—": unimplemented, read as "0" Bit 0 CLWB: Flash Program memory Write buffer clear control bit 0: do not initiate clear Write Buffer or clear process 1: initiate clear Write Buffer process This bit is used to control the Flash Program memory clear Write buffer process. It will be set by software and cleared by hardware. In Application Program – IAP Offering users the convenience of Flash Memory multi-programming features, the HT68FB5x0 series of devices not only provide an ISP function, but also an additional IAP function. The convenience of the IAP function is that it can execute the updated program procedure using its internal firmware, without requiring an external Program Writer or PC. In addition, the IAP interface can also be any type of communication protocol, such as UART or CAN, using I/O pins. Designers can assign I/O pins to communicate with the external memory device, including the updated program. Regarding the internal firmware, the user can select versions provided by HOLTEK or create their own. The following section illustrates the procedures regarding how to implement IAP firmware. Enable Flash Write Control Procedure The first procedure to implement the IAP firmware is to enable the Flash Write control which includes the following steps. • Write data "110" to the Fmod [2:0] bits in the FCR register to enable the Flash write control bit, FWEN. • Set the BWT bit in the FCR register to "1". • The device will start a 1ms counter. The user should write the correct data pattern into the Flash data registers, namely FD1L~FD3L and FD1H~FD3H, during this period of time. • Once the 1ms counter has overflowed or if the written pattern is incorrect, the enable Flash write control procedure will be invalid and the user should repeat the above procedure. • No matter whether the procedure is valid or not, the devices will clear the BWT bit automatically. • The enable Flash write pattern data is (00H 04H 0DH 09H C3H 40H) and it should be written into the Flash data registers. • Once the Flash write operation is enabled, the user can update the Flash memory using the Flash control registers. • To disable the Flash write procedure, the user can only clear the CFWEN bit in the FCR register. There is no need to execute the above procedure. Rev. 1.30 33 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Set FWEN Fmod2~0=110 : Set FWEN bit BWT=1,Hardware set a counter Wrtie the following pattern to Flash Data register FD1L= 00h , FD1H = 04h FD2L=0dh , FD2H = 09h FD3L=C3h , FD3H = 40h No Is counter overflow? BWT=0? Yes Is pattern is correct ? No Yes CFWEN=1 . Set FWEN bit success CFWEN=0 Set FWEN bit fail END Rev. 1.30 34 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Flash Memory Write and Read Procedures The following flow charts illustrate the Write and Read Flash memory procedures. Write Flash ROM Set FWEN procedure Page Erase FAH=xxh, FAL=xxh Fmod2~0=001 FWT=1 No FWT=0 ? Yes Write Fmod2~0=000 Write data to Write Buffer [(ROM ≤ 8K 1~32 Words data) or (ROM > 8K 1~64 Words data)]: Flash address register: FAH=xxh, FAL=xxh Write the following data to register: FD0L=xxh, FD0H=xxh No Write next data Write Buffer Finish? Yes FWT=1 No FWT=0 ? Yes Write Finish ? No Write next Page Yes Clear CFWEN bit END Write Flash Program ROM Procedure Rev. 1.30 35 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Read Flash Fmod2~0=011 FRDEN=1 flash address register: FAH=xxh, FAL=xxh FRD=1 No FRD=0 ? Yes Read value: FD0L=xxh, FD0H=xxh No Read Finish ? Yes FRDEN=0 Clear CFWEN bit END Read Flash Procedure option Procedure Read Flash Program orProgram Configuration Rev. 1.30 36 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI In Circuit Programming – ICP The provision of Flash type Program Memory provides the user with a means of convenient and easy upgrades and modifications to their programs on the same device. As an additional convenience, Holtek has provided a means of programming the microcontroller incircuit using a 4-pin interface. This provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then programming or upgrading the program at a later stage. This enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and reinsertion of the device. Holtek Writer Pins MCU Programming Pins ICPDA UDN Programming Serial Data Pin Description ICPCK RES Programming Clock VDD VDD/HVDD VSS VSS Power Supply Ground The Program Memory can be programmed serially in-circuit using this 4-wire interface. Data is downloaded and uploaded serially on a single pin with an additional line for the clock. Two additional lines are required for the power supply and one line for the reset. The technical details regarding the in-circuit programming of the devices are beyond the scope of this document and will be supplied in supplementary literature. During the programming process, taking control of the UDN and RES pins for data and clock programming purposes. The user must there take care to ensure that no other outputs are connected to these two pins. Note: * may be resistor or capacitor. The resistance of * must be greater than 300W or the capacitance of * must be less than 1nF. On-Chip Debug Support – OCDS There is an EV chip named HT68VB540/HT68VB550/HT68VB560 which is used to emulate the HT68FB540/HT68FB550/HT68FB560 device. The HT68VB540/HT68VB550/HT68VB560 device also provides the “On-Chip Debug” function to debug the HT68FB540/HT68FB550/HT68FB560 device during development process. The two devices, HT68FB540/HT68FB550/HT68FB560 and HT68VB540/HT68VB550/HT68VB560, are almost functional compatible except the “On-Chip Debug” function. Users can use the HT68VB540/HT68VB550/HT68VB560 device to emulate the HT68FB540/HT68FB550/HT68FB560 device behaviors by connecting the OCDSDA and OCDSCK Rev. 1.30 37 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI pins to the Holtek HT-IDE development tools. The OCDSDA pin is the OCDS Data/Address input/ output pin while the OCDSCK pin is the OCDS clock input pin. When users use the HT68VB540/ HT68VB550/HT68VB560 EV chip for debugging, the corresponding pin functions shared with the OCDSDA and OCDSCK pins in the HT68FB540/HT68FB550/HT68FB560 device will have no effect in the HT68VB540/HT68VB550/HT68VB560 EV chip. For more detailed OCDS information, refer to the corresponding document named “Holtek e-Link for 8-bit MCU OCDS User’s Guide”. Holtek e-Link Pins EV Chip Pins Pin Description OCDSDA OCDSDA On-Chip Debug Support Data/Address input/output OCDSCK OCDSCK On-Chip Debug Support Clock input VDD VDD/HVDD GND VSS Power Supply Ground RAM Data Memory The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where temporary information is stored. Structure Divided into two sections, the first of these is an area of RAM, known as the Special Function Data Memory. Here are located registers which are necessary for correct operation of the device. Many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. Device Capacity Banks HT68FB540 256×8 0: 80H~FFH 1: 80H~FFH 512×8 0: 80H~FFH 1: 80H~FFH 2: 80H~FFH 3: 80H~FFH 768×8 0: 80H~FFH 1: 80H~FFH 2: 80H~FFH 3: 80H~FFH 4: 80H~FFH 5: 80H~FFH HT68FB550 HT68FB560 The second area of Data Memory is known as the General Purpose Data Memory, which is reserved for general purpose use. All locations within this area are read and write accessible under program control. The overall Data Memory is subdivided into several banks, the structure of which depends upon the device chosen. The Special Purpose Data Memory registers are accessible in all banks, with the exception of the FRCR, FCR, FARH and FDnH registers at address from 40H to 46H, which are only accessible in Bank 1. Switching between the different Data Memory banks is achieved by setting the Bank Pointer to the correct value. The start address of the Data Memory for all devices is the address 00H. Rev. 1.30 38 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI HT68FB540 Special Purpose Data Memory Rev. 1.30 39 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI HT68FB550 Special Purpose Data Memory Rev. 1.30 40 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI HT68FB560 Special Purpose Data Memory Rev. 1.30 41 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Special Function Register Description Most of the Special Function Register details will be described in the relevant functional section; however several registers require a separate description in this section. Indirect Addressing Registers – IAR0, IAR1 The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM register space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0 and IAR1 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corresponding Memory Pointers, MP0 or MP1. Acting as a pair, IAR0 and MP0 can together access data from Bank 0 while the IAR1 and MP1 register pair can access data from any bank. As the Indirect Addressing Registers are not physically implemented, reading the Indirect Addressing Registers indirectly will return a result of "00H" and writing to the registers indirectly will result in no operation. Memory Pointers – MP0, MP1 Two Memory Pointers, known as MP0 and MP1 are provided. These Memory Pointers are physically implemented in the Data Memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. When any operation to the relevant Indirect Addressing Registers is carried out, the actual address that the microcontroller is directed to, is the address specified by the related Memory Pointer. MP0, together with Indirect Addressing Register, IAR0, are used to access data from Bank 0, while MP1 and IAR1 are used to access data from all banks according to BP register. Direct Addressing can only be used with Bank 0, all other Banks must be addressed indirectly using MP1 and IAR1. The following example shows how to clear a section of four Data Memory locations already defined as locations adres1 to adres4. Indirect Addressing Program Example data .section data adres1db ? adres2db ? adres3db ? adres4db ? block db ? code .section at 0 code org 00h start: mov a,04h; setup size of block mov block,a mov a,offset adres1 ; Accumulator loaded with first RAM address mov mp0,a ; setup memory pointer with first RAM address loop: clr IAR0 ; clear the data at address defined by MP0 inc mp0; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue: The important point to note here is that in the example shown above, no reference is made to specific RAM addresses. Rev. 1.30 42 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Bank Pointer – BP Depending upon which device is used, the Program and Data Memory are divided into several banks. Selecting the required Program and Data Memory area is achieved using the Bank Pointer. Bit 5 of the Bank Pointer is used to select Program Memory Bank 0 or 1, while bits 0~2 are used to select Data Memory Banks 0 ~ 5. The Data Memory is initialised to Bank 0 after a reset, except for a WDT time-out reset in the Power Down Mode, in which case, the Data Memory bank remains unaffected. It should be noted that the Special Function Data Memory is not affected by the bank selection, which means that the Special Function Registers can be accessed from within any bank. Directly addressing the Data Memory will always result in Bank 0 being accessed irrespective of the value of the Bank Pointer. Accessing data from banks other than Bank 0 must be implemented using Indirect addressing. As both the Program Memory and Data Memory share the same Bank Pointer Register, care must be taken during programming. Bit Device 7 6 5 4 3 2 1 0 HT68FB540 — — — — — — — DMBP0 HT68FB550 — — — — — — DMBP1 DMBP0 HT68FB560 — — PMBP0 — — DMBP2 DMBP1 DMBP0 BP Registers List BP Register • HT68FB540 Bit 7 6 5 4 3 2 1 0 Name — — — — — — — DMBP0 R/W R R R R R R R R/W POR 0 0 0 0 0 0 0 0 Bit 7~1 "—": unimplemented, read as "0" Bit 0 DMBP0: Select Data Memory Banks 0: bank 0 1: bank 1 • HT68FB550 Rev. 1.30 Bit 7 6 5 4 3 2 1 0 Name — — — — — — DMBP1 DMBP0 R/W R R R R R R R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~2 "—": unimplemented, read as "0" Bit 1~0 DMBP1, DMBP0: Select Data Memory Banks 00: bank 0 01: bank 1 10: bank 2 11: bank 3 43 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI • HT68FB560 Bit 7 6 5 4 3 2 1 0 Name — — PMBP0 — — DMBP2 DMBP1 DMBP0 R/W R R R/W R R R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 "—": unimplemented, read as "0" Bit 5 PMBP0: Select Program Memory Banks 0: bank 0, program memory address is from 0000H ~ 1FFFH 1: bank 1, program memory address is from 2000H ~ 3FFFH Bit 4~3 "—": unimplemented, read as "0" Bit 2~0 DMBP2 ~ DMBP0: Select Data Memory Banks 000: bank 0 001: bank 1 010: bank 2 011: bank 3 100: bank 4 101: bank 5 110~111: unimplemented Accumulator – ACC The Accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the ALU. The Accumulator is the place where all intermediate results from the ALU are stored. Without the Accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory resulting in higher programming and timing overheads. Data transfer operations usually involve the temporary storage function of the Accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the Accumulator as no direct transfer between two registers is permitted. Program Counter Low Register – PCL To provide additional program control functions, the low byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area of the Data Memory. By manipulating this register, direct jumps to other program locations are easily implemented. Loading a value directly into this PCL register will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only jumps within the current Program Memory page are permitted. When such operations are used, note that a dummy cycle will be inserted. Look-up Table Registers – TBLP, TBHP, TBLH These three special function registers are used to control operation of the look-up table which is stored in the Program Memory. TBLP and TBHP are the table pointer and indicates the location where the table data is located. Their value must be setup before any table read commands are executed. Their value can be changed, for example using the "INC" or "DEC" instructions, allowing for easy table data pointing and reading. TBLH is the location where the high order byte of the table data is stored after a table read data instruction has been executed. Note that the lower order table data byte is transferred to a user defined location. Rev. 1.30 44 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Status Register – STATUS This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/logical operation and system management flags are used to record the status and operation of the microcontroller. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or by executing the "CLR WDT" or "HALT" instruction. The PDF flag is affected only by executing the "HALT" or "CLR WDT" instruction or during a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations. • C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. • AC is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. • Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared. • OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. • PDF is cleared by a system power-up or executing the "CLR WDT" instruction. PDF is set by executing the "HALT" instruction. • TO is cleared by a system power-up or executing the "CLR WDT" or "HALT" instruction. TO is set by a WDT time-out. In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. STATUS Register Bit 7 6 5 4 3 2 1 0 Name — — TO PDF OV Z AC C R/W R R R R R/W R/W R/W R/W POR 0 0 0 0 x x x x "x" unknown Rev. 1.30 Bit 7~6 "—": unimplemented, read as "0" Bit 5 TO: Watchdog Time-Out flag 0: after power up or executing the "CLR WDT" or "HALT" instruction 1: a watchdog time-out occurred. Bit 4 PDF: Power down flag 0: after power up or executing the "CLR WDT" instruction 1: by executing the "HALT" instruction Bit 3 OV: Overflow flag 0: no overflow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. Bit 2 Z: Zero flag 0: the result of an arithmetic or logical operation is not zero 1: the result of an arithmetic or logical operation is zero 45 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Bit 1 AC: Auxiliary flag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction Bit 0 C: Carry flag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation C is also affected by a rotate through carry instruction. Oscillator Various oscillator options offer the user a wide range of functions according to their various application requirements. The flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. Oscillator selections and operation are selected through a combination of configuration options and registers. Oscillator Overview In addition to being the source of the main system clock the oscillators also provide clock sources for the Watchdog Timer Interrupt. External oscillators requiring some external components as well as fully integrated internal oscillators, requiring no external components, are provided to form a wide range of both fast and slow system oscillators. The high speed oscillator, HXT or HIRC, option is selected through the configuration option. The higher frequency oscillators provide higher performance but carry with it the disadvantage of higher power requirements, while the opposite is of course true for the lower frequency oscillator. With the capability of dynamically switching between fast and slow system clock, the device has the flexibility to optimize the performance/ power ratio, a feature especially important in power sensitive portable applications. Type Name Freq. Pins External Crystal HXT 6MHz or 12MHz OSC1/OSC2 Internal High Speed RC HIRC 12MHz — Internal Low Speed RC LIRC 32kHz — Oscillator Types Note: For USB applications, HXT must be connected an 6MHz or 12MHz crystal. System Clock Configurations There are several oscillator sources, two high speed oscillators and one low speed oscillator. The high speed system clocks are sourced from the external crystal/ ceramic oscillator, the PLL frequency generator and the internal 12MHz RC oscillator. The low speed oscillator is the internal 32kHz RC oscillator. Selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the HLCLK bit and CKS2~CKS0 bits in the SMOD register and as the system clock can be dynamically selected. The actual source clock used for each of the high speed oscillators is chosen via configuration options. The frequency of the slow speed or high speed system clock is also determined using the HLCLK bit and CKS2~CKS0 bits in the SMOD register. Note that two oscillator selections must be made namely one high speed and one low speed system oscillators. It is not possible to choose a no-oscillator selection for either the high or low speed oscillator. In addition, the internal PLL frequency generator, whose clock source is supplied by an external crystal oscillator, can be enabled by a software control bit to generate various frequencies for the USB interface and system clock. Rev. 1.30 46 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI USBCKEN �it 48MHz Config.Option Sele�ts 6 o� 1�MHz XTAL ÷� HIRC OSC HOSC 16MHz HOSC HXT OSC High speed Os�illato� To USBCK �i��uits 6MHz PLL 1�MHz SYSCLK Bit SYSCLK �it fH/� fH/4 fH/8 fH/16 fH/3� PLL �it HOSC PLL �it P�es�ale� PLL �lo�k 6MHz Configu�ation Option fH FSYS16MHz �it USBCKEN �it fH/64 fH fL LIRC OSC fSYS HCLK �it CKS0-CKS� �it fL fSUB Fast Wake-Up f�o� SLEEP o� IDLE �ode Cont�ol (fo� HXT only) WDT System Clock Configurations External Crystal Oscillator – HXT The External Crystal System Oscillator is one of the high frequency oscillator. Crystal/Ceramic System Oscillator – HXT Crystal Oscillator C1 and C2 Values Crystal Frequency C1 C2 16MHz 0pF 0pF 12MHz 0pF 0pF 8MHz 0pF 0pF 6MHz 0pF 0pF 4MHz 0pF 0pF 1MHz 100pF 100pF Note: 1. C1 and C2 values are for guidance only. Crystal Recommended Capacitor Values Note: For USB applications, HXT must be connected a 6MHz or 12MHz crystal. Rev. 1.30 47 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Internal PLL Frequency Generator The internal PLL frequency generator is used to generate the frequency for the USB interface and the system clock. This PLL generator can be enabled or disabled by the PLL control bit in the USC register. After a power on reset, the PLL control bit will be set to "0" to turn on the PLL generator. The PLL generator will provide the fixed 48MHz frequency for the USB operating frequency and another frequency for the system clock source which can be either 6MHz, 12MHz or 16MHz. The selection of this system frequency is implemented using the SYSCLK, Fsys16MHZ, and USBCKEN bits in the UCC register. In addition, the system clock can be selected as the HXT via these control bits. The CLK_ADJ bit is used to adjust the PLL clock automatically. SYSC Register Bit 7 6 5 4 3 2 1 0 Name CLK_ADJ USBdis RUBUS — — HFV — — R/W R/W R/W R/W — — R/W — — POR 0 0 0 — — 0 — — Bit 7 Bit 6 Bit 5 Bit 4~3 Rev. 1.30 CLK_ADJ: PLL Clock Automatic Adjustment function: 0: disable 1: enable Note that if the user selects the HIRC as the system clock, the CLK_ADJ bit must be set to "1" to adjust the PLL frequency automatically. USBdis: USB SIE control bit USB related control bit, described elsewhere RUBUS: UBUS pin pull low resistor USB related control bit, described elsewhere "—": unimplemented, read as "0" Bit 2 HFV: Non-USB mode high frequency voltage control 0: For USB mode - bit must be cleared to zero. 1: For non-USB mode - bit must be set high. Ensures that the higher frequency can work at lower voltages. A higher frequency is >8MHz and is used for the system clock fH. Bit 1~0 "—": unimplemented, read as "0" 48 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI UCC Register • HT68FB540 Bit 7 Name Rctrl R/W R/W R/W R/W POR 0 0 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1~0 6 5 SYSCLK Fsys16MHZ 4 3 2 1 0 SUSP2 USBCKEN — EPS1 EPS0 R/W R/W R R/W R/W 0 0 0 0 0 Rctrl: 7.5kΩ resistor between UDP and UBUS control bit USB related control bit, described elsewhere SYSCLK: System clock frequency select bit 0: 12MHz 1: 6MHz Note: If a 6 MHz crystal or resonator is used for the MCU, this bit should be set to "1". If a 12 MHz crystal or resonator is used, then this bit should be set to "0". If the 12MHz HIRC is selected, then this bit must be set to "0". Fsys16MHZ: PLL 16MHz output control bit 0: HXT 1: PLL 16MHz SUSP2: Reduce power consumption in suspend mode control bit USB related control bit, described elsewhere USBCKEN: USB clock control bit 0: disable 1: enable "—": unimplemented, read as "0" EPS1, EPS0: Accessing endpoint FIFO selection USB related control bit, described elsewhere USC Register Rev. 1.30 Bit 7 6 5 Name URD SELPS2 PLL 4 R/W R/W R/W R/W R/W POR 1 0 0 0 3 2 1 0 URST RMWK SUSP R R/W R/W R 0 0 0 0 SELUSB RESUME Bit 7 URD: USB reset signal control function definition USB related control bit, described elsewhere Bit 6 SELPS2: the chip works under PS2 mode indicator bit USB related control bit, described elsewhere Bit 5 PLL: PLL control bit 0: Turn-on PLL 1: Turn-off PLL Bit 4 SELUSB: the chip works under USB mode indicator bit USB related control bit, described elsewhere Bit 3 RESUME: USB resume indication bit USB related control bit, described elsewhere Bit 2 URST: USB reset indication bit USB related control bit, described elsewhere Bit 1 RMWK: USB remote wake-up command USB related control bit, described elsewhere Bit 0 SUSP: USB suspend indication USB related control bit, described elsewhere 49 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI The following table illustrates the PLL output frequency selected by the related control bits. PLL USBCKEN Fsys16MHZ 0 0 0 HOSC (HXT or HIRC) fH 0 0 1 fPLL – 16MHz 0 1 0 fPLL – 6MHz or 12MHz, depending on the "SYSCLK" bit in the UCC register selection 0 1 1 fPLL – 16MHz 1 x x HOSC (HXT or HIRC) x: stand for "don’t care" High Frequency System Clock fH Selection Table Internal RC Oscillator – HIRC The internal RC oscillator is a fully integrated system oscillator requiring no external components. The internal RC oscillator has a fixed frequency of 12MHz. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. As a result, at a power supply of either 3.3V or 5V and at a temperature of 25 degrees, the fixed oscillation frequency of 12MHz will have a tolerance within 3% (Non-USB mode). Note that if this internal system clock option is selected, as it requires no external pins for its operation, I/O pins PA1 and PA2 are free for use as normal I/O pins. The HIRC has its own power supply pin, HVDD. The HVDD pin must be connected to VDD and an 0.1mF capacitor to ground. Internal 32kHz Oscillator – LIRC The Internal 32kHz System Oscillator is a fully integrated RC oscillator with a typical frequency of 32kHz at 5V, requiring no external components for its implementation. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. As a result, at a power supply of 5V and at a temperature of 25 degrees, the fixed oscillation frequency of 32kHz will have a tolerance within 10%. Supplementary Internal Clocks The low speed oscillator, in addition to providing a system clock source is also used to provide a clock source, namely fSUB, to the Watchdog Timer Interrupt. Operating Modes and System Clocks Present day applications require that their microcontrollers have high performance but often still demand that they consume as little power as possible, conflicting requirements that are especially true in battery powered portable applications. The fast clocks required for high performance will by their nature increase current consumption and of course vice versa, lower speed clocks reduce current consumption. As Holtek has provided these devices with both high and low speed clock sources and the means to switch between them dynamically, the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. Rev. 1.30 50 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI System Clocks The device has many different clock sources for both the CPU and peripheral function operation. By providing the user with a wide range of clock options using configuration options and register programming, a clock system can be configured to obtain maximum application performance. The main system clock, can come from either a high frequency, fH, or low frequency, fL, source, and is selected using the HLCLK bit and CKS2~CKS0 bits in the SMOD register. The high speed system clock can be sourced from either a HXT or HIRC oscillator, selected via a configuration option. The low speed system clock source can be provided by internal clock fL, sourced by the LIRC oscillator. The other choice, which is a divided version of the high speed system oscillator has a range of fH/2~fH/64. The fSUB clock is used as the clock source for the Watchdog timer. USBCKEN �it 48MHz Config.Option Sele�ts 6 o� 1�MHz XTAL ÷� HIRC OSC High speed Os�illato� HOSC 16MHz HOSC HXT OSC To USBCK �i��uits 6MHz PLL 1�MHz fH 6MHz Configu�ation Option SYSCLK Bit SYSCLK �it fH/� fH/4 fH/8 fH/16 fH/3� PLL �it HOSC PLL �it P�es�ale� PLL �lo�k FSYS16MHz �it USBCKEN �it fH/64 fH fL LIRC OSC fSYS HCLK �it CKS0-CKS� �it fL fSUB WDT Fast Wake-Up f�o� SLEEP o� IDLE �ode Cont�ol (fo� HXT only) System Clock Configurations Note: when the system clock source fSYS is switched to fL from fH, the high speed oscillation will stop to conserve the power. Thus there is no fH~fH/64 for peripheral circuit to use. System Operation Modes There are six different modes of operation for the microcontroller, each one with its own special characteristics and which can be chosen according to the specific performance and power requirements of the application. There are two modes allowing normal operation of the microcontroller, the NORMAL Mode and SLOW Mode. The remaining four modes, the SLEEP0, SLEEP1, IDLE0 and IDLE1 Mode are used when the microcontroller CPU is switched off to conserve power. Operation Mode Rev. 1.30 Description CPU fSYS fSUB NORMAL Mode On fH ~ fH/64 On SLOW Mode On fL On IDLE0 Mode Off Off On On IDLE1 Mode Off On SLEEP0 Mode Off Off Off SLEEP1 Mode Off Off On 51 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI NORMAL Mode As the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by one of the high speed oscillators. This mode operates allowing the microcontroller to operate normally with a clock source will come from one of the high speed oscillators, either the HXT or HIRC oscillators. The high speed oscillator will however first be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the CKS2~CKS0 and HLCLK bits in the SMOD register. Although a high speed oscillator is used, running the microcontroller at a divided clock ratio reduces the operating current. SLOW Mode This is also a mode where the microcontroller operates normally although now with a slower speed clock source. The clock source is provided by the LIRC. Running the microcontroller in this mode allows it to run with much lower operating currents. In the SLOW Mode, the fH is off. IDLE0 Mode The IDLE0 Mode is entered when a HALT instruction is executed and when the IDLEN bit in the SMOD register is high and the FSYSON bit in the CTRL register is low. In the IDLE0 Mode the system oscillator will be inhibited from driving the CPU but some peripheral functions will remain operational such as the Watchdog Timer, TMs and SIM. In the IDLE0 Mode, the system oscillator will be stopped. In the IDLE0 Mode the Watchdog Timer clock, fSUB, will be on. IDLE1 Mode The IDLE1 Mode is entered when an HALT instruction is executed and when the IDLEN bit in the SMOD register is high and the FSYSON bit in the CTRL register is high. In the IDLE1 Mode the system oscillator will be inhibited from driving the CPU but may continue to provide a clock source to keep some peripheral functions operational such as the Watchdog Timer, TMs and SIM. In the IDLE1 Mode, the system oscillator will continue to run, and this system oscillator may be high speed or low speed system oscillator. In the IDLE1 Mode the Watchdog Timer clock, fSUB, will be on. SLEEP0 Mode The SLEEP0 Mode is entered when an HALT instruction is executed and when the IDLEN bit in the SMOD register is low. In the SLEEP0 mode the CPU will be stopped, and the fL clock will be stopped too, and the Watchdog Timer function is disabled. In this mode, the LVDEN is must set to "0". If the LVDEN is set to "1", it won’t enter the SLEEP0 Mode. SLEEP1 Mode The SLEEP1 Mode is entered when an HALT instruction is executed and when the IDLEN bit in the SMOD register is low. In the SLEEP1 mode the CPU will be stopped. However, the fSUB clock will continue to operate if the LVDEN is "1" or the Watchdog Timer function is enabled. Rev. 1.30 52 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Control Register A single register, SMOD is used for overall control of the internal clocks within the device. SMOD Register Rev. 1.30 Bit 7 6 5 4 3 2 1 0 Name CKS2 CKS1 CKS0 FSTEN LTO HTO IDLEN HLCLK R/W R/W R/W R/W R/W R R R/W R/W POR 0 0 0 0 0 0 1 1 Bit 7~5 CKS2~CKS0: The system clock selection when HLCLK is "0". 000: fL ( fLIRC) 001: fL (fLIRC) 010: fH/64 011: fH/32 100: fH/16 101: fH/8 110: fH/4 111: fH/2 These three bits are used to select which clock is used as the system clock source. In addition to the system clock source, which can be the LIRC, a divided version of the high speed system oscillator can also be chosen as the system clock source. Bit 4 FSTEN: Fast Wake-up Control (only for HXT ) 0: disable 1: enable This is the Fast Wake-up Control bit which determines if the fL clock source is initially used after the device wakes up. When the bit is high, the fL clock source can be used as a temporary system clock to provide a faster wake up time as the fL clock is available. Bit 3 LTO: Low speed system oscillator ready flag 0: not ready 1: ready This is the low speed system oscillator ready flag which indicates when the low speed system oscillator is stable after power on reset or a wake-up has occurred. The flag will be low when in the SLEEP0 Mode but after a wake-up has occurred, the flag will change to a high level after 1~2 clock cycles if the LIRC oscillator is used. Bit 2 HTO: High speed system oscillator ready flag 0: not ready 1: ready This is the high speed system oscillator ready flag which indicates when the high speed system oscillator is stable. This flag is cleared to "0" by hardware when the device is powered on and then changes to a high level after the high speed system oscillator is stable. Therefore this flag will always be read as "1" by the application program after device power-on. The flag will be low when in the SLEEP or IDLE0 Mode but after a wake-up has occurred, the flag will change to a high level after 1024 clock cycles if the HXT oscillator is used and after 1024 clock cycles if the HIRC oscillator is used. Bit 1 IDLEN: IDLE Mode control 0: disable 1: enable This is the IDLE Mode Control bit and determines what happens when the HALT instruction is executed. If this bit is high, when a HALT instruction is executed the device will enter the IDLE Mode. In the IDLE1 Mode the CPU will stop running but the system clock will continue to keep the peripheral functions operational, if FSYSON bit is high. If FSYSON bit is low, the CPU and the system clock will all stop in IDLE0 mode. If the bit is low the device will enter the SLEEP Mode when a HALT instruction is executed. 53 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Bit 0 HLCLK: system clock selection 0: fH/2~fH/64 or fL 1: fH This bit is used to select if the fH clock or the fH/2~fH/64 or fL clock is used as the system clock. When the bit is high the f H clock will be selected and if low the fH/2~fH/64 or fL clock will be selected. When system clock switches from the fH clock to the fL clock and the fH clock will be automatically switched off to conserve power. Fast Wake-up To minimise power consumption the device can enter the SLEEP or IDLE0 Mode, where the system clock source to the device will be stopped. However when the device is woken up again, it can take a considerable time for the original system oscillator to restart, stabilise and allow normal operation to resume. To ensure the device is up and running as fast as possible a Fast Wake-up function is provided, which allows fL, namely the LIRC oscillator, to act as a temporary clock to first drive the system until the original system oscillator has stabilised. As the clock source for the Fast Wake-up function is fL, the Fast Wake-up function is only available in the SLEEP1 and IDLE0 modes. When the device is woken up from the SLEEP0 mode, the Fast Wake-up function has no effect because the fL clock is stopped. The Fast Wake-up enable/disable function is controlled using the FSTEN bit in the SMOD register. If the HXT oscillator is selected as the NORMAL Mode system clock, and if the Fast Wake-up function is enabled, then it will take one to two tL clock cycles of the LIRC oscillator for the system to wake-up. The system will then initially run under the fL clock source until 1024 HXT clock cycles have elapsed, at which point the HTO flag will switch high and the system will switch over to operating from the HXT oscillator. If the HIRC oscillator or LIRC oscillator is used as the system oscillator then it will take 1024 clock cycles of the HIRC or 1~2 cycles of the LIRC to wake up the system from the SLEEP or IDLE0 Mode. The Fast Wake-up bit, FSTEN will have no effect in these cases. System FSTEN Oscillator Bit Wake-up Time (SLEEP0 Mode) Wake-up Time (SLEEP1 Mode) 0 1024 HXT cycles 1024 HXT cycles 1~2 HXT cycles 1 1024 HXT cycles 1~2 fL cycles (System runs with fL first for 1024 HXT cycles and then switches over to run with the HXT clock) 1~2 HXT cycles HIRC x 1024 HIRC cycles 1024 HIRC cycles 1~2 HIRC cycles LIRC x 1~2 LIRC cycles 1~2 LIRC cycles 1~2 LIRC cycles HXT Wake-up Time (IDLE0 Mode) Wake-up Time (IDLE1 Mode) Wake-Up Times Note that if the Watchdog Timer is disabled, which means that the LIRC is off, then there will be no Fast Wake-up function available when the device wakes-up from the SLEEP0 Mode. Rev. 1.30 54 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Operating Mode Switching and Wake-up The device can switch between operating modes dynamically allowing the user to select the best performance/power ratio for the present task in hand. In this way microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. In simple terms, Mode Switching between the NORMAL Mode and SLOW Mode is executed using the HLCLK bit and CKS2~CKS0 bits in the SMOD register while Mode Switching from the NORMAL/SLOW Modes to the SLEEP/IDLE Modes is executed via the HALT instruction. When a HALT instruction is executed, whether the device enters the IDLE Mode or the SLEEP Mode is determined by the condition of the IDLEN bit in the SMOD register and FSYSON in the CTRL register. When the HLCLK bit switches to a low level, which implies that clock source is switched from the high speed clock source, fH, to the clock source, fH/2~fH/64 or fL. If the clock is from the fL, the high speed clock source will stop running to conserve power. When this happens it must be noted that the fH/16 and fH/64 internal clock sources will also stop running, which may affect the operation of other internal functions such as the TMs and the SIM. The accompanying flowchart shows what happens when the device moves between the various operating modes. NORMAL Mode to SLOW Mode Switching When running in the NORMAL Mode, which uses the high speed system oscillator, and therefore consumes more power, the system clock can switch to run in the SLOW Mode by set the HLCLK bit to "0" and set the CKS2~CKS0 bits to "000" or "001" in the SMOD register. This will then use the low speed system oscillator which will consume less power. Users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. The SLOW Mode is sourced from the LIRC oscillator and therefore requires these oscillators to be stable before full mode switching occurs. This is monitored using the LTO bit in the SMOD register. Rev. 1.30 55 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Rev. 1.30 56 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI SLOW Mode to NORMAL Mode Switching In SLOW Mode the system uses the LIRC low speed system oscillator. To switch back to the NORMAL Mode, where the high speed system oscillator is used, the HLCLK bit should be set to "1" or HLCLK bit is "0", but CKS2~CKS0 is set to "010", "011", "100", "101", "110"or "111". As a certain amount of time will be required for the high frequency clock to stabilise, the status of the HTO bit is checked. The amount of time required for high speed system oscillator stabilization depends upon which high speed system oscillator type is used. Entering the SLEEP0 Mode There is only one way for the device to enter the SLEEP0 Mode and that is to execute the "HALT" instruction in the application program with the IDLEN bit in SMOD register equal to "0" and the WDT and LVD both off. When this instruction is executed under the conditions described above, the following will occur: • The system clock and WDT clock will be stopped and the application program will stop at the "HALT" instruction. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and stopped. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Entering the SLEEP1 Mode There is only one way for the device to enter the SLEEP1 Mode and that is to execute the "HALT" instruction in the application program with the IDLEN bit in SMOD register equal to "0"and the WDT or LVD on. When this instruction is executed under the conditions described above, the following will occur: • The system clock will be stopped and the application program will stop at the "HALT" instruction, but the WDT or LVD will remain with the clock source coming from the fSUB clock. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and resume counting if the WDT is enabled. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Rev. 1.30 57 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Entering the IDLE0 Mode There is only one way for the device to enter the IDLE0 Mode and that is to execute the "HALT" instruction in the application program with the IDLEN bit in SMOD register equal to "1" and the FSYSON bit in CTRL register equal to "0". When this instruction is executed under the conditions described above, the following will occur: • The system clock will be stopped and the application program will stop at the "HALT" instruction, but the fSUB clock will be on. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and resume counting if the WDT is enabled. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Entering the IDLE1 Mode There is only one way for the device to enter the IDLE1 Mode and that is to execute the "HALT" instruction in the application program with the IDLEN bit in SMOD register equal to "1" and the FSYSON bit in CTRL register equal to "1". When this instruction is executed under the conditions described above, the following will occur: • The system clock and fSUB clock will be on and the application program will stop at the"HALT" instruction. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and resume counting if the WDT is enabled. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Standby Current Considerations As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the IDLE1 Mode, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. Special attention must be made to the I/O pins on the device. All high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. This also applies to devices which have different package types, as there may be unbonded pins. These must either be setup as outputs or if setup as inputs must have pull-high resistors connected. Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs. These should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other CMOS inputs. Also note that additional standby current will also be required if the LIRC oscillator is enabled. In the IDLE1 Mode the system oscillator is on, if the system oscillator is from the high speed system oscillator, the additional standby current will also be perhaps in the order of several hundred microamps Rev. 1.30 58 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Wake-up After the system enters the SLEEP or IDLE Mode, it can be woken up from one of various sources listed as follows: • An external or USB reset • An external rising or falling edge on PA and a falling edge on PB~PE, except for PE1 • A system interrupt • A WDT overflow If the system is woken up by an external or USB reset, the device will experience a full system reset, however, if the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated. Although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a system power-up or executing the clear Watchdog Timer instructions and is set when executing the "HALT" instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the Program Counter and Stack Pointer, the other flags remain in their original status. Each pin on Ports can be setup using the PAWU and PXWU registers to permit a negative transition on the pin to wake-up the system. When a Port pin wake-up occurs, the program will resume execution at the instruction following the "HALT" instruction. If the system is woken up by an interrupt, then two possible situations may occur. The first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the "HALT" instruction. In this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. The other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. If an interrupt request flag is set high before entering the SLEEP or IDLE Mode, the wake-up function of the related interrupt will be disabled. Programming Considerations • If the device is woken up from the SLEEP0 Mode to the NORMAL Mode, the high speed system oscillator needs an SST period. The device will execute first instruction after HTO is "1". • If the device is woken up from the SLEEP1 Mode to NORMAL Mode, and the system clock source is from HXT oscillator and FSTEN is "1", the system clock can be switched to the LIRC oscillator after wake up. • There are peripheral functions, such as WDT, TMs and SIM, for which the fSYS is used. If the system clock source is switched from fH to fL, the clock source to the peripheral functions mentioned above will change accordingly. • The on/off condition of fL depends upon whether the WDT is enabled or disabled as the WDT clock source is generated from fL. Rev. 1.30 59 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Watchdog Timer The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. Watchdog Timer Clock Source The Watchdog Timer clock source is provided by the internal clock, fSUB, which is sourced from the LIRC oscillator. The Watchdog Timer source clock is then subdivided by a ratio of 28 to 218 to give longer timeouts, the actual value being chosen using the WS2~WS0 bits in the WDTC register. The LIRC internal oscillator has an approximate period of 32kHz at a supply voltage of 5V. However, it should be noted that this specified internal clock period can vary with VDD, temperature and process variations. The WDT function is allowed to enable or disable by setting the WDTC register data. Watchdog Timer Control Register A single register, WDTC, controls the required timeout period as well as the enable/disable operation. The WRF software reset flag will be indicated in the CTRL register. WDTC Register Rev. 1.30 Bit 7 6 5 4 3 2 1 0 Name WE4 WE3 WE2 WE1 WE0 WS2 WS1 WS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 0 1 0 0 1 1 Bit 7~3 WE4~WE0: WDT function software control 10101: WDT disabled 01010: WDT enabled Other values: Reset MCU When these bits are changed to any other values due to environmental noise the microcontroller will be reset; this reset operation will be activated after 2~3 LIRC clock cycles and the WRF bit in the CTRL register will be set to 1 to indicate the reset source. Bit 2~0 WS2, WS1, WS0: WDT time-out period selection 000: 28/fSUB 001: 210/fSUB 010: 212/fSUB 011: 214/fSUB 100: 215/fSUB 101: 216/fSUB 110: 217/fSUB 111: 218/fSUB These three bits determine the division ratio of the Watchdog Timer source clock, which in turn determines the time-out period. 60 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI CTRL Register Bit 7 6 5 4 3 2 1 0 Name FSYSON — — — — LVRF LRF WRF R/W R/W — — — — R/W R/W R/W POR 0 — — — — x 0 0 Bit 7 FSYSON: fSYS control in IDLE Mode Described elsewhere. Bit 6~3 "—": unimplemented, read as "0" Bit 2 LVRF: LVR function reset flag Described elsewhere. Bit 1 LRF: LVR control register software reset flag Described elsewhere. Bit 0 WRF: WDT control register software reset flag 0: not occurred 1: occurred This bit is set to 1 by the WDT Control register software reset and cleared by the application program. Note that this bit can only be cleared to 0 by the application program. Watchdog Timer Operation The Watchdog Timer operates by providing a device reset when its timer overflows. This means that in the application program and during normal operation the user has to strategically clear the Watchdog Timer before it overflows to prevent the Watchdog Timer from executing a reset. This is done using the clear watchdog instructions. If the program malfunctions for whatever reason, jumps to an unknown location, or enters an endless loop, these clear instructions will not be executed in the correct manner, in which case the Watchdog Timer will overflow and reset the device. With regard to the Watchdog Timer enable/disable function, there are also five bits, WE4~WE0, in the WDTC register to offer additional enable/disable and reset control of the Watchdog Timer. WDT Enable/Disabled using the WDT Control Register The WDT is enabled/disabled using the WDT control register, the WE4~WE0 values can determine which mode the WDT operates in. The WDT will be disabled when the WE4~WE0 bits are set to a value of 10101B. The WDT function will be enabled if the WE4~WE0 bit value is equal to 01010B. If the WE4~WE0 bits are set to any other values other than 01010B and 10101B, it will reset the device after 2~3 LIRC clock cycles. After power on these bits will have the value of 01010B. WDT Controlled by WDT Control Register WE4~WE0 Bits WDT Function 10101B Disable 01010B Enable Any other value Reset MCU Watchdog Timer Enable/Disable Control Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set the status bit TO. However, if the system is in the SLEEP or IDLE Mode, when a Watchdog Timer time-out occurs, the TO bit in the status register will be set and only the Program Counter and Stack Pointer will be reset. Three methods can be adopted to clear the Watchdog Timer contents. The first is a WDT reset, which means a value other than 01010B or 10101B is written into the WE4~WE0 bit locations, the second is to use the Watchdog Timer software clear instructions and the third is via a HALT instruction. There is only one method of using software instruction to clear the Watchdog Timer and that is to use the single "CLR WDT" instruction to clear the WDT. Rev. 1.30 61 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI The maximum time out period is when the 218 division ratio is selected. As an example, with a 32kHz LIRC oscillator as its source clock, this will give a maximum watchdog period of around 8 seconds for the 218 division ratio, and a minimum timeout of 7.8ms for the 28 division ration. Watchdog Timer Reset and Initialisation A reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. A hardware reset will of course be automatically implemented after the device is powered-on, however there are a number of other hardware and software reset sources that can be implemented dynamically when the device is running. Reset Overview The most important reset condition is after power is first applied to the microcontroller. In this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready to execute the first program instruction. After this power-on reset, certain important internal registers will be set to defined states before the program instructions commence execution. One of these registers is the Program Counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest Program Memory address. The devices provide several reset sources to generate the internal reset signal, providing extended MCU protection. The different types of resets are listed in the accompanying table. Reset Name Abbreviation Indication Bit Register Notes Power-on reset POR — — Auto generated at power on Reset pin RES — — Hardware reset Low voltage reset LVR LVRF CTRL Watchdog reset WDT TO STATUS WDTC register setting software reset — WRF CTRL Write to WDTC register LVRC register setting sofrware reset — LRF CTRL Write to LVRC register Low VDD voltage Reset Source Summary In addition to the power-on reset, situations may arise where it is necessary to forcefully apply a reset condition when the microcontroller is running. One example of this is where after power has been applied and the microcontroller is already running, the RES line is forcefully pulled low. In such a case, known as a normal operation reset, some of the registers remain unchanged allowing the microcontroller to proceed with normal operation after the reset line is allowed to return high. Rev. 1.30 62 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Another type of reset is when the Watchdog Timer overflows and resets the microcontroller. All types of reset operations result in different register conditions being setup. Another reset exists in the form of a Low Voltage Reset, LVR, where a full reset, similar to the RES reset is implemented in situations where the power supply voltage falls below a certain threshold. Reset Functions There are several ways in which a microcontroller reset can occur, through events occurring both internally and externally: Power-on Reset The most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. As well as ensuring that the Program Memory begins execution from the first memory address, a power-on reset also ensures that certain other registers are preset to known conditions. All the I/O port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs. Note: tRSTD is power-on delay, typical time= 50ms Power-on Reset Timing Chart RES Pin Although the microcontroller has an internal RC reset function, if the VDD power supply rise time is not fast enough or does not stabilise quickly at power-on, the internal reset function may be incapable of providing proper reset operation. For this reason it is recommended that an external RC network is connected to the RES pin, whose additional time delay will ensure that the RES pin remains low for an extended period to allow the power supply to stabilise. During this time delay, normal operation of the microcontroller will be inhibited. After the RES line reaches a certain voltage value, the reset delay time tRSTD is invoked to provide an extra delay time after which the microcontroller will begin normal operation. The abbreviation SST in the figures stands for System Start-up Timer. For most applications a resistor connected between VDD and the RES pin and a capacitor connected between VSS and the RES pin will provide a suitable external reset circuit. Any wiring connected to the RES pin should be kept as short as possible to minimise any stray noise interference. Rev. 1.30 63 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI For applications that operate within an environment where more noise is present the Enhanced Reset Circuit shown is recommended. Note: "*" it is recommended that this component is added for added ESD protection "**" It is recommended that this component is added in environments where power line noise is significant. External RES Circuit More information regarding external reset circuits is located in Application Note HA0075E on the Holtek website. Pulling the RES Pin low using external hardware will also execute a device reset. In this case, as in the case of other resets, the Program Counter will reset to zero and program execution initiated from this point. Note: tRSTD is power-on delay, typical time= 16.7ms RES Reset Timing Chart Low Voltage Reset – LVR The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device and provide an MCU reset should the value fall below a certain predefined level. • LVR Operation The LVR function is always enabled with a specific LVR voltage VLVR. If the supply voltage of the device drops to within a range of 0.9V~VLVR such as might occur when changing the battery in battery powered applications, the LVR will automatically reset the device internally and the LVRF bit in the CTRL register will also be set to 1. For a valid LVR signal, a low supply voltage, i.e., a voltage in the range between 0.9V~VLVR must exist for a time greater than that specified by tLVR in the A.C. characteristics. If the low supply voltage state does not exceed this value, the LVR will ignore the low supply voltage and will not perform a reset function. The actual VLVR value can be selected by the LVS bits in the LVRC register. If the LVS7~LVS0 bits are changed to some different values by environmental noise, the LVR will reset the device after 2~3 LIRC clock cycles. When this happens, the LRF bit in the CTRL register will be set to 1. After power on the register will have the value of 01010101B. Note that the LVR function will be automatically disabled when the device enters the power down mode. Rev. 1.30 64 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Note: tRSTD is power-on delay, typical time= 16.7ms Low Voltage Reset Timing Chart • LVRC Register Bit 7 6 5 4 3 2 1 0 Name LVS7 LVS6 LVS5 LVS4 LVS3 LVS2 LVS1 LVS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 0 1 0 1 0 1 Bit 7~0 LVS7~LVS0: LVR Voltage Select control 01010101: 2.1V 00110011: 2.55V 10011001: 3.15V 10101010: 3.8V Any other value: Generates MCU reset–register is reset to POR value When an actual low voltage condition occurs, as specified by one of the four defined LVR voltage values above, an MCU reset will be generated. The reset operation will be activated after 2~3 LIRC clock cycles. In this situation the register contents will remain the same after such a reset occurs. Any register value, other than the four defined LVR values above, will also result in the generation of an MCU reset. The reset operation will be activated after 2~3 LIRC clock cycles. However in this situation the register contents will be reset to the POR value. • CTRL Register Rev. 1.30 Bit 7 6 5 4 3 2 1 0 Name FSYSON — — — — R/W R/W — — — — LVRF LRF WRF R/W R/W R/W POR 0 — — — — x 0 0 Bit 7 FSYSON: fSYS Control in IDLE Mode Describe elsewhere. Bit 6~3 "—": unimplemented, read as "0" Bit 2 LVRF: LVR function reset flag 0: not occur 1: occurred This bit is set to 1 when a specific Low Voltage Reset situation condition occurs. This bit can only be cleared to 0 by the application program. Bit 1 LRF: LVR Control register software reset flag 0: not occur 1: occurred This bit is set to 1 if the LVRC register contains any non defined LVR voltage register values. This in effect acts like a software reset function. This bit can only be cleared to 0 by the application program. Bit 0 WRF: WDT Control register software reset flag Describe elsewhere. 65 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Watchdog Time-out Reset during Normal Operation The Watchdog time-out Reset during normal operation is the same as a hardware RES pin reset except that the Watchdog time-out flag TO will be set to "1". Note: tRSTD is power-on delay, typical time= 16.7ms WDT Time-out Reset during Normal Operation Timing Chart Watchdog Time-out Reset during SLEEP or IDLE Mode The Watchdog time-out Reset during SLEEP or IDLE Mode is a little different from other kinds of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to "0" and the TO flag will be set to "1". Refer to the A.C. Characteristics for tSST details. Note:The tSST is 15~16 clock cycles if the system clock source is provided by HIRC. The tSST is 1024 clock for HXT. The tSST is 1~2 clock for LIRC. WDT Time-out Reset during SLEEP or IDLE Timing Chart • WDTC Register Software Reset A WDTC software reset will be generated when a value other than "10101" or "01010", exist in the highest five bits of the WDTC register. The WRF bit in the CTRL register will be set high when this occurs, thus indicating the generation of a WDTC software reset. • WDTC Register Rev. 1.30 Bit 7 6 5 4 3 2 1 0 Name WE4 WE3 WE2 WE1 WE0 WS2 WS1 WS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 0 1 0 0 1 1 Bit 7~3 WE4, WE3, WE2, WE1, WE0: WDT Software Control 10101: WDT disable 01010: WDT enable (default) Other: MCU reset Bit 2~0 WS2, WS1, WS0: WDT time-out period selection. Described elsewhere 66 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Reset Initial Conditions The different types of reset described affect the reset flags in different ways. These flags, known as PDF and TO are located in the status register and are controlled by various microcontroller operations, such as the SLEEP or IDLE Mode function or Watchdog Timer. The reset flags are shown in the table: TO PDF 0 0 Power-on reset RESET Conditions u u RES, LVR or USB reset during NORMAL or SLOW Mode operation 1 u WDT time-out reset during NORMAL or SLOW Mode operation 1 1 WDT time-out reset during IDLE or SLEEP Mode operation "u"stands for unchanged The following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. Item Program Counter Interrupts WDT Condition After RESET Reset to zero All interrupts will be disabled Clear after reset, WDT begins counting Timer/Event Counter Timer Counter will be turned off Input/Output Ports I/O ports will be setup as inputs Stack Pointer Stack Pointer will point to the top of the stack The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. The following table describes how each type of reset affects each of the microcontroller internal registers. Note that where more than one package type exists the table will reflect the situation for the larger package type. Rev. 1.30 67 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI • The HT68FB540 register states are summarized below: WDT Timeout/WDTC Reset Register Software (Power On) Reset (Normal Operation) RES Reset/LVRC Software Reset (Normal Operation) RES Reset (HALT) WDT Time-out (HALT)* USB-reset (Normal) USB-reset (HALT) MP0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx MP1 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu PCL 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TBLH xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TBHP ---- xxxx ---- uuuu ---- uuuu ---- uuuu ---- uuuu ---- uuuu ---- uuuu STATUS --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu --uu uuuu --uu uuuu BP ---- ---0 ---- ---0 ---- ---0 ---- ---0 ---- ---u ---- ---0 ---- ---0 SMOD 0000 0011 0000 0011 0000 0011 0000 0011 uuuu uuuu 0000 0011 0000 0011 INTEG 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 LVDC --00 -000 --00 -000 --00 -000 --00 -000 --uu -uuu --00 -000 --00 -000 INTC0 -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu -000 0000 -000 0000 INTC1 00-0 00-0 00-0 00-0 00-0 00-0 00-0 00-0 uu-u uu-u 00-0 00-0 00-0 00-0 INTC2 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 MFI0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 MFI1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PA 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 PAC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 PB -111 1111 -111 1111 -111 1111 -111 1111 -uuu uuuu -111 1111 -111 1111 PBC -111 1111 -111 1111 -111 1111 -111 1111 -uuu uuuu -111 1111 -111 1111 PE ---- -101 ---- -101 ---- -101 ---- -101 ---- -uuu ---- -101 ---- -101 PEC - - - - - 111 - - - - - 111 - - - - - 111 - - - - - 111 ---- -uuu - - - - - 111 - - - - - 111 WDTC 0101 0011 0101 0011 0101 0011 0101 0011 uuuu uuuu 0101 0011 0101 0011 FRCR ---0 ---0 ---0 ---0 ---0 ---0 ---0 ---0 ---u ---u ---0 ---0 ---0 ---0 FCR 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 FARL xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx FARH ---- xxxx ---- xxxx ---- xxxx ---- xxxx ---- uuuu ---- xxxx ---- xxxx FD0L xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx FD0H xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx FD1L xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx FD1H xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx FD2L xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx FD2H xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx FD3L xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx FD3H xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx I2CTOC 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 SIMC0 1110 000- 1110 000- 1110 000- 1110 000- uuuu uuu- 1110 000- 1110 000- SIMC1 1000 0001 1000 0001 1000 0001 1000 0001 uuuu uuuu 1000 0001 1000 0001 Rev. 1.30 68 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Reset Register (Power On) WDT Timeout/WDTC Software Reset (Normal Operation) RES Reset/LVRC Software Reset (Normal Operation) RES Reset (HALT) WDT Time-out (HALT)* USB-reset (Normal) USB-reset (HALT) SIMD xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx SIMA/ SIMC2 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 SPIAC0 111 - - - 0 - 111 - - - 0 - 111 - - - 0 - 111 - - - 0 - uuu- --u- 111 - - - 0 - 111 - - - 0 - SPIAC1 --00 0000 --00 0000 --00 0000 --00 0000 --uu uuuu --00 0000 --00 0000 SPIAD xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx SBSC 0000 ---0 0000 ---0 0000 ---0 0000 ---0 uuuu ---u 0000 ---0 0000 ---0 PAWU 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PADIR 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PAPU 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PXPU -0-- --00 -0-- --00 -0-- --00 -0-- --00 -u-- --uu -0-- --00 -0-- --00 PXWU -0-- --00 -0-- --00 -0-- --00 -0-- --00 -u-- --uu -0-- --00 -0-- --00 TMPC0 --01 --01 --01 --01 --01 --01 --01 --01 --uu --uu --01 --01 --01 --01 TMPC1 --01 --01 --01 --01 --01 --01 --01 --01 --uu --uu --01 --01 --01 --01 TM0C0 0000 0--- 0000 0--- 0000 0--- 0000 0--- uuuu u--- 0000 0--- 0000 0--- TM0C1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM0DL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM0DH 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM0AL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM0AH 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM0RP 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM1C0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM1C1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM1DL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM1DH ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ---- --00 ---- --00 TM1AL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM1AH ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ---- --00 ---- --00 TM2C0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM2C1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM2DL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM2DH ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ---- --00 ---- --00 TM2AL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM2AH ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ---- --00 ---- --00 TM3C0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM3C1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM3DL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM3DH ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ---- --00 ---- --00 TM3AL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM3AH ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ---- --00 ---- --00 USB_ STAT 11xx 000- 11xx 000- 11xx 000- 11xx 000- 11xx 000- 11xx 000- 11xx 000- Rev. 1.30 69 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Reset Register (Power On) WDT Timeout/WDTC Software Reset (Normal Operation) RES Reset/LVRC Software Reset (Normal Operation) RES Reset (HALT) WDT Time-out (HALT)* USB-reset (Normal) USB-reset (HALT) UINT ---- 0000 ---- uuuu ---- 0000 ---- 0000 ---- uuuu ---- 0000 ---- 0000 USC 1000 0000 uuuu xuux 1000 0000 1000 0000 uuuu xuux 1uuu 0100 1uuu 0100 USR ---- 0000 ---- uuuu ---- 0000 ---- 0000 ---- uuuu ---- 0000 ---- 0000 UCC 0000 0-00 uuuu u-uu 0000 0-00 0000 0-00 uuuu u-uu 0uu0 u-00 0uu0 u-00 AWR 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 STLI ---- 0000 ---- uuuu ---- 0000 ---- 0000 ---- uuuu ---- 0000 ---- 0000 STLO ---- 0000 ---- uuuu ---- 0000 ---- 0000 ---- uuuu ---- 0000 ---- 0000 SIES 00-0 0000 uu-x xuuu 00-0 0000 00-0 0000 uu-x xuuu 00-0 0000 00-0 0000 MISC 000- 0000 xxu- uuuu 000- 0000 000- 0000 xxu- uuuu 000- 0000 000- 0000 UFIEN ---- 0000 ---- uuuu ---- 0000 ---- 0000 ---- uuuu ---- 0000 ---- 0000 FIFO0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx FIFO1 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx FIFO2 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx FIFO3 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx UFOEN ---- 0000 ---- uuuu ---- 0000 ---- 0000 ---- uuuu ---- 0000 ---- 0000 UFC0 0000 00-- uuuu uu-- 0000 00-- 0000 00-- uuuu uu-- 0000 00-- 0000 00-- PAPS0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PAPS1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 SYSC 000- -0-- 000- -0-- 000- -0-- 000- -0-- uuu- -u-- 000- -0-- 000- -0-- CTRL 0--- -x00 0--- -x00 0--- -x00 0--- -x00 u--- -xuu 0--- -x00 0--- -x00 LVRC 0101 0101 0101 0101 0101 0101 0101 0101 uuuu uuuu 0101 0101 0101 0101 Note: " * " stands for "warm reset" " - " not implement " u " stands for "unchanged" " x " stands for "unknown" Rev. 1.30 70 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI • The HT68FB550 register states are summarized below: WDT TimeRES out/WDTC Reset/LVRC Reset Register Software Reset Software Reset (Power On) (Normal (Normal Operation) Operation) RES Reset (HALT) WDT Time-out (HALT)* USB-reset (Normal) USB-reset (HALT) MP0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx MP1 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu PCL 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TBLH xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TBHP ---x xxxx ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu STATUS --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu --uu uuuu --uu uuuu BP ---- --00 ---- ---00 ---- --00 ---- --00 ---- --uu ---- --00 ---- --00 SMOD 0000 0011 0000 0011 0000 0011 0000 0011 uuuu uuuu 0000 0011 0000 0011 INTEG 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 LVDC --00 -000 --00 -000 --00 -000 --00 -000 --uu -uuu --00 -000 --00 -000 INTC0 -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu -000 0000 -000 0000 INTC1 00-0 00-0 00-0 00-0 00-0 00-0 00-0 00-0 uu-u uu-u 00-0 00-0 00-0 00-0 INTC2 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 MFI0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 MFI1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PA 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 PAC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 PB -111 1111 -111 1111 -111 1111 -111 1111 -uuu uuuu -111 1111 -111 1111 PBC -111 1111 -111 1111 -111 1111 -111 1111 -uuu uuuu -111 1111 -111 1111 PD 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 PDC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 PE ---- -101 ---- -101 ---- -101 ---- -101 ---- -uuu ---- -101 ---- -101 PEC - - - - - 111 - - - - - 111 - - - - - 111 - - - - - 111 ---- -uuu - - - - - 111 - - - - - 111 WDTC 0101 0011 0101 0011 0101 0011 0101 0011 uuuu uuuu 0101 0011 0101 0011 FRCR ---0 ---0 ---0 ---0 ---0 ---0 ---0 ---0 ---u ---u ---0 ---0 ---0 ---0 FCR 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 FARL xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx FARH ---x xxxx ---x xxxx ---x xxxx ---x xxxx ---u uuuu ---x xxxx ---x xxxx FD0L xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx FD0H xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx FD1L xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx FD1H xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx FD2L xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx FD2H xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx FD3L xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx FD3H xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx Rev. 1.30 71 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI WDT TimeRES out/WDTC Reset/LVRC Reset Register Software Reset Software Reset (Power On) (Normal (Normal Operation) Operation) RES Reset (HALT) WDT Time-out (HALT)* USB-reset (Normal) USB-reset (HALT) I2CTOC 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 SIMC0 1110 000- 1110 000- 1110 000- 1110 000- uuuu uuu- 1110 000- 1110 000- SIMC1 1000 0001 1000 0001 1000 0001 1000 0001 uuuu uuuu 1000 0001 1000 0001 SIMD xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx SIMA/ SIMC2 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 SPIAC0 111 - - - 0 - 111 - - - 0 - 111 - - - 0 - 111 - - - 0 - uuu- --u- 111 - - - 0 - 111 - - - 0 - SPIAC1 --00 0000 --00 0000 --00 0000 --00 0000 --uu uuuu --00 0000 --00 0000 SPIAD xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx SBSC 0000 ---0 0000 ---0 0000 ---0 0000 ---0 uuuu ---u 0000 ---0 0000 ---0 PAWU 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PADIR 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PAPU 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PXPU -000 --00 -000 --00 -000 --00 -000 --00 -uuu --uu -000 --00 -000 --00 PXWU -000 --00 -000 --00 -000 --00 -000 --00 -uuu --uu -000 --00 -000 --00 TMPC0 --01 --01 --01 --01 --01 --01 --01 --01 --uu --uu --01 --01 --01 --01 TMPC1 --01 --01 --01 --01 --01 --01 --01 --01 --uu --uu --01 --01 --01 --01 TM0C0 0000 0--- 0000 0--- 0000 0--- 0000 0--- uuuu u--- 0000 0--- 0000 0--- TM0C1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM0DL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM0DH 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM0AL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM0AH 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM0RP 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM1C0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM1C1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM1DL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM1DH ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ---- --00 ---- --00 TM1AL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM1AH ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ---- --00 ---- --00 TM2C0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM2C1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM2DL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM2DH ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ---- --00 ---- --00 TM2AL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM2AH ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ---- --00 ---- --00 TM3C0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM3C1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM3DL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM3DH ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ---- --00 ---- --00 Rev. 1.30 72 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI WDT TimeRES out/WDTC Reset/LVRC Reset Register Software Reset Software Reset (Power On) (Normal (Normal Operation) Operation) RES Reset (HALT) WDT Time-out (HALT)* USB-reset (Normal) USB-reset (HALT) TM3AL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM3AH ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ---- --00 ---- --00 USB_ STAT 11xx 000- 11xx 000- 11xx 000- 11xx 000- 11xx 000- 11xx 000- 11xx 000- UINT --00 0000 --uu uuuu --00 0000 --00 0000 --uu uuuu --00 0000 --00 0000 USC 1000 0000 uuuu xuux 1000 0000 1000 0000 uuuu xuux 1uuu 0100 1uuu 0100 USR --00 0000 --uu uuuu --00 0000 --00 0000 --uu uuuu --00 0000 --00 0000 UCC 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0uu0 u000 0uu0 u000 AWR 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 STLI --00 0000 --uu uuuu --00 0000 --00 0000 --uu uuuu --00 0000 --00 0000 STLO --00 0000 --uu uuuu --00 0000 --00 0000 --uu uuuu --00 0000 --00 0000 SIES 00-0 0000 uu-x xuuu 00-0 0000 00-0 0000 uu-x xuuu 00-0 0000 00-0 0000 MISC 0000 0000 xxuu uuuu 0000 0000 0000 0000 xxuu uuuu 0000 0000 0000 0000 UFIEN --00 0000 --uu uuuu --00 0000 --00 0000 --uu uuuu --00 0000 --00 0000 FIFO0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx FIFO1 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx FIFO2 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx FIFO3 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx FIFO4 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx FIFO5 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx UFOEN --00 0000 --uu uuuu --00 0000 --00 0000 --uu uuuu --00 0000 --00 0000 UFC0 0000 00-- uuuu uu-- 0000 00-- 0000 00-- uuuu uu-- 0000 00-- 0000 00-- UFC1 ---- 0000 ---- uuuu ---- 0000 ---- 0000 ---- uuuu ---- 0000 ---- 0000 PDPS 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PAPS0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PAPS1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 SYSC 000- -0-- 000- -0-- 000- -0-- 000- -0-- uuu- -u-- 000- -0-- 000- -0-- CTRL 0--- -x00 0--- -x00 0--- -x00 0--- -x00 u--- -xuu 0--- -x00 0--- -x00 LVRC 0101 0101 0101 0101 0101 0101 0101 0101 uuuu uuuu 0101 0101 0101 0101 Note: " * " stands for "warm reset" " - " not implement " u " stands for "unchanged" " x " stands for "unknown" Rev. 1.30 73 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI • The HT68FB560 register states are summarized below: WDT TimeRES out/WDTC Reset/LVRC Reset Register Software Reset Software Reset (Power On) (Normal (Normal Operation) Operation) RES Reset (HALT) WDT Time-out (HALT)* USB-reset (Normal) USB-reset (HALT) MP0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx MP1 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu PCL 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TBLH xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TBHP --xx xxxx --uu uuuu --uu uuuu --uu uuuu --uu uuuu --uu uuuu --uu uuuu STATUS --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu --uu uuuu --uu uuuu BP --0- -000 --0- --000 --0- -000 --0- -000 --u- -uuu --0- -000 --0- -000 SMOD 0000 0011 0000 0011 0000 0011 0000 0011 uuuu uuuu 0000 0011 0000 0011 INTEG 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 LVDC --00 -000 --00 -000 --00 -000 --00 -000 --uu -uuu --00 -000 --00 -000 INTC0 -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu -000 0000 -000 0000 INTC1 00-0 00-0 00-0 00-0 00-0 00-0 00-0 00-0 uu-u uu-u 00-0 00-0 00-0 00-0 INTC2 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 MFI0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 MFI1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PA 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 PAC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 PB 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 PBC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 PC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 PCC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 PD 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 PDC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 PE --11 1101 --11 1101 --11 1101 --11 1101 --uu uuuu --11 1101 --11 1101 PEC --11 1111 --11 1111 --11 1111 --11 1111 --uu uuuu --11 1111 --11 1111 WDTC 0101 0011 0101 0011 0101 0011 0101 0011 uuuu uuuu 0101 0011 0101 0011 FRCR ---0 ---0 ---0 ---0 ---0 ---0 ---0 ---0 ---u ---u ---0 ---0 ---0 ---0 FCR 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 FARL xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx FARH --xx xxxx --xx xxxx --xx xxxx --xx xxxx --uu uuuu --xx xxxx --xx xxxx FD0L xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx FD0H xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx FD1L xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx FD1H xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx FD2L xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx FD2H xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx Rev. 1.30 74 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI WDT TimeRES out/WDTC Reset/LVRC Reset Register Software Reset Software Reset (Power On) (Normal (Normal Operation) Operation) FD3L xxxx xxxx xxxx xxxx xxxx xxxx RES Reset (HALT) WDT Time-out (HALT)* USB-reset (Normal) USB-reset (HALT) xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx FD3H xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx I2CTOC 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 SIMC0 1110 000- 1110 000- 1110 000- 1110 000- uuuu uuu- 1110 000- 1110 000- SIMC1 1000 0001 1000 0001 1000 0001 1000 0001 uuuu uuuu 1000 0001 1000 0001 SIMD xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx SIMA/ SIMC2 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 SPIAC0 111 - - - 0 - 111 - - - 0 - 111 - - - 0 - 111 - - - 0 - uuu- --u- 111 - - - 0 - 111 - - - 0 - SPIAC1 --00 0000 --00 0000 --00 0000 --00 0000 --uu uuuu --00 0000 --00 0000 SPIAD xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx SBSC 0000 ---0 0000 ---0 0000 ---0 0000 ---0 uuuu ---u 0000 ---0 0000 ---0 PAWU 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PADIR 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PAPU 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PXPU 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PXWU 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TMPC0 --01 --01 --01 --01 --01 --01 --01 --01 --uu --uu --01 --01 --01 --01 TMPC1 --01 --01 --01 --01 --01 --01 --01 --01 --uu --uu --01 --01 --01 --01 TM0C0 0000 0--- 0000 0--- 0000 0--- 0000 0--- uuuu u--- 0000 0--- 0000 0--- TM0C1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM0DL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM0DH 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM0AL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM0AH 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM0RP 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM1C0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM1C1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM1DL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM1DH ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ---- --00 ---- --00 TM1AL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM1AH ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ---- --00 ---- --00 TM2C0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM2C1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM2DL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM2DH ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ---- --00 ---- --00 TM2AL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM2AH ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ---- --00 ---- --00 TM3C0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 Rev. 1.30 75 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI WDT TimeRES out/WDTC Reset/LVRC Reset Register Software Reset Software Reset (Power On) (Normal (Normal Operation) Operation) RES Reset (HALT) WDT Time-out (HALT)* USB-reset (Normal) USB-reset (HALT) TM3C1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM3DL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM3DH ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ---- --00 ---- --00 TM3AL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM3AH ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu ---- --00 ---- --00 USB_ STAT 11xx 000- 11xx 000- 11xx 000- 11xx 000- 11xx 000- 11xx 000- 11xx 000- UINT 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 USC 1000 0000 uuuu xuux 1000 0000 1000 0000 uuuu xuux 1uuu 0100 1uuu 0100 USR 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 UCC 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0uu0 u000 0uu0 u000 AWR 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 STLI 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 STLO 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 SIES 00-0 0000 uu-x xuuu 00-0 0000 00-0 0000 uu-x xuuu 00-0 0000 00-0 0000 MISC 0000 0000 xxuu uuuu 0000 0000 0000 0000 xxuu uuuu 0000 0000 0000 0000 UFIEN 0000 0000 00uu uuuu 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 FIFO0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx FIFO1 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx FIFO2 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx FIFO3 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx FIFO4 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx FIFO5 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx FIFO6 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx FIFO7 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx UFOEN 0000 0000 00uu uuuu -0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 UFC0 0000 00-- uuuu uu-- 0000 00-- 0000 00-- uuuu uu-- 0000 00-- 0000 00-- UFC1 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PDPS 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PAPS0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PAPS1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 SYSC 000- -0-- 000- -0-- 000- -0-- 000- -0-- uuu- -u-- 000- -0-- 000- -0-- CTRL 0--- -x00 0--- -x00 0--- -x00 0--- -x00 u--- -xuu 0--- -x00 0--- -x00 LVRC 0101 0101 0101 0101 0101 0101 0101 0101 uuuu uuuu 0101 0101 0101 0101 Note: " * " stands for "warm reset" " - " not implement " u " stands for "unchanged" " x " stands for "unknown" Rev. 1.30 76 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Input/Output Ports Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an I/O structure to meet the needs of a wide range of application possibilities. The devices provide bidirectional input/output lines labeled with port names PA~PE. These I/O ports are mapped to the RAM Data Memory with specific addresses as shown in the Special Purpose Data Memory table. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge of instruction "MOV A, [m]", where m denotes the port address. For output operation, all the data is latched and remains unchanged until the output latch is rewritten. I/O Register List • HT68FB540 Register Name Rev. 1.30 Bit 7 6 5 4 3 2 1 0 PAWU D7 D6 D5 D4 D3 D2 D1 D0 PAPU D7 D6 D5 D4 D3 D2 D1 D0 PA D7 D6 D5 D4 D3 D2 D1 D0 PAC D7 D6 D5 D4 D3 D2 D1 D0 PADIR D7 D6 D5 D4 D3 D2 D1 D0 PXWU — PELWU — — — — PBHWU PBLWU PXPU — PELPU — — — — PBHPU PBLPU PAPS0 PA3S1 PA3S0 PA2S1 PA2S0 PA1S1 PA1S0 PA0S1 PA0S0 PAPS1 PA7S1 PA7S0 PA6S1 PA6S0 PA5S1 PA5S0 PA4S1 PA4S0 PB — D6 D5 D4 D3 D2 D1 D0 PBC — D6 D5 D4 D3 D2 D1 D0 PE — — — — — D2 D1 D0 PEC — — — — — D2 D1 D0 77 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI • HT68FB550 Bit Register Name 7 6 5 4 3 2 1 0 PAWU D7 D6 D5 D4 D3 D2 D1 D0 PAPU D7 D6 D5 D4 D3 D2 D1 D0 PA D7 D6 D5 D4 D3 D2 D1 D0 PAC D7 D6 D5 D4 D3 D2 D1 D0 PADIR D7 D6 D5 D4 D3 D2 D1 D0 PXWU — PELWU PDHWU PDLWU — — PBHWU PBLWU PXPU — PELPU PDHPU PDLPU — — PBHPU PBLPU PAPS0 PA3S1 PA3S0 PA2S1 PA2S0 PA1S1 PA1S0 PA0S1 PA0S0 PAPS1 PA7S1 PA7S0 PA6S1 PA6S0 PA5S1 PA5S0 PA4S1 PA4S0 PB — D6 D5 D4 D3 D2 D1 D0 PBC — D6 D5 D4 D3 D2 D1 D0 PD D7 D6 D5 D4 D3 D2 D1 D0 PDC D7 D6 D5 D4 D3 D2 D1 D0 PE — — — — — D2 D1 D0 PEC — — — — — D2 D1 D0 Register Name 7 6 5 4 3 2 1 0 PAWU D7 D6 D5 D4 D3 D2 D1 D0 PAPU D7 D6 D5 D4 D3 D2 D1 D0 PA D7 D6 D5 D4 D3 D2 D1 D0 PAC D7 D6 D5 D4 D3 D2 D1 D0 PADIR D7 D6 D5 D4 D3 D2 D1 D0 PXWU PEHWU PELWU PDHWU PDLWU PCHWU PCLWU PBHWU PBLWU PXPU PEHPU PELPU PDHPU PDLPU PCHPU PCLPU PBHPU PBLPU PAPS0 PA3S1 PA3S0 PA2S1 PA2S0 PA1S1 PA1S0 PA0S1 PA0S0 PAPS1 PA7S1 PA7S0 PA6S1 PA6S0 PA5S1 PA5S0 PA4S1 PA4S0 PB D7 D6 D5 D4 D3 D2 D1 D0 PBC D7 D6 D5 D4 D3 D2 D1 D0 PC D7 D6 D5 D4 D3 D2 D1 D0 PCC D7 D6 D5 D4 D3 D2 D1 D0 PD D7 D6 D5 D4 D3 D2 D1 D0 PDC D7 D6 D5 D4 D3 D2 D1 D0 PE — — D5 D4 D3 D2 D1 D0 PEC — — D5 D4 D3 D2 D1 D0 • HT68FB560 Rev. 1.30 Bit 78 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Pull-high Resistors Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when configured as an input have the capability of being connected to an internal pull-high resistor. These pull-high resistors are selected using registers, namely PAPU and PXPU, and are implemented using weak PMOS transistors. Note that the PA pull-high resistors are controlled by bits in the PAPU register, other than the PB, PC, PD, PE pull-high resistors are controlled by nibble in the PXPU register. PAPU Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 PAPU: I/O PA bit 7~bit 0 Pull-High Control 0: disable 1: enable PXPU Register • HT68FB540 Bit 7 6 5 4 3 2 1 0 Name — PELPU — — — — PBHPU PBLPU R/W R R/W R R R R R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 "—": unimplemented, read as "0" Bit 6 PELPU: PE2, PE0 pins Pull-High control 0: disable 1: enable Note that the PE1 pin has no pull-up resistor. Bit 5~2 "—": unimplemented, read as "0" Bit 1 PBHPU: PB6~PB4 pins Pull-High control 0: disable 1: enable Bit 0 PBLPU: PB3~PB0 pins Pull-High control 0: disable 1: enable • HT68FB550 Rev. 1.30 Bit 7 6 5 4 3 2 1 0 Name — PELPU PDHPU PDLPU — — PBHPU PBLPU R/W R R/W R/W R/W R R R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 "—": unimplemented, read as "0" Bit 6 PELPU: PE2, PE0 pins Pull-High control 0: disable 1: enable Note that the PE1 pin has no pull-up resistor. 79 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Bit 5 PDHPU: PD7~PD4 pins Pull-High control 0: disable 1: enable Bit 4 PDLPU: PD3~PD0 pins Pull-High control 0: disable 1: enable Bit 3~2 "—": unimplemented, read as "0" Bit 1 PBHPU: PB6~PB4 pins Pull-High control 0: disable 1: enable Bit 0 PBLPU: PB3~PB0 pins Pull-High control 0: disable 1: enable • HT68FB560 Rev. 1.30 Bit 7 6 5 4 3 2 1 0 Name PEHPU PELPU PDHPU PDLPU PCHPU PCLPU PBHPU PBLPU R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 PEHPU: PE5~PE4 pins Pull-High control 0: disable 1: enable Bit 6 PELPU: PE3~PE2, PE0 pins Pull-High control 0: disable 1: enable Note that the PE1 pin has no pull-up resistor. Bit 5 PDHPU: PD7~PD4 pins Pull-High control 0: disable 1: enable Bit 4 PDLPU: PD3~PD0 pins Pull-High control 0: disable 1: enable Bit 3 PCHPU: PC7~PC4 pins Pull-High control 0: disable 1: enable Bit 2 PCLPU: PC3~PC0 pins Pull-High control 0: disable 1: enable Bit 1 PBHPU: PB7~PB4 pins Pull-High control 0: disable 1: enable Bit 0 PBLPU: PB3~PB0 pins Pull-High control 0: disable 1: enable 80 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Port Wake-up The HALT instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves power, a feature that is important for battery and other low-power applications. Various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port A~Port E pins from high to low. This function is especially suitable for applications that can be woken up via external switches. Each pin on Port A~Port E can be selected by bits or nibble to have this wake-up feature using the PAWU and PXWU registers. PAWU Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 PAWU: Port A bit 7~bit 0 Wake-up Control 0: disable 1: enable PXWU Register • HT68FB540 Bit 7 6 5 4 3 2 1 0 Name — PELWU — — — — PBHWU PBLWU R/W R R/W R R R R R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 "—": unimplemented, read as "0" Bit 6 PELWU: PE2, PE0 pins Wake-up control 0: disable 1: enable Note that the PE1 pin has no wake-up function. Bit 5~2 "—": unimplemented, read as "0" Bit 1 PBHWU: PB6~PB4 pins Wake-up control 0: disable 1: enable Bit 0 PBLWU: PB3~PB0 pins Wake-up control 0: disable 1: enable • HT68FB550 Rev. 1.30 Bit 7 6 5 4 3 2 1 0 Name — PELWU PDHWU PDLWU — — PBHWU PBLWU R/W R R/W R/W R/W R R R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 "—": unimplemented, read as "0" Bit 6 PELWU: PE2, PE0 pins Wake-up control 0: disable 1: enable Note that the PE1 pin has no wake-up function. 81 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Bit 5 PDHWU: PD7~PD4 pins Wake-up control 0: disable 1: enable Bit 4 PDLWU: PD3~PD0 pins Wake-up control 0: disable 1: enable Bit 3~2 "—": unimplemented, read as "0" Bit 1 PBHWU: PB6~PB4 pins Wake-up control 0: disable 1: enable Bit 0 PBLWU: PB3~PB0 pins Wake-up control 0: disable 1: enable • HT68FB560 Bit 7 6 5 4 3 2 1 0 Name PEHWU PELWU PDHWU PDLWU PCHWU PCLWU PBHWU PBLWU R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 PEHWU: PE5~PE4 pins Wake-up control 0: disable 1: enable Bit 6 PELWU: PE3~PE2, PE0 pins Wake-up control 0: disable 1: enable Note that the PE1 pin has no wake-up function. Bit 5 PDHWU: PD7~PD4 pins Wake-up control 0: disable 1: enable Bit 4 PDLWU: PD3~PD0 pins Wake-up control 0: disable 1: enable Bit 3 PCHWU: PC7~PC4 pins Wake-up control 0: disable 1: enable Bit 2 PCLWU: PC3~PC0 pins Wake-up control 0: disable 1: enable Bit 1 PBHWU: PB7~PB4 pins Wake-up control 0: disable 1: enable Bit 0 PBLWU: PB3~PB0 pins Wake-up control 0: disable 1: enable Port A Wake-up Polarity Control Register The I/O port, PA, can be setup to have a choice of wake-up polarity using specific register. Each pin on Port A can be selected individually to have this Wake-up polarity feature using the PADIR register. Rev. 1.30 82 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI PADIR Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 PADIR: PA7~PA0 pins Wake-up edge control 0: rising edge 1: falling edge I/O Port Control Registers Each I/O port has its own control register known as PAC~PEC, to control the input/output configuration. With this control register, each CMOS output or input can be reconfigured dynamically under software control. Each pin of the I/O ports is directly mapped to a bit in its associated port control register. For the I/O pin to function as an input, the corresponding bit of the control register must be written as a "1". This will then allow the logic state of the input pin to be directly read by instructions. When the corresponding bit of the control register is written as a "0", the I/O pin will be setup as a CMOS output. If the pin is currently setup as an output, instructions can still be used to read the output register. However, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. PAC Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 PBC Register • HT68FB540/HT68FB550 Bit 7 6 5 4 3 2 1 0 Name — D6 D5 D4 D3 D2 D1 D0 R/W — R/W R/W R/W R/W R/W R/W R/W POR — 1 1 1 1 1 1 1 • HT68FB560 Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 PCC Register • HT68FB560 Rev. 1.30 Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 83 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI PDC Register • HT68FB550/HT68FB560 Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 PEC Register • HT68FB540/HT68FB550 Bit 7 6 5 4 3 2 1 0 Name — — — — — D2 D1 D0 R/W — — — — — R/W R/W R/W POR — — — — — 1 1 1 • HT68FB560 Bit 7 6 5 4 3 2 1 0 Name — — D5 D4 D3 D2 D1 D0 R/W — — R/W R/W R/W R/W R/W R/W POR — — 1 1 1 1 1 1 Bit 7~6 Bit 5~0 "—": unimplemented, read as "0" PEC: I/O Port bit 5~bit 0 Input/Output Control 0: Output 1: Input Port A , Port D Power Source Control Registers Port A and Port D can be setup to have a choice of various power source using specific registers. Each pin on Port A and Port D [7:4] can be selected individually to have various power sources using the PAPS0, PAPS1 and PDPS registers. PAPS0 Register Bit 7 6 5 4 3 2 1 0 Name PA3S1 PA3S0 PA2S1 PA2S0 PA1S1 PA1S0 PA0S1 PA0S0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 Bit 5~4 Bit 3~2 Bit 1~0 Rev. 1.30 PA3S1, PA3S0: PA3 power supply control 00: VDD 01: VDD 10: VDDIO 11: V33O, 3.3V regulator output PA2S1, PA2S0: PA2 power supply control 00: VDD 01: VDD 10: VDDIO 11: V33O, 3.3V regulator output PA1S1, PA1S0: PA1 power supply control 00: VDD 01: VDD 10: VDDIO 11: V33O, 3.3V regulator output PA0S1, PA0S0: PA0 power supply control 00: VDD 01: VDD 10: VDDIO 11: V33O, 3.3V regulator output 84 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI PAPS1 Register Bit 7 6 5 4 3 2 1 0 Name PA7S1 PA7S0 PA6S1 PA6S0 PA5S1 PA5S0 PA4S1 PA4S0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 PA7S1, PA7S0: PA7 power supply control 00: VDD 01: VDD 10: VDDIO 11: V33O, 3.3V regulator output Bit 5~4 PA6S1, PA6S0: PA6 power supply control 00: VDD 01: VDD 10: VDDIO 11: V33O, 3.3V regulator output Bit 3~2 PA5S1, PA5S0: PA5 power supply control 00: VDD 01: VDD 10: VDDIO 11: V33O, 3.3V regulator output Bit 1~0 PA4S1, PA4S0: PA4 power supply control 00: VDD 01: VDD 10: VDDIO 11: V33O, 3.3V regulator output PDPS Register • HT68FB550/HT68FB560 Rev. 1.30 Bit 7 6 5 4 3 2 1 0 Name PD7S1 PD7S0 PD6S1 PD6S0 PD5S1 PD5S0 PD4S1 PD4S0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 PD7S1, PD7S0: PD7 power supply control 00: VDD 01: VDD 10: VDDIO 11: V33O, 3.3V regulator output Bit 5~4 PD6S1, PD6S0: PD6 power supply control 00: VDD 01: VDD 10: VDDIO 11: V33O, 3.3V regulator output Bit 3~2 PD5S1, PD5S0: PD5 power supply control 00: VDD 01: VDD 10: VDDIO 11: V33O, 3.3V regulator output Bit 1~0 PD4S1, PD4S0: PD4 power supply control 00: VDD 01: VDD 10: VDDIO 11: V33O, 3.3V regulator output 85 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI I/O Pin Structures The accompanying diagrams illustrate the internal structures of some generic I/O pin types. As the exact logical construction of the I/O pin will differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the I/O pins. The wide range of pin-shared structures does not permit all types to be shown. Programming Considerations Within the user program, one of the first things to consider is port initialisation. After a reset, all of the I/O data and port control registers will be set high. This means that all I/O pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high selections have been chosen. If the port control registers, PAC~PEC, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers, PA~PE, are first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the "SET [m].i" and "CLR [m].i" instructions. Note that when using these bit control instructions, a read-modify-write operation takes place. The microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. All Ports provide the wake-up function which can be set by individual pin in the Port A while it has to be set by nibble pins in the Port B, Port C, Port D and Port E. When the device is in the SLEEP or IDLE Mode, various methods are available to wake the device up. One of these is a voltage level transition on any of the Port pins. Single or multiple pins on Ports can be setup to have this function. Generic Input/Output Structure Rev. 1.30 86 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Timer Modules – TM One of the most fundamental functions in any microcontroller device is the ability to control and measure time. To implement time related functions each device includes several Timer Modules, abbreviated to the name TM. The TMs are multi-purpose timing units and serve to provide operations such as Timer/Counter, Input Capture, Compare Match Output and Single Pulse Output as well as being the functional unit for the generation of PWM signals. Each of the TMs has two individual interrupts. The addition of input and output pins for each TM ensures that users are provided with timing units with a wide and flexible range of features. The common features of the different TM types are described here with more detailed information provided in the individual Compact and Standard TM sections. Introduction The devices contain four TMs having a reference name of TM0, TM1, TM2 and TM3. Each individual TM can be categorised as a certain type, namely Compact Type TM or Standard Type TM. Although similar in nature, the different TM types vary in their feature complexity. The common features to all of the Compact and Standard TMs will be described in this section. The detailed operation regarding each of the TM types will be described in separate sections. The main features and differences between the two types of TMs are summarised in the accompanying table. Function CTM STM Timer/Counter √ √ I/P Capture — √ Compare Match Output √ √ PWM Channels 1 1 Single Pulse Output — 1 PWM Alignment PWM Adjustment Period & Duty Edge Edge Duty or Period Duty or Period TM Function Summary Each device in the series contains a specific number of either Compact Type and Standard Type TM units which are shown in the table together with their individual reference name, TM0~TM3. Device TM0 TM1 TM2 TM3 HT68FB540/HT68FB550/HT68FB560 16-bit STM 10-bit STM 10-bit CTM 10-bit CTM TM Name/Type Reference TM Operation The different types of TM offer a diverse range of functions, from simple timing operations to PWM signal generation. The key to understanding how the TM operates is to see it in terms of a free running counter whose value is then compared with the value of pre-programmed internal comparators. When the free running counter has the same value as the pre-programmed comparator, known as a compare match situation, a TM interrupt signal will be generated which can clear the counter and perhaps also change the condition of the TM output pin. The internal TM counter is driven by a user selectable clock source, which can be an internal clock or an external pin. Rev. 1.30 87 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI TM Clock Source The clock source which drives the main counter in each TM can originate from various sources. The selection of the required clock source is implemented using the TnCK2~TnCK0 bits in the TM control registers. The clock source can be a ratio of either the system clock fSYS or the internal high clock fH, the fL clock source or the external TCKn pin. Note that setting these bits to the value 101 will select an undefined clock input, in effect disconnecting the TM clock source. The TCKn pin clock source is used to allow an external signal to drive the TM as an external clock source or for event counting. TM Interrupts The Compact and Standard type TMs each have two internal interrupts, one for each of the internal comparator A or comparator P, which generate a TM interrupt when a compare match condition occurs. When a TM interrupt is generated it can be used to clear the counter and also to change the state of the TM output pin. TM External Pins Each of the TMs, irrespective of what type, has one TM input pin, with the label TCKn. The TM input pin, is essentially a clock source for the TM and is selected using the TnCK2~TnCK0 bits in the TMnC0 register. This external TM input pin allows an external clock source to drive the internal TM. This external TM input pin is shared with other functions but will be connected to the internal TM if selected using the TnCK2~TnCK0 bits. The TM input pin can be chosen to have either a rising or falling active edge. The TMs each have two output pins with the label TPn. When the TM is in the Compare Match Output Mode, these pins can be controlled by the TM to switch to a high or low level or to toggle when a compare match situation occurs. The external TPn output pin is also the pin where the TM generates the PWM output waveform. As the TM output pins are pin-shared with other function, the TM output function must first be setup using registers. A single bit in one of the registers determines if its associated pin is to be used as an external TM output pin or if it is to have another function. The number of output pins for each TM type and device is different, the details are provided in the accompanying table. All TM output pin names have a "_n" suffix. Pin names that include a "_0" or "_1" suffix indicate that they are from a TM with multiple output pins. This allows the TM to generate a complimentary output pair, selected using the I/O register data bits. Device CTM STM Registers HT68FB540 HT68FB550 HT68FB560 TP2_0, TP2_1 TP3_0, TP3_1 TP0_0, TP0_1 TP1_0, TP1_1 TMPC0, TMPC1 TM Output Pins Rev. 1.30 88 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI TM Input/Output Pin Control Registers Selecting to have a TM input/output or whether to retain its other shared function, is implemented using one or two registers, with a single bit in each register corresponding to a TM input/output pin. Setting the bit high will setup the corresponding pin as a TM input/output, if reset to zero the pin will retain its original other function. Registers Device Bit 7 6 5 4 3 2 1 0 TMPC0 HT68FB540 HT68FB550 HT68FB560 — — T1CP1 T1CP0 — — T0CP1 T0CP0 TMPC1 HT68FB540 HT68FB550 HT68FB560 — — T3CP1 T3CP0 — — T2CP1 T2CP0 TM Input/Output Pin Control Registers List TM0 Function Pin Control Block Diagram Note: 1. The I/O register data bits shown are used for TM output inversion control. 2. In the Capture Input Mode, the TM pin control register must never enable more than one TM input. Rev. 1.30 89 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI TM1 Function Pin Control Block Diagram Note: 1. The I/O register data bits shown are used for TM output inversion control. 2. In the Capture Input Mode, the TM pin control register must never enable more than one TM input. TM2 Function Pin Control Block Diagram Note: The I/O register data bits shown are used for TM output inversion control. Rev. 1.30 90 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI TM3 Function Pin Control Block Diagram Note: The I/O register data bits shown are used for TM output inversion control. TMPC0 Register Bit 7 6 5 4 3 2 1 0 Name — — T1CP1 T1CP0 — — T0CP1 T0CP0 R/W R R R/W R/W R R R/W R/W POR 0 0 0 1 0 0 0 1 Bit 7~6 "—": unimplemented, read as "0" Rev. 1.30 Bit 5 T1CP1: TP1_1 pin Control 0: disable 1: enable Bit 4 T1CP0: TP1_0 pin Control 0: disable 1: enable Bit 3~2 "—": unimplemented, read as "0" Bit 1 T0CP1: TP0_1 pin Control 0: disable 1: enable Bit 0 T0CP0: TP0_0 pin Control 0: disable 1: enable 91 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI TMPC1 Register Bit 7 6 5 4 3 2 1 0 Name — — T3CP1 T3CP0 — — T2CP1 T2CP0 R/W R R R/W R/W R R R/W R/W POR 0 0 0 1 0 0 0 1 Bit 7~6 "—": unimplemented, read as "0" Bit 5 T3CP1: TP3_1 pin Control 0: disable 1: enable Bit 4 T3CP0: TP3_0 pin Control 0: disable 1: enable Bit 3~2 "—": unimplemented, read as "0" Bit 1 T2CP1: TP2_1 pin Control 0: disable 1: enable Bit 0 T2CP0: TP2_0 pin Control 0: disable 1: enable Programming Considerations The TM Counter Registers and the Capture/Compare CCRA register, being either 10-bit or 16bit, all have a low and high byte structure. The high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buffer, reading or writing to these register pairs must be carried out in a specific way. The important point to note is that data transfer to and from the 8-bit buffer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed. Rev. 1.30 92 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI The following steps show the read and write procedures: • Writing Data to CCRA ♦♦ Step 1. Write data to Low Byte TMxAL – note that here data is only written to the 8-bit buffer. ♦♦ Step 2. Write data to High Byte TMxAH – here data is written directly to the high byte registers and simultaneously data is latched from the 8-bit buffer to the Low Byte registers. • Reading Data from the Counter Registers and CCRA ♦♦ Step 1. Read data from the High Byte TMxDH or TMxAH – here data is read directly from the high byte registers and simultaneously data is latched from the Low Byte register into the 8-bit buffer. ♦♦ Step 2. Read data from the Low Byte TMxDL or TMxAL – this step reads data from the 8-bit buffer. As the CCRA register implemented in the way shown in the following diagram and accessing these register pairs is carried out in a specific way described above, it is recommended to use the "MOV" instruction to access the CCRA low byte register, named TMxAL, using the following access procedures. Accessing the CCRA low byte register without following these access procedures will result in unpredictable values. Compact Type TM Although the simplest form of the two TM types, the Compact TM type still contains three operating modes, which are Compare Match Output, Timer/Event Counter and PWM Output modes. The Compact TM can also be controlled with an external input pin and can drive two external output pins. These two external output pins can be the same signal or the inverse signal. CTM Name TM No. TM Input Pin TM Output Pin HT68FB540 HT68FB550 HT68FB560 10-bit CTM 2,3 TCK2, TCK3 TP2_0, TP2_1, TP3_0, TP3_1, Compact Type TM Block Diagram Rev. 1.30 93 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Compact TM Operation At its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. There are also two internal comparators with the names, Comparator A and Comparator P. These comparators will compare the value in the counter with CCRP and CCRA registers. The CCRP is three bits wide whose value is compared with the highest three bits in the counter while the CCRA is the ten bits and therefore compares with all counter bits. The only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the TnON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur, a TM interrupt signal will also usually be generated. The Compact Type TM can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. All operating setup conditions are selected using relevant internal registers. Compact Type TM Register Description Overall operation of the Compact TM is controlled using six registers. A read only register pair exists to store the internal counter 10-bit value, while a read/write register pair exists to store the internal 10-bit CCRA value. The remaining two registers are control registers which setup the different operating and control modes as well as the three CCRP bits. Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TMnC0 TnPAU TnCK2 TnCK1 TnCK0 TnON TnRP2 TnRP1 TnRP0 TMnC1 TnM1 TnM0 TnIO1 TnIO0 TnOC TnPOL TnDPX TnCCLR TMnDL D7 D6 D5 D4 D3 D2 D1 D0 TMnDH — — — — — — D9 D8 TMnAL D7 D6 D5 D4 D3 D2 D1 D0 TMnAH — — — — — — D9 D8 Compact TM Register List (n=2,3) TMnDL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0 TMnDL: TMn Counter Low Byte Register bit 7 ~ bit 0 TMn 10-bit Counter bit 7 ~ bit 0 TMnDH Register Rev. 1.30 Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R R POR — — — — — — 0 0 Bit 7~2 "—": unimplemented, read as "0" Bit 1~0 TMnDH: TMn Counter High Byte Register bit 1~bit 0 TMn 10-bit Counter bit 9~bit 8 94 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI TMnAL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 1 0 Bit 7~0 TMnAL: TMn CCRA Low Byte Register bit 7 ~ bit 0 TMn 10-bit CCRA bit 7 ~ bit 0 TMnAH Register Bit 7 6 5 4 3 2 Name — — — — — — D9 D8 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 "—": unimplemented, read as "0" Bit 1~0 TMnAH: TMn CCRA High Byte Register bit 1~bit 0 TMn 10-bit CCRA bit 9~bit 8 TMnC0 Register Rev. 1.30 Bit 7 6 5 4 3 2 1 0 Name TnPAU TnCK2 TnCK1 TnCK0 TnON TnRP2 TnRP1 TnRP0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 TnPAU: TMn Counter Pause Control 0: run 1: pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the TM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. Bit 6~4 TnCK2~TnCK0: Select TMn Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fL 101: Undefined 110: TCKn rising edge clock 111: TCKn falling edge clock These three bits are used to select the clock source for the TMn. Selecting the Reserved clock input will effectively disable the internal counter. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fL are other internal clocks, the details of which can be found in the oscillator section. 95 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Bit 3 TnON: TMn Counter On/Off Control 0: Off 1: On This bit controls the overall on/off function of the TMn. Setting the bit high enables the counter to run, clearing the bit disables the TMn. Clearing this bit to zero will stop the counter from counting and turn off the TMn which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value. If the TMn is in the Compare Match Output Mode then the TMn output pin will be reset to its initial condition, as specified by the TnOC bit, when the TnON bit changes from low to high. Bit 2~0 TnRP2~TnRP0: TMn CCRP 3-bit register, compared with the TMn Counter bit 9~bit 7 Comparator P Match Period 000: 1024 TMn clocks 001: 128 TMn clocks 010: 256 TMn clocks 011: 384 TMn clocks 100: 512 TMn clocks 101: 640 TMn clocks 110: 768 TMn clocks 111: 896 TMn clocks These three bits are used to setup the value on the internal CCRP 3-bit register, which are then compared with the internal counter’s highest three bits. The result of this comparison can be selected to clear the internal counter if the TnCCLR bit is set to zero. Setting the TnCCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. As the CCRP bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. Clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value. TMnC1 Register Rev. 1.30 Bit 7 6 5 4 3 2 1 0 Name TnM1 TnM0 TnIO1 TnIO0 TnOC TnPOL TnDPX TnCCLR R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 TnM1 ~ TnM0: Select TMn Operating Mode 00: Compare Match Output Mode 01: Undefined 10: PWM Mode 11: Timer/Counter Mode These bits setup the required operating mode for the TM. To ensure reliable operation the TM should be switched off before any changes are made to the TnM1 and TnM0 bits. In the Timer/Counter Mode, the TM output pin control must be disabled. Bit 5~4 TnIO1~TnIO0: Select TPn_0, TPn_1 output function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Mode 00: PWM Output inactive state 01: PWM Output active state 10: PWM output 11: Undefined Timer/counter Mode unused 96 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI These two bits are used to determine how the TMn output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the TMn is running. In the Compare Match Output Mode, the TnIO1 and TnIO0 bits determine how the TMn output pin changes state when a compare match occurs from the Comparator A. The TMn output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the TMn output pin should be setup using the TnOC bit in the TMnC1 register. Note that the output level requested by the TnIO1 and TnIO0 bits must be different from the initial value setup using the TnOC bit otherwise no change will occur on the TMn output pin when a compare match occurs. After the TMn output pin changes state it can be reset to its initial level by changing the level of the TnON bit from low to high. In the PWM Mode, the TnIO1 and TnIO0 bits determine how the TM output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to only change the values of the TnIO1 and TnIO0 bits only after the TMn has been switched off. Unpredictable PWM outputs will occur if the TnIO1 and TnIO0 bits are changed when the TM is running. Rev. 1.30 Bit 3 TnOC: TPn_0, TPn_1 Output control bit Compare Match Output Mode 0: Initial low 1: Initial high PWM Mode 0: Active low 1: Active high This is the output control bit for the TMn output pin. Its operation depends upon whether TMn is being used in the Compare Match Output Mode or in the PWM Mode. It has no effect if the TMn is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the TMn output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. Bit 2 TnPOL: TPn_0, TPn_1 Output polarity Control 0: Non-invert 1: Invert This bit controls the polarity of the TPn_0 or TPn_1 output pin. When the bit is set high the TMn output pin will be inverted and not inverted when the bit is zero. It has no effect if the TMn is in the Timer/Counter Mode. Bit 1 TnDPX: TMn PWM period/duty Control 0: CCRP - period; CCRA - duty 1: CCRP - duty; CCRA - period This bit determines which of the CCRA and CCRP registers are used for period and duty control of the PWM waveform. Bit 0 TnCCLR: Select TMn Counter clear condition 0: TMn Comparator P match 1: TMn Comparator A match This bit is used to select the method which clears the counter. Remember that the Compact TMn contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the TnCCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The TnCCLR bit is not used in the PWM Mode. 97 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Compact Type TM Operating Modes The Compact Type TM can operate in one of three operating modes, Compare Match Output Mode, PWM Mode or Timer/Counter Mode. The operating mode is selected using the TnM1 and TnM0 bits in the TMnC1 register. Compare Match Output Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register, should be set to "00" respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the TnCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match occurs from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both TnAF and TnPF interrupt request flags for the Comparator A and Comparator P respectively, will both be generated. If the TnCCLR bit in the TMnC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the TnAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when TnCCLR is high no TnPF interrupt request flag will be generated. If the CCRA bits are all zero, the counter will overflow when its reaches its maximum 10-bit, 3FF Hex, value, however here the TnAF interrupt request flag will not be generated. As the name of the mode suggests, after a comparison is made, the TM output pin will change state. The TM output pin condition however only changes state when a TnAF interrupt request flag is generated after a compare match occurs from Comparator A. The TnPF interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the TM output pin. The way in which the TM output pin changes state are determined by the condition of the TnIO1 and TnIO0 bits in the TMnC1 register. The TM output pin can be selected using the TnIO1 and TnIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the TM output pin, which is setup after the TnON bit changes from low to high, is setup using the TnOC bit. Note that if the TnIO1 and TnIO0 bits are zero then no pin change will take place. Rev. 1.30 98 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Counter Value Counter overflow CCRP=0 0x3FF TnCCLR = 0; TnM [1:0] = 00 CCRP > 0 Counter cleared by CCRP value CCRP > 0 Counter Restart Resume CCRP Pause CCRA Stop Time TnON TnPAU TnPOL CCRP Int. Flag TnPF CCRA Int. Flag TnAF TM O/P Pin Output pin set to initial Level Low if TnOC=0 Output not affected by TnAF flag. Remains High until reset by TnON bit Output Toggle with TnAF flag Here TnIO [1:0] = 11 Toggle Output select Note TnIO [1:0] = 10 Active High Output select Output Inverts when TnPOL is high Output Pin Reset to Initial value Output controlled by other pin-shared function Compare Match Output Mode – TnCCLR= 0 Note: 1. With TnCCLR= 0, a Comparator P match will clear the counter 2. The TM output pin is controlled only by the TnAF flag 3. The output pin is reset to its initial state by a TnON bit rising edge Rev. 1.30 99 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Counter Value TnCCLR = 1; TnM [1:0] = 00 CCRA = 0 Counter overflow CCRA > 0 Counter cleared by CCRA value 0x3FF CCRA=0 Resume CCRA Pause Stop Counter Restart CCRP Time TnON TnPAU TnPOL No TnAF flag generated on CCRA overflow CCRA Int. Flag TnAF CCRP Int. Flag TnPF TnPF not generated Output does not change TM O/P Pin Output pin set to initial Level Low if TnOC=0 Output not affected by TnAF flag. Remains High until reset by TnON bit Output Toggle with TnAF flag Here TnIO [1:0] = 11 Toggle Output select Note TnIO [1:0] = 10 Active High Output select Output Inverts when TnPOL is high Output Pin Reset to Initial value Output controlled by other pin-shared function Compare Match Output Mode – TnCCLR= 1 Note: 1. With TnCCLR= 1, a Comparator A match will clear the counter 2. The TM output pin is controlled only by the TnAF flag 3. The output pin is reset to its initial state by a TnON bit rising edge 4. The TnPF flag is not generated when TnCCLR= 1 Timer/Counter Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the TM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. Rev. 1.30 100 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI PWM Output Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 10 respectively. The PWM function within the TM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the TM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM mode, the TnCCLR bit has no effect on the PWM operation. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. Which register is used to control either frequency or duty cycle is determined using the TnDPX bit in the TMnC1 register. The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers. An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match occurs from either Comparator A or Comparator P. The TnOC bit in the TMnC1 register is used to select the required polarity of the PWM waveform while the two TnIO1 and TnIO0 bits are used to enable the PWM output or to force the TM output pin to a fixed high or low level. The TnPOL bit is used to reverse the polarity of the PWM output waveform. CTM, PWM Mode, Edge-aligned Mode, TnDPX= 0 CCRP 001b 010b 011b 100b 101b 110b 111b 000b Period 128 256 384 512 640 768 896 1024 Duty CCRA If fSYS = 16MHz, TM clock source is fSYS/4, CCRP = 100b and CCRA = 128, The CTM PWM output frequency = (fSYS/4)/512 = fSYS/2048 = 7.8125kHz, duty = 128/512 = 25%. If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty is 100%. CTM, PWM Mode, Edge-aligned Mode, TnDPX= 1 CCRP 001b 010b 011b 100b 128 256 384 512 Period Duty 101b 110b 111b 000b 768 896 1024 CCRA 640 The PWM output period is determined by the CCRA register value together with the TM clock while the PWM duty cycle is defined by the CCRP register value. Rev. 1.30 101 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Counter Value TnDPX = 0; TnM [1:0] = 10 Counter cleared by CCRP Counter Reset when TnON returns high CCRP Pause Resume CCRA Counter Stop if TnON bit low Time TnON TnPAU TnPOL CCRA Int. Flag TnAF CCRP Int. Flag TnPF TM O/P Pin (TnOC=1) TM O/P Pin (TnOC=0) PWM Duty Cycle set by CCRA PWM Period set by CCRP PWM resumes operation Output controlled by Output Inverts other pin-shared function when TnPOL = 1 PWM Mode – TnDPX= 0 Note: 1. Here TnDPX= 0 – Counter cleared by CCRP 2. A counter clear sets the PWM Period 3. The internal PWM function continues even when TnIO [1:0] = 00 or 01 4. The TnCCLR bit has no influence on PWM operation Rev. 1.30 102 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Counter Value TnDPX = 1; TnM [1:0] = 10 Counter cleared by CCRA Counter Reset when TnON returns high CCRA Pause Resume CCRP Counter Stop if TnON bit low Time TnON TnPAU TnPOL CCRP Int. Flag TnPF CCRA Int. Flag TnAF TM O/P Pin (TnOC=1) TM O/P Pin (TnOC=0) PWM Duty Cycle set by CCRP PWM Period set by CCRA PWM resumes operation Output controlled by Output Inverts other pin-shared function when TnPOL = 1 PWM Mode – TnDPX= 1 Note: 1. Here TnDPX = 1 – Counter cleared by CCRA 2. A counter clear sets the PWM Period 3. The internal PWM function continues even when TnIO [1:0] = 00 or 01 4. The TnCCLR bit has no influence on PWM operation Rev. 1.30 103 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Standard Type TM – STM The Standard Type TM contains five operating modes, which are Compare Match Output, Timer/ Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Standard TM can also be controlled with an external input pin and can drive one or two external output pins. STM Name TM No. TM Input Pin TM Output Pin HT68FB540 HT68FB550 HT68FB560 16-bit STM 10-bit STM 0, 1 TCK0, TCK1 TP0_0, TP0_1 TP1_0, TP1_1 Standard TM Operation There are two sizes of Standard TMs, one is 10-bit wide and the other is 16-bit wide. At the core is a 10 or 16-bit count-up counter which is driven by a user selectable internal or external clock source. There are also two internal comparators with the names, Comparator A and Comparator P. These comparators will compare the value in the counter with CCRP and CCRA registers. The CCRP comparator is 3 or 8-bits wide whose value is compared the with highest 3 or 8 bits in the counter while the CCRA is the ten or sixteen bits and therefore compares all counter bits. The only way of changing the value of the 10 or 16-bit counter using the application program, is to clear the counter by changing the TnON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur, a TM interrupt signal will also usually be generated. The Standard Type TM can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. All operating setup conditions are selected using relevant internal registers. Standard Type TM Block Diagram Rev. 1.30 104 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Standard Type TM Register Description Overall operation of the Standard TM is controlled using a series of registers. A read only register pair exists to store the internal counter 10 or 16-bit value, while a read/write register pair exists to store the internal 10 or 16-bit CCRA value. The remaining two registers are control registers which setup the different operating and control modes as well as the three or eight CCRP bits. 16-bit Standard TM Register List Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TM0C0 T0PAU T0CK2 T0CK1 T0CK0 T0ON — — — TM0C1 T0M1 T0M0 T0IO1 T0IO0 T0OC T0POL T0PX T0CLR TM0DL D7 D6 D5 D4 D3 D2 D1 D0 TM0DH D15 D14 D13 D12 D11 D10 D9 D8 TM0AL D7 D6 D5 D4 D3 D2 D1 D0 TM0AH D15 D14 D13 D12 D11 D10 D9 D8 TM0RP D7 D6 D5 D4 D3 D2 D1 D0 • TM0C0 Register Rev. 1.30 Bit 7 6 5 4 3 2 1 0 Name T0PAU T0CK2 T0CK1 T0CK0 T0ON — — — R/W R/W R/W R/W R/W R/W R R R POR 0 0 0 0 0 0 0 0 Bit 7 T0PAU: TM0 Counter Pause Control 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the TM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. Bit 6~4 T0CK2, T0CK1, T0CK0: Select TM0 Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fL 101: Reserved 110: TCK0 rising edge clock 111: TCK0 falling edge clock These three bits are used to select the clock source for the TM. Selecting the Reserved clock input will effectively disable the internal counter. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fL are other internal clocks, the details of which can be found in the oscillator section. 105 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Bit 3 Bit 2~0 T0ON: TM0 Counter On/Off Control 0: Off 1: On This bit controls the overall on/off function of the TM. Setting the bit high enables the counter to run, clearing the bit disables the TM. Clearing this bit to zero will stop the counter from counting and turn off the TM which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial condition, as specified by the T0OC bit, when the T0ON bit changes from low to high. "—": unimplemented, read as "0" • TM0C1 Register Bit 7 6 5 4 3 2 1 0 Name T0M1 T0M0 T0IO1 T0IO0 T0OC T0POL T0DPX T0CCLR R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 Bit 5~4 T0M1~T0M0: Select TM0 Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the TM. To ensure reliable operation the TM should be switched off before any changes are made to the T0M1 and T0M0 bits. In the Timer/Counter Mode, the TM output pin control must be disabled. T0IO1~T0IO0: Select TP0_0, TP0_1 output function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Mode/ Single Pulse Output Mode 00: Force inactive state 01: Force active state 10: PWM output 11: Single pulse output Capture Input Mode 00: Input capture at rising edge of TP0_0, TP0_1 01: Input capture at falling edge of TP0_0, TP0_1 10: Input capture at falling/rising edge of TP0_0, TP0_1 11: Input capture disabled Timer/counter Mode: Unused These two bits are used to determine how the TM output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the TM is running. In the Compare Match Output Mode, the T0IO1 and T0IO0 bits determine how the TM output pin changes state when a compare match occurs from the Comparator A. The TM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the TM output pin should be setup using the T0OC bit in the TM0C1 register. Note that the output level requested by the T0IO1 and T0IO0 bits must be different from the initial value setup using the T0OC bit otherwise no change will occur on the TM output pin when a compare match occurs. After the TM output pin changes state it can be reset to its initial level by changing the level of the T0ON bit from low to high. Rev. 1.30 106 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI In the PWM Mode, the T0IO1 and T0IO0 bits determine how the TM output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to only change the values of the T0IO1 and T0IO0 bits only after the TM has been switched off. Unpredictable PWM outputs will occur if the T0IO1 and T0IO0 bits are changed when the TM is running. Bit 3 T0OC: TP0_0, TP0_1 Output control bit Compare Match Output Mode 0: Initial low 1: Initial high PWM Mode/ Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the TM output pin. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode/ Single Pulse Output Mode. It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. Bit 2 T0POL: TP0_0, TP0_1 Output polarity Control 0: Non-invert 1: Invert This bit controls the polarity of the TP0_0 or TP0_1 output pin. When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the Timer/Counter Mode. Bit 1 T0DPX: TM0 PWM period/duty Control 0: CCRP - period; CCRA - duty 1: CCRP - duty; CCRA - period This bit, determines which of the CCRA and CCRP registers are used for period and duty control of the PWM waveform. Bit 0 T0CCLR: Select TM0 Counter clear condition 0: TM0 Comparator P match 1: TM0 Comparator A match This bit is used to select the method which clears the counter. Remember that the Standard TM contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the T0CCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The T0CCLR bit is not used in the PWM, Single Pulse or Input Capture Mode. • TM0DL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0 Rev. 1.30 TM0DL: TM0 Counter Low Byte Register bit 7~bit 0 TM0 16-bit Counter bit 7~bit 0 107 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI • TM0DH Register Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0 TM0DH: TM0 Counter High Byte Register bit 7~bit 0 TM0 16-bit Counter bit 15~bit 8 • TM0AL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 TM0AL: TM0 CCRA Low Byte Register bit 7~bit 0 TM0 16-bit CCRA bit 7~bit 0 • TM0AH Register Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 TM0AH: TM0 CCRA High Byte Register bit 7~bit 0 TM0 16-bit CCRA bit 15~bit 8 • TM0RP Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 TM0RP: TM0 CCRP Register bit 7~bit 0 TM0 CCRP 8-bit register, compared with the TM0 Counter bit 15~bit 8. Comparator P Match Period 0: 65536 TM0 clocks 1~255: 256 x (1~255) TM0 clocks These eight bits are used to setup the value on the internal CCRP 8-bit register, which are then compared with the internal counter’s highest eight bits. The result of this comparison can be selected to clear the internal counter if the T0CCLR bit is set to zero. Setting the T0CCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. As the CCRP bits are only compared with the highest eight counter bits, the compare values exist in 256 clock cycle multiples. Clearing all eight bits to zero is in effect allowing the counter to overflow at its maximum value. 10-bit Standard TM Register List Rev. 1.30 Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TM1C0 T1PAU T1CK2 T1CK1 T1CK0 T1ON T1RP2 T1RP1 T1RP0 TM1C1 T1M1 T1M0 T1IO1 T1IO0 T1OC T1POL T1DPX T1CCLR TM1DL D7 D6 D5 D4 D3 D2 D1 D0 TM1DH — — — — — — D9 D8 TM1AL D7 D6 D5 D4 D3 D2 D1 D0 TM1AH — — — — — — D9 D8 108 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI • TM1C0 Register Bit 7 6 5 4 3 2 1 0 Name T1PAU T1CK2 T1CK1 T1CK0 T1ON T1RP2 T1RP1 T1RP0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 Bit 6~4 Bit 3 Bit 2~0 Rev. 1.30 T1PAU: TM1 Counter Pause Control 0: run 1: pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the TM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. T1CK2~T1CK0: Select TM1 Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fL 101: Undefined 110: TCK1 rising edge clock 111: TCK1 falling edge clock These three bits are used to select the clock source for the TM. Selecting the Reserved clock input will effectively disable the internal counter. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fL are other internal clocks, the details of which can be found in the oscillator section. T1ON: TM1 Counter On/Off Control 0: Off 1: On This bit controls the overall on/off function of the TM. Setting the bit high enables the counter to run, clearing the bit disables the TM. Clearing this bit to zero will stop the counter from counting and turn off the TM which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial condition, as specified by the T1OC bit, when the T1ON bit changes from low to high. T1RP2~T1RP0: TMn CCRP 3-bit register, compared with the TMn Counter bit 9~bit 7 Comparator P Match Period 000: 1024 TM1 clocks 001: 128 TM1 clocks 010: 256 TM1 clocks 011: 384 TM1 clocks 100: 512 TM1 clocks 101: 640 TM1 clocks 110: 768 TM1 clocks 111: 896 TM1 clocks These three bits are used to setup the value on the internal CCRP 3-bit register, which are then compared with the internal counter’s highest three bits. The result of this comparison can be selected to clear the internal counter if the T1CCLR bit is set to zero. Setting the T1CCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. As the CCRP bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. Clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value. 109 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI • TM1C1 Register Rev. 1.30 Bit 7 6 5 4 3 2 1 0 Name T1M1 T1M0 T1IO1 T1IO0 T1OC T1POL T1DPX T1CCLR R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 T1M1~T1M0: Select TM1 Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the TM. To ensure reliable operation the TM should be switched off before any changes are made to the T1M1 and T1M0 bits. In the Timer/Counter Mode, the TM output pin control must be disabled. Bit 5~4 T1IO1~T1IO0: Select TP1_0, TP1_1 output function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Mode/Single Pulse Output Mode 00: PWM Output inactive state 01: PWM Output active state 10: PWM output 11: Single pulse output Capture Input Mode 00: Input capture at rising edge of TP1_0, TP1_1 01: Input capture at falling edge of TP1_0, TP1_1 10: Input capture at falling/rising edge of TP1_0, TP1_1 11: Input capture disabled Timer/counter Mode: Unused These two bits are used to determine how the TM output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the TM is running. In the Compare Match Output Mode, the T1IO1 and T1IO0 bits determine how the TM output pin changes state when a compare match occurs from the Comparator A. The TM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the TM output pin should be setup using the T1OC bit in the TM1C1 register. Note that the output level requested by the T1IO1 and T1IO0 bits must be different from the initial value setup using the T1OC bit otherwise no change will occur on the TM output pin when a compare match occurs. After the TM output pin changes state it can be reset to its initial level by changing the level of the T1ON bit from low to high. In the PWM Mode, the T1IO1 and T1IO0 bits determine how the TM output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to only change the values of the T1IO1 and T1IO0 bits only after the TM has been switched off. Unpredictable PWM outputs will occur if the T1IO1 and T1IO0 bits are changed when the TM is running 110 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Bit 3 T1OC: TP1_0, TP1_1 Output control bit Compare Match Output Mode 0: initial low 1: initial high PWM Mode/ Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the TM output pin. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode/ Single Pulse Output Mode. It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. Bit 2 T1POL: TP1_0, TP1_1 Output polarity Control 0: non-invert 1: invert This bit controls the polarity of the TP1_0 or TP1_1 output pin. When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the Timer/Counter Mode. Bit 1 T1DPX: TMn PWM period/duty Control 0: CCRP - period; CCRA - duty 1: CCRP - duty; CCRA - period This bit, determines which of the CCRA and CCRP registers are used for period and duty control of the PWM waveform. Bit 0 T1CCLR: Select TM1 Counter clear condition 0: TM1 Comparator P match 1: TM1 Comparator A match This bit is used to select the method which clears the counter. Remember that the Standard TM contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the T1CCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The T1CCLR bit is not used in the PWM, Single Pulse or Input Capture Mode. • TM1DL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0 TM1DL: TM1 Counter Low Byte Register bit 7~bit 0 TM1 10-bit Counter bit 7~bit 0 • TM1DH Register Rev. 1.30 Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R R POR — — — — — — 0 0 Bit 7~2 "—": unimplemented, read as "0" Bit 1~0 TM1DH: TM1 Counter High Byte Register bit 1~bit 0 TM1 10-bit Counter bit 9~bit 8 111 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI • TM1AL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 1 0 Bit 7~0 TM1AL: TM1 CCRA Low Byte Register bit 7~bit 0 TM1 10-bit CCRA bit 7~bit 0 • TM1AH Register Bit 7 6 5 4 3 2 Name — — — — — — D9 D8 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 "—": unimplemented, read as "0" Bit 1~0 TM1AH: TM1 CCRA High Byte Register bit 1~bit 0 TM1 10-bit CCRA bit 9~bit 8 Standard Type TM Operating Modes The Standard Type TM can operate in one of five operating modes, Compare Match Output Mode, PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The operating mode is selected using the TnM1 and TnM0 bits in the TMnC1 register. Compare Output Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register, should be set to 00 respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the TnCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both TnAF and TnPF interrupt request flags for Comparator A and Comparator P respectively, will both be generated. If the TnCCLR bit in the TMnC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the TnAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when TnCCLR is high no TnPF interrupt request flag will be generated. In the Compare Match Output Mode, the CCRA can not be set to "0". As the name of the mode suggests, after a comparison is made, the TM output pin, will change state. The TM output pin condition however only changes state when a TnAF interrupt request flag is generated after a compare match occurs from Comparator A. The TnPF interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the TM output pin. The way in which the TM output pin changes state are determined by the condition of the TnIO1 and TnIO0 bits in the TMnC1 register. The TM output pin can be selected using the TnIO1 and TnIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the TM output pin, which is setup after the TnON bit changes from low to high, is setup using the TnOC bit. Note that if the TnIO1 and TnIO0 bits are zero then no pin change will take place. Rev. 1.30 112 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Timer/Counter Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the TM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. Counter Value Counter overflow CCRP=0 0x3FF TnCCLR = 0; TnM [1:0] = 00 CCRP > 0 Counter cleared by CCRP value CCRP > 0 Counter Restart Resume CCRP Pause CCRA Stop Time TnON TnPAU TnPOL CCRP Int. Flag TnPF CCRA Int. Flag TnAF TM O/P Pin Output pin set to initial Level Low if TnOC=0 Output not affected by TnAF flag. Remains High until reset by TnON bit Output Toggle with TnAF flag Here TnIO [1:0] = 11 Toggle Output select Note TnIO [1:0] = 10 Active High Output select Output Inverts when TnPOL is high Output Pin Reset to Initial value Output controlled by other pin-shared function Compare Match Output Mode – TnCCLR= 0 Note: 1. With TnCCLR= 0 a Comparator P match will clear the counter 2. The TM output pin is controlled only by the TnAF flag 3. The output pin is reset to its initial state by a TnON bit rising edge Rev. 1.30 113 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Counter Value TnCCLR = 1; TnM [1:0] = 00 CCRA = 0 Counter overflow CCRA > 0 Counter cleared by CCRA value 0x3FF CCRA=0 Resume CCRA Pause Stop Counter Restart CCRP Time TnON TnPAU TnPOL No TnAF flag generated on CCRA overflow CCRA Int. Flag TnAF CCRP Int. Flag TnPF TnPF not generated Output does not change TM O/P Pin Output pin set to initial Level Low if TnOC=0 Output not affected by TnAF flag. Remains High until reset by TnON bit Output Toggle with TnAF flag Here TnIO [1:0] = 11 Toggle Output select Note TnIO [1:0] = 10 Active High Output select Output Inverts when TnPOL is high Output Pin Reset to Initial value Output controlled by other pin-shared function Compare Match Output Mode – TnCCLR= 1 Note: 1. With TnCCLR= 1 a Comparator A match will clear the counter 2. The TM output pin is controlled only by the TnAF flag 3. The output pin is reset to its initial state by a TnON bit rising edge 4. A TnPF flag is not generated when TnCCLR= 1 Timer/Counter Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the TM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 10 respectively and also the TnIO1 and TnIO0 bits should be set to 10 respectively. The PWM function within the TM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the TM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. Rev. 1.30 114 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM mode, the TnCCLR bit has no effect as the PWM period. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. Which register is used to control either frequency or duty cycle is determined using the TnDPX bit in the TMnC1 register. The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers. An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match occurs from either Comparator A or Comparator P. The TnOC bit in the TMnC1 register is used to select the required polarity of the PWM waveform while the two TnIO1 and TnIO0 bits are used to enable the PWM output or to force the TM output pin to a fixed high or low level. The TnPOL bit is used to reverse the polarity of the PWM output waveform. 16-bit STM, PWM Mode, Edge-aligned Mode, T0DPX= 0 CCRP 1~255 000b Period CCRP x 256 65536 Duty CCRA If fSYS = 16MHz, TM clock source select fSYS/4, CCRP = 2 and CCRA = 128, The STM PWM output frequency = (fSYS/4)/(2x256)= fSYS/2048 = 7.8125kHz, duty= 128/512= 25% If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty is 100%. 16-bit STM, PWM Mode, Edge-aligned Mode, T0DPX= 1 CCRP 1~255 Period 000b CCRA 65536 CCRP x 256 Duty The PWM output period is determined by the CCRA register value together with the TM clock while the PWM duty cycle is defined by the (CCRP x 256) except when CCRP value is equal to 000b. 10-bit STM, PWM Mode, Edge-aligned Mode, T1DPX= 0 CCRP 001b 010b 011b 100b 101b 110b 111b 000b Period 128 256 384 512 640 768 896 1024 Duty CCRA If fSYS = 16MHz, TM clock source select fSYS/4, CCRP = 100b and CCRA = 128, The STM PWM output frequency = (fSYS/4)/512 = fSYS/2048 = 7.8125kHz, duty = 128/512 = 25% If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty is 100%. 10-bit STM, PWM Mode, Edge-aligned Mode, T1DPX= 1 CCRP 001b 010b 011b 100b Period Duty 101b 110b 111b 000b 768 896 1024 CCRA 128 256 384 512 640 The PWM output period is determined by the CCRA register value together with the TM clock while the PWM duty cycle is defined by the CCRP register value. Rev. 1.30 115 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Counter Value TnDPX = 0; TnM [1:0] = 10 Counter cleared by CCRP Counter Reset when TnON returns high CCRP Pause Resume CCRA Counter Stop if TnON bit low Time TnON TnPAU TnPOL CCRA Int. Flag TnAF CCRP Int. Flag TnPF TM O/P Pin (TnOC=1) TM O/P Pin (TnOC=0) PWM Duty Cycle set by CCRA PWM Period set by CCRP PWM resumes operation Output controlled by Output Inverts other pin-shared function when TnPOL = 1 PWM Mode – TnDPX= 0 Note: 1. Here TnDPX= 0 – Counter cleared by CCRP 2. A counter clear sets the PWM Period 3. The internal PWM function continues running even when TnIO [1:0]= 00 or 01 4. The TnCCLR bit has no influence on PWM operation Rev. 1.30 116 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Counter Value TnDPX = 1; TnM [1:0] = 10 Counter cleared by CCRA Counter Reset when TnON returns high CCRA Pause Resume CCRP Counter Stop if TnON bit low Time TnON TnPAU TnPOL CCRP Int. Flag TnPF CCRA Int. Flag TnAF TM O/P Pin (TnOC=1) TM O/P Pin (TnOC=0) PWM Duty Cycle set by CCRP PWM Period set by CCRA PWM resumes operation Output controlled by Output Inverts other pin-shared function when TnPOL = 1 PWM Mode – TnDPX= 1 Note: 1. Here TnDPX= 1 – Counter cleared by CCRA 2. A counter clear sets the PWM Period 3. The internal PWM function continues even when TnIO [1:0]= 00 or 01 4. The TnCCLR bit has no influence on PWM operation Single Pulse Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 10 respectively and also the TnIO1 and TnIO0 bits should be set to 11 respectively. The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the TM output pin. The trigger for the pulse output leading edge is a low to high transition of the TnON bit, which can be implemented using the application program. However in the Single Pulse Mode, the TnON bit can also be made to automatically change from low to high using the external TCKn pin, which will in turn initiate the Single Pulse output. When the TnON bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. The TnON bit should remain high when the pulse is in its active state. The generated pulse trailing edge will be generated when the TnON bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from Comparator A. However a compare match from Comparator A will also automatically clear the TnON bit and thus generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control Rev. 1.30 117 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI the pulse width. A compare match from Comparator A will also generate a TM interrupt. The counter can only be reset back to zero when the TnON bit changes from low to high when the counter restarts. In the Single Pulse Mode CCRP is not used. The TnCCLR and TnDPX bits are not used in this Mode. Single Pulse Generation Counter Value TnM [1:0] = 10 ; TnIO [1:0] = 11 Counter stopped by CCRA Counter Reset when TnON returns high CCRA Pause Counter Stops by software Resume CCRP Time TnON Software Trigger Auto. set by TCKn pin Cleared by CCRA match TCKn pin Software Trigger Software Trigger Software Software Trigger Clear TCKn pin Trigger TnPAU TnPOL CCRP Int. Flag TnPF No CCRP Interrupts generated CCRA Int. Flag TnAF TM O/P Pin (TnOC=1) TM O/P Pin (TnOC=0) Output Inverts when TnPOL = 1 Pulse Width set by CCRA Single Pulse Mode Note: 1. Counter stopped by CCRA 2. CCRP is not used 3. The pulse is triggered by the TCKn pin or by setting the TnON bit high 4. A TCKn pin active edge will automatically set the TnON bit hight 5. In the Single Pulse Mode, TnIO [1:0] must be set to "11" and can not be changed. Rev. 1.30 118 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Capture Input Mode To select this mode bits TnM1 and TnM0 in the TMnC1 register should be set to 01 respectively. This mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. The external signal is supplied on the TPn_0 or TPn_1 pin, whose active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the TnIO1 and TnIO0 bits in the TMnC1 register. The counter is started when the TnON bit changes from low to high which is initiated using the application program. When the required edge transition appears on the TPn_0 or TPn_1 pin the present value in the counter will be latched into the CCRA registers and a TM interrupt generated. Irrespective of what events occur on the TPn_0 or TPn_1 pin the counter will continue to free run until the TnON bit changes from high to low. When a CCRP compare match occurs the counter will reset back to zero; in this way the CCRP value can be used to control the maximum counter value. When a CCRP compare match occurs from Comparator P, a TM interrupt will also be generated. Counting the number of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse widths. The TnIO1 and TnIO0 bits can select the active trigger edge on the TPn_0 or TPn_1 pin to be a rising edge, falling edge or both edge types. If the TnIO1 and TnIO0 bits are both set high, then no capture operation will take place irrespective of what happens on the TPn_0 or TPn_1 pin, however it must be noted that the counter will continue to run. As the TPn_0 or TPn_1 pin is pin shared with other functions, care must be taken if the TM is in the Input Capture Mode. This is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. The TnCCLR and TnDPX bits are not used in this Mode. Rev. 1.30 119 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Counter Value TnM [1:0] = 01 Counter cleared by CCRP Counter Counter Stop Reset CCRP YY Pause Resume XX Time TnON TnPAU TM capture pin TPn_x Active edge Active edge Active edge CCRA Int. Flag TnAF CCRP Int. Flag TnPF CCRA Value TnIO [1:0] Value XX 00 – Rising edge YY 01 – Falling edge XX 10 – Both edges YY 11 – Disable Capture Capture Input Mode Note: 1. TnM [1:0] = 01 and active edge set by the TnIO [1:0] bits 2. A TM Capture input pin active edge transfers the counter value to CCRA 3. TnCCLR bit not used 4. No output function – TnOC and TnPOL bits are not used 5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to zero. Rev. 1.30 120 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Serial Interface Module – SIM The devices contain a Serial Interface Module, which includes both the four line SPI interface and the two line I2C interface types, to allow an easy method of communication with external peripheral hardware. Having relatively simple communication protocols, these serial interface types allow the microcontroller to interface to external SPI or I2C based hardware such as sensors, Flash or EEPROM memory, etc. The SIM interface pins are pin-shared with other I/O pins therefore the SIM interface function must first be selected by software control. As both interface types share the same pins and registers, the choice of whether the SPI or I2C type is used is made using the SIM operating mode control bits, named SIM2~SIM0, in the SIMC0 register. These pull-high resistors of the SIM pin-shared I/O are selected using pull-high control registers, and also if the SIM function is enabled. There is one control register associated with the serial interface control, namely SBSC. This is used to enable the SIM_WCOL bit function, SA_WCOL bit function and I2C debounce selection. The devices provide two kinds of SPI function, namely SPI and SPIA, each of them has the corresponding WCOL control bits to enable the SIM WCOL and SPIA WCOL control bits, namely SIM_WCOL and SA_WCOL respectively. In addition, the I2CDB1 and I2CDB0 bits are used to select the I2C debounce time. SPI Interface This SPI interface function, which is part of the Serial Interface Module, should not be confused with the other independent SPI function, known as SPIA, which is described in another section of this datasheet. The SPI interface is often used to communicate with external peripheral devices such as sensors, Flash or EEPROM memory devices etc. Originally developed by Motorola, the four line SPI interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices. The communication is full duplex and operates as a slave/master type, where the device can be either master or slave. Although the SPI interface specification can control multiple slave devices from a single master, but this device provided only one SCS pin. If the master needs to control multiple slave devices from a single master, the master can use I/O pin to select the slave devices. SPI Interface Operation The SPI interface is a full duplex synchronous serial data link. It is a four line interface with pin names SDI, SDO, SCK and SCS. Pins SDI and SDO are the Serial Data Input and Serial Data Output lines, SCK is the Serial Clock line and SCS is the Slave Select line. As the SPI interface pins are pinshared with other functions and with the I2C function pins, the SPI interface must first be selected by the correct bits in the SIMC0 and SIMC2 registers. After the SPI option has been selected, it can also be additionally disabled or enabled using the SIMEN bit in the SIMC0 register. SPI Master/Slave Connection Rev. 1.30 121 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI SPI Block Diagram The SPI function in these devices offer the following features: • Full duplex synchronous data transfer • Both Master and Slave modes • LSB first or MSB first data transmission modes • Transmission complete flag • Rising or falling active clock edge • WCOL bit enabled or disable select The status of the SPI interface pins is determined by a number of factors such as whether the device is in the master or slave mode and upon the condition of certain control bits such as CSEN and SIMEN. SPI Registers There are four internal registers which control the overall operation of the SPI interface. These are the SIMD data register and three registers SIMC0, SIMC2 and SBSC. Note that the SIMC1 register is only used by the I2C interface. Bit Register Name 7 6 5 4 3 2 1 0 SIMC0 SIM2 SIM1 SIM0 PCKEN PCKP1 PCKP0 SIMEN — SIMD D7 D6 D5 D4 D3 D2 D1 D0 SIMC2 D7 D6 CKPOLB CKEG MLS CSEN WCOL TRF SBSC SIM_WCOL — I2CDB1 I2CDB0 — — — SA_WCOL SIM Registers List The SIMD register is used to store the data being transmitted and received. The same register is used by both the SPI and I2C functions. Before the device writes data to the SPI bus, the actual data to be transmitted must be placed in the SIMD register. After the data is received from the SPI bus, the device can read it from the SIMD register. Any transmission or reception of data from the SPI bus must be made via the SIMD register. The SIM_WCOL bit in the SBSC register is used to control the SPI WCOL function. Rev. 1.30 122 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI SIMD Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x "x" unknown There are also three control registers for the SPI interface, SIMC0 SIMC2 and SBSC. Note that the SIMC2 register also has the name SIMA which is used by the I2C function. The SIMC1 register is not used by the SPI function, only by the I2C function. Register SIMC0 is used to control the enable/ disable function and to set the data transmission clock frequency. Although not connected with the SPI function, the SIMC0 register is also used to control the Peripheral Clock Prescaler. Register SIMC2 is used for other control functions such as LSB/MSB selection, write collision flag etc. SIMC0 Register Rev. 1.30 Bit 7 6 5 4 3 2 1 0 Name SIM2 SIM1 SIM0 PCKEN PCKP1 PCKP0 SIMEN — R/W R/W R/W R/W R/W R/W R/W R/W R POR 1 1 1 0 0 0 0 0 Bit 7~5 SIM2, SIM1, SIM0: SIM Operating Mode Control 000: SPI master mode; SPI clock is fSYS/4 001: SPI master mode; SPI clock is fSYS/16 010: SPI master mode; SPI clock is fSYS/64 011: SPI master mode; SPI clock is fL 100: SPI master mode; SPI clock is TM0 CCRP match frequency/2 101: SPI slave mode 110: I2C slave mode 111: Non SIM function These bits setup the overall operating mode of the SIM function. As well as selecting if the I2C or SPI function, they are used to control the SPI Master/Slave selection and the SPI Master clock frequency. The SPI clock is a function of the system clock but can also be chosen to be sourced from fL or TM0. If the SPI Slave Mode is selected then the clock will be supplied by an external Master device. Bit 4 PCKEN: PCK Output Pin Control 0: disable 1: enable Bit 3~2 PCKP1, PCKP0: Select PCK output pin frequency 00: fSYS 01: fSYS/4 10: fSYS/8 11: TM0 CCRP match frequency/2 123 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Bit 1 SIMEN: SIM Control 0: disable 1: enable The bit is the overall on/off control for the SIM interface. When the SIMEN bit is cleared to zero to disable the SIM interface, the SDI, SDO, SCK and SCS, or SDA and SCL lines will lose their SPI or I2C function and the SIM operating current will be reduced to a minimum value. When the bit is high the SIM interface is enabled. If the SIM is configured to operate as an SPI interface via the SIM2~SIM0 bits, the contents of the SPI control registers will remain at the previous settings when the SIMEN bit changes from low to high and should therefore be first initialised by the application program. If the SIM is configured to operate as an I2C interface via the SIM2~SIM0 bits and the SIMEN bit changes from low to high, the contents of the I2C control bits such as HTX and TXAK will remain at the previous settings and should therefore be first initialised by the application program while the relevant I2C flags such as HCF, HAAS, HBB, SRW and RXAK will be set to their default states. Bit 0 "—": unimplemented, read as "0" SIMC2 Register Bit Rev. 1.30 7 6 5 4 3 2 1 0 Name D7 D6 CKPOLB CKEG MLS CSEN WCOL TRF R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 Undefined bit This bit can be read or written by the application program. Bit 5 CKPOLB: Determines the base condition of the clock line 0: the SCK line will be high when the clock is inactive 1: the SCK line will be low when the clock is inactive The CKPOLB bit determines the base condition of the clock line, if the bit is high, then the SCK line will be low when the clock is inactive. When the CKPOLB bit is low, then the SCK line will be high when the clock is inactive. Bit 4 CKEG: Determines SPI SCK active clock edge type CKPOLB=0 0: SCK is high base level and data capture at SCK rising edge 1: SCK is high base level and data capture at SCK falling edge CKPOLB=1 0: SCK is low base level and data capture at SCK falling edge 1: SCK is low base level and data capture at SCK rising edge The CKEG and CKPOLB bits are used to setup the way that the clock signal outputs and inputs data on the SPI bus. These two bits must be configured before data transfer is executed otherwise an erroneous clock edge may be generated. The CKPOLB bit determines the base condition of the clock line, if the bit is high, then the SCK line will be low when the clock is inactive. When the CKPOLB bit is low, then the SCK line will be high when the clock is inactive. The CKEG bit determines active clock edge type which depends upon the condition of CKPOLB bit. Bit 3 MLS: SPI Data shift order 0: LSB 1: MSB This is the data shift select bit and is used to select how the data is transferred, either MSB or LSB first. Setting the bit high will select MSB first and low for LSB first. 124 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Bit 2 CSEN: SPI SCS pin Control 0: disable 1: enable The CSEN bit is used as an enable/disable for the SCS pin. If this bit is low, then the SCS pin will be disabled and placed into I/O pin or the other functions. If the bit is high the SCS pin will be enabled and used as a select pin. Bit 1 WCOL: SPI Write Collision flag 0: No collision 1: Collision The WCOL flag is used to detect if a data collision has occurred. If this bit is high it means that data has been attempted to be written to the SIMD register during a data transfer operation. This writing operation will be ignored if data is being transferred. The bit can be cleared by the application program. Note that using the WCOL bit can be disabled or enabled via the SIM_WCOL bit in the SBSC register. Bit 0 TRF: SPI Transmit/Receive Complete flag 0: Data is being transferred 1: SPI data transmission is completed The TRF bit is the Transmit/Receive Complete flag and is set "1" automatically when an SPI data transmission is completed, but must set to "0" by the application program. It can be used to generate an interrupt. SBSC Register Bit 7 6 5 4 Name R/W POR 3 SIM_WCOL — I2CDB1 I2CDB0 — R/W — R/W R/W — 0 — 0 0 — — Bit 7 SIM_WCOL: SIM WCOL control bit 0: disable 1: enable Bit 6 "—": unimplemented, read as "0" Bit 5~4 I2CDB1, I2CDB0 : I2C debounce selection bits Related to I2C function, described elsewhere Bit 3~1 "—": unimplemented, read as "0" Bit 0 SA_WCOL : SPIA WCOL function control Related to SPIA function, described elsewhere 2 1 0 — — SA_WCOL — — R/W — 0 SPI Communication After the SPI interface is enabled by setting the SIMEN bit high, then in the Master Mode, when data is written to the SIMD register, transmission/reception will begin simultaneously. When the data transfer is complete, the TRF flag will be set automatically, but must be cleared using the application program. In the Slave Mode, when the clock signal from the master has been received, any data in the SIMD register will be transmitted and any data on the SDI pin will be shifted into the SIMD register. The master should output an SCS signal to enable the slave device before a clock signal is provided. The slave data to be transferred should be well prepared at the appropriate moment relative to the SCS signal depending upon the configurations of the CKPOLB bit and CKEG bit. The accompanying timing diagram shows the relationship between the slave data and SCS signal for various configurations of the CKPOLB and CKEG bits. The SPI will continue to function even in the IDLE Mode. Rev. 1.30 125 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI SPI Master Mode Timing SPI Slave Mode Timing – CKEG=0 SPI Slave Mode Timing – CKEG=1 Rev. 1.30 126 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI SPI Transfer Control Flowchart SPI Bus Enable/Disable To enable the SPI bus, set CSEN= 1 and SCS= 0, then wait for data to be written into the SIMD (TXRX buffer) register. For the Master Mode, after data has been written to the SIMD (TXRX buffer) register, then transmission or reception will start automatically. When all the data has been transferred, the TRF bit should be set. For the Slave Mode, when clock pulses are received on SCK, data in the TXRX buffer will be shifted out or data on SDI will be shifted in.To disable the SPI bus, the SCK, SDI, SDO and SCS will become I/O pins or the other functions. Rev. 1.30 127 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI SPI Operation All communication is carried out using the 4-line interface for either Master or Slave Mode.The CSEN bit in the SIMC2 register controls the overall function of the SPI interface. Setting this bit high will enable the SPI interface by allowing the SCS line to be active, which can then be used to control the SPI interface. If the CSEN bit is low, the SPI interface will be disabled and the SCS line will be an I/O pin or the other functions and can therefore not be used for control of the SPI interface. If the CSEN bit and the SIMEN bit in the SIMC0 are set high, this will place the SDI line in a floating condition and the SDO line high. If in Master Mode the SCK line will be either high or low depending upon the clock polarity selection bit CKPOLB in the SIMC2 register. If in Slave Mode the SCK line will be in a floating condition. If the SIMEN bit is low, then the bus will be disabled and SCS, SDI, SDO and SCK will all become I/O pins or the other functions. In the Master Mode the Master will always generate the clock signal. The clock and data transmission will be initiated after data has been written into the SIMD register. In the Slave Mode, the clock signal will be received from an external master device for both data transmission and reception. The following sequences show the order to be followed for data transfer in both Master and Slave Mode: Master Mode • Step 1 Select the SPI Master mode and clock source using the SIM2~SIM0 bits in the SIMC0 control register • Step 2 Setup the CSEN bit and setup the MLS bit to choose if the data is MSB or LSB first, this setting must be the same with the Slave device. • Step 3 Setup the SIMEN bit in the SIMC0 control register to enable the SPI interface. • Step 4 For write operations: write the data to the SIMD register, which will actually place the data into the TXRX buffer. Then use the SCK and SCS lines to output the data. After this, go to step5. For read operations: the data transferred in on the SDI line will be stored in the TXRX buffer until all the data has been received at which point it will be latched into the SIMD register. • Step 5 Check the WCOL bit if set high then a collision error has occurred so return to step 4. If equal to zero then go to the following step. • Step 6 Check the TRF bit or wait for a SPI serial bus interrupt. • Step 7 Read data from the SIMD register. • Step 8 Clear TRF. • Step 9 Go to step 4. Rev. 1.30 128 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Slave Mode • Step 1 Select the SPI Slave mode using the SIM2~SIM0 bits in the SIMC0 control register • Step 2 Setup the CSEN bit and setup the MLS bit to choose if the data is MSB or LSB first, this setting must be the same with the Master device. • Step 3 Setup the SIMEN bit in the SIMC0 control register to enable the SPI interface. • Step 4 For write operations: write the data to the SIMD register, which will actually place the data into the TXRX buffer. Then wait for the master clock SCK and SCS signal. After this, go to step5. For read operations: the data transferred in on the SDI line will be stored in the TXRX buffer until all the data has been received at which point it will be latched into the SIMD register. • Step 5 Check the WCOL bit if set high then a collision error has occurred so return to step 4. If equal to zero then go to the following step. • Step 6 Check the TRF bit or wait for a SPI serial bus interrupt. • Step 7 Read data from the SIMD register. • Step 8 Clear TRF. • Step 9 Go to step 4. Error Detection The WCOL bit in the SIMC2 register is provided to indicate errors during data transfer. The bit is set by the SPI serial Interface but must be cleared by the application program. This bit indicates a data collision has occurred which happens if a write to the SIMD register takes place during a data transfer operation and will prevent the write operation from continuing. The overall function of the WCOL bit can be disabled or enabled by the SIM_WCOL bit in the SBSC register. . I2C Interface The I 2C interface is used to communicate with external peripheral devices such as sensors, EEPROM memory etc. Originally developed by Philips, it is a two line low speed serial interface for synchronous serial data transfer. The advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. I2C Master Slave Bus Connection Rev. 1.30 129 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI I2C Interface Operation The I2C serial interface is a two line interface, a serial data line, SDA, and serial clock line, SCL. As many devices may be connected together on the same bus, their outputs are both open drain types. For this reason it is necessary that external pull-high resistors are connected to these outputs. Note that no chip select line exists, as each device on the I2C bus is identified by a unique address which will be transmitted and received on the I2C bus. When two devices communicate with each other on the bidirectional I2C bus, one is known as the master device and one as the slave device. Both master and slave can transmit and receive data, however, it is the master device that has overall control of the bus. For these devices, which only operate in slave mode, there are two methods of transferring data on the I2C bus, the slave transmit mode and the slave receive mode. The debounce time of the I2C interface can be determined by the I2CDB1 and I2CDB0 bits in the SBSC register. This uses the internal clock to in effect add a debounce time to the external clock to reduce the possibility of glitches on the clock line causing erroneous operation. The debounce time, if selected, can be chosen to be either 1 or 2 system clocks. S T A R T s ig n a l fro m M a s te r S e n d s la v e a d d r e s s a n d R /W b it fr o m M a s te r A c k n o w le d g e fr o m s la v e S e n d d a ta b y te fro m M a s te r A c k n o w le d g e fr o m s la v e S T O P s ig n a l fro m M a s te r I2C Registers There are three control registers associated with the I2C bus, SIMC0, SIMC1 and SBSC, one address register SIMA and one data register, SIMD. The SIMD register, which is shown in the above SPI section, is used to store the data being transmitted and received on the I2C bus. Before the microcontroller writes data to the I2C bus, the actual data to be transmitted must be placed in the SIMD register. After the data is received from the I2C bus, the microcontroller can read it from the SIMD register. Any transmission or reception of data from the I2C bus must be made via the SIMD register. Note that the SIMA register also has the name SIMC2 which is used by the SPI function. Bit SIMEN and bits SIM2~SIM0 in register SIMC0 are used by the I2C interface. The I2CDB0 and I2CDB1 in the SBSC register are used to select the I2C debounce time. Rev. 1.30 130 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Bit Register Name 7 SIMC0 SIMC1 SIMD 6 5 4 3 2 1 0 SIM2 SIM1 SIM0 PCKEN PCKP1 PCKP0 SIMEN — HCF HAAS HBB HTX TXAK SRW IAMWU RXAK D7 D6 D5 D4 D3 D2 D1 D0 SIMA IICA6 IICA5 IICA4 IICA3 IICA2 IICA1 IICA0 D0 SBSC SIM_WCOL — I2CDB1 I2CDB0 — — — SA_WCOL I2C Registers List • SIMC0 Register Rev. 1.30 Bit 7 6 5 4 3 2 1 0 Name SIM2 SIM1 SIM0 PCKEN PCKP1 PCKP0 SIMEN — R/W R/W R/W R/W R/W R/W R/W R/W R POR 1 1 1 0 0 0 0 0 Bit 7~5 SIM2, SIM1, SIM0: SIM Operating Mode Control 000: SPI master mode; SPI clock is fSYS/4 001: SPI master mode; SPI clock is fSYS/16 010: SPI master mode; SPI clock is fSYS/64 011: SPI master mode; SPI clock is fL 100: SPI master mode; SPI clock is TM0 CCRP match frequency/2 101: SPI slave mode 110: I2C slave mode 111: Non SIM function These bits setup the overall operating mode of the SIM function. As well as selecting if the I2C or SPI function, they are used to control the SPI Master/Slave selection and the SPI Master clock frequency. The SPI clock is a function of the system clock but can also be chosen to be sourced from the fL or TM0. If the SPI Slave Mode is selected then the clock will be supplied by an external Master device. Bit 4 PCKEN: PCK Output Pin Control 0: disable 1: enable Bit 3~2 PCKP1, PCKP0: Select PCK output pin frequency 00: fSYS 01: fSYS/4 10: fSYS/8 11: TM0 CCRP match frequency/2 Bit 1 SIMEN: SIM Control 0: disable 1: enable The bit is the overall on/off control for the SIM interface. When the SIMEN bit is cleared to zero to disable the SIM interface, the SDI, SDO, SCK and SCS, or SDA and SCL lines will be in a floating condition and the SIM operating current will be reduced to a minimum value. When the bit is high the SIM interface is enabled. If the SIM is configured to operate as an SPI interface via SIM2~SIM0 bits, the contents of the SPI control registers will remain at the previous settings when the SIMEN bit changes from low to high and should therefore be first initialised by the application program. If the SIM is configured to operate as an I2C interface via the SIM2~SIM0 bits and the SIMEN bit changes from low to high, the contents of the I2C control bits such as HTXand TXAK will remain at the previous settings and should therefore be first initialised by the application program while the relevant I2C flags such as HCF, HAAS, HBB, SRW and RXAK will be set to their default states. Bit 0 "—": unimplemented, read as "0". 131 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI • SIMC1 Register Rev. 1.30 Bit 7 6 5 4 3 2 1 0 Name HCF HAAS HBB HTX TXAK SRW IAMWU RXAK R/W R R R R/W R/W R R/W R POR 1 0 0 0 0 0 0 1 Bit 7 HCF: I2C Bus data transfer completion flag 0: Data is being transferred 1: Completion of an 8-bit data transfer The HCF flag is the data transfer flag. This flag will be zero when data is being transferred. Upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated. Bit 6 HAAS: I2C Bus address match flag 0: Not address match 1: Address match The HASS flag is the address match flag. This flag is used to determine if the slave device address is the same as the master transmit address. If the addresses match then this bit will be high, if there is no match then the flag will be low. Bit 5 HBB: I2C Bus busy flag 0: I2C Bus is not busy 1: I2C Bus is busy The HBB flag is the I2C busy flag. This flag will be "1" when the I2C bus is busy which will occur when a START signal is detected. The flag will be set to "0" when the bus is free which will occur when a STOP signal is detected. Bit 4 HTX: Select I2C slave device is transmitter or receiver 0: Slave device is the receiver 1: Slave device is the transmitter Bit 3 TXAK: I2C Bus transmit acknowledge flag 0: Slave send acknowledge flag 1: Slave do not send acknowledge flag The TXAK bit is the transmit acknowledge flag. After the slave device receipt of 8-bits of data,this bit will be transmitted to the bus on the 9th clock from the slave device. The slave device must always set TXAK bit to "0" before further data is received. Bit 2 SRW: I2C Slave Read/Write flag 0: Slave device should be in receive mode 1: Slave device should be in transmit mode The SRW flag is the I 2C Slave Read/Write flag. This flag determines whether the master device wishes to transmit or receive data from the I2C bus. When the transmitted address and slave address is match, that is when the HAAS flag is set high, the slave device will check the SRW flag to determine whether it should be in transmit mode or receive mode. If the SRW flag is high, the master is requesting to read data from the bus, so the slave device should be in transmit mode. When the SRW flag is zero, the master will write data to the bus, therefore the slave device should be in receive mode to read this data. Bit 1 IAMWU: I2C Address Match Wake-up Control 0: disable 1: enable This bit should be set to "1" to enable I2C address match wake up from SLEEP or IDLE Mode. 132 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Bit 0 RXAK: I2C Bus Receive acknowledge flag 0: Slave receive acknowledge flag 1: Slave does not receive acknowledge flag The RXAK flag is the receiver acknowledge flag. When the RXAK flag is "0", it means that a acknowledge signal has been received at the 9th clock, after 8 bits of data have been transmitted. When the slave device in the transmit mode, the slave device checks the RXAK flag to determine if the master receiver wishes to receive the next byte. The slave transmitter will therefore continue sending out data until the RXAK flag is "1". When this occurs, the slave transmitter will release the SDA line to allow the master to send a STOP signal to release the I2C Bus. The SIMD register is used to store the data being transmitted and received. The same register is used by both the SPI and I2C functions. Before the device writes data to the SPI bus, the actual data to be transmitted must be placed in the SIMD register. After the data is received from the SPI bus, the device can read it from the SIMD register. Any transmission or reception of data from the SPI bus must be made via the SIMD register. • SIMD Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x "x" unknown • SIMA Register Bit 7 6 5 4 3 2 1 0 Name IICA6 IICA5 IICA4 IICA3 IICA2 IICA1 IICA0 — R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x 0 "x" unknown Bit 7~1 IICA6~ IICA0: I2C slave address IICA6~ IICA0 is the I2C slave address bit 6~bit 0. The SIMA register is also used by the SPI interface but has the name SIMC2. The SIMA register is the location where the 7-bit slave address of the slave device is stored. Bits 7~1 of the SIMA register define the device slave address. Bit 0 is not defined. When a master device, which is connected to the I2C bus, sends out an address, which matches the slave address in the SIMA register, the slave device will be selected. Note that the SIMA register is the same register address as SIMC2 which is used by the SPI interface. Bit 0 Undefined bit This bit can be read or written by user software program. • SBSC Register Rev. 1.30 Bit 7 6 5 4 3 2 1 0 Name SIM_WCOL — I2CDB1 I2CDB0 — — — SA_WCOL R/W R/W — R/W R/W — — — R/W POR 0 — 0 0 — — — 0 Bit 7 SIM_WCOL : SIM WCOL control bit Related to SPI, described elsewhere. Bit 6 "—": unimplemented, read as "0" 133 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI I2CDB1, I2CDB0: I2C debounce selection bits 00: No debounce (default) 01: 1 system clock debounce 10, 11: 2 system clocks debounce Bit 5~4 Bit 3~1 "—": unimplemented, read as "0" Bit 0 SA_WCOL : SPIA WCOL function control Related to SPIA, described elsewhere. I2C Block Diagram I2C Bus Communication Communication on the I2C bus requires four separate steps, a START signal, a slave device address transmission, a data transmission and finally a STOP signal. When a START signal is placed on the I2C bus, all devices on the bus will receive this signal and be notified of the imminent arrival of data on the bus. The first seven bits of the data will be the slave address with the first bit being the MSB. If the address of the slave device matches that of the transmitted address, the HAAS bit in the SIMC1 register will be set and an I2C interrupt will be generated. After entering the interrupt service routine, the slave device must first check the condition of the HAAS bit to determine whether the interrupt source originates from an address match or from the completion of an 8-bit data transfer. During a data transfer, note that after the 7-bit slave address has been transmitted, the following bit, which is the 8th bit, is the read/write bit whose value will be placed in the SRW bit. This bit will be checked by the slave device to determine whether to go into transmit or receive mode. Before any transfer of data to or from the I2C bus, the microcontroller must initialise the bus, the following are steps to achieve this: • Step 1 Set the SIM2~SIM0 and SIMEN bits in the SIMC0 register to "1" to enable the I2C bus. • Step 2 Write the slave address of the device to the I2C bus address register SIMA. • Step 3 Set the SIME interrupt enable bit of the interrupt control register to enable the SIM interrupt. Rev. 1.30 134 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI I2C Bus Initialisation Flow Chart I2C Bus Start Signal The START signal can only be generated by the master device connected to the I2C bus and not by the slave device. This START signal will be detected by all devices connected to the I2C bus. When detected, this indicates that the I2C bus is busy and therefore the HBB bit will be set. A START condition occurs when a high to low transition on the SDA line takes place when the SCL line remains high. I2C Bus Slave Address The transmission of a START signal by the master will be detected by all devices on the I2C bus. To determine which slave device the master wishes to communicate with, the address of the slave device will be sent out immediately following the START signal. All slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. If the address sent out by the master matches the internal address of the microcontroller slave device, then an internal I2C bus interrupt signal will be generated. The next bit following the address, which is the 8th bit, defines the read/write status and will be saved to the SRW bit of the SIMC1 register. The slave device will then transmit an acknowledge bit, which is a low level, as the 9th bit. The slave device will also set the status flag HAAS when the addresses match. As an I 2C bus interrupt can come from two sources, when the program enters the interrupt subroutine, the HAAS bit should be examined to see whether the interrupt source has come from a matching slave address or from the completion of a data byte transfer. When a slave address is matched, the device must be placed in either the transmit mode and then write data to the SIMD register, or in the receive mode where it must implement a dummy read from the SIMD register to release the SCL line. Rev. 1.30 135 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI I2C Bus Read/Write Signal The SRW bit in the SIMC1 register defines whether the slave device wishes to read data from the I2C bus or write data to the I2C bus. The slave device should examine this bit to determine if it is to be a transmitter or a receiver. If the SRW flag is "1" then this indicates that the master device wishes to read data from the I2C bus, therefore the slave device must be setup to send data to the I2C bus as a transmitter. If the SRW flag is "0" then this indicates that the master wishes to send data to the I2C bus, therefore the slave device must be setup to read data from the I2C bus as a receiver. I2C Bus Slave Address Acknowledge Signal After the master has transmitted a calling address, any slave device on the I 2C bus, whose own internal address matches the calling address, must generate an acknowledge signal. The acknowledge signal will inform the master that a slave device has accepted its calling address. If no acknowledge signal is received by the master then a STOP signal must be transmitted by the master to end the communication. When the HAAS flag is high, the addresses have matched and the slave device must check the SRW flag to determine if it is to be a transmitter or a receiver. If the SRW flag is high, the slave device should be setup to be a transmitter so the HTX bit in the SIMC1 register should be set to "1" . If the SRW flag is low, then the microcontroller slave device should be setup as a receiver and the HTX bit in the SIMC1 register should be set to "0" . I2C Bus Data and Acknowledge Signal The transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged receipt of its slave address. The order of serial bit transmission is the MSB first and the LSB last. After receipt of 8-bits of data, the receiver must transmit an acknowledge signal, level "0"., before it can receive the next data byte. If the slave transmitter does not receive an acknowledge bit signal from the master receiver, then the slave transmitter will release the SDA line to allow the master to send a STOP signal to release the I2C Bus. The corresponding data will be stored in the SIMD register. If setup as a transmitter, the slave device must first write the data to be transmitted into the SIMD register. If setup as a receiver, the slave device must read the transmitted data from the SIMD register. When the slave receiver receives the data byte, it must generate an acknowledge bit, known as TXAK, on the 9th clock. The slave device, which is setup as a transmitter will check the RXAK bit in the SIMC1 register to determine if it is to send another data byte, if not then it will release the SDA line and await the receipt of a STOP signal from the master. Rev. 1.30 136 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI I2C Communication Timing Diagram Note: *When a slave address is matched, the device must be placed in either the transmit mode and then write data to the SIMD register, or in the receive mode where it must implement a dummy read from the SIMD register to release the SCL line. I2C Bus ISR Flow Chart Rev. 1.30 137 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI I2C Time Out Function The I2C interface provides a time-out scheme to prevent a locked situation which might take place by an unexpected clock timing generated by a noise input signal. When the I2C interface has been locked for a period of time, the I2C hardware and the register, SIMC1, will be initialized automatically and the I2CTOF bit in the I2CTOC register will be set high. The Time Out function enable/disable and the time-out period are managed by the I2CTOC register. I2C Time Out Operation The time-out counter will start counting when the I2C interface received the START bit and address match. After that the counter will be cleared on each falling edge of the SCL pin. If the time counter is larger than the selected time-out time, then the anti-locked protection scheme will take place and the time-out counter will be stopped by hardware automatically, the I2CTOF bit will be set high and an I2C interrupt will also take place. Note that this scheme can also be stopped when the I2C received the STOP bit. There are several time-out periods can be selected by the I2CTOS0~I2CTOS5 bits in the I2CTOC register. • I2CTOC Register Bit 7 6 5 4 3 2 1 0 Name I2CTOEN I2CTOF R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 I2CTOS5 I2CTOS4 I2CTOS3 I2CTOS2 I2CTOS1 I2CTOS0 Bit 7 I2CTOEN: I C Time Out function control bit 0: disable 1: enable Bit 6 I2CTOF: I2C Time Out indication bit 0: Not occurred 1: Occurred Bit 5~0 I2CTOS5~I2CTOS0: I2C Time out time period select The I2C Time out clock is provided by the fL/32. The time out time period can be calculated from the accompanying equation. ([I2CTOS5:I2CTOS0]+1) x (32/fL) 2 Serial Interface – SPIA The devices contain an independent SPI function. It is important not to confuse this independent SPI function with the additional one contained within the combined SIM function, which is described in another section of this datasheet. This independent SPI function will carry the name SPIA to distinguish it from the other one in the SIM. The SPI interface is often used to communicate with external peripheral devices such as sensors, Flash or EEPROM memory devices etc. Originally developed by Motorola, the four line SPI interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices. The communication is full duplex and operates as a slave/master type, where the device can be either master or slave. Although the SPIA interface specification can control multiple slave devices from a single master, however this device is provided with only one SCSA pin. If the master needs to control multiple slave devices from a single master, the master can use I/O pins to select the slave devices. Rev. 1.30 138 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI SPIA Interface Operation The SPIA interface is a full duplex synchronous serial data link. It is a four line interface with pin names SDIA, SDOA, SCKA and SCSA. Pins SDIA and SDOA are the Serial Data Input and Serial Data Output lines, SCKA is the Serial Clock line and SCSA is the Slave Select line. As the SPIA interface pins are pin-shared with normal I/O pins, the SPIA interface must first be enabled by setting the correct bits in the SPIAC0 and SPIAC1 registers. the SPIA can be disabled or enabled using the SPIAEN bit in the SPIAC0 register. Communication between devices connected to the SPIA interface is carried out in a slave/master mode with all data transfer initiations being implemented by the master. The Master also controls the clock signal. As the device only contains a single SCSA pin only one slave device can be utilized. The SCSA pin is controlled by the application program, set the SACSEN bit to "1" to enable the SCSA pin function and clear the SACSEN bit to "0" to place the SCSA pin into a floating state. SPIA Master/Slave Connection SPIA Block Diagram The SPIA function in this device offers the following features: • Full duplex synchronous data transfer • Both Master and Slave modes • LSB first or MSB first data transmission modes • Transmission complete flag • Rising or falling active clock edge • SAWCOL bit enabled or disable select The status of the SPIA interface pins is determined by a number of factors such as whether the device is in the master or slave mode and upon the condition of certain control bits such as SACSEN and SPIAEN. Rev. 1.30 139 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI SPIA Registers There are four internal registers which control the overall operation of the SPIA interface. These are the SPIAD data register and three registers SPIAC0, SPIAC1 and SBSC. The SA_WCOL bit in the SBSC register is used to control the SPIA WCOL function. Bit Register Name 7 6 SPIAC0 SASPI2 SASPI1 SPIAC1 — — SPIAD D7 D6 D5 D4 D3 D2 D1 D0 SBSC SIM_WCOL — I2CDB1 I2CDB0 — — — SA_WCOL 5 4 3 2 1 0 SASPI0 — — — SPIAEN SACKPOL SACKEG SAMLS SACSEN SAWCOL — SATRF SPIA Registers List The SPIAD register is used to store the data being transmitted and received. Before the device writes data to the SPIA bus, the actual data to be transmitted must be placed in the SPIAD register. After the data is received from the SPIA bus, the device can read it from the SPIAD register. Any transmission or reception of data from the SPIA bus must be made via the SPIAD register. SPIAD Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x "x" unknown There are also three control registers for the SPIA interface, SPIAC0, SPIAC1 and SBSC. Register SPIAC0 is used to control the enable/disable function and to set the data transmission clock frequency. Register SPIAC1 is used for other control functions such as LSB/MSB selection, write collision flag etc. SPIAC0 Register Rev. 1.30 Bit 7 6 5 4 3 2 1 0 Name SASPI2 SASPI1 SASPI0 — — — SPIAEN — R/W R/W R/W R/W — — — R/W — POR 1 1 1 0 0 0 0 0 Bit 7~5 SASPI2 ~ SASPI0: Master/Slave Clock Select 000 : SPIA master, fSYS/4 001 : SPIA master, fSYS/16 010 : SPIA master, fSYS/64 011 : SPIA master, fL 100 : SPIA master, TM0 CCRP match frequency/2 101 : SPIA slave 110: unimplemented 111: unimplemented These bits are used to control the SPIA Master/Slave selection and the SPIA Master clock frequency. The SPIA clock is a function of the system clock but can also be chosen to be sourced from TM0. If the SPIA Slave Mode is selected then the clock will be supplied by an external Master device Bit 4~2 "—": unimplemented, read as "0" 140 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Bit 1 SPIAEN: SPIA enable or disable 0: disable 1: enable The bit is the overall on/off control for the SIMA interface. When the SPIAEN bit is cleared to zero to disable the SPIA interface, the SDIA, SDOA, SCKA and SCSA lines will lose their SPI function and the SPIA operating current will be reduced to a minimum value. When the bit is high the SPIA interface is enabled. Bit 0 "—": unimplemented, read as "0" SPIAC1 Register Rev. 1.30 Bit 7 6 Name — — 5 4 R/W — — R/W R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 SACKPOL SACKEG 3 SAMLS 2 1 SACSEN SAWCOL 0 SATRF Bit 7~6 "—": unimplemented, read as "0". This bit can be read or written by user software program. Bit 5 SACKPOL: Determines the base condition of the clock line 0: SCKA line will be high when the clock is inactive 1: SCKA line will be low when the clock is inactive The SACKPOL bit determines the base condition of the clock line, if the bit is high, then the SCKA line will be low when the clock is inactive. When the SACKPOL bit is low, then the SCKA line will be high when the clock is inactive. Bit 4 SACKEG: Determines the SPIA SCKA active clock edge type SACKPOL= 0: 0: SCKA has high base level with data capture on SCKA rising edge 1: SCKA has high base level with data capture on SCKA falling edge SACKPOL= 1: 0: SCKA has low base level with data capture on SCKA falling edge 1: SCKA has low base level with data capture on SCKA rising edge The SACKEG and SACKPOL bits are used to setup the way that the clock signal outputs and inputs data on the SPI bus. These two bits must be configured before a data transfer is executed otherwise an erroneous clock edge may be generated. The SACKPOL bit determines the base condition of the clock line, if the bit is high, then the SCKA line will be low when the clock is inactive. When the SACKPOL bit is low, then the SCKA line will be high when the clock is inactive. The SACKEG bit determines active clock edge type which depends upon the condition of the SACKPOL bit. Bit 3 SAMLS: MSB/LSB First Bit 0: LSB shift first 1: MSB shift first This is the data shift select bit and is used to select how the data is transferred, either MSB or LSB first. Setting the bit high will select MSB first and low for LSB first. Bit 2 SACSEN: Select Signal Enable/Disable Bit 0: disable, other functions 1: Enable The SACSEN bit is used as an enable/disable for the SCSA pin. If this bit is low, then the SCSA pin will be disabled and placed into other functions. If the bit is high the SCSA pin will be enabled and used as a select pin. 141 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI Bit 1 SAWCOL: Write Collision Bit 0: Collision free 1: Collision detected The SAWCOL flag is used to detect if a data collision has occurred. If this bit is high it means that data has been attempted to be written to the SPIAD register during a data transfer operation. This writing operation will be ignored if data is being transferred. The bit can be cleared by the application program. Note that this function can be disabled or enabled via the SA_WCOL bit in the SBSC register. Bit 0 SATRF: Transmit/Receive Flag 0: Not complete 1: Transmission/reception complete The SATRF bit is the Transmit/Receive Complete flag and is set "1" automatically when an SPIA data transmission is completed, but must set to zero by the application program. It can be used to generate an interrupt. SBSC Register Bit 7 6 5 4 Name R/W POR 3 SIM_WCOL — I2CDB1 I2CDB0 — R/W — R/W R/W — 0 — 0 0 — — Bit 7 SIM_WCOL: SIM WCOL control bit Related to SPI, described elsewhere. Bit 6 "—": unimplemented, read as "0" Bit 5~4 I2CDB1, I2CDB0 : I2C debounce selection bits Related to I2C, described elsewhere. Bit 3~1 "—": unimplemented, read as "0" Bit 0 SA_WCOL: SPIA WCOL function control 0: disable 1: enable. 2 1 0 — — SA_WCOL — — R/W — 0 SPIA Communication After the SPIA interface is enabled by setting the SPIAEN bit high, then in the Master Mode, when data is written to the SPIAD register, transmission/reception will begin simultaneously. When the data transfer is complete, the SATRF flag will be set automatically, but must be cleared using the application program. In the Slave Mode, when the clock signal from the master has been received, any data in the SPIAD register will be transmitted and any data on the SDIA pin will be shifted into the SPIAD register. The master should output an SCSA signal to enable the slave device before a clock signal is provided. The slave data to be transferred should be well prepared at the appropriate moment relative to the SCSA signal depending upon the configurations of the SACKPOL bit and SACKEG bit. The accompanying timing diagram shows the relationship between the slave data and SCS signal for various configurations of the SACKPOL and SACKEG bits. The SPIA will continue to function even in the IDLE Mode. Rev. 1.30 142 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI SPIA Master Mode Timing SPIA Slave Mode Timing – SACKEG= 0 SPIA Slave Mode Timing – SACKEG= 1 Rev. 1.30 143 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI SPIA Transfer Control Flowchart SPIA Bus Enable/Disable To enable the SPIA bus, set SACSEN= 1 and SCSA=0, then wait for data to be written into the SPIAD (TXRX buffer) register. For the Master Mode, after data has been written to the SPIAD (TXRX buffer) register, then transmission or reception will start automatically. When all the data has been transferred the SATRF bit should be set. For the Slave Mode, when clock pulses are received on SCKA, data in the TXRX buffer will be shifted out or data on SDIA will be shifted in. To disable the SPIA bus SCKA, SDIA, SDOA, SCSA will become I/O pins or the other functions. Rev. 1.30 144 December 11, 2013 HT68FB540/HT68FB550/HT68FB560 I/O Flash USB 8-Bit MCU with SPI SPIA Operation All communication is carried out using the 4-line interface for either Master or Slave Mode. The SACSEN bit in the SPIAC1 register controls the overall function of the SPIA interface. Setting this bit high will enable the SPIA interface by allowing the SCSA line to be active, which can then be used to control the SPIA interface. If the SACSEN bit is low, the SPIA interface will be disabled and the SCSA line will be an I/O pin or the other functions and can therefore not be used for control of the SPIA interface. If the SACSEN bit and the SPIAEN bit in the SPIAC0 register are set high, this will place the SDIA line in a floating condition and the SDOA line high. If in Master Mode the SCKA line will be either high or low depending upon the clock polarity selection bit SACKPOLB in the SPIAC1 register. If in Slave Mode the SCKA line will be in a floating condition. If SPIAEN is low then the bus will be disabled and SCSA, SDIA, SDOA and SCKA will all become I/O pins or the other functions. In the Master Mode the Master will always generate the clock signal. The clock and data transmission will be initiated after data has been written into the SPIAD register. In the Slave Mode, the clock signal will be received from an external master device for both data transmission and reception. The following sequences show the order to be followed for data transfer in both Master and Slave Mode: Master Mode • Step 1 Select the clock source and Master mode using the SASPI2~SASPI0 bits in the SPIAC0 control register • Step 2 Setup the SACSEN bit and setup the SAMLS bit to choose if the data is MSB or LSB first, this must be same as the Slave device. • Step 3 Setup the SPIAEN bit in the SPIAC0 control register to enabl