Data Sheet

HT46R12A
A/D Type 8-Bit OTP MCU
Technical Document
· Tools Information
· FAQs
· Application Note
- HA0004E HT48 & HT46 MCU UART Software Implementation Method
- HA0005E Controlling the I^2C bus with the HT48 & HT46 MCU Series
- HA0011E HT48 & HT46 Keyboard Scan Program
- HA0013E HT48 & HT46 LCM Interface Design
- HA0075E MCU Reset and Oscillator Circuits Application Note
- HA0101E Using the HT46R12A in an Induction Cooker
Features
· Operating voltage:
· Power-down and wake-up functions for reduced
fSYS= 4MHz: 2.2V~5.5V
fSYS= 8MHz: 3.3V~5.5V
power consumption
· Up to 0.5ms instruction cycle with 8MHz system
· 17 bidirectional I/O lines
clock at VDD= 5V
· Two 8-bit programmable timer/event counters with
· 8-level subroutine nesting
overflow interrupt and 7-stage prescaler
· 4 channel 9-bit resolution A/D converter
· Single 8-bit programmable pulse generator - PPG -
· Two comparators with interrupt function
output channel with prescaler and 8-bit programmable timer counter, supporting both active low or
active high output
· Bit manipulation instruction
· 14-bit table read instruction
· 63 powerful instructions
· Integrated crystal and RC oscillator
· Instructions executed in one or two machine cycles
· Watchdog Timer
· Low voltage reset function
· 2048´14 program memory
· 24-pin SKDIP/SOP package types available
· 88´8 data memory RAM
· PFD for audio generation
General Description
The HT46R12A is an 8-bit, high performance, RISC architecture microcontroller devices specifically designed
for A/D applications that interface directly to analog signals, such as those from sensors.
satility to meet the requirements of wide range of A/D
application possibilities such as external analog sensor
signal processing.
With the inclusion of two comparators and a fully integrated programmable pulse generator, the device is particularly suitable for use in products such as induction
cookers and other home appliance application areas.
The advantages of low power consumption, I/O flexibility, programmable frequency divider, timer functions,
oscillator options, multi-channel A/D Converter, HALT
and wake-up functions, provide the device with the ver-
Rev. 1.01
1
December 29, 2008
HT46R12A
Block Diagram
In te rru p t
C ir c u it
T M R 0 C
T M R 0
P F D 0
IN T C
T M R 1 C
T M R 1
P F D 1
S ta c k
P ro g ra m
R O M
P ro g ra m
C o u n te r
M
M
M
M P
U
X
P P G 0 C
P P G T 0
P P G
P C
S T A T U S
A L U
Y S
T M R 0
X
fS
X
fS
Y S
Y S
/4
/4
W D T O S C
fS
P r e s c a le r
P o rt C
P C C
S h ifte r
T im in g
G e n e ra to r
X
fS
D a ta
M e m o ry
M U X
In s tr u c tio n
D e c o d e r
U
P r e s c a le r
T M R 1
U
M
W D T
In s tr u c tio n
R e g is te r
U
P C
P C
P C
P C
P C
0 /C
1 /C
2 /C
3 /C
4 /C
0 V
0 V
0 O
1 O
1 V
Y S
IN
IN
U
U
IN
T
T
+
-
4 -C h a n n e l
A /D C o n v e rte r
O S C 2
O S
R E
V D
V S
S
S
C 1
P B
A C C
H A L T
D
E N /D IS
P o rt B
P B C
L V R
P A
P P G 0 C
P P G
P P G
P o rt A
P A C
P B 0 /A N 0 ~ P B 3 /A N 3
P A
P A
P A
P A
P A
0 ~ P
3 /P
4 /T
5 , P
7 /T
A 2
F D
M R 0
A 6
M R 1
Pin Assignment
P B 1 /A N 1
1
2 4
P B 2 /A N 2
P B 0 /A N 0
2
2 3
P B 3 /A N 3
P A 3 /P F D
3
2 2
P A 4 /T M R 0
P A 2
4
2 1
P A 5
P A 1
5
2 0
P A 6
P A 0
6
1 9
P A 7 /T M R 1
C 1 V IN +
7
1 8
O S C 2
P C 4 /C 1 V IN 8
1 7
O S C 1
P C 3 /C 1 O U T
9
1 6
V D D
P C 2 /C 0 O U T
1 0
1 5
R E S
V S S
1 1
1 4
P P G
P C 1 /C 0 V IN +
1 2
1 3
P C 0 /C 0 V IN -
H T 4 6 R 1 2 A
2 4 S K D IP -A /S O P -A
Rev. 1.01
2
December 29, 2008
HT46R12A
Pin Description
Pin Name
PA0~PA2
PA3/PFD
PA4/TMR0
PA5, PA6
PA7/TMR1
PB0/AN0
PB1/AN1
PB2/AN2
PB3/AN3
I/O
Options
Description
I/O
Pull-high
Wake-up
PA3 or PFD
Bidirectional 8-bit input/output port. Each pin can be configured as a wake-up
input by configuration option. Software instructions determine if the pin is a
CMOS output or Schmitt trigger input. Configuration options determine which pins
on the port have pull-high resistors. Pins PA3, PA4 and PA7 are pin-shared with
PFD, TMR0 and TMR1 respectively.
Pull-high
Bidirectional 4-bit input/output port. Software instructions determine if the pin is
a CMOS output or Schmitt trigger input. Configuration options determine which
pins on the port have pull-high resistors. PB is shared with the A/D input pins. The
A/D inputs are selected via software instructions. Once selected as an A/D input,
the I/O function and pull-high resistor functions are disabled automatically.
I/O
PC0/C0VINPC1/C0VIN+
PC2/C0OUT
PC3/C1OUT
PC4/C1VINC1VIN+
I/O
Pull-high
I/O or
Comparator
Bi-directional 5-bit input/output port. Software instructions determine if the pin
is a CMOS output or Schmitt trigger input. A configuration option determines if all
pins on the the port have pull-high resistors. C0VIN-, C0VIN+ and C0OUT are
pin-shared with PC0, PC1 and PC2. Once the comparator 0 is enabled, the internal PC2 port control register can be used as input only, the PC2 output function
and the PC0/PC1/PC2 pull-high resistors will be disabled automatically, however
PC0 and PC1 maintain their I/O function. Software instructions determine if the
Comparator 0 function is enabled or not.
C1VIN+ and C1VIN- are the Comparator 1 inputs, C1OUT and C1VIN- are
pin-shared with PC3 and PC4. Once the Comparator 1 function is enabled, the internal PC3 port control register can be used as input only, the PC3 output function
and the PC3/PC4 pull-high resistors will be disabled automatically, however PC4
maintains its I/O function. Software instructions determine if the Comparator 1
function is enabled or not.
The PC1/C0VIN+ pin is also the external interrupt input pin. A falling edge on this
pin will form an interrupt trigger source whether the pin is setup as a Comparator
input or I/O pin.
PPG
O
¾
Programmable pulse generator output pin, the pin is floating when the power is
first applied. The PPG0 output level can be selected to be either active low or
active high, selected via configuration option.
OSC1
OSC2
I
O
Crystal
or RC
OSC1, OSC2 are connected to an RC network or a Crystal (determined by option) for the internal system clock. If the RC system clock option is selected, pin
OSC2 can be used to monitor the system clock at 1/4 frequency.
RES
I
¾
Schmitt trigger reset input. Active low.
VDD
¾
¾
Positive power supply
VSS
¾
¾
Negative power supply, ground.
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V
Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V
IOL Total ..............................................................150mA
Total Power Dissipation .....................................500mW
Operating Temperature...........................-40°C to 85°C
IOH Total............................................................-100mA
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev. 1.01
3
December 29, 2008
HT46R12A
D.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
VDD
IDD2
Typ.
Max.
Unit
¾
fSYS=4MHz
2.2
¾
5.5
V
¾
fSYS=8MHz
3.3
¾
5.5
V
Operating Current
(Crystal OSC)
3V
No load, fSYS=4MHz
ADC off
¾
0.6
1.5
mA
¾
2
4
mA
Operating Current
(RC OSC)
3V
¾
0.8
1.5
mA
¾
2.5
4
mA
¾
4
8
mA
¾
¾
5
mA
¾
¾
10
mA
¾
¾
1
mA
¾
¾
2
mA
Operating Voltage
IDD1
Min.
Conditions
VDD
5V
5V
No load, fSYS=4MHz
ADC off
IDD3
Operating Current
(Crystal OSC, RC OSC)
ISTB1
Standby Current
(WDT Enabled)
3V
Standby Current
(WDT Disabled)
3V
VIL1
Input Low Voltage for I/O Ports,
TMR0 and TMR1
¾
¾
0
¾
0.3VDD
V
VIH1
Input High Voltage for I/O Ports,
TMR0 and TMR1
¾
¾
0.7VDD
¾
VDD
V
VIL2
Input Low Voltage (RES)
¾
¾
0
¾
0.4VDD
V
VIH2
Input High Voltage (RES)
¾
¾
0.9VDD
¾
VDD
V
VLVR
Low Voltage Reset
¾
¾
2.7
3
3.3
V
IOL
3V
VOL=0.1VDD
4
8
¾
mA
I/O Port & PPG Pin Sink Current
5V
VOL=0.1VDD
10
20
¾
mA
3V
VOH=0.9VDD
-2
-4
¾
mA
5V
VOH=0.9VDD
-5
-10
¾
mA
3V
¾
20
60
100
kW
5V
¾
10
30
50
kW
ISTB2
IOH
5V
No load, system HALT
5V
No load, system HALT
5V
I/O Port & PPG Pin Source Current
RPH
No load, fSYS=8MHz
ADC off
Pull-high Resistance
VAD
A/D Input Voltage
¾
¾
0
¾
VDD
V
EAD
A/D Conversion Error
¾
¾
¾
±0.5
±1
LSB
IADC
Additional Power Consumption
if A/D Converter is Used
3V
¾
0.5
1
mA
¾
1.5
3
mA
Note:
¾
5V
If the comparator input voltage is not equal to VDD or VSS, there may be more IDD/ISTB current consumed by the
pin-shared logic input function whether the comparator is enabled or disabled.
Typically, the current for each comparator input pin is about 500mA (VDD=5V) if its input voltage is 2.5V.
Rev. 1.01
4
December 29, 2008
HT46R12A
A.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
fSYS
System Clock
Timer I/P Frequency
(TMR0/TMR1)
fTIMER
tWDTOSC
Min.
Typ.
Max.
Unit
Conditions
VDD
¾
2.2V~5.5V
400
¾
4000
kHz
¾
3.3V~5.5V
400
¾
8000
kHz
¾
2.2V~5.5V
0
¾
4000
kHz
¾
3.3V~5.5V
0
¾
8000
kHz
3V
¾
45
90
180
ms
5V
¾
32
65
130
ms
Watchdog Oscillator Period
tRES
External Reset Low Pulse Width
¾
¾
1
¾
¾
ms
tSST
System Start-up Timer Period
¾
Power-up or Wake-up
from HALT
¾
1024
¾
*tSYS
tINT
Interrupt Pulse Width
¾
¾
1
¾
¾
ms
tAD
A/D Clock Period
¾
¾
1
¾
¾
ms
tADC
A/D Conversion Time
¾
¾
¾
76
¾
tAD
tADCS
A/D Sampling Time
¾
¾
¾
32
¾
tAD
Note: *tSYS=1/fSYS
Comparator Electrical Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
¾
2.2
¾
5.5
V
5V
¾
¾
¾
200
mA
Comparator Input Offset Voltage
5V
¾
-10
¾
10
mV
VOPOS2
Comparator Input Offset Voltage
5V
-2
¾
2
mV
VCM
Comparator Common Mode
Voltage Range
¾
VSS
¾
VDD1.4V
V
tPD
Comparator Response Time
¾
¾
¾
2
ms
VDD
Conditions
Comparator Operating Voltage
¾
Comparator Operating Current
VOPOS1
Note:
By calibraton
¾
With 10mV overdrive
If the comparator input voltage is not equal to VDD or VSS, there may be more IDD/ISTB current consumed by the
pin-shared logic input function whether the comparator is enabled or disabled.
Typically, the current for each comparator input pin is about 500mA (VDD=5V) if its input voltage is 2.5V.
Rev. 1.01
5
December 29, 2008
HT46R12A
Functional Description
Execution Flow
cremented by 1. The program counter then points to the
memory word containing the next instruction code.
The system clock for the microcontroller is derived from
either a crystal or an RC oscillator. The system clock is
internally divided into four non-overlapping clocks. One
instruction cycle consists of four system clock cycles.
When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset, internal interrupt, external interrupt or return from
subroutine, the PC manages the program transfer by
loading the address corresponding to each instruction.
Instruction fetching and execution are pipelined in such
a way that a fetch takes an instruction cycle while decoding and execution takes the next instruction cycle.
However, the pipelining scheme allows each instruction
to be effectively executed in a cycle. If an instruction
changes the program counter, two cycles are required to
complete the instruction.
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get the proper instruction.
Otherwise proceed with the next instruction.
The lower byte of the program counter (PCL) is a readable and writeable register (06H). Moving data into the
PCL performs a short jump. The destination will be
within 256 locations.
Program Counter - PC
The program counter (PC) controls the sequence in
which the instructions stored in the program ROM are
executed and its contents specify a full range of program memory.
When a control transfer takes place, an additional
dummy cycle is required.
After accessing a program memory word to fetch an instruction code, the contents of the program counter are in-
S y s te m
C lo c k
O S C 2 (R C
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
o n ly )
P C
P C
P C + 1
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
P C + 2
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Mode
Program Counter
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial Reset
0
0
0
0
0
0
0
0
0
0
0
Comparator 0 Interrupt
0
0
0
0
0
0
0
0
1
0
0
Comparator 1 Interrupt
0
0
0
0
0
0
0
1
0
0
0
External interrupt (from PC1)
0
0
0
0
0
0
0
1
1
0
0
Timer/Event Counter 0 Overflow
0
0
0
0
0
0
1
0
0
0
0
Timer/Event Counter 1 Overflow
0
0
0
0
0
0
1
0
1
0
0
A/D Converter Interrupt
0
0
0
0
0
0
1
1
0
0
0
Loading PCL
*10
*9
*8
@7
@6
@5
@4
@3
@2
@1
@0
Jump, Call Branch
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from Subroutine
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Skip
Program Counter+2
Program Counter
Note:
*10~*0: Program counter bits
#10~#0: Instruction code bits
Rev. 1.01
S10~S0: Stack register bits
@[email protected]: PCL bits
6
December 29, 2008
HT46R12A
Program Memory - ROM
receives a falling edge, and if the interrupt is enabled,
and the stack is not full, the program will jump to this
location and begin execution.
The program memory is used to store the executable
program instructions. It also contains data, table, interrupt entries, and is organized into 2048´14 bits, addressed by the program counter and table pointer.
· Location 010H
Location 010H is reserved for the Timer/Event Counter 0 interrupt service program. If a timer interrupt results from a Timer/Event Counter 0 overflow, and if the
interrupt is enabled and the stack is not full, the program will jump to this location and begin execution.
Certain locations in the program memory are reserved
for special usage:
· Location 000H
Location 000H is reserved for program initialization.
After a chip reset, the program will jump to this location and begin execution.
· Location 014H
Location 014H is reserved for the Timer/Event Counter 1 interrupt service program. If a timer interrupt results from a Timer/Event Counter 1 overflow, and if the
interrupt is enabled and the stack is not full, the program will jump to this location and begin execution.
· Location 004H
Location 004H is reserved for the Comparator 0 interrupt service program. If the Comparator 0 output pin is
activated, and if the interrupt is enabled and the stack
is not full, the program will jump to this location and
begin execution.
· Location 018H
Location 018H is reserved for the A/D converter interrupt service program. If an A/D converter interrupt results from an end of A/D conversion, and if the
interrupt is enabled and the stack is not full, the program will jump to this location and begin execution.
· Location 008H
Location 008H is reserved for the Comparator 1 interrupt service program. If the Comparator 1 output pin is
activated, and if the interrupt is enabled and the stack
is not full, the program will jump to this location and
begin execution.
· Table location
Any location in the ROM space can be used as a
look-up table. The instructions ²TABRDC [m]² (the
current page, 1 page=256 words) and ²TABRDL [m]²
(the last page) transfer the contents of the lower-order
byte to the specified data memory, and the higher-order byte to TBLH (08H). Only the destination of the
lower-order byte in the table is well-defined, the other
bits of the table word are transferred to the lower portion of TBLH, and the remaining 2 bits are read as ²0².
The Table Higher-order byte register (TBLH) is read
only. The table pointer (TBLP) is a read/write register
(07H), which indicates the table location. Before accessing the table, the location must be placed in
TBLP. The TBLH is read only and cannot be restored.
If the main routine and the Interrupt Service Routine
both employ the table read instruction, the contents of
the TBLH in the main routine are likely to be changed
by the table read instruction used in the Interrupt Service Routine and errors may occur. Therefore, using
the table read instruction in the main routine and simultaneously in the Interrupt Service Routine should
be avoided. However, if the table read instruction has
to be applied in both the main routine and the interrupt
Service Routine, the interrupt should be disabled prior
to the table read instruction. It should not be re-enabled until the TBLH has been backed up. All table related instructions require two cycles to complete the
· Location 00CH
Location 00CH is reserved for the external interrupt,
which is the PC1 pin, service program. If the PC1 pin
0 0 0 H
D e v ic e In itia liz a tio n P r o g r a m
0 0 4 H
C o m p a r a to r 0 In te r r u p t S u b r o u tin e
0 0 8 H
C o m p a r a to r 1 In te r r u p t S u b r o u tin e
0 0 C H
0 1 0 H
0 1 4 H
E x te rn a l In te rru p t (fro m
P C 1 )
T im e r /E v e n t C o u n te r 0 In te r r u p t S u b r o u tin e
T im e r /E v e n t C o u n te r 1 In te r r u p t S u b r o u tin e
0 1 8 H
A /D
n 0 0 H
C o n v e r te r In te r r u p t S u b r o u tin e
P ro g ra m
M e m o ry
L o o k - u p T a b le ( 2 5 6 w o r d s )
n F F H
7 0 0 H
L o o k - u p T a b le ( 2 5 6 w o r d s )
7 F F H
1 4 b its
Program Memory
Instruction
Table Location
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P10
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note:
*10~*0: Table location bits
@[email protected]: Table pointer bits
Rev. 1.01
P10~P8: Current program counter bits
7
December 29, 2008
HT46R12A
operation. These areas may function as normal program memory depending upon requirements.
0 0 H
Stack Register - STACK
In d ir e c t A d d r e s s in g R e g is te r 0
0 1 H
M P 0
0 2 H
In d ir e c t A d d r e s s in g R e g is te r 1
0 3 H
M P 1
0 4 H
This is a special part of the memory which is used to
save the contents of the program counter only. The
stack is organized into 8 levels and is neither part of the
data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the
stack pointer, SP, and is neither readable nor writeable.
At a subroutine call or interrupt acknowledge signal, the
contents of the program counter are pushed onto the
stack. At the end of a subroutine or an interrupt routine,
indicated by a return instruction, RET or RETI, the program counter is restored to its previous value from the
stack. After a chip reset, the SP will point to the top of the
stack.
0 5 H
A C C
0 6 H
P C L
0 7 H
T B L P
0 8 H
T B L H
0 9 H
0 A H
S T A T U S
0 B H
IN T C 0
0 C H
0 D H
T M R 0
0 E H
T M R 0 C
0 F H
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledge signal will be inhibited. When the stack
pointer is decremented, using RET or RETI, the interrupt will be serviced. This feature prevents a stack overflow allowing the programmer to use the structure more
easily. In a similar case, if the stack is full and a ²CALL²
is subsequently executed, a stack overflow will occur
and the first entry will be lost as only the most recent 8
return addresses are stored.
1 0 H
T M R 1
1 1 H
T M R 1 C
1 2 H
P A
1 3 H
P A C
1 4 H
P B
1 5 H
P B C
1 6 H
P C
1 7 H
P C C
1 8 H
1 9 H
1 A H
1 B H
Data Memory - RAM
1 C H
C M P 0 C
1 D H
C O M 1 C
1 E H
IN T C 1
The data memory has a capacity of 115´8 bits, and is divided into two functional groups, namely the special
function registers and the general purpose data memory (88´8 bits), most of which are readable/writeable,
although some are read only.
1 F H
2 4 H
A D R L
The unused space before address 28H is reserved for
future expansion usage and reading these locations will
obtain a result of ²00H². The general purpose data
memory, addressed from 28H to 7FH is used for data
and control information under instruction commands.
2 5 H
A D R H
2 6 H
A D C R
2 7 H
A C S R
2 0 H
P P G 0 C
2 1 H
P P G T 0
2 2 H
2 3 H
2 8 H
All of the data memory areas can handle arithmetic,
logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the
data memory can be set and reset by ²SET [m].i² and
²CLR [m].i². They are also indirectly accessible through
the memory pointer registers, MP0 and MP1.
Rev. 1.01
S p e c ia l P u r p o s e
D a ta M e m o ry
7 F H
G e n e ra l P u rp o s e
D a ta M e m o ry
(8 8 B y te s )
: U n u s e d
R e a d a s "0 0 "
RAM Mapping
8
December 29, 2008
HT46R12A
Indirect Addressing Register
Status Register - STATUS
Location 00H and 02H are indirect addressing registers
that are not physically implemented. Any read/write operation on [00H] and [02H] accesses the Data Memory
pointed to by the MP0 and MP1 registers respectively.
Reading locations 00H or 02H indirectly returns the result 00H. Writing to it indirectly leads to no operation.
The function of data movement between two indirect addressing registers is not supported.
This 8-bit register contains the 0 flag (Z), carry flag (C),
auxiliary carry flag (AC), overflow flag (OV), power down
flag (PDF), and watchdog time-out flag (TO). It also records the status information and controls the operation
sequence.
The memory pointer registers, MP0 and MP1, are 7-bit
registers. Bit 7 of MP0 and MP1 are undefined and if
read will return the result ²1². Any write operation to
MP0 and MP1 will only transfer the lower 7 bits of
data to MP0 and MP1.
With the exception of the TO and PDF flags, bits in
the status register can be altered by instructions like
most other registers. Any data written into the status
register will not change the TO or PDF flag. In addition operations related to the status register may give
different results from those intended. The TO flag
can be affected only by system power-up, a WDT
time-out or executing the ²CLR WDT² or ²HALT² instruction. The PDF flag can be affected only by executing the ²HALT² or ²CLR WDT² instruction or a
system power-up.
Accumulator
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
The memory pointer registers, MP0 and MP1, are both
7-bit registers used to access the RAM by combining the
corresponding indirect addressing registers.
The accumulator is closely related to ALU operations. It
is also mapped to location 05H of the data memory and
can carry out immediate data operations. The data
movement between two data memory locations must
pass through the accumulator.
In addition, on entering the interrupt sequence or executing the subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status are important and if the subroutine can corrupt the status register, precautions must be taken to
save it properly.
Arithmetic and Logic Unit - ALU
Interrupt
This circuit performs 8-bit arithmetic and logic operations.
The ALU provides the following functions:
The device provides two internal timer/event counter 0/1
interrupts, two comparator interrupt, and an A/D converter interrupt. The interrupt control register 0, INTC0,
and interrupt control register 1, INTC1, contains the interrupt control bits to enable or disable the interrupt and
to record the interrupt request flags.
· Arithmetic operations - ADD, ADC, SUB, SBC, DAA
· Logic operations - AND, OR, XOR, CPL
· Rotation - RL, RR, RLC, RRC
· Increment and Decrement - INC, DEC
· Branch decision - SZ, SNZ, SIZ, SDZ
Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the EMI bit will be automatically cleared. This scheme may prevent any further
The ALU not only saves the results of data operations but
also changes the status register.
Bit No.
Label
Function
0
C
C is set if an operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation, otherwise C is cleared. C is also affected by a
rotate through carry instruction.
1
AC
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow
from the high nibble into the low nibble in subtraction, otherwise AC is cleared.
2
Z
3
OV
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa, otherwise OV is cleared.
4
PDF
PDF is cleared by a system power-up or executing the ²CLR WDT² instruction. PDF is set
by executing the ²HALT² instruction.
5
TO
TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction.
TO is set by a WDT time-out.
6, 7
¾
Unused bit, read as ²0²
Z is set if the result of an arithmetic or logic operation is 0; otherwise Z is cleared.
Status (0AH) Register
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December 29, 2008
HT46R12A
The Comparator 1 output interrupt is initialised by setting the Comparator 1 output Interrupt request flag
(C1F; bit 5 of the INTC0), which is caused by a falling
edge transition from the Comparator 1 output. After the
interrupt is enabled, and the stack is not full, and the
C1F bit is set, a subroutine call to location 08H occurs.
The related interrupt request flag, C1F, is reset, and the
EMI bit is cleared to disable further maskable interrupts.
interrupt nesting. Other interrupt requests may happen
during this interval but only the interrupt request flag is
recorded. If a certain interrupt requires servicing within
the service routine, the EMI bit and the corresponding bit
of INTC0 and INTC1 may be set to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until
the stack pointer is decremented. If immediate service is
desired, the stack must be prevented from becoming full.
The external interrupt is triggered by a failing edge on
PC1 and the related request flag, EIF, is also set. After
the interrupt is enabled, the stack is not full, and the external interrupt is active, a subroutine call occurs. The
interrupt request flag, EIF, is reset and the EMI bit is
cleared to disable further interrupts.
All these kind of interrupts have a wake-up capability. As
an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack, followed by
a branch to a subroutine at specified location in the program memory. Only the program counter is pushed onto
the stack. If the contents of the register or status register
are altered by the interrupt service program which corrupts the desired control sequence, the contents should
be saved in advance.
The internal Timer/Event Counter 0 interrupt is initialised
by setting the Timer/Event Counter 0 interrupt request
flag (T0F; bit 4 of the INTC1), caused by a timer overflow.
When the interrupt is enabled, the stack is not full and the
T0F bit is set, a subroutine call to location 010H will occur.
The related interrupt request flag, T0F, will be reset and
the EMI bit cleared to disable further interrupts.
The Comparator 0 output interrupt is initialised by setting the Comparator 0 output interrupt request flag (C0F;
bit 4 of INTC0), which is caused by a falling edge transition from the Comparator 0 output. After the interrupt is
enabled, and the stack is not full, and the C0F bit is set,
a subroutine call to location 04H occurs. The related interrupt request flag, C0F, is reset, and the EMI bit is
cleared to disable further maskable interrupts.
The internal Timer/Event Counter 1 is operated in the
same manner. The Timer/Event Counter 1 related interrupt request flag is T1F (bit 5 of the INTC1) and its subroutine call location is 014H. The related interrupt
request flag, T1F, will be reset and the EMI bit cleared to
disable further interrupts.
Bit No.
Label
Function
0
EMI
Controls the master (global) interrupt (1=enable; 0=disable)
1
EC0I
Controls the Comparator 0 interrupt (1=enable; 0=disable)
2
EC1I
Controls the Comparator 1 interrupt (1=enable; 0=disable)
3
EEI
Control external interrupt (1=enabled, 0=disabled)
4
C0F
Comparator 0 request flag (1=active; 0=inactive)
5
C1F
Comparator 1 request flag (1=active; 0=inactive)
6
EIF
External interrupt flag (1=active, 0=inactive)
7
¾
Unused bit, read as ²0²
INTC0 (0BH) Register
Bit No.
Label
Function
0
ET0I
Controls the Timer/Event Counter 0 interrupt (1=enable; 0=disable)
1
ET1I
Controls the Timer/Event Counter 1 interrupt (1=enable; 0=disable)
2
EADI
Controls the A/D converter interrupt (1=enable; 0=disable)
3
¾
4
T0F
Internal Timer/Event Counter 0 request flag (1=active; 0=inactive)
Unused bit, read as ²0²
5
T1F
Internal Timer/Event Counter 1 request flag (1=active; 0=inactive)
6
ADF
A/D converter request flag (1=active; 0=inactive)
7
¾
Unused bit, read as ²0²
INTC1 (1EH) Register
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December 29, 2008
HT46R12A
There are two types of system oscillator circuits within the
microcontroller. These are an RC oscillator and a Crystal oscillator, the choice of which is determined via a
configuration option.
The A/D converter interrupt is initialised by setting the
A/D converter request flag (ADF; bit 6 of the INTC1),
caused by an end of A/D conversion. When the interrupt
is enabled, the stack is not full and the ADF is set, a subroutine call to location 018H will occur. The related interrupt request flag, ADF, will be reset and the EMI bit
cleared to disable further interrupts.
If an RC oscillator is used, an external resistor between
OSC1 and VSS is required and whose resistance
should range from 24kW to 1MW. Pin OSC2 can be
used to monitor the system frequency at 1/4 the system
frequency or can be used to synchronize external circuitry. The RC oscillator provides the most cost effective means of oscillator implementation, however, the
frequency of oscillation may vary with VDD, temperature and process variations. It is, therefore, not recommended for use in timing sensitive applications where
an accurate oscillator frequency is desired.
During the execution of an interrupt subroutine, other interrupt acknowledgements are held until the ²RETI² instruction is executed or the EMI bit and the related
interrupt control bit are set to 1, if the stack is not full. To
return from the interrupt subroutine, a RET or RETI
instruction may be executed. The RETI instruction will set
the EMI bit to re-enable an interrupt service, but the RET
will not.
If a Crystal oscillator is used, a crystal connected between OSC1 and OSC2 is required. No other external
components are required. Instead of a crystal, a resonator can also be connected between OSC1 and OSC2 to
obtain a frequency reference, but two external capacitors connected between OSC1, OSC2 and ground are
required, if the oscillating frequency is less than 1MHz.
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
Interrupt Source
Priority Vector
Comparator 0 output interrupt
1
004H
Comparator 1 output interrupt
2
008H
External Interrupt - from PC1
3
00CH
Timer/Event Counter 0 overflow
4
010H
Timer/Event Counter 1 overflow
5
014H
A/D converter completed overflow
6
018H
When the system enters the Power-down mode the system oscillator is stopped to conserve power.
The WDT oscillator is a free running on-chip RC oscillator,
and no external components are required. Even if the system enters the power down mode where the system clock
is stopped, the WDT oscillator will continue to operate with
a period of approximately 65ms at 5V. The WDT oscillator
can be disabled using a configuration option to conserve
power.
The EMI, EC0I, EC1I, EEI, ET0I, ET1I, and EADI bits
are all used to control the enable/disable status of the interrupts. These bits prevent the requested interrupt from
being serviced. Once the interrupt request flags, C0F,
C1F, EIF, T0F, T1F, ADF are set, they remain in the
INTC1 or INTC0 register until the interrupts are serviced
or cleared by a software instruction. It is recommended
that a program does not use the ²CALL subroutine² within
the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in
some applications. If only one stack is left and enabling
the interrupt is not well controlled, the original control sequence will be damaged if the ²CALL² operates within the
interrupt subroutine.
Watchdog Timer - WDT
The WDT clock source is implemented using a dedicated internal RC oscillator (WDT oscillator) or by the instruction clock, which is the system clock divided by 4.
The choice of which one is used is determined by a
configuration option. This timer is designed to prevent a
software malfunction or a sequence jumping to an unknown location with unpredictable results. The
Watchdog Timer can be disabled by a configuration option. If the Watchdog Timer is disabled, all instructions
relating to the WDT result in no operation.
The WDT clock source will be subsequently divided by
either 213, 214 , 215 or 216, determined by a configuration
option, to get the actual WDT time-out period. Using the
internal WDT clock source, the minimum WDT time-out
period is about 600ms. This time-out period may vary
with temperature, VDD and process variations. By selecting appropriate WDT options, longer time-out periods can be implemented. If the WDT time-out is
selected to be fS/216, then a maximum time-out period of
about 4.7s can be achieved.
Oscillator Configuration
V
D D
O S C 1
O S C 1
O S C 2
C r y s ta l O s c illa to r
fS Y S /4
N M O S O p e n D r a in
O S C 2
R C
O s c illa to r
System Oscillator
Rev. 1.01
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December 29, 2008
HT46R12A
S y s te m
C lo c k /4
W D T
O S C
M a s k
o p tio n
s e le c t
fs
fs/2
D iv id e r
8
W D T P r e s c a le r
M a s k O p tio n
W D T C le a r
T im e - o u t R e s e t
fs/2 1 6
fs/2 1 5
fs/2 1 4
fs/2 1 3
Watchdog Timer
If the WDT oscillator is disabled, the WDT clock may still
be sourced from the instruction clock and operate in the
same manner except that in the Power-down mode the
WDT will stop counting and lose its protecting purpose.
In this situation the device can only be restarted by external logic. If the device operates in a noisy environment, using the internal WDT oscillator is strongly
recommended, since the Power-down mode will stop
the system clock.
The system can leave the Power-down mode by means
of an external reset, an interrupt, an external falling
edge signal on port A or a WDT overflow. An external reset causes a device initialisation and the WDT overflow
performs a ²warm reset². After the TO and PDF flags
are examined, the reason for the device reset can be determined.
The PDF flag is cleared by a system power-up or executing the ²CLR WDT² instruction and is set when executing the ²HALT² instruction. The TO flag is set if a
WDT time-out occurs, and causes a wake-up that only
resets the program counter and the stack pointer, the
other circuits will maintain their original status.
The WDT overflow under normal operation will initialise a
device reset and set the status bit TO. In the Power-down
mode, the overflow will initialise a warm reset where only
the program counter and stack pointer are reset to 0. To
clear the WDT contents, three methods are adopted; external reset (a low level to RES), software instructions, or a
HALT instruction. The software instructions include CLR
WDT and the other set - CLR WDT1 and CLR WDT2. Of
these two types of instruction, only one can be active depending on the options - ²CLR WDT times selection option². If the ²CLR WDT² is selected (i.e. CLRWDT times
equal 1), any execution of the CLR WDT instruction will
clear the WDT. If the ²CLR WDT1² and ²CLR WDT2² option is selected (i.e. CLRWDT times equal two), these two
instructions must be executed to clear the WDT, otherwise, the WDT will reset the chip due to a time-out.
A port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit in
port A can be independently selected to wake up the device, setup via configuration options. Awakening from
an I/O port stimulus, the program will resume execution
at the next instruction. If it is awakening from an interrupt, two sequences may occur. If the related interrupt is
disabled or the interrupt is enabled but the stack is full,
the program will resume execution at the next instruction. If the interrupt is enabled and the stack is not full,
the regular interrupt response takes place. If an interrupt
request flag is set to ²1² before entering the
Power-down mode, the wake-up function of the related
interrupt will be disabled. Once a wake-up event occurs,
it takes 1024 system clock periods to resume normal operation. In other words, a dummy period will be inserted
after the wake-up. If the wake-up results from an interrupt acknowledge, the actual interrupt subroutine execution will be delayed by one or more cycles. If the
wake-up results in the next instruction execution, this
will be executed immediately after the dummy period is
finished.
Power Down Operation - HALT
The Power-down mode is entered by the execution of a
²HALT² instruction and results in the following:
· The system oscillator will be turned off but the WDT
oscillator will keep running, if the WDT is enabled and
if its clock is sourced from the internal WDT oscillator.
· The contents of the Data Memory and registers re-
main unchanged.
· The WDT will be cleared and will start counting again,
if the WDT clock is sourced from the internal WDT oscillator.
To minimise power consumption, all the I/O pins should
be carefully managed before entering the Power-down
mode.
· All of the I/O ports maintain their original status.
· The PDF flag is set and the TO flag is cleared.
Rev. 1.01
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December 29, 2008
HT46R12A
Reset
The functional unit chip reset status are shown below.
There are three ways in which a reset can occur:
· RES pin reset during normal operation
· RES pin reset during Power-down
· WDT time-out reset during normal operation
The WDT time-out during a Power-down is different
from other device reset conditions, since it can perform
a ²warm reset² that resets only the program counter and
the SP, leaving the other circuits in their original state.
Some registers remain unchanged during other reset
conditions. Most registers are reset to the ²initial condition² when the reset conditions are met. By examining
the PDF and TO flags, the program can distinguish between different ²chip resets².
TO
PDF
0
0
Program Counter
000H
Interrupt
Disable
Prescaler, Divider
Cleared
WDT
Clear. After master reset,
WDT begins counting
Timer/Event Counter
Off
PPG Timer
Off
PPG output
Floating
Input/Output Ports
Input mode
Stack Pointer
Points to the top of the stack
V
RESET Conditions
V
D D
0 .0 1 m F
RES reset during power-up
u
u
RES reset during normal operation
0
1
RES wake-up HALT
1
u
WDT time-out during normal operation
1
1
WDT wake-up HALT
D D
1 0 0 k W
1 0 0 k W
R E S
R E S
0 .1 m F
1 0 k W
B a s ic
R e s e t
C ir c u it
Note: ²u² means unchanged
H i-n o is e
R e s e t
C ir c u it
0 .1 m F
Reset Circuit
To guarantee that the system oscillator is started and
stabilised, the SST (System Start-up Timer) provides an
extra delay of 1024 system clock pulses when the system reset (power-up, WDT time-out or RES reset) or the
system awakes from the Power-down state.
Note: Most applications can use the Basic Reset Circuit
as shown, however for applications with extensive noise,
it is recommended to use the Hi-noise Reset Circuit.
When a system reset occurs, the SST delay is added
during the reset period. Any wake-up from a
Power-down will enable the SST delay.
H A L T
An extra option load time delay is added during a system
reset (power-up, WDT time-out at normal mode or RES
reset).
W a rm
W D T
R E S
C o ld
R e s e t
V D D
R E S
tS
O S C 1
S T
S S T T im e - o u t
C h ip
S S T
1 0 - b it R ip p le
C o u n te r
S y s te m
R e s e t
R e s e t
Reset Configuration
Reset Timing Chart
Rev. 1.01
R e s e t
13
December 29, 2008
HT46R12A
The registers states are summarised in the following table.
Register
Reset
(Power On)
WDT Time-out
RES Reset
(Normal Operation) (Normal Operation)
RES Reset
(HALT)
WDT Time-out
(HALT)*
MP0
1xxx xxxx
1uuu uuuu
1uuu uuuu
1uuu uuuu
1uuu uuuu
MP1
1xxx xxxx
1uuu uuuu
1uuu uuuu
1uuu uuuu
1uuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
000H
000H
000H
000H
000H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--01 uuuu
--11 uuuu
INTC0
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
TMR0
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR0C
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
TMR1
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR1C
00-0 1---
00-0 1---
00-0 1---
00-0 1---
uu-u u---
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
---- 1111
---- 1111
---- 1111
---- 1111
---- uuuu
Program
Counter
TBLP
PB
PBC
---- 1111
---- 1111
---- 1111
---- 1111
---- uuuu
PC
---1 1111
---1 1111
---1 1111
---1 1111
---u uuuu
PCC
---1 1111
---1 1111
---1 1111
---1 1111
---u uuuu
INTC1
-000 -000
-000 -000
-000 -000
-000 -000
-uuu -uuu
PPG0C
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
PPGT0
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
CMP0C
-000 1000
-000 1000
-000 1000
-000 1000
-uuu uuuu
CMP1C
-000 1000
-000 1000
-000 1000
-000 1000
-uuu uuuu
ADRL
x--- ----
x--- ----
x--- ----
x--- ----
u--- ----
ADRH
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
ADCR
0100 0000
0100 0000
0100 0000
0100 0000
uuuu uuuu
ACSR
---- --00
---- --00
---- --00
---- --00
---- --uu
Note:
²*² stands for warm reset
²u² stands for unchanged
²x² stands for unknown
Rev. 1.01
14
December 29, 2008
HT46R12A
Timer/Event Counter
measured result remains in the timer/event counter
even if the activated transient occurs again, as only a
single 1-cycle measurement is made. Not until the
T0ON/T1ON bit is once again set can further measurements be made. In this operational mode, the
timer/event counter begins counting not according to
the logic level but according to the transient edges. In
the case of a counter overflow, the counter is reloaded
from the timer/event counter register and issues an interrupt request, as in the other two modes, i.e.the event
and timer modes.
Two timer/event counters are implemented in the
microcontroller. Timer/Event Counter 0 contains an 8-bit
programmable count-up counter whose clock may be
sourced from an external source or an internal clock
source. The internal clock source comes from fSYS.
Timer/Event Counter 1 contains an 8-bit programmable
count-up counter whose clock may come from an external source or an internal clock source. The internal clock
source comes from fSYS/4. The external clock input allows external events to be counted, time intervals or
pulse widths to be measure.
To enable the counting operation, the Timer ON bit,
namely the T0ON bit of TMR0C or the T1ON of TMR1C,
should be set to 1. In the pulse width measurement
mode, the T0ON/T1ON is automatically cleared after
the measurement cycle is completed. But in the other
two modes, the T0ON/T1ON can only be reset by instructions. The overflow of the Timer/Event Counters is
one of the wake-up sources. The Timer/Event Counters
can also be use to drive a PFD (Programmable Frequency Divider) output on pin PA3, selected via configuration options. Only one PFD, (PFD0 or PFD1) can be
used with PA3 selected via configuration options. No
matter what the operation mode is, writing a 0 to ET0I or
ET1I disables the related interrupt service. When the
PFD function is selected, executing a ²SET [PA].3² instruction will enable the PFD output while executing a
²CLR [PA].3² instruction will disable the PFD output.
Using the internal system clock, the timer/event counter
is has only one reference time base. If the timer clock
source is sourced externally then timer intervals can be
measured time intervals or pulse widths measured.
Using the internal clock allows the user to generate an
accurate time base.
There are two registers associated with Timer/Event
Counter 0, TMR0 and TMR0C (0EH) and two registers
for Timer/Event Counter 1, TMR1 and TMR1C. Writing
values into the TMR0 or TMR1 registers places a start
value into the respective Timer/Event Counter 0/1
preload register while reading TMR0 or TMR1 retrieves
the contents of the respective Timer/Event Counter. The
TMR0C and TMR1C registers are the Timer/Event
Counter control registers, which define the operating
mode, the counting enable or disable and define the active edge.
In the case of timer/event counter OFF condition, writing
data to the timer/event counter preload register also reloads that data to the timer/event counter. However if
the timer/event counter is already on, any data written to
the timer/event counter is kept only in the timer/event
counter preload register. The timer/event counter will
continue normal operation until an overflow occurs.
The T0M0/T1M0 and T0M1/T1M1 bits in the control registers define the operation mode. The event count mode
is used to count external events, which means that the
clock source will be sourced from the timer external
pins, TMR0 and TMR1. The timer mode functions as a
normal timer with the clock source coming from the internally selected clock source. The pulse width measurement mode can be used to measure the duration of
a high or low level signal on either TMR0 or TMR1,
whose time reference is based on the internally selected
clock source.
When the timer/event counter is read, the clock is
blocked to avoid errors, and as this may results in a
counting error, his should be taken into account by the
programmer.
It is strongly recommended to load a desired value into
the TMR0/TMR1 registers first, before turning on the related timer/event counter, as the initial power on value of
the TMR0/TMR1 registers are unknown. Due to the
timer/event structure, the programmer should pay special attention when using instructions to enable then disable the timer for the first time, whenever there is a need
to use the timer/event function, to avoid unpredictable
results. After this procedure, the timer/event function
can be operated normally.
In the event count or timer mode, the timer/event counter starts counting from the current contents in the
timer/event counter register and ends at FFH. Once an
overflow occurs, the counter is reloaded from the
timer/event counter preload register, and generates an
interrupt request flag, which is the T0F bit in the INTC0
register or the T1F bit in the INTC1 register.
In the pulse width measurement mode with the values of
the T0ON/T1ON and T0E/T1E bits equal to ²1², after the
respective Timer/Event counter has received a transient
from low to high, or high to low dependent upon the
value of the T0E/T1E bit, it will start counting until the respective logic level on the TMR0 or TMR1 pin returns to
its original level and resets the T0ON/T1ON bit. The
Rev. 1.01
Bit0~bit2 of TMR0C can be used to define the pre-scaling
stages for the internal clock sources for the timer/event
counter. The overflow signal of the timer/event counter
are used to generate the PFD signals.
15
December 29, 2008
HT46R12A
fS
8 - s ta g e P r e s c a le r
Y S
f IN
8 -1 M U X
T
D a ta b u s
T 0 P S C 2 ~ T 0 P S C 0
(1 /1 ~ 1 /1 2 8 )
T 0 M 1
T 0 M 0
T M R 0
8 - b it T im e r /E v e n t C o u n te r
P r e lo a d R e g is te r
R e lo a d
T 0 E
T 0 M 1
T 0 M 0
T 0 O N
8 - b it T im e r /E v e n t
C o u n te r (T M R 0 )
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
O v e r flo w
T o In te rru p t
P F D 0
Timer/Event Counter 0
fS
Y S
D a ta b u s
/4
T 1 M 1
T 1 M 0
T M R 1
8 - b it T im e r /E v e n t C o u n te r
P r e lo a d R e g is te r
R e lo a d
T 1 E
8 - b it T im e r /E v e n t
C o u n te r (T M R 1 )
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
T 1 M 1
T 1 M 0
T 1 O N
O v e r flo w
T o In te rru p t
P F D 1
Timer/Event Counter 1
P F D 0
P F D 1
M
U
T
X
Q
P F D
P A 3 D a ta C T R L
P F D S o u r c e O p tio n
PFD Source Option
Bit No.
0
1
2
Label
T0PSC0
T0PSC1
T0PSC2
3
T0E
4
T0ON
5
¾
6
7
T0M0
T0M1
Function
Define the prescaler stages, T0PSC2, T0PSC1, T0PSC0=
000: fINT=fSYS
001: fINT=fSYS/2
010: fINT=fSYS/4
011: fINT=fSYS/8
100: fINT=fSYS/16
101: fINT=fSYS/32
110: fINT=fSYS/64
111: fINT=fSYS/128
Defines the TMR0 active edge of the timer/event counter:
In Event Counter Mode (T0M1,T0M0)=(0,1):
1:count on falling edge;
0:count on rising edge
In Pulse Width measurement mode (T0M1,T0M0)=(1,1):
1: start counting on the rising edge, stop on the falling edge;
0: start counting on the falling edge, stop on the rising edge
Enable/disable the timer counting
(0=disable; 1=enable)
Unused bit, read as ²0²
Define the operating mode (T0M1, T0M0)
01 = Event count mode (External clock)
10 = Timer mode (Internal clock)
11 = Pulse Width measurement mode (External clock)
00 = Unused
TMR0C (0EH) Register
Rev. 1.01
16
December 29, 2008
HT46R12A
Bit No.
Label
0~2
¾
Function
Unused bit, read as ²0²
Defines the TMR1 active edge of the timer/event counter:
In Event Counter Mode (T1M1,T1M0)=(0,1):
1:count on falling edge;
0:count on rising edge
In Pulse Width measurement mode (T1M1,T1M0)=(1,1):
1: start counting on the rising edge, stop on the falling edge;
0: start counting on the falling edge, stop on the rising edge
3
T1E
4
T1ON
5
¾
6
7
T1M0
T1M1
Enable/disable timer counting (0= disable; 1= enable)
Unused bit, read as ²0²
Define the operating mode (T1M1, T1M0)
01= Event count mode (External clock)
10= Timer mode (Internal clock)
11= Pulse Width measurement mode (External clock)
00= Unused
TMR1C (11H) Register
Programmable Pulse Generator - PPG
and an 8-bit preload data register. The programmable
pulse generator starts counting from the current contents in the preload register and ends at ²FFH®
00H². Once an overflow occurs, the counter is reloaded from the PPG0 timer counter preload register,
and generates a signal to stop the PPG timer. The
software trigger bit, P0ST, will be cleared when a PPG
timer overflow occurs.
There are two registers related to the PPG0 output
function, a control register, PPG0C, and a timer
preload register, PPGT0. The control register,
PPG0C, defines the PPG0 input control mode trigger
source, the enable or disable of the comparators, defines the PPG0 timer prescaler rate which have value
of fSYS/1, fSYS/2, fSYS/4, fSYS/8, fSYS/16, fSYS/32, fSYS/64,
fSYS/128, enable or disable stopping the PPG0 timer
using the C0VO triggered input, enable or disable the
restarting of the PPG0 timer using the C1VO triggered
input, and control the PPG0 software trigger bit to trigger the PPG0 timer On or Off. The PPGT0 register is
the PPG0 preload register, whose contents determine
the output pulse width.
This HT46R12A device contains a single 8-bit PPG output channel. The PPG has a programmable period of
256´T, where ²T² can be 1/fSYS, 2/fSYS, 4/fSYS, 8/fSYS,
16/fSYS, 32/fSYS, 64/fSYS, 128/fSYS for an output pulse
width.
The PPG detects the falling edge of a trigger input, and
then outputs a single pulse. The falling edge trigger may
be sourced from either comparators or from a software
trigger bit, which can be selected by software. The PPG
is capable of generating pulse widths ranging from
0.25ms to 8.192ms for a system frequency of 4MHz. An
active low or active high output can be selected for the
PPG via a configuration option. Writing ²00H² to the
PPGT0 register yields a pulse width of 256´T output.
· PPG0 functional description
The PPG0 module consists of PPG0 timers, a PPG
Mode Control, and two comparators. The PPG0 timer
consists of a prescaler, one 8-bit up-counter timer,
· PPG0C control register
Bit No.
PPG0C (20H)
POR value
7
6
5
4
3
2
1
0
P0ST
P0RSEN
P0SPEN
P0PSC2
P0PSC1
P0PSC0
CMP1EN
CMP0EN
0
0
0
0
0
0
0
0
CMP0EN: Enables or disables Comparator 0 (0: disable, 1: enable)
CMP1EN: Enables or disables Comparator 1 (0: disable, 1: enable)
P0PSC2, P0PSC1, P0PSC0: These three bits select the PPG0 timer prescaler rate.
P0SPEN: Enables or disables the stopping of the PPG0 timer using the C0VO trigger input (0: disable, 1: enable)
P0RSEN: Enables or disables the restarting of the PPG0 timer using the C1VO trigger input. (0: disable, 1: enable)
P0ST: PPG0 software trigger bit. (0: Stop PPG0, 1: Restart PPG0)
Rev. 1.01
17
December 29, 2008
HT46R12A
P 0 S T
+
C 1 IN T
C 0 IN T
P C 1 /C 0 V IN +
D a ta b u s
C 0 V O
P C 0 /C 0 V IN -
P r e lo a d R e g is te r
P C 2 /C 0 O U T
P P G M o d e
C o n tro l
C 1 V IN +
+
O v e r flo w
P P G 0 T im e r
C 1 V O
P P G 0 T im e r O ff
C le a r
P r e s c a le r
P C 3 /C 1 O U T
P 0 L E V ( O p tio n )
P P G 0 O u tp u t
P P G
P 0 fs
U
fP
P r e s c a le r
C M P 1 E N
M
Y S
C M P 0 E N
fS
P P G 0 T im e r O n /O ff
-
C 1 V IN -
R e lo a d
P 0 P S C 2
P 0 P S C 1
P 0 P S C 0
P G
X
R is in g o r F a llg in g S e le c tio n
T r ig g e r E d g e C o n tr o l
P P G
S ta rt
P P G
A c tiv e ( S y n c M o d e )
S ta r t S Y N C O p tio n
PPG0 Block Diagram
The CMP0EN and CMP1EN bits are used as the comparator enable or disable bits.
¨ CMP0EN= ²0² (comparator is disabled) ® PC0/C0VIN-, PC1/C0VIN+, PC2/C0OUT are all GPIO pins
¨ CMP1EN= ²0² (comparator is disabled) ® PC3/C1OUT, PC4/C1VIN+ are all GPIO.
¨ CMP0EN= ²1² (comparator is enabled) ® PC2 will be automatically set to be an input only, the PC2 output function
and the PC0/PC1/PC2 pull-high resistors are disabled automatically but PC0/PC1 will maintain their I/O function.
Software instructions determine if Comparator 0 is enabled or not.
¨ CMP1EN= ²1² (comparator is enabled) ® PC3 will be automatically set to be an input only, the PC3 output function
and the PC3/PC4 pull-high resistors will be disabled automatically but PC4 will maintain its I/O function. Software
instructions determine if Comparator 1 is enabled or not.
Any action causing PPG to stop such as a PPG timer overflow, a SW stop (P0ST=1 ® 0) - will cause the following actions to occur:
¨ Stop and clear the PPG prescaler (prescaler means prescaling counter, not P0PSC[2:0] in PPG0C)
¨ The PPG timer will be reloaded
¨ P0ST will cleared
¨ PPGO will be inactive
For a start delay £ 0.5 ´ (1/fSYS), when the start SYNC with clock is selected, the PPG pulse output will be trgiggered
by either the rising or falling edge of the next clock(fsys) edge. After the PPG starts, the PPG output becomes active
and its prescaler begins to count as soon as first transition (falling or raising) of the system clock arrives. After the first
trigger has completed, the following clock edge trigger type is decided by the first one. For example, once the PPG
starts and if the next arriving clock transition is a falling edge, the PPG will be triggered by a falling edge until the PPG
stops and vice versa.
Rev. 1.01
18
December 29, 2008
HT46R12A
EX1: Since the first trigger type is a falling edge after the PPG starts, the PPG timer is triggered by a falling edge until
the PPG stops.
tS Y S
S y s te m
C lo c k
S ta r t T r ig g e r
P P G
P u ls e
< 0 .5 tS
P P G
Y S
n
T im e r
n + 1
n + 2
EX2: Since the first trigger type is a raising edge after the PPG starts, the PPG timer is triggered by a raising edge until the PPG stops.
tS
S y s te m
Y S
C lo c k
S ta r t T r ig g e r
P P G
P u ls e
< 0 .5 tS
P P G
T im e r
Y S
n
n + 1
n + 2
PPG0C: CMP1EN, CMP0EN comparator enable/disable bits
CMP0EN
Description
0
Disable the Comparator 0. PC0/C0VIN-, PC1/C0VIN+, PC2/C0OUT are all I/O pins.
1
Enable the Comparator 0. The PC0/C0VIN-, PC1/C0VIN+ are Comparator 0 input pins, PC2/C0OUT
is a Comparator 0 output pin, PC2 output disabled, PC2 Pull-high resistor disabled.
CMP1EN
Description
0
Disable the Comparator 1. PC3/C1OUT is a PGIO pin.
1
Enable the Comparator 1. The PC3/C1OUT is a Comparator 1 output pin, PC3 output disable, PC3
Pull-high resistor disabled.
Bits2~4 of the PPG0 control register, PPG0C, can be used to define the pre-scaling stages of the PPG0 timer counter
clock.
PPG0C: PPG0 timer prescaler rate bits
P0PSC2
P0PSC1
P0PSC0
0
0
0
P0fS=fSYS
0
0
1
P0fS=fSYS/2
0
1
0
P0fS=fSYS/4
0
1
1
P0fS=fSYS/8
1
0
0
P0fS=fSYS/16
1
0
1
P0fS=fSYS/32
1
1
0
P0fS=fSYS/64
1
1
1
P0fS=fSYS/128
Rev. 1.01
Prescaler Stage Definition
19
December 29, 2008
HT46R12A
P0SPEN is the PPG0 timer OFF enable or disable bit using the C0VO trigger input, if this bit is enabled, the PPG0
stop input can be triggered by C0VO or a PC2 falling edge. P0RSEN is the PPG0 restart enable or disable bit using
the C1VO trigger input. If this bit is enabled, the PPG0 timer restart input can be trigger by C1VO or a PC3 falling
edge.The status of C0VO or C1VO can be read by setting PC2 or PC3 to be an input pin when Comparator 0 or Comparator 1 is enabled.
P0SPEN
Description
0
Disable stopping the PPG0 timer using the C0VO trigger input.
The PPG0 module output can be stopped by software control (P0ST) only.
1
Enable stopping the PPG0 timer using the C0VO trigger input.
The PPG0 module output can be stopped by a C0VO falling edge trigger or software control
(P0ST bit is cleared to ²0²).
P0RSEN
Description
0
Disable restarting the PPG0 timer using the C1VO trigger input.
The PPG0 module output can be restarted by software control (P0ST) only.
1
Enable restarting the PPG0 timer using the C1VO trigger input.
The PPG0 module output can be restarted by a C1VO falling edge trigger or software control
(P0ST is set to ²1²)
The P0ST bit is a software trigger bit, if this bit is set to ²1², the PPG0 timer will start counting and will be cleared when
a PPG timer overflow occurs or PPG timer stop counting. If this bit is cleared to ²0², the PPG0 timer will stop counting.
When the PPG timer is counting and if a falling edge is generated from C1VO, PC3 or if the software control bit,
P0ST, is set, the PPG0 timer counter will not be affected, therefore a re-trigger signal from C1V0, PC3 or P0ST will
have no effect. The P0ST bit can also be used as a status bit for the PPG0 timer output.
The PPG0 module output pulse active level is decided by a configuration option, if cleared to ²0², the PPG output will be
defined as an active high output, if the P0LEV bit is set to ²1², the PPG output will be defined as an active low output.
Another function, which enables the point when the PPG timer starts counting and if it is to be synchronised with the
clock or not is determined by a configuration option.
To start the PPG0 operation:
-
Set the PPG0 output active level - by configuration option.
-
Select the input mode for PPG0 - P0RSEN, P0SPEN
-
Determine the PPG0 output pulse width. Write data to PPGT0 and the PPG0 timer prescaler
- P0PSC2, P0PSC1, PPSC0
-
Decide if the PPG0 timer start count is to be synchronised with the system clock (fSYS) or not via configuration option.
-
When the PPG0 input is triggered by a C1VO falling edge transition or triggered by a software bit which is set to
²1²; (P0ST ® 1), the PPG0 will start counting from the current contents of the preload register. When the PPG0
input is triggered by a C0VO falling edge transition, triggered by a software bit which is cleared to ²0² (P0ST ® 0)
or when a PPG0 timer overflow occurs, the PPG0 will stop counting.
Rev. 1.01
20
December 29, 2008
HT46R12A
Comparator
The input voltage offset of the PPG comparator is adjustable by using common mode inputs to calibrate the offset.
V r
C N
C P
C O
S 1
S 2
C O
S 3
The calibration steps are as follows:
· Set CnCOFM = 1 to offset the cancellation mode
- S3 is closed
· Set CnCRS to select which input pin is the reference voltage - S1 or S2 closed
· Adjust CnCOF0~CnCOF3 until the output status changes
· Set CnCOFM = 0 for the normal comparator operation mode.
Bit No.
Label
Function
POR
0
1
2
3
C0COF0
C0COF1
C0COF2
C0COF3
Comparator input offset voltage cancellation control bits
4
C0CRS
Comparator input offset voltage cancellation reference selection bit
1/0: select CP/CN as the reference input
0
5
C0COFM
Input offset voltage cancellation mode and comparator mode selection
1: input offset voltage cancellation mode
0: comparator mode
0
6
C0CMPOP
7
¾
1000B
Comparator output; positive logic
0
Unused bit, read as ²0²
0
CMP0C (1BH) Register
Bit No.
Label
Function
POR
0
1
2
3
C1COF0
C1COF1
C1COF2
C1COF3
Comparator input offset voltage cancellation control bits
4
C1CRS
Comparator input offset voltage cancellation reference selection bit
1/0: select CP/CN as the reference input
0
5
C1COFM
Input offset voltage cancellation mode and comparator mode selection
1: input offset voltage cancellation mode
0: comparator mode
0
6
C1CMPOP
Comparator output; positive logic
0
7
¾
Unused bit, read as ²0²
0
1000B
CMP1C (1CH) Register
Rev. 1.01
21
December 29, 2008
HT46R12A
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²CLR
[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
Input/Output Ports
There are 16 bidirectional input/output lines in the
microcontroller, labeled as PA, PB and PC, which are
mapped to the data memory of [12H], [14H] and [16H]
respectively. All of these I/O ports can be used for input
and output operations. For input operation, these ports
are non-latching, that is, the inputs must be ready at the
T2 rising edge of instruction ²MOV A,[m]² (m=12H, 14H
or 16H). For output operation, all the data is latched and
remains unchanged until the output latch is rewritten.
Each line of port A has the capability of waking-up the
device. Each I/O port has a pull-high option. Once the
pull-high option is selected, the I/O port has a pull-high
resistor, otherwise, there¢s none. Take note that a
non-pull-high I/O port operating in input mode will cause
a floating state.
Each I/O line has its own control register (PAC, PBC,
PCC) to control the input/output configuration. With this
control register, CMOS output or Schmitt trigger input
with or without pull-high resistor structures can be reconfigured dynamically under software control. To function as an input, the corresponding latch of the control
register must write ²1². The input source also depends
on the control register. If the control register bit is ²1²,
the input will read the pad state. If the control register bit
is ²0², the contents of the latches will move to the internal bus. The latter is possible in the ²read-modify-write²
instruction.
The PA3, PA4 and PA7 are pin-shared with PFD, TMR0
and TMR1 pins respectively. And the PC0, PC1, PC2,
PC3 and PC4 are pin-shared with C0VIN1-, C0VIN+,
C0OUT, C1OUT and C1VIN-.
The PA3 is pin-shared with the PFD signal. If the PFD option is selected, the output signal in output mode of PA3
will be the PFD signal generated by a timer/event counter
overflow signal. The input mode always remain in its original functions. Once the PFD option is selected, the PFD
output signal is controlled by the PA3 data register only.
Writing ²1² to PA3 data register will enable the PFD output function and writing ²0² will force the PA3 to remain at
²0². The I/O functions of PA3 are shown below.
For output function, CMOS is the only configuration.
These control registers are mapped to locations 13H,
15H and 17H.
After a chip reset, these input/output lines remain at high
levels or floating state (depending on pull-high options).
Each bit of these input/output latches can be set or
cleared by ²SET [m].i² and ²CLR [m].i² (m=12H, 14H or
16H) instructions.
I/O
Mode
Logical
Input
PA3
Note:
I/P
O/P
(Normal) (Normal)
W r ite C o n tr o l R e g is te r
Q
S
C h ip R e s e t
R e a d C o n tr o l R e g is te r
W r ite D a ta R e g is te r
D a ta B it
Q
D
Q
C K
D D
P A
P A
P A
P A
P A
P B
P C
P C
P C
P C
P C
Q
C K
Logical
PFD
Input (Timer on)
P u ll- h ig h
O p tio n
C o n tr o l B it
D
Logical
Output
O/P
(PFD)
The PFD frequency is the timer/event counter
overflow frequency divided by 2.
V
D a ta B u s
I/P
(PFD)
0 ~ P
3 /P
4 /T
5 ~ P
7 /T
0 /A
0 /C
1 /C
2 /C
3 /C
4 /C
A 2
F D
M R
A 6
M R
N 0
0 V
0 V
0 O
1 O
1 V
0
1
~ P
IN
IN
U
U
IN
B 3 /A N 3
T
T
+
-
S
M
(P A 0 ) P A 3
(P P G 1 ) P F D
M
R e a d D a ta R e g is te r
S y s te m
W a k e - u p ( P A o n ly )
U
U
X
E N
(P F D )
X
O P 0 ~ O P 7
T M R 0 fo r P A 4 O n ly
T M R 1 fo r P A 7 O n ly
Input/Output Ports
Rev. 1.01
22
December 29, 2008
HT46R12A
The A/D converter control register is used to control the
A/D converter. The bit2~bit0 of the ADCR are used to
select an analog input channel. There¢s a total of 4
channels to select. The bit5~bit3 of the ADCR are used
to set the PB configurations. PB can be an analog input
or as digital I/O line determined by these 3 bits.
It is recommended that unused or not bonded out I/O
lines should be set as output pins by software instruction
to avoid consuming power under input floating state.
The PFD (PFD0 or PFD1) output shares pin with PA3,
as determined by options. When the PFD (PFD0 or
PFD1) option is selected, setting PA3 ²1² (²SET PA.3²)
will enable the PFD output and setting PA3 ²0² (²CLR
PA.3²) will disable the PFD output and PA3 output at low
level.
PCR2 PCR1 PCR0
The definitions of PFD control signal and PFD output
frequency are listed in the following table.
Timer
PA3 Data PA3 Pad
Timer Preload
Register
State
Value
PFD
Frequency
3
2
1
0
0
0
0
PB3
PB2
PB1
PB0
0
0
1
PB3
PB2
PB1
AN0
0
1
0
PB3
PB2
AN1
AN0
0
1
1
PB3
AN2
AN1
AN0
1
x
x
AN3
AN2
AN1
AN0
Port B Configuration
OFF
X
0
0
X
OFF
X
1
U
X
ON
N
0
0
X
ON
N
1
PFD
fTMR/[2´(M-N)]
Note:
Once a PB line is selected as an analog input, the I/O
functions and pull-high resistor of this I/O line are disabled and the A/D converter circuit is powered on. The
EOCB bit (bit6 of the ADCR) is end of A/D conversion
flag. Check this bit to know when A/D conversion is completed. The START bit of the ADCR is used to begin the
conversion of the A/D converter. Giving START bit a rising edge and falling edge means that the A/D conversion has started. In order to ensure that A/D conversion
is completed, the START should remain at ²0² until the
EOCB is cleared to ²0² (end of A/D conversion).
²X² stands for unused
²U² stands for unknown
²M² is ²256² for PFD
²N² is preload value for the timer/event counter
²f T M R ² is input clock frequency for the
timer/event counter
Bit 7 of the ACSR register is used for test purposes only
and must not be used for other purposes by the application program. Bit1 and bit0 of the ACSR register are
used to select the A/D clock source.
A/D Converter
The 4 channels and 9-bit resolution A/D (8-bit accuracy)
converter are implemented in this microcontroller. The
reference voltage is VDD. The A/D converter contains
four special registers which are; ADRL (24H), ADRH
(25H), ADCR (26H) and ACSR (27H). The ADRH and
ADRL are A/D result register higher-order byte and
lower-order byte and are read-only. After the A/D conversion is completed, the ADRH and ADRL should be
read to get the conversion result data. The ADCR is an
A/D converter control register, which defines the A/D
channel number, analog channel select, start A/D conversion control bit and end of A/D conversion flag. If users want to start an A/D conversion, define the PB
configuration, select the converted analog channel, and
give START bit a raising edge and falling edge
(0®1®0). At the end of A/D conversion, the EOCB bit is
cleared and an A/D converter interrupt occurs (if the A/D
converter interrupt is enabled). The ACSR is A/D clock
setting register, which is used to select the A/D clock
source.
Rev. 1.01
When the A/D conversion has completed, the A/D interrupt request flag will be set. The EOCB bit is set to ²1²
when the START bit is set from ²0² to ²1².
Important Note for A/D initialization:
Special care must be taken to initialize the A/D converter each time the Port B A/D channel selection bits
are modified, otherwise the EOCB flag may be in an undefined condition. An A/D initialization is implemented
by setting the START bit high and then clearing it to zero
within 10 instruction cycles of the Port B channel selection bits being modified. Note that if the Port B channel
selection bits are all cleared to zero then an A/D initialization is not required.
23
December 29, 2008
HT46R12A
Bit No.
Label
Function
Selects the A/D converter clock source
00: system clock/2
ADCS0
01: system clock/8
ADCS1
10: system clock/32
11: undefined
0
1
2~6
¾
Unused bit, read as ²0²
7
TEST
For test mode used only
ACSR (27H) Register
Bit No.
Label
Function
0
1
2
ACS0
ACS1
ACS2
ACS2, ACS1, ACS0: Select A/D channel
0, 0, 0: AN0
0, 0, 1: AN1
0, 1, 0: AN2
0, 1, 1: AN3
1, x, x: Undefined, cannot be used
3
4
5
PCR0
PCR1
PCR2
Defines the port B configuration select. If PCR0, PCR1 and PCR2 are all zero, the ADC circuit is
powered off to reduce power consumption
6
EOCB
Indicates end of A/D conversion. (0: end of A/D conversion)
Each time bits 3~5 change state the A/D should be initialized by issuing a START signal, otherwise the EOCB flag may have an undefined condition. See ²Important note for A/D initialization².
7
START Starts the A/D conversion. (0®1®0= start; 0®1= Reset A/D converter and set EOCB to ²1²)
ADCR (26H) Register
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
ADRL (24H)
Register
D0
¾
¾
¾
¾
¾
¾
¾
ADRH (25H)
D8
D7
D6
D5
D4
D3
D2
D1
Note:
D0~D8 is A/D conversion result data bit LSB~MSB.
ADRL (24H), ADRH (25H) Register
The following two programming examples illustrate how to setup and implement an A/D conversion. In the first example, the method of polling the EOCB bit in the ADCR register is used to detect when the conversion cycle is complete,
whereas in the second example, the A/D interrupt is used to determine when the conversion is complete.
Example: using EOCB Polling Method to detect end of conversion
clr
EADI
; disable ADC interrupt
mov
a,00000001B
mov
ACSR,a
; setup the ACSR register to select fSYS/8 as the A/D clock
mov
a,00100000B
; setup ADCR register to configure Port PB0~PB3 as A/D inputs
mov
ADCR,a
; and select AN0 to be connected to the A/D converter
:
:
; As the Port B channel bits have changed the following START
; signal (0-1-0) must be issued within 10 instruction cycles
:
Start_conversion:
clr
START
set
START
; reset A/D
clr
START
; start A/D
Polling_EOC:
sz
EOCB
; poll the ADCR register EOCB bit to detect end of A/D conversion
jmp
polling_EOC
; continue polling
mov
a,ADRH
; read conversion result high byte value from the ADRH register
mov
adrh_buffer,a
; save result to user defined memory
mov
a,ADRL
; read conversion result low byte value from the ADRL register
mov
adrl_buffer,a
; save result to user defined memory
:
:
jmp
start_conversion
; start next A/D conversion
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Example: using interrupt method to detect end of conversion
clr
EADI
; disable ADC interrupt
mov
a,00000001B
mov
ACSR,a
; setup the ACSR register to select fSYS/8 as the A/D clock
mov
mov
a,00100000B
ADCR,a
:
; setup ADCR register to configure Port PB0~PB3 as A/D inputs
; and select AN0 to be connected to the A/D converter
; As the Port B channel bits have changed the following START
; signal (0-1-0) must be issued within 10 instruction cycles
:
Start_conversion:
clr
START
set
START
clr
START
clr
ADF
set
EADI
set
EMI
:
:
:
; ADC interrupt service routine
ADC_ISR:
mov
acc_stack,a
mov
a,STATUS
mov
status_stack,a
:
:
mov
a,ADRH
mov
adrh_buffer,a
mov
a,ADRL
mov
adrl_buffer,a
clr
START
set
START
clr
START
:
:
EXIT_INT_ISR:
mov
a,status_stack
mov
STATUS,a
mov
a,acc_stack
reti
M in im u m
; reset A/D
; start A/D
; clear ADC interrupt request flag
; enable ADC interrupt
; enable global interrupt
; save ACC to user defined memory
; save STATUS to user defined memory
; read conversion result high byte value from the ADRH register
; save result to user defined register
; read conversion result low byte value from the ADRL register
; save result to user defined register
; reset A/D
; start A/D
; restore STATUS from user defined memory
; restore ACC from user defined memory
o n e in s tr u c tio n c y c le n e e d e d , M a x im u m
te n in s tr u c tio n c y c le s a llo w e d
S T A R T
E O C B
A /D
tA
P C R 2 ~
P C R 0
s a m p lin g tim e
A /D
tA
D C S
0 0 0 B
s a m p lin g tim e
A /D
tA
D C S
1 0 0 B
1 0 0 B
s a m p lin g tim e
D C S
1 0 1 B
0 0 0 B
1 . P B p o rt s e tu p a s I/O s
2 . A /D c o n v e r te r is p o w e r e d o ff
to r e d u c e p o w e r c o n s u m p tio n
A C S 2 ~
A C S 0
0 0 0 B
P o w e r-o n
R e s e t
0 1 0 B
0 0 0 B
0 0 1 B
S ta rt o f A /D
c o n v e r s io n
S ta rt o f A /D
c o n v e r s io n
S ta rt o f A /D
c o n v e r s io n
R e s e t A /D
c o n v e rte r
R e s e t A /D
c o n v e rte r
E n d o f A /D
c o n v e r s io n
1 : D e fin e P B c o n fig u r a tio n
2 : S e le c t a n a lo g c h a n n e l
A /D
N o te :
A /D c lo c k m u s t b e fS
tA D C S = 3 2 tA D
tA D C = 7 6 tA D
Y S
/2 , fS
tA D C
c o n v e r s io n tim e
Y S
/8 o r fS
Y S
R e s e t A /D
c o n v e rte r
E n d o f A /D
c o n v e r s io n
A /D
tA D C
c o n v e r s io n tim e
d o n 't c a r e
E n d o f A /D
c o n v e r s io n
A /D
tA D C
c o n v e r s io n tim e
/3 2
A/D Conversion Timing
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Low Voltage Reset - LVR
The relationship between VDD and VLVR is shown below.
The microcontroller provides low voltage reset circuit in
order to monitor the supply voltage of the device. If the
supply voltage of the device is within the range
0.9V~VLVR, such as changing a battery, the LVR will automatically reset the device internally.
V D D
5 .5 V
The LVR includes the following specifications:
3 .0 V
V
V
L V R
2 .2 V
· The low voltage (0.9V~VLVR) state has to be main-
tained for more than 1ms. If the low voltage state does
not exceed 1ms, the LVR will ignore it and do not perform a reset function.
0 .9 V
Note: VOPR is the voltage range for proper chip
operation at 4MHz system clock.
· The LVR uses the ²OR² function with the external RES
signal to perform a chip reset.
V
O P R
5 .5 V
D D
5 .5 V
V
L V R
L V R
D e te c t V o lta g e
0 .9 V
0 V
R e s e t S ig n a l
N o r m a l O p e r a tio n
R e s e t
*1
R e s e t
*2
Low Voltage Reset
Note:
*1: To ensure oscillator stabilisation, the SST provides an extra 1024 system clock pulse delay before normal
operation commences.
*2: Since the low voltage state has to be maintained for over 1ms, after this 1ms delay, the device will enter
the reset mode.
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Options
The following shows ten kinds of options in the microcontroller. ALL the options must be defined to ensure proper system function.
Options
OSC type selection.
This option is to determine if an RC or crystal oscillator is chosen as system clock.
WDT source selection.
There are three types of selection: On-chip RC oscillator, instruction clock or disable the WDT.
CLRWDT times selection.
This option defines how to clear the WDT by instruction. ²One time² means that the ²CLR WDT² instruction can clear
the WDT. ²Two times² means only if both of the ²CLR WDT1² and ²CLR WDT2² instructions have been executed,
then WDT can be cleared.
WDT time-out period selection.
There are four types of selection: fS/213, fS/214, fS/215 and fS/216
Wake-up selection.
This option defines the wake-up function activity. External I/O pins (PA only) all have the capability to wake-up the
chip from a HALT.
Pull-high selection.
This option is to determine whether a pull-high resistance is viable or not in the input mode of the I/O ports. PA0~PA7,
can be independently selected.
Pull-high selection.
This option is to decide whether a pull-high resistance is viable or not in the input mode of the I/O ports. PB0~PB3,
can be independently selected
Pull-high selection.
This option is to determine whether a pull-high resistance is viable or not in the input mode of the I/O ports.
PC0~PC4, can be independently selected
I/O pins share with other function selections.
PA3/PFD: PA3 can be set as I/O pins or PFD output.
PFD selection.
If PA3 is set as PFD output, there are two types of selections; One is PFD0 as the PFD output, the other is PFD1 as
the PFD output. PFD0, PFD1 are generated by the timer overflow signals of the Timer/Event Counter 0, Timer/Event
Counter 1 respectively.
Low voltage reset selection.
Enable or disable LVR function.
PPG0 output level selection; P0LEV.
This option is to determine the PPG output level. Active Low or Active High selection. Disable this bit to ²0², the PPG
output will be defined as an active high output, Enable this bit to ²1², the PPG output will be defined as an active low
output
PPG0 timer start counting synchronized with clock; P0TSYN.
This option is to determine the PPG0 timer start counting is synchronized with input clock or not.
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Application Circuits
V
D D
P A 0 ~ P A 2
V D D
P A 3 /P F D
P A 4 /T M R 0
R e s e t
C ir c u it
1 0 0 k W
0 .1 m F
V
P A 5 ~ P A 6
4 7 0 p F
P A 7 /T M R 1
R E S
P B 0 /A N 0
P B 3 /A N 3
R
~
0 .1 m F
P C 0 /C 0 V IN V S S
O S C 1
O S C 2
O S C 1
fS
Y S
/4
P C 3 /C 1 O U T
P C 4 /V 1 V IN -
C 2
R C S y s te m O s c illa to r
2 4 k W < R O S C < 1 M W
O S C 2
O S C 1
R 1
H T 4 6 R 1 2 A
Note:
O S C
C 1
P C 1 /C 0 V IN +
P C 2 /C 0 O U T
O S C
C ir c u it
D D
O S C 2
O S C
C r y s ta l/R e s o n a to r
S y s te m O s c illa to r
F o r R 1 , C 1 , C 2 s e e n o te
C ir c u it
1. Crystal/resonator system oscillators
For crystal oscillators, C1 and C2 are only required for some crystal frequencies to ensure oscillation. For
resonator applications C1 and C2 are normally required for oscillation to occur. For most applications it is
not necessary to add R1. However if the LVR function is disabled, and if it is required to stop the oscillator
when VDD falls below its operating range, it is recommended that R1 is added. The values of C1 and C2
should be selected in consultation with the crystal/resonator manufacturer specifications.
2. Reset circuit
The reset circuit resistance and capacitance values should be chosen to ensure that VDD is stable and remains within its operating voltage range before the RES pin reaches a high level. Ensure that the length of
the wiring connected to the RES pin is kept as short as possible, to avoid noise interference.
3. For applications where noise may interfere with the reset circuit and for details on the oscillator external
components, refer to Application Note HA0075E for more information.
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Instruction Set
subtract instruction mnemonics to enable the necessary
arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for
subtraction. The increment and decrement instructions
INC, INCA, DEC and DECA provide a simple means of
increasing or decreasing by a value of one of the values
in the destination specified.
Introduction
C e n t ra l t o t he s u c c e s s f u l oper a t i on o f a n y
microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to
perform certain operations. In the case of Holtek
microcontrollers, a comprehensive and flexible set of
over 60 instructions is provided to enable programmers
to implement their application with the minimum of programming overheads.
Logical and Rotate Operations
For easier understanding of the various instruction
codes, they have been subdivided into several functional groupings.
The standard logical operations such as AND, OR, XOR
and CPL all have their own instruction within the Holtek
microcontroller instruction set. As with the case of most
instructions involving data manipulation, data must pass
through the Accumulator which may involve additional
programming steps. In all logical data operations, the
zero flag may be set if the result of the operation is zero.
Another form of logical data manipulation comes from
the rotate instructions such as RR, RL, RRC and RLC
which provide a simple means of rotating one bit right or
left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for
serial port programming applications where data can be
rotated from an internal register into the Carry bit from
where it can be examined and the necessary serial bit
set high or low. Another application where rotate data
operations are used is to implement multiplication and
division calculations.
Instruction Timing
Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are
required. One instruction cycle is equal to 4 system
clock cycles, therefore in the case of an 8MHz system
oscillator, most instructions would be implemented
within 0.5ms and branch or call instructions would be implemented within 1ms. Although instructions which require one more cycle to implement are generally limited
to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions
which involve manipulation of the Program Counter Low
register or PCL will also take one more cycle to implement. As instructions which change the contents of the
PCL will imply a direct jump to that new address, one
more cycle will be required. Examples of such instructions would be ²CLR PCL² or ²MOV PCL, A². For the
case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then
this will also take one more cycle, if no skip is involved
then only one cycle is required.
Branches and Control Transfer
Program branching takes the form of either jumps to
specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the
sense that in the case of a subroutine call, the program
must return to the instruction immediately when the subroutine has been carried out. This is done by placing a
return instruction RET in the subroutine which will cause
the program to jump back to the address right after the
CALL instruction. In the case of a JMP instruction, the
program simply jumps to the desired location. There is
no requirement to jump back to the original jumping off
point as in the case of the CALL instruction. One special
and extremely useful set of branch instructions are the
conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program
will continue with the next instruction or skip over it and
jump to the following instruction. These instructions are
the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits.
Moving and Transferring Data
The transfer of data within the microcontroller program
is one of the most frequently used operations. Making
use of three kinds of MOV instructions, data can be
transferred from registers to the Accumulator and
vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most
important data transfer applications is to receive data
from the input ports and transfer data to the output ports.
Arithmetic Operations
The ability to perform certain arithmetic operations and
data manipulation is a necessary feature of most
microcontroller applications. Within the Holtek
microcontroller instruction set are a range of add and
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Bit Operations
Other Operations
The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek
microcontrollers. This feature is especially useful for
output port bit programming where individual bits or port
pins can be directly set high or low using either the ²SET
[m].i² or ²CLR [m].i² instructions respectively. The feature removes the need for programmers to first read the
8-bit output port, manipulate the input data to ensure
that other bits are not changed and then output the port
with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used.
In addition to the above functional instructions, a range
of other instructions also exist such as the ²HALT² instruction for Power-down operations and instructions to
control the operation of the Watchdog Timer for reliable
program operations under extreme electric or electromagnetic environments. For their relevant operations,
refer to the functional related sections.
Instruction Set Summary
The following table depicts a summary of the instruction
set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions.
Table Read Operations
Table conventions:
Data storage is normally implemented by using registers. However, when working with large amounts of
fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an
area of Program Memory to be setup as a table where
data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be
referenced and retrieved from the Program Memory.
Mnemonic
x: Bits immediate data
m: Data Memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Description
Cycles
Flag Affected
1
1Note
1
1
1Note
1
1
1Note
1
1Note
1Note
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
C
1
1
1
1Note
1Note
1Note
1
1
1
1Note
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
1
1Note
1
1Note
Z
Z
Z
Z
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Add Data Memory to ACC
Add ACC to Data Memory
Add immediate data to ACC
Add Data Memory to ACC with Carry
Add ACC to Data memory with Carry
Subtract immediate data from the ACC
Subtract Data Memory from ACC
Subtract Data Memory from ACC with result in Data Memory
Subtract Data Memory from ACC with Carry
Subtract Data Memory from ACC with Carry, result in Data Memory
Decimal adjust ACC for Addition with result in Data Memory
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
Logical AND Data Memory to ACC
Logical OR Data Memory to ACC
Logical XOR Data Memory to ACC
Logical AND ACC to Data Memory
Logical OR ACC to Data Memory
Logical XOR ACC to Data Memory
Logical AND immediate Data to ACC
Logical OR immediate Data to ACC
Logical XOR immediate Data to ACC
Complement Data Memory
Complement Data Memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rev. 1.01
Increment Data Memory with result in ACC
Increment Data Memory
Decrement Data Memory with result in ACC
Decrement Data Memory
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Mnemonic
Description
Cycles
Flag Affected
Rotate Data Memory right with result in ACC
Rotate Data Memory right
Rotate Data Memory right through Carry with result in ACC
Rotate Data Memory right through Carry
Rotate Data Memory left with result in ACC
Rotate Data Memory left
Rotate Data Memory left through Carry with result in ACC
Rotate Data Memory left through Carry
1
1Note
1
1Note
1
1Note
1
1Note
None
None
C
C
None
None
C
C
Move Data Memory to ACC
Move ACC to Data Memory
Move immediate data to ACC
1
1Note
1
None
None
None
Clear bit of Data Memory
Set bit of Data Memory
1Note
1Note
None
None
Jump unconditionally
Skip if Data Memory is zero
Skip if Data Memory is zero with data movement to ACC
Skip if bit i of Data Memory is zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1Note
1note
1Note
1Note
1Note
1Note
1Note
1Note
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read table (current page) to TBLH and Data Memory
Read table (last page) to TBLH and Data Memory
2Note
2Note
None
None
No operation
Clear Data Memory
Set Data Memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACC
Enter power down mode
1
1Note
1Note
1
1
1
1Note
1
1
None
None
None
TO, PDF
TO, PDF
TO, PDF
None
None
TO, PDF
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note:
1. For skip instructions, if the result of the comparison involves a skip then two cycles are required,
if no skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by
the execution status. The TO and PDF flags are cleared after both ²CLR WDT1² and
²CLR WDT2² instructions are consecutively executed. Otherwise the TO and PDF flags
remain unchanged.
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Instruction Definition
ADC A,[m]
Add Data Memory to ACC with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the Accumulator.
Operation
ACC ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADCM A,[m]
Add ACC to Data Memory with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADD A,[m]
Add Data Memory to ACC
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
ADD A,x
Add immediate data to ACC
Description
The contents of the Accumulator and the specified immediate data are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + x
Affected flag(s)
OV, Z, AC, C
ADDM A,[m]
Add ACC to Data Memory
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
AND A,[m]
Logical AND Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
Z
AND A,x
Logical AND immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical AND
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
Z
ANDM A,[m]
Logical AND ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
Z
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CALL addr
Subroutine call
Description
Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the
stack. The specified address is then loaded and the program continues execution from this
new address. As this instruction requires an additional operation, it is a two cycle instruction.
Operation
Stack ¬ Program Counter + 1
Program Counter ¬ addr
Affected flag(s)
None
CLR [m]
Clear Data Memory
Description
Each bit of the specified Data Memory is cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
None
CLR [m].i
Clear bit of Data Memory
Description
Bit i of the specified Data Memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
None
CLR WDT
Clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT1
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT2
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
Rev. 1.01
33
December 29, 2008
HT46R12A
CPL [m]
Complement Data Memory
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa.
Operation
[m] ¬ [m]
Affected flag(s)
Z
CPLA [m]
Complement Data Memory with result in ACC
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa. The complemented result
is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
Z
DAA [m]
Decimal-Adjust ACC for addition with result in Data Memory
Description
Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or
if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of
6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C
flag may be affected by this instruction which indicates that if the original BCD sum is
greater than 100, it allows multiple precision decimal addition.
Operation
[m] ¬ ACC + 00H or
[m] ¬ ACC + 06H or
[m] ¬ ACC + 60H or
[m] ¬ ACC + 66H
Affected flag(s)
C
DEC [m]
Decrement Data Memory
Description
Data in the specified Data Memory is decremented by 1.
Operation
[m] ¬ [m] - 1
Affected flag(s)
Z
DECA [m]
Decrement Data Memory with result in ACC
Description
Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] - 1
Affected flag(s)
Z
HALT
Enter power down mode
Description
This instruction stops the program execution and turns off the system clock. The contents
of the Data Memory and registers are retained. The WDT and prescaler are cleared. The
power down flag PDF is set and the WDT time-out flag TO is cleared.
Operation
TO ¬ 0
PDF ¬ 1
Affected flag(s)
TO, PDF
Rev. 1.01
34
December 29, 2008
HT46R12A
INC [m]
Increment Data Memory
Description
Data in the specified Data Memory is incremented by 1.
Operation
[m] ¬ [m] + 1
Affected flag(s)
Z
INCA [m]
Increment Data Memory with result in ACC
Description
Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] + 1
Affected flag(s)
Z
JMP addr
Jump unconditionally
Description
The contents of the Program Counter are replaced with the specified address. Program
execution then continues from this new address. As this requires the insertion of a dummy
instruction while the new address is loaded, it is a two cycle instruction.
Operation
Program Counter ¬ addr
Affected flag(s)
None
MOV A,[m]
Move Data Memory to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
None
MOV A,x
Move immediate data to ACC
Description
The immediate data specified is loaded into the Accumulator.
Operation
ACC ¬ x
Affected flag(s)
None
MOV [m],A
Move ACC to Data Memory
Description
The contents of the Accumulator are copied to the specified Data Memory.
Operation
[m] ¬ ACC
Affected flag(s)
None
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
No operation
Affected flag(s)
None
OR A,[m]
Logical OR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
Z
Rev. 1.01
35
December 29, 2008
HT46R12A
OR A,x
Logical OR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
Z
ORM A,[m]
Logical OR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²OR² [m]
Affected flag(s)
Z
RET
Return from subroutine
Description
The Program Counter is restored from the stack. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
Affected flag(s)
None
RET A,x
Return from subroutine and load immediate data to ACC
Description
The Program Counter is restored from the stack and the Accumulator loaded with the
specified immediate data. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
None
RETI
Return from interrupt
Description
The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending
when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
None
RL [m]
Rotate Data Memory left
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ [m].7
Affected flag(s)
None
RLA [m]
Rotate Data Memory left with result in ACC
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ [m].7
Affected flag(s)
None
Rev. 1.01
36
December 29, 2008
HT46R12A
RLC [m]
Rotate Data Memory left through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RLCA [m]
Rotate Data Memory left through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces
the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RR [m]
Rotate Data Memory right
Description
The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into
bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ [m].0
Affected flag(s)
None
RRA [m]
Rotate Data Memory right with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data
Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ [m].0
Affected flag(s)
None
RRC [m]
Rotate Data Memory right through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
C
RRCA [m]
Rotate Data Memory right through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is
stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
C
Rev. 1.01
37
December 29, 2008
HT46R12A
SBC A,[m]
Subtract Data Memory from ACC with Carry
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result
of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or
zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SBCM A,[m]
Subtract Data Memory from ACC with Carry and result in Data Memory
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SDZ [m]
Skip if decrement Data Memory is 0
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0 the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] - 1
Skip if [m] = 0
Affected flag(s)
None
SDZA [m]
Skip if decrement Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0, the program proceeds with the following instruction.
Operation
ACC ¬ [m] - 1
Skip if ACC = 0
Affected flag(s)
None
SET [m]
Set Data Memory
Description
Each bit of the specified Data Memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
None
SET [m].i
Set bit of Data Memory
Description
Bit i of the specified Data Memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
None
Rev. 1.01
38
December 29, 2008
HT46R12A
SIZ [m]
Skip if increment Data Memory is 0
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] + 1
Skip if [m] = 0
Affected flag(s)
None
SIZA [m]
Skip if increment Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
Operation
ACC ¬ [m] + 1
Skip if ACC = 0
Affected flag(s)
None
SNZ [m].i
Skip if bit i of Data Memory is not 0
Description
If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is 0 the program proceeds with the following instruction.
Operation
Skip if [m].i ¹ 0
Affected flag(s)
None
SUB A,[m]
Subtract Data Memory from ACC
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUBM A,[m]
Subtract Data Memory from ACC with result in Data Memory
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUB A,x
Subtract immediate data from ACC
Description
The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will
be set to 1.
Operation
ACC ¬ ACC - x
Affected flag(s)
OV, Z, AC, C
Rev. 1.01
39
December 29, 2008
HT46R12A
SWAP [m]
Swap nibbles of Data Memory
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged.
Operation
[m].3~[m].0 « [m].7 ~ [m].4
Affected flag(s)
None
SWAPA [m]
Swap nibbles of Data Memory with result in ACC
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged. The
result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC.3 ~ ACC.0 ¬ [m].7 ~ [m].4
ACC.7 ~ ACC.4 ¬ [m].3 ~ [m].0
Affected flag(s)
None
SZ [m]
Skip if Data Memory is 0
Description
If the contents of the specified Data Memory is 0, the following instruction is skipped. As
this requires the insertion of a dummy instruction while the next instruction is fetched, it is a
two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
Operation
Skip if [m] = 0
Affected flag(s)
None
SZA [m]
Skip if Data Memory is 0 with data movement to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator. If the value is
zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the
program proceeds with the following instruction.
Operation
ACC ¬ [m]
Skip if [m] = 0
Affected flag(s)
None
SZ [m].i
Skip if bit i of Data Memory is 0
Description
If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is not 0, the program proceeds with the following instruction.
Operation
Skip if [m].i = 0
Affected flag(s)
None
TABRDC [m]
Read table (current page) to TBLH and Data Memory
Description
The low byte of the program code (current page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
TABRDL [m]
Read table (last page) to TBLH and Data Memory
Description
The low byte of the program code (last page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
Rev. 1.01
40
December 29, 2008
HT46R12A
XOR A,[m]
Logical XOR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XORM A,[m]
Logical XOR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XOR A,x
Logical XOR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical XOR
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Z
Rev. 1.01
41
December 29, 2008
HT46R12A
Package Information
24-pin SKDIP (300mil) Outline Dimensions
A
A
1 3
2 4
B
1 3
2 4
B
1 2
1
1 2
1
H
H
C
C
D
D
E
F
I
G
E
F
I
G
Fig2. 1/2 Lead Packages
Fig1. Full Lead Packages
· MS-001d (see fig1)
Symbol
Dimensions in mil
Min.
Nom.
Max.
A
1230
¾
1280
B
240
¾
280
C
115
¾
195
D
115
¾
150
E
14
¾
22
F
45
¾
70
G
¾
100
¾
H
300
¾
325
I
¾
¾
430
· MS-001d (see fig2)
Symbol
Rev. 1.01
Dimensions in mil
Min.
Nom.
Max.
A
1160
¾
1195
B
240
¾
280
C
115
¾
195
D
115
¾
150
E
14
¾
22
F
45
¾
70
G
¾
100
¾
H
300
¾
325
I
¾
¾
430
42
December 29, 2008
HT46R12A
· MO-095a (see fig2)
Symbol
Rev. 1.01
Dimensions in mil
Min.
Nom.
Max.
A
1145
¾
1185
B
275
¾
295
C
120
¾
150
D
110
¾
150
E
14
¾
22
F
45
¾
60
G
¾
100
¾
H
300
¾
325
I
¾
¾
430
43
December 29, 2008
HT46R12A
24-pin SOP (300mil) Outline Dimensions
1 3
2 4
A
B
1 2
1
C
C '
G
H
D
E
a
F
· MS-013
Symbol
Rev. 1.01
Dimensions in mil
Min.
Nom.
Max.
A
393
¾
419
B
256
¾
300
C
12
¾
20
C¢
598
¾
613
D
¾
¾
104
E
¾
50
¾
F
4
¾
12
G
16
¾
50
H
8
¾
13
a
0°
¾
8°
44
December 29, 2008
HT46R12A
Product Tape and Reel Specifications
Reel Dimensions
D
T 2
A
C
B
T 1
SOP 24W
Symbol
Description
Dimensions in mm
A
Reel Outer Diameter
330.0±1.0
B
Reel Inner Diameter
100.0±1.5
C
Spindle Hole Diameter
13.0+0.5/-0.2
D
Key Slit Width
T1
Space Between Flange
T2
Reel Thickness
Rev. 1.01
2.0±0.5
24.8+0.3/-0.2
30.2±0.2
45
December 29, 2008
HT46R12A
Carrier Tape Dimensions
P 0
D
P 1
t
E
F
W
C
D 1
B 0
P
K 0
A 0
R e e l H o le
IC p a c k a g e p in 1 a n d th e r e e l h o le s
a r e lo c a te d o n th e s a m e s id e .
SOP 24W
Symbol
Description
Dimensions in mm
W
Carrier Tape Width
24.0±0.3
P
Cavity Pitch
12.0±0.1
E
Perforation Position
1.75±0.1
F
Cavity to Perforation (Width Direction)
11.5±0.1
D
Perforation Diameter
1.55+0.10/-0.00
D1
Cavity Hole Diameter
1.50+0.25/-0.00
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
10.9±0.1
B0
Cavity Width
15.9±0.1
K0
Cavity Depth
3.1±0.1
t
Carrier Tape Thickness
0.35±0.05
C
Cover Tape Width
21.3±0.1
Rev. 1.01
46
December 29, 2008
HT46R12A
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor (China) Inc. (Dongguan Sales Office)
Building No. 10, Xinzhu Court, (No. 1 Headquarters), 4 Cuizhu Road, Songshan Lake, Dongguan, China 523808
Tel: 86-769-2626-1300
Fax: 86-769-2626-1311
Holtek Semiconductor (USA), Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538, USA
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com
Copyright Ó 2008 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.01
47
December 29, 2008