Data Sheet

HT46R23/HT46C23
A/D Type 8-Bit MCU
Technical Document
· Tools Information
· FAQs
· Application Note
- HA0004E HT48 & HT46 MCU UART Software Implementation Method
- HA0005E Controlling the I2C bus with the HT48 & HT46 MCU Series
- HA0013E HT48 & HT46 LCM Interface Design
- HA0047E An PWM application example using the HT46 series of MCUs
- HA0075E MCU Reset and Oscillator Circuits Application Note
Features
· Operating voltage:
· Up to 0.5ms instruction cycle with 8MHz system clock
fSYS=4MHz: 2.2V~5.5V
fSYS=8MHz: 3.3V~5.5V
at VDD=5V
· 8-level subroutine nesting
· 23 bidirectional I/O lines (max.)
· 8 channels 10-bit resolution A/D converter
· 1 interrupt input shared with an I/O line
· 2-channel 8-bit PWM output shared with two I/O lines
· 16-bit programmable timer/event counter with
· Bit manipulation instruction
overflow interrupt and 7-stage prescaler
· 15-bit table read instruction
· On-chip crystal and RC oscillator
· 63 powerful instructions
· Watchdog Timer
· All instructions in one or two machine cycles
· 4096´15 program memory
· Low voltage reset function
· 192´8 data memory RAM
· I2C Bus (slave mode)
· Supports PFD for sound generation
· 24/28-pin SKDIP/SOP packages
· HALT function and wake-up feature reduce power
consumption
General Description
The advantages of low power consumption, I/O flexibility, programmable frequency divider, timer functions,
oscillator options, multi-channel A/D Converter, Pulse
Width Modulation function, I2C interface, HALT and
wake-up functions, enhance the versatility of these devices to suit a wide range of A/D application possibilities
such as sensor signal processing, motor driving, industrial control, consumer products, subsystem controllers,
etc.
The HT46R23/HT46C23 are 8-bit, high performance,
RISC architecture microcontroller devices specifically
designed for A/D applications that interface directly to
analog signals, such as those from sensors. The mask
version HT46C23 is fully pin and functionally compatible
with the OTP version HT46R23 device.
I2C is a trademark of Philips Semiconductors.
Rev. 2.11
1
December 29, 2008
HT46R23/HT46C23
Block Diagram
P A 5 /IN T
In te rru p t
C ir c u it
T M R
S T A C K
P ro g ra m
R O M
M
T M R C
P ro g ra m
C o u n te r
U
P r e s c a le r
X
P A 3 /P F D
M
M P
U
W D T
P r e s c a le r
D A T A
M e m o ry
X
P W
P A 4
M
W D T
U
/4
X
R C
P o rt D
P D 0 /P W
P D
O S C
M 0 ~ P D 1 /P W
M 1
M U X
In s tr u c tio n
D e c o d e r
8 -C h a n n e l
A /D C o n v e rte r
S T A T U S
A L U
P B C
S h ifte r
T im in g
G e n e ra to r
P A 3 , P A 5
S
S
A C C
C 1
P o rt B
P B 0 /A N 0 ~ P B 7 /A N 7
P B
P A C
O S
R E
V D
V S
Y S
M
P D C
O S C 2
Y S
IN T C
fS
In s tr u c tio n
R e g is te r
fS
P A 4 /T M R
P A
P A
P A
P A
P A
P A
P o rt A
P A
L V R
I2 C B u s
S la v e M o d e
D
P C
P o rt C
0 ~
3 /
4 /
5 /
6 /
7 /
P
P F
T M
IN
S D
S C
A 2
D
R
T
A
L
P C 0 ~ P C 4
P C C
Pin Assignment
1
2 8
P B 6 /A N 6
2
2 7
P B 7 /A N 7
P B 5 /A N 5
1
2 4
P B 6 /A N 6
P A 3 /P F D
3
2 6
P A 4 /T M R
P B 4 /A N 4
2
2 3
P B 7 /A N 7
P A 2
4
2 5
P A 5 /IN T
P A 3 /P F D
3
2 2
P A 4 /T M R
P A 1
5
2 4
P A 6 /S D A
P A 2
4
2 1
P A 5 /IN T
P A 0
6
2 3
P A 7 /S C L
P A 1
5
2 0
P A 6 /S D A
P B 3 /A N 3
7
2 2
O S C 2
P A 0
6
1 9
P A 7 /S C L
P B 2 /A N 2
8
2 1
O S C 1
P B 3 /A N 3
7
1 8
O S C 2
P B 1 /A N 1
9
2 0
V D D
P B 2 /A N 2
8
1 7
O S C 1
P B 0 /A N 0
1 0
1 9
R E S
P B 1 /A N 1
9
1 6
V D D
V S S
1 1
1 8
P D 1 /P W M 1
P B 0 /A N 0
1 0
1 5
R E S
P C 0
1 2
1 7
P D 0 /P W M 0
V S S
1 1
1 4
P D 0 /P W M 0
P C 1
1 3
1 6
P C 4
P C 0
1 2
1 3
P C 1
P C 2
1 4
1 5
P C 3
H T 4 6 R 2 3 /H T 4 6 C 2 3
2 4 S K D IP -A /S O P -A
Rev. 2.11
P B 5 /A N 5
P B 4 /A N 4
H T 4 6 R 2 3 /H T 4 6 C 2 3
2 8 S K D IP -A /S O P -A
2
December 29, 2008
HT46R23/HT46C23
Pad Description
Pad Name
PA0~PA2
PA3/PFD
PA4/TMR
PA5/INT
PA6/SDA
PA7/SCL
I/O
Option
Description
I/O
Pull-high
Wake-up
PA3 or PFD
I/O or Serial Bus
Bidirectional 8-bit input/output port. Each bit can be configured as wake-up
input by options. Software instructions determine the CMOS output or
Schmitt trigger input with or without pull-high resistor (determined by
pull-high options: bit option). The PFD, TMR and INT are pin-shared with
PA3, PA4 and PA5, respectively. Once the I2C Bus function is used, the internal registers related to PA6 and PA7 can not be used.
PB0/AN0
PB1/AN1
PB2/AN2
PB3/AN3
PB4/AN4
PB5/AN5
PB6/AN6
PB7/AN7
I/O
Pull-high
Bidirectional 8-bit input/output port. Software instructions determine the
CMOS output, Schmitt trigger input with or without pull-high resistor (determined by pull-high: port option) or A/D input.
Once a PB line is selected as an A/D input (by using software control), the
I/O function and pull-high resistor are disabled automatically.
PC0~PC4
I/O
Pull-high
Bidirectional 5-bit input/output port. Software instructions determine the
CMOS output, Schmitt trigger input with or without pull-high resistor (determine by pull-high option: port option).
I/O
Pull-high
I/O or PWM
Bidirectional 2-bit input/output port. Software instructions determine the
CMOS output, Schmitt trigger input with or without a pull-high resistor (determined by pull-high option: port option). The PWM0/PWM1 output function are pin-shared with PD0/PD1 (dependent on PWM options).
RES
I
¾
Schmitt trigger reset input. Active low.
VDD
¾
¾
Positive power supply
VSS
¾
¾
Negative power supply, ground.
OSC1
OSC2
I
O
Crystal
or RC
TEST1
TEST2
TEST3
I
¾
PD0/PWM0
PD1/PWM1
OSC1, OSC2 are connected to an RC network or a Crystal (determined by
options) for the internal system clock. In the case of RC operation, OSC2 is
the output terminal for 1/4 system clock.
TEST mode input pin.
It disconnects in normal operation.
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V
Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V
Operating Temperature...........................-40°C to 85°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev. 2.11
3
December 29, 2008
HT46R23/HT46C23
D.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
VDD
IDD1
IDD2
Operating Voltage
Operating Current
(Crystal OSC)
Operating Current
(RC OSC)
IDD3
Operating Current
(Crystal OSC, RC OSC)
ISTB1
Standby Current
(WDT Enabled)
Min.
Typ.
Max.
Unit
Conditions
VDD
¾
fSYS=4MHz
2.2
¾
5.5
V
¾
fSYS=8MHz
3.3
¾
5.5
V
3V
No load, fSYS=4MHz
ADC disable
¾
0.6
1.5
mA
¾
2
4
mA
¾
0.8
1.5
mA
¾
2.5
4
mA
¾
4
8
mA
¾
¾
5
mA
¾
¾
10
mA
¾
¾
1
mA
¾
¾
2
mA
5V
3V
5V
5V
No load, fSYS=4MHz
ADC disable
No load, fSYS=8MHz
ADC disable
3V
No load, system HALT
5V
3V
Standby Current
(WDT Disabled)
5V
VIL1
Input Low Voltage for I/O Ports,
TMR and INT
¾
¾
0
¾
0.3VDD
V
VIH1
Input High Voltage for I/O Ports,
TMR and INT
¾
¾
0.7VDD
¾
VDD
V
VIL2
Input Low Voltage (RES)
¾
¾
0
¾
0.4VDD
V
VIH2
Input High Voltage (RES)
¾
¾
0.9VDD
¾
VDD
V
VLVR
Low Voltage Reset
¾
¾
2.7
3
3.3
V
IOL
I/O Port Sink Current
ISTB2
IOH
RPH
No load, system HALT
3V
VOL=0.1VDD
4
8
¾
mA
5V
VOL=0.1VDD
10
20
¾
mA
3V
VOH=0.9VDD
-2
-4
¾
mA
5V
VOH=0.9VDD
-5
-10
¾
mA
3V
¾
20
60
100
kW
5V
¾
10
30
50
kW
I/O Port Source Current
Pull-high Resistance
VAD
A/D Input Voltage
¾
¾
0
¾
VDD
V
EAD
A/D Conversion Error
¾
¾
¾
±0.5
±1
LSB
IADC
Additional Power Consumption
if A/D Converter is Used
3V
¾
0.5
1
mA
¾
1.5
3
mA
Rev. 2.11
¾
5V
4
December 29, 2008
HT46R23/HT46C23
A.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
fSYS
fTIMER
tWDTOSC
System Clock
Timer I/P Frequency
(TMR)
Min.
Typ.
Max.
Unit
Conditions
VDD
¾
2.2V~5.5V
400
¾
4000
kHz
¾
3.3V~5.5V
400
¾
8000
kHz
¾
2.2V~5.5V
0
¾
4000
kHz
¾
3.3V~5.5V
0
¾
8000
kHz
3V
¾
45
90
180
ms
5V
¾
32
65
130
ms
¾
1
¾
¾
ms
¾
1024
¾
*tSYS
Watchdog Oscillator Period
tRES
External Reset Low Pulse Width
¾
tSST
System Start-up Timer Period
¾
tINT
Interrupt Pulse Width
¾
¾
1
¾
¾
ms
tAD
A/D Clock Period
¾
¾
1
¾
¾
ms
tADC
A/D Conversion Time
¾
¾
¾
76
¾
tAD
tADCS
A/D Sampling Time
¾
¾
¾
32
¾
tAD
tIIC
I2C Bus Clock Period
¾
64
¾
¾
*tSYS
Wake-up from HALT
Connect to external
pull-high resistor 2kW
Note: *tSYS=1/fSYS
Rev. 2.11
5
December 29, 2008
HT46R23/HT46C23
Functional Description
Execution Flow
When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset, internal interrupt, external interrupt or return from
subroutine, the PC manipulates the program transfer by
loading the address corresponding to each instruction.
The system clock for the microcontroller is derived from
either a crystal or an RC oscillator. The system clock is
internally divided into four non-overlapping clocks. One
instruction cycle consists of four system clock cycles.
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get the proper instruction.
Otherwise proceed with the next instruction.
Instruction fetching and execution are pipelined in such
a way that a fetch takes an instruction cycle while decoding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruction to effectively execute in a cycle. If an instruction
changes the program counter, two cycles are required to
complete the instruction.
The lower byte of the program counter (PCL) is a readable and writeable register (06H). Moving data into the
PCL performs a short jump. The destination will be
within 256 locations.
Program Counter - PC
The program counter (PC) controls the sequence in
which the instructions stored in program PROM are executed and its contents specify full range of program
memory.
When a control transfer takes place, an additional
dummy cycle is required.
After accessing a program memory word to fetch an instruction code, the contents of the program counter are incremented by one. The program counter then points to the
memory word containing the next instruction code.
The program memory is used to store the program instructions which are to be executed. It also contains
data, table, and interrupt entries, and is organized into
4096´15 bits, addressed by the program counter and table pointer.
S y s te m
O S C 2 (R C
C lo c k
T 1
T 2
T 3
T 4
Program Memory - ROM
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
o n ly )
P C
P C
P C + 1
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
P C + 2
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Mode
Program Counter
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial Reset
0
0
0
0
0
0
0
0
0
0
0
0
External Interrupt
0
0
0
0
0
0
0
0
0
1
0
0
Timer/Event Counter Overflow
0
0
0
0
0
0
0
0
1
0
0
0
A/D Converter Interrupt
0
0
0
0
0
0
0
0
1
1
0
0
I2C Bus Interrupt
0
0
0
0
0
0
0
1
0
0
0
0
@0
Skip
Program Counter + 2
Loading PCL
*11
*10
*9
*8
@7
@6
@5
@4
@3
@2
@1
Jump, Call Branch
#11
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from Subroutine
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note:
*11~*0: Program counter bits
#11~#0: Instruction code bits
Rev. 2.11
S11~S0: Stack register bits
@[email protected]: PCL bits
6
December 29, 2008
HT46R23/HT46C23
0 0 0 H
Certain locations in the program memory are reserved
for special usage:
D e v ic e In itia liz a tio n P r o g r a m
0 0 4 H
· Location 000H
This area is reserved for program initialization. After
chip reset, the program always begins execution at location 000H.
E x te r n a l In te r r u p t S u b r o u tin e
0 0 8 H
T im e r /E v e n t C o u n te r In te r r u p t S u b r o u tin e
0 0 C H
A /D
· Location 004H
0 1 0 H
This area is reserved for the external interrupt service
program. If the INT input pin is activated, the interrupt
is enabled and the stack is not full, the program begins
execution at location 004H.
I2C
n 0 0 H
· Location 008H
P ro g ra m
M e m o ry
B u s In te r r u p t S u b r o u tin e
L o o k - u p T a b le ( 2 5 6 w o r d s )
n F F H
This area is reserved for the timer/event counter interrupt service program. If a timer interrupt results from a
timer/event counter overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 008H.
C o n v e r te r In te r r u p t S u b r o u tin e
F 0 0 H
L o o k - u p T a b le ( 2 5 6 w o r d s )
F F F H
1 5 b its
· Location 00CH
N o te : n ra n g e s fro m
This area is reserved for the A/D converter interrupt
service program. If an A/D converter interrupt results
from an end of A/D conversion, and if the interrupt is
enabled and the stack is not full, the program begins
execution at location 00CH.
0 to F
Program Memory
changed by the table read instruction used in the ISR.
Errors can occur. In other words, using the table read
instruction in the main routine and the ISR simultaneously should be avoided. However, if the table read
instruction has to be applied in both the main routine
and the ISR, the interrupt is supposed to be disabled
prior to the table read instruction. It will not be enabled
until the TBLH has been backed up. All table related
instructions require two cycles to complete the operation. These areas may function as normal program
memory depending upon the requirements.
· Location 010H
This area is reserved for the I2C Bus interrupt service
program. If the I2C Bus interrupt resulting from a slave
address is match or completed one byte of data transfer, and if the interrupt is enable and the stack is not
full, the program begins execution at location 010H.
· Table location
Any location in the PROM space can be used as
look-up tables. The instructions ²TABRDC [m]² (the
current page, 1 page=256 words) and ²TABRDL [m]²
(the last page) transfer the contents of the lower-order
byte to the specified data memory, and the
higher-order byte to TBLH (08H). Only the destination
of the lower-order byte in the table is well-defined, the
other bits of the table word are transferred to the lower
portion of TBLH, and the remaining 1 bit is read as ²0².
The Table Higher-order byte register (TBLH) is read
only. The table pointer (TBLP) is a read/write register
(07H), which indicates the table location. Before accessing the table, the location must be placed in
TBLP. The TBLH is read only and cannot be restored.
If the main routine and the ISR (Interrupt Service Routine) both employ the table read instruction, the contents of the TBLH in the main routine are likely to be
Stack Register - STACK
This is a special part of the memory which is used to
save the contents of the program counter (PC) only. The
stack is organized into 8 levels and is neither part of the
data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the
stack pointer (SP) and is neither readable nor writeable.
At a subroutine call or interrupt acknowledgment, the
contents of the program counter are pushed onto the
stack. At the end of a subroutine or an interrupt routine,
signaled by a return instruction (RET or RETI), the program counter is restored to its previous value from the
stack. After a chip reset, the SP will point to the top of the
stack.
Table Location
Instruction
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P11
P10
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note:
*11~*0: Table location bits
@[email protected]: Table pointer bits
Rev. 2.11
P11~P8: Current program counter bits
7
December 29, 2008
HT46R23/HT46C23
The memory pointer registers (MP0 and MP1 are 8-bit
registers).
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledgment will be inhibited. When the stack
pointer is decremented (by RET or RETI), the interrupt
will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily.
In a similar case, if the stack is full and a ²CALL² is subsequently executed, stack overflow occurs and the first
entry will be lost (only the most recent 8 return addresses are stored).
Accumulator
The accumulator is closely related to ALU operations. It
is also mapped to location 05H of the data memory and
can carry out immediate data operations. The data
movement between two data memory locations must
pass through the accumulator.
0 0 H
Data Memory - RAM
The data memory is designed with 224´8 bits. The
data memory is divided into two functional groups: special function registers and general purpose data memory (192´8). Most are read/write, but some are read
only.
M P 0
0 2 H
In d ir e c t A d d r e s s in g R e g is te r 1
0 3 H
M P 1
0 4 H
0 5 H
The special function registers include the indirect addressing registers (00H;02H), timer/event counter
higher-order byte register (TMRH;0CH), timer/event
counter low-order byte register (TMRL;0DH),
timer/event counter control register (TMRC;0EH), program counter lower-order byte register (PCL;06H),
memory pointer registers (MP0;01H, MP1;03H), accumulator (ACC;05H), table pointer (TBLP;07H), table
higher-order byte register (TBLH;08H), status register
(STATUS;0AH), interrupt control register 0 (INTC0;
0BH), PWM data register (PWM0;1AH, PWM1;1BH),
the I2C Bus slave address register (HADR;20H), the I2C
Bus control register (HCR;21H), the I2C Bus status register (HSR;22H), the I2C Bus data register (HDR;23H),
the A/D result lower-order byte register (ADRL;24H), the
A/D result higher-order byte register (ADRH;25H), the
A/D control register (ADCR;26H), the A/D clock setting
register (ACSR;27H), I/O registers (PA;12H, PB;14H,
PC;16H, PD;18H) and I/O control registers (PAC;13H,
PBC;15H, PCC;17H, PDC;19H). The remaining space
before the 40H is reserved for future expanded usage
and reading these locations will get ²00H². The general
purpose data memory, addressed from 40H to FFH, is
used for data and control information under instruction
commands.
A C C
0 6 H
P C L
0 7 H
T B L P
0 8 H
T B L H
0 9 H
0 A H
S T A T U S
0 B H
IN T C 0
0 C H
T M R H
0 D H
T M R L
0 E H
T M R C
0 F H
1 0 H
1 1 H
1 2 H
P A
1 3 H
P A C
1 4 H
P B
1 5 H
P B C
1 6 H
P C
1 7 H
P C C
1 8 H
P D
1 9 H
P D C
1 A H
P W M 0
1 B H
P W M 1
S p e c ia l P u r p o s e
D a ta M e m o ry
1 C H
1 D H
1 E H
IN T C 1
1 F H
All of the data memory areas can handle arithmetic,
logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the
data memory can be set and reset by ²SET [m].i² and
²CLR [m].i². They are also indirectly accessible through
memory pointer registers (MP0;01H/MP1;03H).
2 0 H
H A D R
2 1 H
H C R
2 2 H
H S R
2 3 H
H D R
2 4 H
A D R L
2 5 H
A D R H
2 6 H
A D C R
2 7 H
2 8 H
A C S R
3 F H
4 0 H
Indirect Addressing Register
Location 00H and 02H are indirect addressing registers
that are not physically implemented. Any read/write operation of [00H] or [02H] will access data memory
pointed to by MP0[01H] or MP1[03H] respectively.
Reading location 00H or 02H itself indirectly will return
the result 00H. Writing indirectly result in no operation.
Rev. 2.11
In d ir e c t A d d r e s s in g R e g is te r 0
0 1 H
F F H
G e n e ra l P u rp o s e
D a ta M e m o ry
(1 9 2 B y te s )
: U n u s e d
R e a d a s "0 0 "
RAM Mapping
8
December 29, 2008
HT46R23/HT46C23
Arithmetic and Logic Unit - ALU
Interrupt
This circuit performs 8-bit arithmetic and logic operations.
The ALU provides the following functions:
The device provides an external interrupt, an internal
timer/event counter interrupt, the A/D converter interrupt
and the I2C Bus interrupts. The interrupt control register
0 (INTC0;0BH) and interrupt control register 1
(INTC1;1EH) contains the interrupt control bits to set the
enable or disable and the interrupt request flags.
· Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
· Logic operations (AND, OR, XOR, CPL)
· Rotation (RL, RR, RLC, RRC)
· Increment and Decrement (INC, DEC)
Once an interrupt subroutine is serviced, all the other interrupts will be blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may happen during this interval but
only the interrupt request flag is recorded. If a certain interrupt requires servicing within the service routine, the
EMI bit and the corresponding bit of INTC0 and INTC1
may be set to allow interrupt nesting. If the stack is full,
the interrupt request will not be acknowledged, even if the
related interrupt is enabled, until the SP is decremented.
If immediate service is desired, the stack must be prevented from becoming full.
· Branch decision (SZ, SNZ, SIZ, SDZ ....)
The ALU not only saves the results of a data operation but
also changes the status register.
Status Register - STATUS
This 8-bit register (0AH) contains the zero flag (Z), carry
flag (C), auxiliary carry flag (AC), overflow flag (OV),
power down flag (PDF), and watchdog time-out flag
(TO). It also records the status information and controls
the operation sequence.
With the exception of the TO and PDF flags, bits in
the status register can be altered by instructions like
most other registers. Any data written into the status
register will not change the TO or PDF flag. In addition operations related to the status register may give
different results from those intended. The TO flag
can be affected only by system power-up, a WDT
time-out or executing the ²CLR WDT² or ²HALT² instruction. The PDF flag can be affected only by executing the ²HALT² or ²CLR WDT² instruction or a
system power-up.
All these kinds of interrupts have a wake-up capability.
As an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack, followed by
a branch to a subroutine at specified location in the program memory. Only the program counter is pushed onto
the stack. If the contents of the register or status register
(STATUS) are altered by the interrupt service program
which corrupts the desired control sequence, the contents should be saved in advance.
External interrupts are triggered by a high to low transition of INT and the related interrupt request flag (EIF; bit
4 of INTC0) will be set. When the interrupt is enabled,
the stack is not full and the external interrupt is active, a
subroutine call to location 04H will occur. The interrupt
request flag (EIF) and EMI bits will be cleared to disable
other interrupts.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
In addition, on entering the interrupt sequence or executing the subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status are important and if the subroutine can corrupt the status register, precautions must be taken to
save it properly.
Bit No.
Label
Function
0
C
C is set if the operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction.
1
AC
AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
2
Z
3
OV
OV is set if the operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
4
PDF
PDF is cleared by system power-up or executing the ²CLR WDT² instruction. PDF is set by
executing the ²HALT² instruction.
5
TO
TO is cleared by system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is
set by a WDT time-out.
6, 7
¾
Unused bit, read as ²0²
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
Status (0AH) Register
Rev. 2.11
9
December 29, 2008
HT46R23/HT46C23
²RETI² may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not.
The internal timer/event counter interrupt is initialized by
setting the timer/event counter interrupt request flag
(TF; bit 5 of INTC0), caused by a timer overflow. When
the interrupt is enabled, the stack is not full and the TF
bit is set, a subroutine call to location 08H will occur. The
related interrupt request flag (TF) will be reset and the
EMI bit cleared to disable further interrupts.
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
The A/D converter interrupt is initialized by setting the
A/D converter request flag (ADF; bit 6 of INTC0),
caused by an end of A/D conversion. When the interrupt
is enabled, the stack is not full and the ADF is set, a subroutine call to location 0CH will occur. The related interrupt request flag (ADF) will be reset and the EMI bit
cleared to disable further interrupts.
Bit No. Label
Function
0
EMI
Controls the master (global) interrupt
(1=enabled; 0=disabled)
1
EEI
Controls the external interrupt
(1=enabled; 0=disabled)
2
ETI
Controls the timer/event counter
interrupt
(1=enabled; 0=disabled)
3
EADI
4
EIF
External interrupt request flag
(1=active; 0=inactive)
5
TF
Internal timer/event counter request
flag
(1=active; 0=inactive)
6
ADF
7
¾
Interrupt Source
Priority
Vector
External Interrupt
1
04H
Timer/Event Counter Overflow
2
08H
A/D Converter Interrupt
3
0CH
Serial bus interrupt
4
10H
The timer/event counter interrupt request flag (TF), external interrupt request flag (EIF), A/D converter request
flag (ADF), the I2C Bus interrupt request flag (HIF), enable timer/event counter bit (ETI), enable external interrupt bit (EEI), enable A/D converter interrupt bit (EADI),
enable I2C Bus interrupt bit (EHI) and enable master interrupt bit (EMI) constitute an interrupt control register 0
(INTC0) and an interrupt control register 1 (INTC1)
which are located at 0BH and 1EH in the data memory.
EMI, EEI, ETI, EADI, EHI are used to control the enabling/disabling of interrupts. These bits prevent the requested interrupt from being serviced. Once the
interrupt request flags (TF, EIF, ADF, HIF) are set, they
will remain in the INTC0 and INTC1 register until the interrupts are serviced or cleared by a software instruction.
Controls the A/D converter interrupt
(1=enabled; 0=disabled)
A/D converter request flag
(1=active; 0=inactive)
For test mode used only.
Must be written as ²0²; otherwise may
result in unpredictable operation.
Bit No.
Label
0
EHI
1~3
¾
2
4
HIF
The I C Bus interrupt is initialized by setting the I C Bus
interrupt request flag (HIF; bit 4 of INTC1), caused by a
slave address match (HAAS=²1²) or one byte of data transfer is completed. When the interrupt is enabled, the stack
is not full and the HIF bit is set, a subroutine call to location
10H will occur. The related interrupt request flag (HIF) will
be reset and the EMI bit cleared to disable further interrupts.
5~7
¾
I2C Bus interrupt request flag
(1= active; 0= inactive)
Unused bit, read as ²0²
INTC1 (1EH) Register
It is recommended that a program does not use the
²CALL subroutine² within the interrupt subroutine. Interrupts often occur in an unpredictable manner or
need to be serviced immediately in some applications.
If only one stack is left and enabling the interrupt is not
well controlled, the original control sequence will be damaged once the ²CALL² operates in the interrupt subroutine.
During the execution of an interrupt subroutine, other interrupt acknowledgments are held until the ²RETI² instruction is executed or the EMI bit and the related
interrupt control bit are set to 1 (of course, if the stack is
not full). To return from the interrupt subroutine, ²RET² or
Rev. 2.11
Controls the I2C Bus interrupt
(1= enabled; 0= disabled)
Unused bit, read as ²0²
INTC0 (0BH) Register
2
Function
10
December 29, 2008
HT46R23/HT46C23
(system clock divided by 4) decided by options. This
timer is designed to prevent a software malfunction or
sequence jumping to an unknown location with unpredictable results. The watchdog timer can be disabled by
an option. If the watchdog timer is disabled, all the executions related to the WDT result in no operation.
Oscillator Configuration
There are two oscillator circuits in the microcontroller.
V
D D
O S C 1
4 7 0 p F
fS
O S C 2
Y S
O S C 1
Once an internal WDT oscillator (RC oscillator with period [email protected] normally) is selected, it is divided by
212~215 (by options to get the WDT time-out period).
The minimum period of WDT time-out period is about
300ms~600ms. This time-out period may vary with temperature, VDD and process variations. By selection the
WDT options, longer time-out periods can be realized. If
the WDT time-out is selected 215, the maximum time-out
period is divided by 215~216 about 2.1s~4.3s.
O S C 2
/4
C r y s ta l O s c illa to r
R C
O s c illa to r
System Oscillator
Both are designed for system clocks, namely the RC oscillator and the Crystal oscillator, which are determined
by options. No matter what oscillator type is selected,
the signal provides the system clock. The HALT mode
stops the system oscillator and ignores an external signal to conserve power.
If the WDT oscillator is disabled, the WDT clock may still
come from the instruction clock and operate in the same
manner except that in the halt state the WDT may stop
counting and lose its protecting purpose. In this situation
the logic can only be restarted by external logic. If the
device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT will stop the system clock.
If an RC oscillator is used, an external resistor between
OSC1 and VSS is required and the resistance must
range from 30kW to 750kW. The system clock, divided by
4, is available on OSC2 with pull-high resistor, which can
be used to synchronize external logic. The RC oscillator
provides the most cost effective solution. However, the
frequency of oscillation may vary with VDD, temperatures and the chip itself due to process variations. It is,
therefore, not suitable for timing sensitive operations
where an accurate oscillator frequency is desired.
The WDT overflow under normal operation will initialize
²chip reset² and set the status bit TO. Whereas in the halt
mode, the overflow will initialize a ²warm reset² only the
program counter and stack pointer are reset to zero. To
clear the contents of WDT, three methods are adopted; external reset (a low level to RES), software instructions, or a
HALT instruction. The software instructions include CLR
WDT and the other set - CLR WDT1 and CLR WDT2. Of
these two types of instruction, only one can be active depending on the options - ²CLR WDT times selection option². If the ²CLR WDT² is selected (i.e. CLRWDT times
equal one), any execution of the CLR WDT instruction will
clear the WDT. In case ²CLR WDT1² and ²CLR WDT2²
are chosen (i.e. CLRWDT times equal two), these two instructions must be executed to clear the WDT; otherwise,
the WDT may reset the chip because of time-out.
If the Crystal oscillator is used, a crystal across OSC1
and OSC2 is needed to provide the feedback and phase
shift required for the oscillator, and no other external
components are required. Instead of a crystal, a resonator can also be connected between OSC1 and OSC2 to
get a frequency reference, but two external capacitors in
OSC1 and OSC2 are required (If the oscillating frequency is less than 1MHz).
The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Even if
the system enters the power down mode, the system
clock is stopped, but the WDT oscillator still works with a
period of approximately [email protected] The WDT oscillator
can be disabled by options to conserve power.
If the WDT time-out period is selected fs/212 (by options),
the WDT time-out period ranges from fs/212~fs/213, since
the ²CLR WDT² or ²CLR WDT1² and ²CLR WDT2² instructions only clear the last two stages of the WDT.
Watchdog Timer - WDT
The clock source of the WDT is implemented by an dedicated RC oscillator (WDT oscillator) or instruction clock
S y s te m
C lo c k /4
M a s k
o p tio n
s e le c t
W D T
O S C
fs
D iv id e r
fs/2
8
W D T P r e s c a le r
M a s k O p tio n
W D T C le a r
C K
R
T
C K
R
T
T im e
2 1 5/fS
2 1 4/fS
2 1 3/fS
2 1 2/fS
-o
~
~
~
~
u t
2 1
2 1
2 1
2 1
6
5
R e s e t
/fS
/fS
4
/fS
3
/fS
Watchdog Timer
Rev. 2.11
11
December 29, 2008
HT46R23/HT46C23
Power Down Operation - HALT
set² that resets only the program counter and stack
pointer, leaving the other circuits in their original state.
Some registers remain unchanged during other reset
conditions. Most registers are reset to the ²initial condition² when the reset conditions are met. By examining
the PDF and TO flags, the program can distinguish between different ²chip resets².
The HALT mode is initialized by the ²HALT² instruction
and results in the following...
· The system oscillator will be turned off but the WDT os-
cillator keeps running (if the WDT oscillator is selected).
· The contents of the on chip RAM and registers remain
unchanged.
· WDT will be cleared and recounted again (if the WDT
clock is from the WDT oscillator).
· All of the I/O ports maintain their original status.
· The PDF flag is set and the TO flag is cleared.
The system can leave the HALT mode by means of an external reset, an interrupt, an external falling edge signal on
port A or a WDT overflow. An external reset causes a device initialization and the WDT overflow performs a ²warm
reset². After the TO and PDF flags are examined, the reason for chip reset can be determined. The PDF flag is
cleared by system power-up or executing the ²CLR WDT²
instruction and is set when executing the ²HALT² instruction. The TO flag is set if the WDT time-out occurs, and
causes a wake-up that only resets the program counter
and stack pointer; the others keep their original status.
TO
PDF
RESET Conditions
0
0
RES reset during power-up
u
u
RES reset during normal operation
0
1
RES wake-up HALT
1
u
WDT time-out during normal operation
1
1
WDT wake-up HALT
Note: ²u² means ²unchanged²
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the system reset (power-up, WDT time-out or RES reset) or the
system awakes from the HALT state.
V D D
The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit
in port A can be independently selected to wake up the
device by the options. Awakening from an I/O port stimulus, the program will resume execution of the next instruction. If it is awakening from an interrupt, two
sequences may happen. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the
program will resume execution at the next instruction. If
the interrupt is enabled and the stack is not full, the regular interrupt response takes place. If an interrupt request
flag is set to ²1² before entering the HALT mode, the
wake-up function of the related interrupt will be disabled.
Once a wake-up event occurs, it takes 1024 tSYS (system clock period) to resume normal operation. In other
words, a dummy period will be inserted after wake-up. If
the wake-up results from an interrupt acknowledgment,
the actual interrupt subroutine execution will be delayed
by one or more cycles. If the wake-up results in the next
instruction execution, this will be executed immediately
after the dummy period is finished.
R E S
tS
S T
S S T T im e - o u t
C h ip
R e s e t
Reset Timing Chart
V
V
D D
D D
0 .0 1 m F
1 0 0 k W
1 0 0 k W
R E S
R E S
0 .1 m F
1 0 k W
B a s ic
R e s e t
C ir c u it
H i-n o is e
R e s e t
C ir c u it
0 .1 m F
Reset Circuit
Note: Most applications can use the Basic Reset Circuit
as shown, however for applications with extensive noise,
it is recommended to use the Hi-noise Reset Circuit.
H A L T
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
W a rm
R e s e t
W D T
Reset
R E S
C o ld
R e s e t
There are three ways in which a reset can occur:
· RES reset during normal operation
O S C 1
· RES reset during HALT
S S T
1 0 - b it R ip p le
C o u n te r
· WDT time-out reset during normal operation
S y s te m
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a ²warm re -
Rev. 2.11
R e s e t
Reset Configuration
12
December 29, 2008
HT46R23/HT46C23
When a system reset occurs, the SST delay is added
during the reset period. Any wake-up from HALT will enable the SST delay. The functional unit chip reset status
are shown below.
An extra option load time delay is added during system
reset (power-up, WDT time-out at normal mode or RES
reset).
Program Counter
000H
Interrupt
Disable
WDT
Clear. After master reset, WDT
begins counting
Timer/Event Counter Off
Input/Output Ports
Input mode
Stack Pointer
Points to the top of the stack
The registers states are summarized in the following table.
Register
Reset
(Power On)
WDT Time-out
RES Reset
(Normal Operation) (Normal Operation)
RES Reset
(HALT)
WDT Time-out
(HALT)*
TMRL
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMRH
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMRC
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
000H
000H
000H
000H
000H
MP0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
-xxx xxxx
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
Program
Counter
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--01 uuuu
--11 uuuu
INTC0
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
INTC1
---0 ---0
---0 ---0
---0 ---0
---0 ---0
---u ---u
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PBC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PC
---1 1111
---1 1111
---1 1111
---1 1111
---u uuuu
PCC
---1 1111
---1 1111
---1 1111
---1 1111
---u uuuu
PD
---- --11
---- --11
---- --11
---- --11
---- --uu
PDC
---- --11
---- --11
---- --11
---- --11
---- --uu
PWM0
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
PWM1
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
HADR
xxxx xxx-
xxxx xxx-
xxxx xxx-
xxxx xxx-
uuuu uuu-
HCR
0--0 0---
0--0 0---
0--0 0---
0--0 0---
u--u u---
HSR
100- -0-1
100- -0-1
100- -0-1
100- -0-1
uuu- -u-u
HDR
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
ADRL
xx-- ----
xx-- ----
xx-- ----
xx-- ----
uuuu ----
ADRH
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
ADCR
0100 0000
0100 0000
0100 0000
0100 0000
uuuu uuuu
ACSR
1--- --00
1--- --00
1--- --00
1--- --00
u--- --uu
Note:
²*² stands for warm reset
²u² stands for unchanged
²x² stands for unknown
Rev. 2.11
13
December 29, 2008
HT46R23/HT46C23
In the pulse width measurement mode with the TON and
TE bits equal to one, once the TMR has received a transient from low to high (or high to low if the TE bits is ²0²)
it will start counting until the TMR returns to the original
level and resets the TON. The measured result will remain in the timer/event counter even if the activated
transient occurs again. In other words, only one cycle
measurement can be done. Until setting the TON, the
cycle measurement will function again as long as it receives further transient pulse. Note that, in this operating mode, the timer/event counter starts counting not
according to the logic level but according to the transient
edges. In the case of counter overflows, the counter is
reloaded from the timer/event counter preload register
and issues the interrupt request just like the other two
modes. To enable the counting operation, the timer ON
bit (TON; bit 4 of TMRC) should be set to 1. In the pulse
width measurement mode, the TON will be cleared automatically after the measurement cycle is completed.
But in the other two modes the TON can only be reset by
instructions. The overflow of the timer/event counter is
one of the wake-up sources. No matter what the operation mode is, writing a 0 to ETI can disable the interrupt
service.
Timer/Event Counter
A timer/event counter (TMR) is implemented in the
microcontroller. The timer/event counter contains an
16-bit programmable count-up counter and the clock
may come from an external source or the system clock.
Using the internal system clock, there is only one reference time-base. The internal clock source comes from
fSYS. The external clock input allows the user to count
external events, measure time intervals or pulse widths,
or to generate an accurate time base.
There are three registers related to the timer/event
counter; TMRH (0CH), TMRL (0DH), TMRC (0EH).
Writing TMRL will only put the written data to an internal
lower-order byte buffer (8 bits) and writing TMRH will
transfer the specified data and the contents of the
lower-order byte buffer to TMRH and TMRL preload registers, respectively. The timer/event counter preload
register is changed by each writing TMRH operations.
Reading TMRH will latch the contents of TMRH and
TMRL counters to the destination and the lower-order
byte buffer, respectively. Reading the TMRL will read the
contents of the lower-order byte buffer. The TMRC is the
timer/event counter control register, which defines the
operating mode, counting enable or disable and active
edge.
In the case of timer/event counter OFF condition, writing
data to the timer/event counter preload register will also
reload that data to the timer/event counter. But if the
timer/event counter is turned on, data written to it will
only be kept in the timer/event counter preload register.
The timer/event counter will still operate until overflow
occurs. When the timer/event counter (reading TMRH)
is read, the clock will be blocked to avoid errors. As
clock blocking may results in a counting error, this must
be taken into consideration by the programmer.
The TM0, TM1 bits define the operating mode. The
event count mode is used to count external events,
which means the clock source comes from an external
(TMR) pin. The timer mode functions as a normal timer
with the clock source coming from the fINT clock. The
pulse width measurement mode can be used to count the
high or low level duration of the external signal (TMR).
The counting is based on the fINT.
In the event count or timer mode, once the timer/event
counter starts counting, it will count from the current contents in the timer/event counter to FFFFH. Once overflow
occurs, the counter is reloaded from the timer/event counter preload register and generates the interrupt request
flag (TF; bit 5 of INTC0) at the same time.
The bit0~bit2 of the TMRC can be used to define the
pre-scaling stages of the internal clock sources of the
timer/event counter. The definitions are as shown. The
overflow signal of the timer/event counter can be used
to generate the PFD signal.
P W M
(6 + 2 ) o r (7 + 1 )
C o m p a re
fS
Y S
T o P D 0 /P D 1 C ir c u it
D a ta B u s
8 - s ta g e p r e s c a le r
f IN
8 -1 M U X
P S C 2 ~ P S C 0
L o w B y te
B u ffe r
T
T M 1
T M 0
T M R
1 6 - B it
P r e lo a d R e g is te r
T E
T M 1
T M 0
T O N
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
H ig h B y te
L o w
R e lo a d
O v e r flo w
B y te
to In te rru p t
1 6 - B it T im e r /E v e n t C o u n te r
1 /2
P F D
Timer/Event Counter
Rev. 2.11
14
December 29, 2008
HT46R23/HT46C23
Bit No.
0
1
2
Label
PSC0
PSC1
PSC2
3
TE
4
TON
5
¾
6
7
TM0
TM1
Function
To define the prescaler stages, PSC2, PSC1, PSC0=
000: fINT=fSYS
001: fINT=fSYS/2
010: fINT=fSYS/4
011: fINT=fSYS/8
100: fINT=fSYS/16
101: fINT=fSYS/32
110: fINT=fSYS/64
111: fINT=fSYS/128
Defines the TMR active edge of the timer/event counter:
In Event Counter Mode (TM1,TM0)=(0,1):
1:count on falling edge;
0:count on rising edge
In Pulse Width measurement mode (TM1,TM0)=(1,1):
1: start counting on the rising edge, stop on the falling edge;
0: start counting on the falling edge, stop on the rising edge
To enable or disable timer counting
(0=disabled; 1=enabled)
Unused bits, read as ²0²
To define the operating mode
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMRC (0EH) Register
Input/Output Ports
Each bit of these input/output latches can be set or
cleared by ²SET [m].i² and ²CLR [m].i² (m=12H, 14H,
16H or 18H) instructions.
There are 23 bidirectional input/output lines in the
microcontroller, labeled as PA, PB, PC and PD, which
are mapped to the data memory of [12H], [14H], [16H]
and [18H] respectively. All of these I/O ports can be
used for input and output operations. For input operation, these ports are non-latching, that is, the inputs
must be ready at the T2 rising edge of instruction ²MOV
A,[m]² (m=12H, 14H, 16H or 18H). For output operation,
all the data is latched and remains unchanged until the
output latch is rewritten.
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²CLR
[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
Each line of port A has the capability of waking-up the
device. The highest 3-bit of port C and 6-bit of port D are
not physically implemented; on reading them a ²0² is returned whereas writing then results in a no-operation.
See Application note.
Each I/O line has its own control register (PAC, PBC,
PCC, PDC) to control the input/output configuration.
With this control register, CMOS output or schmitt trigger input with or without pull-high resistor structures can
be reconfigured dynamically (i.e. on-the-fly) under software control. To function as an input, the corresponding
latch of the control register must write ²1². The input
source also depends on the control register. If the control register bit is ²1², the input will read the pad state. If
the control register bit is ²0², the contents of the latches
will move to the internal bus. The latter is possible in the
²read-modify-write² instruction.
Each I/O port has a pull-high option. Once the pull-high
option is selected, the I/O port has a pull-high resistor,
otherwise, there¢s none. Take note that a non-pull-high
I/O port operating in input mode will cause a floating
state.
The PA3 is pin-shared with the PFD signal. If the PFD
option is selected, the output signal in output mode of
PA3 will be the PFD signal generated by the timer/event
counter overflow signal. The input mode always remaining its original functions. Once the PFD option is selected, the PFD output signal is controlled by PA3 data
register only. Writing ²1² to PA3 data register will enable
the PFD output function and writing ²0² will force the
For output function, CMOS is the only configuration.
These control registers are mapped to locations 13H,
15H, 17H and 19H.
After a chip reset, these input/output lines remain at high
levels or floating state (dependent on pull-high options).
Rev. 2.11
15
December 29, 2008
HT46R23/HT46C23
V
C o n tr o l B it
D a ta B u s
W r ite C o n tr o l R e g is te r
Q
D
C K
W r ite D a ta R e g is te r
P U
P A
P A
P A
P A
P A
P A
P B
P C
P D
P D
Q
S
C h ip R e s e t
R e a d C o n tr o l R e g is te r
D D
D a ta B it
Q
D
Q
C K
0 ~ P A 2
3 /P F D
4 /T M R
5 /IN T
6 /S D A
7 /S C L
0 /A N 0 ~ P B 7 /A N 7
0 ~ P C 4
0 /P W M 0
1 /P W M 1
S
M
(P D 0 o r P W M 0 ) P A 3
(P D 1 o r P W M 1 ) P F D
M
R e a d D a ta R e g is te r
U
U
X
P F D E N
(P A 3 )
X
S y s te m W a k e -u p
( P A o n ly )
O P 0 ~ O P 7
IN T fo r P A 5 O n ly
T M R
fo r P A 4 O n ly
Input/Output Ports
PA3 to remain at ²0². The I/O functions of PA3 are
shown below.
I/O
I/P
Mode (Normal)
Logical
Input
PA3
Note:
O/P
(Normal)
I/P
(PFD)
O/P
(PFD)
Logical
Output
Logical
Input
PFD
(Timer on)
PD0/PD1. The PWM channels have their data registers
denoted as PWM0 (1AH) and PWM1 (1BH). The frequency source of the PWM counter comes from fSYS.
The PWM registers are two 8-bit registers. The waveforms of PWM outputs are as shown. Once the
PD0/PD1 are selected as the PWM outputs and the output function of PD0/PD1 are enabled (PDC.0/PDC.1
=²0²), writing ²1² to PD0/PD1 data register will enable
the PWM output function and writing ²0² will force the
PD0/PD1 to stay at ²0².
The PFD frequency is the timer/event counter
overflow frequency divided by 2.
The PA4, PA5, PA6 and PA7 are pin-shared with TMR,
INT, SDA and SCL pins respectively.
A (6+2) bits mode PWM cycle is divided into four modulation cycles (modulation cycle 0~modulation cycle 3).
Each modulation cycle has 64 PWM input clock period.
In a (6+2) bit PWM function, the contents of the PWM
register is divided into two groups. Group 1 of the PWM
register is denoted by DC which is the value of
PWM.7~PWM.2. The group 2 is denoted by AC which is
the value of PWM.1~PWM.0.
The PB can also be used as A/D converter inputs. The
A/D function will be described later. There is a PWM
function shared with PD0/PD1. If the PWM function is
enabled, the PWM0/PWM1 signal will appear on
PD0/PD1 (if PD0/PD1 is operating in output mode).
Writing ²1² to PD0/PD1 data register will enable the
PWM0/PWM1 output function and writing ²0² will force
the PD0/PD1 to remain at ²0². The I/O functions of
PD0/PD1 are as shown.
I/O
I/P
Mode (Normal)
PD0
PD1
Logical
Input
O/P
(Normal)
Logical
Output
I/P
(PWM)
Logical
Input
In a (6+2) bits mode PWM cycle, the duty cycle of each
modulation cycle is shown in the table.
Parameter
O/P
(PWM)
Duty Cycle
i<AC
DC+1
64
i³AC
DC
64
Modulation cycle i
(i=0~3)
PWM0
PWM1
It is recommended that unused or not bonded out I/O
lines should be set as output pins by software instruction
to avoid consuming power under input floating state.
A (7+1) bits mode PWM cycle is divided into two modulation cycles (modulation cycle 0 ~ modulation cycle 1).
Each modulation cycle has 128 PWM input clock period.
PWM
In a (7+1) bits PWM function, the contents of the PWM
register is divided into two groups. Group 1 of the PWM
register is denoted by DC which is the value of
The microcontroller provides 2 channels (6+2)/(7+1)
(dependent on options) bits PWM output shared with
Rev. 2.11
AC (0~3)
16
December 29, 2008
HT46R23/HT46C23
fS
/2
Y S
[P W M ] = 1 0 0
P W M
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 6 /6 4
2 6 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 6 /6 4
2 6 /6 4
2 5 /6 4
2 6 /6 4
[P W M ] = 1 0 1
P W M
[P W M ] = 1 0 2
P W M
[P W M ] = 1 0 3
P W M
2 6 /6 4
P W M
m o d u la tio n p e r io d : 6 4 /fS
M o d u la tio n c y c le 0
Y S
M o d u la tio n c y c le 1
P W M
M o d u la tio n c y c le 2
c y c le : 2 5 6 /fS
M o d u la tio n c y c le 3
M o d u la tio n c y c le 0
Y S
(6+2) PWM Mode
fS
/2
Y S
[P W M ] = 1 0 0
P W M
5 0 /1 2 8
5 0 /1 2 8
5 0 /1 2 8
5 1 /1 2 8
5 0 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 2 /1 2 8
[P W M ] = 1 0 1
P W M
[P W M ] = 1 0 2
P W M
[P W M ] = 1 0 3
P W M
5 2 /1 2 8
P W M
m o d u la tio n p e r io d : 1 2 8 /fS
Y S
M o d u la tio n c y c le 0
M o d u la tio n c y c le 1
P W M
c y c le : 2 5 6 /fS
M o d u la tio n c y c le 0
Y S
(7+1) PWM Mode
PWM.7~PWM.1. The group 2 is denoted by AC which is
the value of PWM.0.
A/D Converter
The 8 channels and 10-bit resolution A/D converter are
implemented in this microcontroller. The reference voltage is VDD. The A/D converter contains 4 special registers which are; ADRL (24H), ADRH (25H), ADCR (26H)
and ACSR (27H). The ADRH and ADRL are A/D result
register higher-order byte and lower-order byte and are
read-only. After the A/D conversion is completed, the
ADRH and ADRL should be read to get the conversion
result data. The ADCR is an A/D converter control register, which defines the A/D channel number, analog
channel select, start A/D conversion control bit and the
end of A/D conversion flag. If the users want to start an
A/D conversion, define PB configuration, select the converted analog channel, and give START bit a raising
edge and falling edge (0®1®0). At the end of A/D conversion, the EOCB bit is cleared and an A/D converter
interrupt occurs (if the A/D converter interrupt is enabled). The ACSR is A/D clock setting register, which is
used to select the A/D clock source.
In a (7+1) bits mode PWM cycle, the duty cycle of each
modulation cycle is shown in the table.
Parameter
AC (0~1)
Duty Cycle
i<AC
DC+1
128
i³AC
DC
128
Modulation cycle i
(i=0~1)
The modulation frequency, cycle frequency and cycle
duty of the PWM output signal are summarized in the
following table.
PWM
Modulation Frequency
fSYS/64 for (6+2) bits mode
fSYS/128 for (7+1) bits mode
Rev. 2.11
PWM Cycle PWM Cycle
Frequency
Duty
fSYS/256
[PWM]/256
17
December 29, 2008
HT46R23/HT46C23
START should remain at ²0² until the EOCB is cleared
to ²0² (end of A/D conversion).
The A/D converter control register is used to control the
A/D converter. The bit2~bit0 of the ADCR are used to
select an analog input channel. There are a total of eight
channels to select. The bit5~bit3 of the ADCR are used
to set PB configurations. PB can be an analog input or
as digital I/O line decided by these 3 bits. Once a PB line
is selected as an analog input, the I/O functions and
pull-high resistor of this I/O line are disabled and the A/D
converter circuit is power on. The EOCB bit (bit6 of the
ADCR) is end of A/D conversion flag. Check this bit to
know when A/D conversion is completed. The START
bit of the ADCR is used to begin the conversion of the
A/D converter. Giving START bit a rising edge and falling edge means that the A/D conversion has started. In
order to ensure the A/D conversion is completed, the
Bit No.
Label
Function
Selects the A/D converter
clock source
00= system clock/2
01= system clock/8
10= system clock/32
11= undefined
0
1
ADCS0
ADCS1
2~6
¾
Unused bit, read as ²0²
7
TEST
For test mode used only
ACSR (27H) Register
Bit No.
Label
Function
0
1
2
ACS0
ACS1
ACS2
Defines the analog channel select.
3
4
5
PCR0
PCR1
PCR2
Defines the port B configuration select. If PCR0, PCR1 and PCR2 are all zero, the ADC circuit
is power off to reduce power consumption
6
EOCB
Indicates end of A/D conversion. (0 = end of A/D conversion)
Each time bits 3~5 change state the A/D should be initialized by issuing a START signal, otherwise the EOCB flag may have an undefined condition. See ²Important note for A/D initialization².
7
START Starts the A/D conversion. (0®1®0= start; 0®1= Reset A/D converter and set EOCB to ²1²)
ADCR (26H) Register
PCR2
PCR1
PCR0
7
6
5
4
3
2
1
0
0
0
0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
0
0
1
PB7
PB6
PB5
PB4
PB3
PB2
PB1
AN0
0
1
0
PB7
PB6
PB5
PB4
PB3
PB2
AN1
AN0
0
1
1
PB7
PB6
PB5
PB4
PB3
AN2
AN1
AN0
1
0
0
PB7
PB6
PB5
PB4
AN3
AN2
AN1
AN0
1
0
1
PB7
PB6
PB5
AN4
AN3
AN2
AN1
AN0
1
1
0
PB7
PB6
AN5
AN4
AN3
AN2
AN1
AN0
1
1
1
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
Port B Configuration
ACS2
ACS1
ACS0
Analog Channel
0
0
0
AN0
0
0
1
AN1
0
1
0
AN2
0
1
1
AN3
1
0
0
AN4
1
0
1
AN5
1
1
0
AN6
1
1
1
AN7
Analog Input Channel Selection
Rev. 2.11
18
December 29, 2008
HT46R23/HT46C23
Bit 7 of the ACSR register is used for test purposes only
and must not be used for other purposes by the application program. Bit1 and bit0 of the ACSR register are
used to select the A/D clock source.
by setting the START bit high and then clearing it to zero
within 10 instruction cycles of the Port B channel selection bits being modified. Note that if the Port B channel
selection bits are all cleared to zero then an A/D initialization is not required.
When the A/D conversion has completed, the A/D interrupt request flag will be set. The EOCB bit is set to ²1²
when the START bit is set from ²0² to ²1².
Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Important Note for A/D initialization:
Special care must be taken to initialize the A/D converter each time the Port B A/D channel selection bits
are modified, otherwise the EOCB flag may be in an undefined condition. An A/D initialization is implemented
ADRL
D1
D0
¾
¾
¾
¾
¾
¾
ADRH
D9
D8
D7
D6
D5
D4
D3
D2
Note:
D0~D9 is A/D conversion result data bit
LSB~MSB.
ADRL (24H), ADRH (25H) Register
The following two programming examples illustrate how to setup and implement an A/D conversion. In the first example, the method of polling the EOCB bit in the ADCR register is used to detect when the conversion cycle is complete,
whereas in the second example, the A/D interrupt is used to determine when the conversion is complete.
Example: using EOCB Polling Method to detect end of conversion
clr
EADI
mov
a,00000001B
; disable ADC interrupt
mov
mov
ACSR,a
a,00100000B
; setup the ACSR register to select fSYS/8 as the A/D clock
; setup ADCR register to configure Port PB0~PB3 as A/D inputs
mov
ADCR,a
; and select AN0 to be connected to the A/D converter
:
:
; As the Port B channel bits have changed the following START
; signal (0-1-0) must be issued within 10 instruction cycles
:
Start_conversion:
clr
START
set
START
; reset A/D
clr
START
; start A/D
Polling_EOC:
sz
EOCB
; poll the ADCR register EOCB bit to detect end of A/D conversion
jmp
polling_EOC
; continue polling
mov
a,ADRH
; read conversion result high byte value from the ADRH register
mov
adrh_buffer,a
; save result to user defined memory
mov
a,ADRL
; read conversion result low byte value from the ADRL register
mov
adrl_buffer,a
; save result to user defined memory
:
:
jmp
start_conversion
; start next A/D conversion
Example: using interrupt method to detect end of conversion
clr
EADI
mov
a,00000001B
; disable ADC interrupt
mov
ACSR,a
; setup the ACSR register to select fSYS/8 as the A/D clock
mov
a,00100000B
; setup ADCR register to configure Port PB0~PB3 as A/D inputs
mov
ADCR,a
; and select AN0 to be connected to the A/D converter
:
; As the Port B channel bits have changed the following START
; signal (0-1-0) must be issued within 10 instruction cycles
:
Rev. 2.11
19
December 29, 2008
HT46R23/HT46C23
Start_conversion:
clr
START
set
START
; reset A/D
clr
START
; start A/D
clr
ADF
; clear ADC interrupt request flag
set
EADI
; enable ADC interrupt
set
EMI
; enable global interrupt
:
:
:
; ADC interrupt service routine
ADC_ISR:
mov
acc_stack,a
mov
a,STATUS
; save ACC to user defined memory
mov
status_stack,a
; save STATUS to user defined memory
:
:
mov
a,ADRH
; read conversion result high byte value from the ADRH register
mov
adrh_buffer,a
; save result to user defined register
mov
a,ADRL
; read conversion result low byte value from the ADRL register
mov
adrl_buffer,a
; save result to user defined register
clr
START
set
START
; reset A/D
clr
START
; start A/D
:
:
EXIT_INT_ISR:
mov
a,status_stack
mov
STATUS,a
; restore STATUS from user defined memory
mov
reti
a,acc_stack
; restore ACC from user defined memory
M in im u m
o n e in s tr u c tio n c y c le n e e d e d , M a x im u m
te n in s tr u c tio n c y c le s a llo w e d
S T A R T
E O C B
A /D
tA
P C R 2 ~
P C R 0
s a m p lin g tim e
A /D
tA
D C S
0 0 0 B
s a m p lin g tim e
A /D
tA
D C S
1 0 0 B
1 0 0 B
s a m p lin g tim e
D C S
1 0 1 B
0 0 0 B
1 . P B p o rt s e tu p a s I/O s
2 . A /D c o n v e r te r is p o w e r e d o ff
to r e d u c e p o w e r c o n s u m p tio n
A C S 2 ~
A C S 0
0 0 0 B
P o w e r-o n
R e s e t
0 1 0 B
0 0 0 B
0 0 1 B
S ta rt o f A /D
c o n v e r s io n
S ta rt o f A /D
c o n v e r s io n
S ta rt o f A /D
c o n v e r s io n
R e s e t A /D
c o n v e rte r
R e s e t A /D
c o n v e rte r
E n d o f A /D
c o n v e r s io n
1 : D e fin e P B c o n fig u r a tio n
2 : S e le c t a n a lo g c h a n n e l
tA D C
A /D c o n v e r s io n tim e
N o te :
A /D
tA D
tA
C S
D C
c lo c k m u s t b e fS
= 3 2 tA D
= 7 6 tA D
Y S
/2 , fS
Y S
/8 o r fS
Y S
R e s e t A /D
c o n v e rte r
E n d o f A /D
c o n v e r s io n
A /D
tA D C
c o n v e r s io n tim e
d o n 't c a r e
E n d o f A /D
c o n v e r s io n
A /D
tA D C
c o n v e r s io n tim e
/3 2
A/D Conversion Timing
Rev. 2.11
20
December 29, 2008
HT46R23/HT46C23
Low Voltage Reset - LVR
I2C Bus Serial Interface
The microcontroller provides low voltage reset circuit in
order to monitor the supply voltage of the device. If the
supply voltage of the device is within the range
0.9V~3.3V, such as changing a battery, the LVR will automatically reset the device internally.
I2C Bus is implemented in the device. The I2C Bus is a
bidirectional two-wire lines. The data line and clock line
are implement in SDA pin and SCL pin. The SDA and
SCL are NMOS open drain output pin. They must connect a pull-high resistor respectively.
The LVR includes the following specifications:
Using the I2C Bus, the device has two ways to transfer
data. One is in slave transmit mode, the other is in slave
receive mode. There are four registers related to I2C
Bus; HADR([20H]), HCR([21H]), HSR([22H]),
HDR([23H]). The HADR register is the slave address
setting of the device, if the master sends the calling address which match, it means that this device is selected.
The HCR is I2C Bus control register which defines the
device enable or disable the I2C Bus as a transmitter or
as a receiver. The HSR is I2C Bus status register, it responds with the I2C Bus status. The HDR is input/output
data register, data to transmit or receive must be via the
HDR register.
· The low voltage (0.9V~VLVR) has to remain in their
original state to exceed 1ms. If the low voltage state
does not exceed 1ms, the LVR will ignore it and do not
perform a reset function.
· The LVR uses the ²OR² function with the external RES
signal to perform chip reset.
The relationship between VDD and VLVR is shown below.
V D D
5 .5 V
V
O P R
5 .5 V
V
The I2C Bus control register contains three bits. The
HEN bit define the enable or disable the I2C Bus. If the
data wants transfer via I2C Bus, this bit must be set. The
HTX bit defines whether the I2C Bus is in transmit or receive mode. If the device is as a transmitter, this bit must
be set to ²1². The TXAK defines the transmit acknowledge signal, when the device received 8-bit data, the
device sends this bit to I2C Bus at the 9th clock. If the receiver wants to continue to receive the next data, this bit
must be reset to ²0² before receiving data.
L V R
3 .0 V
2 .2 V
0 .9 V
Note: VOPR is the voltage range for proper chip
operation at 4MHz system clock.
V
D D
5 .5 V
V
L V R
L V R
D e te c t V o lta g e
0 .9 V
0 V
R e s e t S ig n a l
N o r m a l O p e r a tio n
R e s e t
*1
R e s e t
*2
Low Voltage Reset
Note:
*1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system
clock pulses before entering the normal operation.
*2: Since low voltage state has to be maintained in its original state for over 1ms, therefore after 1ms delay,
the device enters the reset mode.
Rev. 2.11
21
December 29, 2008
HT46R23/HT46C23
The I2C Bus status register contains 5 bits. The HCF bit
is reset to ²0² when one data byte is being transferred. If
one data transfer is completed, this bit is set to ²1². The
HASS bit is set ²1² when the address is match, and the
I2C Bus interrupt request flag is set to ²1². If the interrupt
is enabled and the stack is not full, a subroutine call to
location 10H will occur. Writing data to the I2C Bus control register clears HAAS bit. If the address is not match,
this bit is reset to ²0². The HBB bit is set to respond the
I2C Bus is busy. It mean that a START signal is detected.
This bit is reset to ²0² when the I2C Bus is not busy. It
means that a STOP signal is detected and the I2C Bus is
free. The SRW bit defines the read/write command bit, if
the calling address is match. When HAAS is set to ²1²,
the device check SRW bit to determine whether the device is working in transmit or receive mode. When SRW
bit is set ²1², it means that the master wants to read data
from I2C Bus, the slave device must write data to I2C
Bus, so the slave device is working in transmit mode.
When SRW is reset to ²0², it means that the master
wants to write data to I2C Bus, the slave device must
read data from the bus, so the slave device is working in
receive mode. The RXAK bit is reset ²0² indicates an acknowledges signal has been received. In the transmit
mode, the transmitter checks RXAK bit to know the receiver which wants to receive the next data byte, so the
transmitter continue to write data to the I2C Bus until the
RXAK bit is set to ²1² and the transmitter releases the
SDA line, so that the master can send the STOP signal
to release the bus.
ister. At the beginning of the transfer of the I2C Bus, the
device must initial the bus, the following are the notes for
initialing the I2C Bus.
Note:
1. Write the I2C Bus address register (HADR) to define
its own slave address.
2. Set HEN bit of I2C Bus control register (HCR) bit 0 to
enable the I2C Bus.
Slave Address
Label
2~0
¾
3
Unused bit, read as ²0²
To enable or disable transmit acTXAK knowledge (0=acknowledge; 1=don¢t
acknowledge)
4
HTX
5~6
¾
7
HEN
To define the transmit/receive mode
(0= receive mode; 1= transmit)
Unused bit, read as ²0²
To enable or disable I2C Bus function
(0= disable; 1= enable)
3. Set EHI bit of the interrupt control register 1 (INTC1)
bit 0 to enable the I2C Bus interrupt.
Bit
No.
0
1
Label
¾
SRW
3~4
¾
5
HBB
Bit0
¾
The HDR register is the I2C Bus input/output data register. Before transmitting data, the HDR must write the
data which we want to transmit. Before receiving data,
the device must dummy read data from HDR. Transmit
or Receive data from I2C Bus must be via the HDR reg-
Function
RXAK is cleared to ²0² when the
master receives an 8-bit data and acRXAK knowledgment at the 9th clock,
RXAK is set to ²1² means not acknowledged.
2
Unused bit, read as ²0²
SRW is set to ²1² when the master
wants to read data from the I2C Bus,
so the slave must transmit data to the
master. SRW is cleared to ²0² when
the master wants to write data to the
I2C Bus, so the slave must receive
data from the master.
Unused bit, read as ²0²
HBB is set to ²1² when I2C Bus is
busy and HBB is cleared to ²0²
means that the I2C Bus is not busy.
6
HAAS is set to ²1² when the calling
HAAS address has matched, and I2C Bus
interrupt will occur and HIF is set.
7
HCF is clear to ²0² when one data
byte is being transferred, HCF is set
to ²1² indicating 8-bit data communication has been finished.
²¾² means undefined
HADR (20H) Register
Rev. 2.11
Function
HCR (21H) Register
The HADR bit7-bit1 define the device slave address. At
the beginning of transfer, the master must select a device by sending the address of the slave device. The bit
0 is unused and is not defined. If the I2C Bus receives a
start signal, all slave device notice the continuity of the
8-bit data. The front of 7 bits is slave address and the
first bit is MSB. If the address is match, the HAAS status
bit is set and generate an I2C Bus interrupt. In the ISR,
the slave device must check the HAAS bit to know the
I2C Bus interrupt comes from the slave address that has
match or completed one 8-bit data transfer. The last bit
of the 8-bit data is read/write command bit, it responds in
SRW bit. The slave will check the SRW bit to know if the
master wants to transmit or receive data. The device
check SRW bit to know it is as a transmitter or receiver.
Bit7~Bit1
Bit
No.
HCF
HSR (22H) Register
22
December 29, 2008
HT46R23/HT46C23
S ta rt
W r ite S la v e
A d d re s s to H A D R
S E T H E N
D is a b le
I2C B u s
In te rru p t= ?
E n a b le
C L R E H I
P o ll H IF to d e c id e
w h e n to g o to I2C B u s IS R
S E T E H I
W a it fo r In te r r u p t
G o to M a in P r o g r a m
G o to M a in P r o g r a m
S ta rt
N o
N o
R e a d fro m
Y e s
Y e s
H T X = 1
?
H D R
R E T I
Y e s
Y e s
H A A S = 1
?
R X A K = 1
?
N o
C L R H T X
C L R T X A K
W r ite to H D R
D u m m y R e a d
fro m H D R
R E T I
S R W = 1
?
N o
S E T H T X
C L R H T X
C L R T X A K
W r ite to H D R
D u m m y R e a d
F ro m H D R
R E T I
R E T I
R E T I
Rev. 2.11
23
December 29, 2008
HT46R23/HT46C23
S C L
S R W
S la v e A d d r e s s
S ta rt
0
1
S D A
1
1
0
1
0
1
D a ta
S C L
1
0
0
1
A C K
0
A C K
0
1
0
S to p
0
S D A
S =
S A
S R
M =
D =
A =
P =
S ta rt (1
= S la v e
= S R W
S la v e d
D a ta (8
A C K (R
S to p (1
S
S A
b it)
A d d r e s s ( 7 b its )
b it ( 1 b it)
e v ic e s e n d a c k n o w le d g e b it ( 1 b it)
b its )
X A K b it fo r tr a n s m itte r , T X A K b it fo r r e c e iv e r 1 b it)
b it)
S R
M
D
A
D
A
S
S A
S R
M
D
A
D
A
P
I2C Communication Timing Diagram
Start Signal
In interrupt subroutine, check HAAS bit to know whether
the I2C Bus interrupt comes from a slave address that is
matched or a data byte transfer is completed. When the
slave address is matched, the device must be in transmit mode or receive mode and write data to HDR or
dummy read from HDR to release the SCL line.
The START signal is generated only by the master device. The other device in the bus must detect the START
signal to set the I2C Bus busy bit (HBB). The START signal is SDA line from high to low, when SCL is high.
S C L
SRW Bit
The SRW bit means that the master device wants to
read from or write to the I2C Bus. The slave device
check this bit to understand itself if it is a transmitter or a
receiver. The SRW bit is set to ²1² means that the master wants to read data from the I2C Bus, so the slave device must write data to a bus as a transmitter. The SRW
is cleared to ²0² means that the master wants to write
data to the I2C Bus, so the slave device must read data
from the I2C Bus as a receiver.
S D A
Start Bit
Slave Address
The master must select a device for transferring the
data by sending the slave device address after the
START signal. All device in the I2C Bus will receive the
I2C Bus slave address (7 bits) to compare with its own
slave address (7 bits). If the slave address is matched,
the slave device will generate an interrupt and save the
following bit (8th bit) to SRW bit and sends an acknowledge bit (low level) to the 9th bit. The slave device also
sets the status flag (HAAS), when the slave address is
matched.
Rev. 2.11
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December 29, 2008
HT46R23/HT46C23
Acknowledge Bit
byte data. If the transmitter checks and there¢s no acknowledge signal, then it release the SDA line, and the
master sends a STOP signal to release the I2C Bus. The
data is stored in the HDR register. The transmitter must
write data to the HDR before transmit data and the receiver must read data from the HDR after receiving
data.
One of the slave device generates an acknowledge signal,
when the slave address is matched. The master device
can check this acknowledge bit to know if the slave device
accepts the calling address. If no acknowledge bit, the
master must send a STOP bit and end the communication.
When the I2C Bus status register bit 6 HAAS is high, it
means the address is matched, so the slave must check
SRW as a transmitter (set HTX) to ²1² or as a receiver
(clear HTX) to ²0².
S C L
S D A
S ta r t b it
S C L
S to p b it
D a ta
s ta b le
S D A
D a ta
a llo w
c h a n g e
Data Timing Diagram
Stop Bit
Receive Acknowledge Bit
When the receiver wants to continue to receive the next
data byte, it generates an acknowledge bit (TXAK) at
the 9th clock. The transmitter checks the acknowledge
bit (RXAK) to continue to write data to the I2C Bus or
change to receive mode and dummy read the HDR register to release the SDA line and the master sends the
STOP signal.
Data Byte
The data is 8 bits and is sent after the slave device has
acknowledges the slave address. The first bit is MSB
and the 8th bit is LSB. The receiver sends the acknowledge signal (²0²) and continues to receive the next one
Options
The following table shows all kinds of options in the microcontroller. All of the options must be defined to ensure proper
system function.
No.
Options
1
OSC type selection.
This option is to decide if an RC or crystal oscillator is chosen as system clock.
2
WDT source selection.
There are three types of selection: on-chip RC oscillator, instruction clock or disable the WDT.
3
CLRWDT times selection.
This option defines how to clear the WDT by instruction. ²One time² means that the CLR WDT instruction can
clear the WDT. ²Two times² means only if both of the CLR WDT1 and CLR WDT2 instructions have been executed, then WDT can be cleared.
4
Wake-up selection.
This option defines the wake-up function activity. External I/O pins (PA only) all have the capability to wake-up
the chip from a HALT.
5
Pull-high selection.
This option is to decide whether a pull-high resistance is visible or not in the input mode of the I/O ports.
PA0~PA7, can be independently selected.
6
PFD selection.
PA3: level output or PFD output
7
PWM selection: (7+1) or (6+2) mode
PD0: level output or PWM0 output
PD1: level output or PWM1 output
8
WDT time-out period selection.
212/fS~213/fS, 213/fS~214/fS, 214/fS~215/fS, 215/fS~216/fS.
9
Low voltage reset selection: Enable or disable LVR function.
10
I2C Bus selection.
PA6 and PA7: I/O or I2C Bus function
Rev. 2.11
25
December 29, 2008
HT46R23/HT46C23
Application Circuits
V
D D
V D D
P A 0 ~ P A 2
P A 3 /P F D
R e s e t
C ir c u it
1 0 0 k W
0 .1 m F
R E S
V
P A 4 /T M R
4 7 0 p F
P A 5 /IN T
P A 6 /S D A
0 .1 m F
R
P A 7 /S C L
O S C
C ir c u it
C 1
P C 0 ~ P C 4
R 1
O S C 1
P D 0 /P W M 0
O S C 2
P D 1 /P W M 1
C 2
H T 4 6 R 2 3 /H T 4 6 C 2 3
Note:
O S C
P B 0 /A N 0
P B 7 /A N 7
~
V S S
D D
O S C 1
fS
Y S
/4
R C S y s te m O s c illa to r
2 4 k W < R O S C < 1 M W
O S C 2
O S C 1
O S C 2
O S C
C r y s ta l/R e s o n a to r
S y s te m O s c illa to r
F o r R 1 , C 1 , C 2 s e e n o te
C ir c u it
1. Crystal/resonator system oscillators
For crystal oscillators, C1 and C2 are only required for some crystal frequencies to ensure oscillation. For
resonator applications C1 and C2 are normally required for oscillation to occur. For most applications it is
not necessary to add R1. However if the LVR function is disabled, and if it is required to stop the oscillator
when VDD falls below its operating range, it is recommended that R1 is added. The values of C1 and C2
should be selected in consultation with the crystal/resonator manufacturer specifications.
2. Reset circuit
The reset circuit resistance and capacitance values should be chosen to ensure that VDD is stable and remains within its operating voltage range before the RES pin reaches a high level. Ensure that the length of
the wiring connected to the RES pin is kept as short as possible, to avoid noise interference.
3. For applications where noise may interfere with the reset circuit and for details on the oscillator external
components, refer to Application Note HA0075E for more information.
Rev. 2.11
26
December 29, 2008
HT46R23/HT46C23
Instruction Set
subtract instruction mnemonics to enable the necessary
arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for
subtraction. The increment and decrement instructions
INC, INCA, DEC and DECA provide a simple means of
increasing or decreasing by a value of one of the values
in the destination specified.
Introduction
Central to the successful operation of any
microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to
perform certain operations. In the case of Holtek
microcontrollers, a comprehensive and flexible set of
over 60 instructions is provided to enable programmers
to implement their application with the minimum of programming overheads.
Logical and Rotate Operations
For easier understanding of the various instruction
codes, they have been subdivided into several functional groupings.
The standard logical operations such as AND, OR, XOR
and CPL all have their own instruction within the Holtek
microcontroller instruction set. As with the case of most
instructions involving data manipulation, data must pass
through the Accumulator which may involve additional
programming steps. In all logical data operations, the
zero flag may be set if the result of the operation is zero.
Another form of logical data manipulation comes from
the rotate instructions such as RR, RL, RRC and RLC
which provide a simple means of rotating one bit right or
left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for
serial port programming applications where data can be
rotated from an internal register into the Carry bit from
where it can be examined and the necessary serial bit
set high or low. Another application where rotate data
operations are used is to implement multiplication and
division calculations.
Instruction Timing
Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are
required. One instruction cycle is equal to 4 system
clock cycles, therefore in the case of an 8MHz system
oscillator, most instructions would be implemented
within 0.5ms and branch or call instructions would be implemented within 1ms. Although instructions which require one more cycle to implement are generally limited
to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions
which involve manipulation of the Program Counter Low
register or PCL will also take one more cycle to implement. As instructions which change the contents of the
PCL will imply a direct jump to that new address, one
more cycle will be required. Examples of such instructions would be ²CLR PCL² or ²MOV PCL, A². For the
case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then
this will also take one more cycle, if no skip is involved
then only one cycle is required.
Branches and Control Transfer
Program branching takes the form of either jumps to
specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the
sense that in the case of a subroutine call, the program
must return to the instruction immediately when the subroutine has been carried out. This is done by placing a
return instruction RET in the subroutine which will cause
the program to jump back to the address right after the
CALL instruction. In the case of a JMP instruction, the
program simply jumps to the desired location. There is
no requirement to jump back to the original jumping off
point as in the case of the CALL instruction. One special
and extremely useful set of branch instructions are the
conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program
will continue with the next instruction or skip over it and
jump to the following instruction. These instructions are
the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits.
Moving and Transferring Data
The transfer of data within the microcontroller program
is one of the most frequently used operations. Making
use of three kinds of MOV instructions, data can be
transferred from registers to the Accumulator and
vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most
important data transfer applications is to receive data
from the input ports and transfer data to the output ports.
Arithmetic Operations
The ability to perform certain arithmetic operations and
data manipulation is a necessary feature of most
microcontroller applications. Within the Holtek
microcontroller instruction set are a range of add and
Rev. 2.11
27
December 29, 2008
HT46R23/HT46C23
Bit Operations
Other Operations
The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek
microcontrollers. This feature is especially useful for
output port bit programming where individual bits or port
pins can be directly set high or low using either the ²SET
[m].i² or ²CLR [m].i² instructions respectively. The feature removes the need for programmers to first read the
8-bit output port, manipulate the input data to ensure
that other bits are not changed and then output the port
with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used.
In addition to the above functional instructions, a range
of other instructions also exist such as the ²HALT² instruction for Power-down operations and instructions to
control the operation of the Watchdog Timer for reliable
program operations under extreme electric or electromagnetic environments. For their relevant operations,
refer to the functional related sections.
Instruction Set Summary
The following table depicts a summary of the instruction
set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions.
Table Read Operations
Table conventions:
Data storage is normally implemented by using registers. However, when working with large amounts of
fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an
area of Program Memory to be setup as a table where
data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be
referenced and retrieved from the Program Memory.
Mnemonic
x: Bits immediate data
m: Data Memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Description
Cycles
Flag Affected
1
1Note
1
1
1Note
1
1
1Note
1
1Note
1Note
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
C
1
1
1
1Note
1Note
1Note
1
1
1
1Note
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
1
1Note
1
1Note
Z
Z
Z
Z
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Add Data Memory to ACC
Add ACC to Data Memory
Add immediate data to ACC
Add Data Memory to ACC with Carry
Add ACC to Data memory with Carry
Subtract immediate data from the ACC
Subtract Data Memory from ACC
Subtract Data Memory from ACC with result in Data Memory
Subtract Data Memory from ACC with Carry
Subtract Data Memory from ACC with Carry, result in Data Memory
Decimal adjust ACC for Addition with result in Data Memory
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
Logical AND Data Memory to ACC
Logical OR Data Memory to ACC
Logical XOR Data Memory to ACC
Logical AND ACC to Data Memory
Logical OR ACC to Data Memory
Logical XOR ACC to Data Memory
Logical AND immediate Data to ACC
Logical OR immediate Data to ACC
Logical XOR immediate Data to ACC
Complement Data Memory
Complement Data Memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rev. 2.11
Increment Data Memory with result in ACC
Increment Data Memory
Decrement Data Memory with result in ACC
Decrement Data Memory
28
December 29, 2008
HT46R23/HT46C23
Mnemonic
Description
Cycles
Flag Affected
Rotate Data Memory right with result in ACC
Rotate Data Memory right
Rotate Data Memory right through Carry with result in ACC
Rotate Data Memory right through Carry
Rotate Data Memory left with result in ACC
Rotate Data Memory left
Rotate Data Memory left through Carry with result in ACC
Rotate Data Memory left through Carry
1
1Note
1
1Note
1
1Note
1
1Note
None
None
C
C
None
None
C
C
Move Data Memory to ACC
Move ACC to Data Memory
Move immediate data to ACC
1
1Note
1
None
None
None
Clear bit of Data Memory
Set bit of Data Memory
1Note
1Note
None
None
Jump unconditionally
Skip if Data Memory is zero
Skip if Data Memory is zero with data movement to ACC
Skip if bit i of Data Memory is zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1Note
1note
1Note
1Note
1Note
1Note
1Note
1Note
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read table (current page) to TBLH and Data Memory
Read table (last page) to TBLH and Data Memory
2Note
2Note
None
None
No operation
Clear Data Memory
Set Data Memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACC
Enter power down mode
1
1Note
1Note
1
1
1
1Note
1
1
None
None
None
TO, PDF
TO, PDF
TO, PDF
None
None
TO, PDF
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note:
1. For skip instructions, if the result of the comparison involves a skip then two cycles are required,
if no skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by
the execution status. The TO and PDF flags are cleared after both ²CLR WDT1² and
²CLR WDT2² instructions are consecutively executed. Otherwise the TO and PDF flags
remain unchanged.
Rev. 2.11
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HT46R23/HT46C23
Instruction Definition
ADC A,[m]
Add Data Memory to ACC with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the Accumulator.
Operation
ACC ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADCM A,[m]
Add ACC to Data Memory with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADD A,[m]
Add Data Memory to ACC
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
ADD A,x
Add immediate data to ACC
Description
The contents of the Accumulator and the specified immediate data are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + x
Affected flag(s)
OV, Z, AC, C
ADDM A,[m]
Add ACC to Data Memory
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
AND A,[m]
Logical AND Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
Z
AND A,x
Logical AND immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical AND
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
Z
ANDM A,[m]
Logical AND ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
Z
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HT46R23/HT46C23
CALL addr
Subroutine call
Description
Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the
stack. The specified address is then loaded and the program continues execution from this
new address. As this instruction requires an additional operation, it is a two cycle instruction.
Operation
Stack ¬ Program Counter + 1
Program Counter ¬ addr
Affected flag(s)
None
CLR [m]
Clear Data Memory
Description
Each bit of the specified Data Memory is cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
None
CLR [m].i
Clear bit of Data Memory
Description
Bit i of the specified Data Memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
None
CLR WDT
Clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT1
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT2
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
Rev. 2.11
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HT46R23/HT46C23
CPL [m]
Complement Data Memory
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa.
Operation
[m] ¬ [m]
Affected flag(s)
Z
CPLA [m]
Complement Data Memory with result in ACC
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa. The complemented result
is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
Z
DAA [m]
Decimal-Adjust ACC for addition with result in Data Memory
Description
Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or
if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of
6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C
flag may be affected by this instruction which indicates that if the original BCD sum is
greater than 100, it allows multiple precision decimal addition.
Operation
[m] ¬ ACC + 00H or
[m] ¬ ACC + 06H or
[m] ¬ ACC + 60H or
[m] ¬ ACC + 66H
Affected flag(s)
C
DEC [m]
Decrement Data Memory
Description
Data in the specified Data Memory is decremented by 1.
Operation
[m] ¬ [m] - 1
Affected flag(s)
Z
DECA [m]
Decrement Data Memory with result in ACC
Description
Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] - 1
Affected flag(s)
Z
HALT
Enter power down mode
Description
This instruction stops the program execution and turns off the system clock. The contents
of the Data Memory and registers are retained. The WDT and prescaler are cleared. The
power down flag PDF is set and the WDT time-out flag TO is cleared.
Operation
TO ¬ 0
PDF ¬ 1
Affected flag(s)
TO, PDF
Rev. 2.11
32
December 29, 2008
HT46R23/HT46C23
INC [m]
Increment Data Memory
Description
Data in the specified Data Memory is incremented by 1.
Operation
[m] ¬ [m] + 1
Affected flag(s)
Z
INCA [m]
Increment Data Memory with result in ACC
Description
Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] + 1
Affected flag(s)
Z
JMP addr
Jump unconditionally
Description
The contents of the Program Counter are replaced with the specified address. Program
execution then continues from this new address. As this requires the insertion of a dummy
instruction while the new address is loaded, it is a two cycle instruction.
Operation
Program Counter ¬ addr
Affected flag(s)
None
MOV A,[m]
Move Data Memory to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
None
MOV A,x
Move immediate data to ACC
Description
The immediate data specified is loaded into the Accumulator.
Operation
ACC ¬ x
Affected flag(s)
None
MOV [m],A
Move ACC to Data Memory
Description
The contents of the Accumulator are copied to the specified Data Memory.
Operation
[m] ¬ ACC
Affected flag(s)
None
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
No operation
Affected flag(s)
None
OR A,[m]
Logical OR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
Z
Rev. 2.11
33
December 29, 2008
HT46R23/HT46C23
OR A,x
Logical OR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
Z
ORM A,[m]
Logical OR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²OR² [m]
Affected flag(s)
Z
RET
Return from subroutine
Description
The Program Counter is restored from the stack. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
Affected flag(s)
None
RET A,x
Return from subroutine and load immediate data to ACC
Description
The Program Counter is restored from the stack and the Accumulator loaded with the
specified immediate data. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
None
RETI
Return from interrupt
Description
The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending
when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
None
RL [m]
Rotate Data Memory left
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ [m].7
Affected flag(s)
None
RLA [m]
Rotate Data Memory left with result in ACC
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ [m].7
Affected flag(s)
None
Rev. 2.11
34
December 29, 2008
HT46R23/HT46C23
RLC [m]
Rotate Data Memory left through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RLCA [m]
Rotate Data Memory left through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces
the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RR [m]
Rotate Data Memory right
Description
The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into
bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ [m].0
Affected flag(s)
None
RRA [m]
Rotate Data Memory right with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data
Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ [m].0
Affected flag(s)
None
RRC [m]
Rotate Data Memory right through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
C
RRCA [m]
Rotate Data Memory right through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is
stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
C
Rev. 2.11
35
December 29, 2008
HT46R23/HT46C23
SBC A,[m]
Subtract Data Memory from ACC with Carry
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result
of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or
zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SBCM A,[m]
Subtract Data Memory from ACC with Carry and result in Data Memory
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SDZ [m]
Skip if decrement Data Memory is 0
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0 the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] - 1
Skip if [m] = 0
Affected flag(s)
None
SDZA [m]
Skip if decrement Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0, the program proceeds with the following instruction.
Operation
ACC ¬ [m] - 1
Skip if ACC = 0
Affected flag(s)
None
SET [m]
Set Data Memory
Description
Each bit of the specified Data Memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
None
SET [m].i
Set bit of Data Memory
Description
Bit i of the specified Data Memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
None
Rev. 2.11
36
December 29, 2008
HT46R23/HT46C23
SIZ [m]
Skip if increment Data Memory is 0
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] + 1
Skip if [m] = 0
Affected flag(s)
None
SIZA [m]
Skip if increment Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
Operation
ACC ¬ [m] + 1
Skip if ACC = 0
Affected flag(s)
None
SNZ [m].i
Skip if bit i of Data Memory is not 0
Description
If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is 0 the program proceeds with the following instruction.
Operation
Skip if [m].i ¹ 0
Affected flag(s)
None
SUB A,[m]
Subtract Data Memory from ACC
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUBM A,[m]
Subtract Data Memory from ACC with result in Data Memory
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUB A,x
Subtract immediate data from ACC
Description
The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will
be set to 1.
Operation
ACC ¬ ACC - x
Affected flag(s)
OV, Z, AC, C
Rev. 2.11
37
December 29, 2008
HT46R23/HT46C23
SWAP [m]
Swap nibbles of Data Memory
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged.
Operation
[m].3~[m].0 « [m].7 ~ [m].4
Affected flag(s)
None
SWAPA [m]
Swap nibbles of Data Memory with result in ACC
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged. The
result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC.3 ~ ACC.0 ¬ [m].7 ~ [m].4
ACC.7 ~ ACC.4 ¬ [m].3 ~ [m].0
Affected flag(s)
None
SZ [m]
Skip if Data Memory is 0
Description
If the contents of the specified Data Memory is 0, the following instruction is skipped. As
this requires the insertion of a dummy instruction while the next instruction is fetched, it is a
two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
Operation
Skip if [m] = 0
Affected flag(s)
None
SZA [m]
Skip if Data Memory is 0 with data movement to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator. If the value is
zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the
program proceeds with the following instruction.
Operation
ACC ¬ [m]
Skip if [m] = 0
Affected flag(s)
None
SZ [m].i
Skip if bit i of Data Memory is 0
Description
If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is not 0, the program proceeds with the following instruction.
Operation
Skip if [m].i = 0
Affected flag(s)
None
TABRDC [m]
Read table (current page) to TBLH and Data Memory
Description
The low byte of the program code (current page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
TABRDL [m]
Read table (last page) to TBLH and Data Memory
Description
The low byte of the program code (last page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
Rev. 2.11
38
December 29, 2008
HT46R23/HT46C23
XOR A,[m]
Logical XOR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XORM A,[m]
Logical XOR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XOR A,x
Logical XOR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical XOR
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Z
Rev. 2.11
39
December 29, 2008
HT46R23/HT46C23
Package Information
24-pin SKDIP (300mil) Outline Dimensions
A
A
1 3
2 4
B
1 3
2 4
B
1 2
1
1 2
1
H
H
C
C
D
D
E
F
I
G
E
F
I
G
Fig2. 1/2 Lead Packages
Fig1. Full Lead Packages
· MS-001d (see fig1)
Symbol
Dimensions in mil
Min.
Nom.
Max.
A
1230
¾
1280
B
240
¾
280
C
115
¾
195
D
115
¾
150
E
14
¾
22
F
45
¾
70
G
¾
100
¾
H
300
¾
325
I
¾
¾
430
· MS-001d (see fig2)
Symbol
Rev. 2.11
Dimensions in mil
Min.
Nom.
Max.
A
1160
¾
1195
B
240
¾
280
C
115
¾
195
D
115
¾
150
E
14
¾
22
F
45
¾
70
G
¾
100
¾
H
300
¾
325
I
¾
¾
430
40
December 29, 2008
HT46R23/HT46C23
· MO-095a (see fig2)
Symbol
A
Rev. 2.11
Dimensions in mil
Min.
Nom.
Max.
1145
¾
1185
B
275
¾
295
C
120
¾
150
D
110
¾
150
E
14
¾
22
F
45
¾
60
G
¾
100
¾
H
300
¾
325
I
¾
¾
430
41
December 29, 2008
HT46R23/HT46C23
28-pin SKDIP (300mil) Outline Dimensions
A
B
2 8
1 5
1
1 4
H
C
D
E
Symbol
A
Rev. 2.11
F
I
G
Dimensions in mil
Min.
Nom.
Max.
1375
¾
1395
B
278
¾
298
C
125
¾
135
D
125
¾
145
E
16
¾
20
F
50
¾
70
G
¾
100
¾
H
295
¾
315
I
¾
¾
375
42
December 29, 2008
HT46R23/HT46C23
24-pin SOP (300mil) Outline Dimensions
1 3
2 4
A
B
1 2
1
C
C '
G
H
D
E
a
F
· MS-013
Symbol
Rev. 2.11
Dimensions in mil
Min.
Nom.
Max.
A
393
¾
419
B
256
¾
300
C
12
¾
20
C¢
598
¾
613
D
¾
¾
104
E
¾
50
¾
F
4
¾
12
G
16
¾
50
H
8
¾
13
a
0°
¾
8°
43
December 29, 2008
HT46R23/HT46C23
28-pin SOP (300mil) Outline Dimensions
2 8
1 5
A
B
1
1 4
C
C '
G
H
D
E
a
F
· MS-013
Symbol
Rev. 2.11
Dimensions in mil
Min.
Nom.
Max.
A
393
¾
419
B
256
¾
300
C
12
¾
20
C¢
697
¾
713
D
¾
¾
104
E
¾
50
¾
F
4
¾
12
G
16
¾
50
H
8
¾
13
a
0°
¾
8°
44
December 29, 2008
HT46R23/HT46C23
Product Tape and Reel Specifications
Reel Dimensions
D
T 2
A
C
B
T 1
SOP 24W
Symbol
Description
Dimensions in mm
A
Reel Outer Diameter
330.0±1.0
B
Reel Inner Diameter
100.0±1.5
C
Spindle Hole Diameter
13.0+0.5/-0.2
D
Key Slit Width
T1
Space Between Flange
T2
Reel Thickness
2.0±0.5
24.8+0.3/-0.2
30.2±0.2
SOP 28W (300mil)
Symbol
Description
Dimensions in mm
A
Reel Outer Diameter
330.0±1.0
B
Reel Inner Diameter
100.0±1.5
C
Spindle Hole Diameter
13.0+0.5/-0.2
D
Key Slit Width
T1
Space Between Flange
T2
Reel Thickness
Rev. 2.11
2.0±0.5
24.8+0.3/-0.2
30.2±0.2
45
December 29, 2008
HT46R23/HT46C23
Carrier Tape Dimensions
P 0
D
P 1
t
E
F
W
C
D 1
P
B 0
K 0
A 0
R e e l H o le
IC p a c k a g e p in 1 a n d th e r e e l h o le s
a r e lo c a te d o n th e s a m e s id e .
SOP 24W
Symbol
W
Description
Dimensions in mm
Carrier Tape Width
24.0±0.3
P
Cavity Pitch
12.0±0.1
E
Perforation Position
1.75±0.1
F
Cavity to Perforation (Width Direction)
D
Perforation Diameter
1.55+0.10/-0.00
D1
Cavity Hole Diameter
1.50+0.25/-0.00
11.5±0.1
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
10.9±0.1
B0
Cavity Width
15.9±0.1
K0
Cavity Depth
3.1±0.1
t
Carrier Tape Thickness
0.35±0.05
C
Cover Tape Width
21.3±0.1
SOP 28W
Symbol
Description
Dimensions in mm
W
Carrier Tape Width
P
Cavity Pitch
12.0±0.1
E
Perforation Position
1.75±0.10
F
Cavity to Perforation (Width Direction)
11.5±0.1
D
Perforation Diameter
1.5+0.1/-0.0
D1
Cavity Hole Diameter
1.50+0.25/-0.00
24.0±0.3
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
10.85±0.10
B0
Cavity Width
18.34±0.10
K0
Cavity Depth
2.97±0.10
t
Carrier Tape Thickness
0.35±0.01
C
Cover Tape Width
21.3±0.1
Rev. 2.11
46
December 29, 2008
HT46R23/HT46C23
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor (China) Inc. (Dongguan Sales Office)
Building No. 10, Xinzhu Court, (No. 1 Headquarters), 4 Cuizhu Road, Songshan Lake, Dongguan, China 523808
Tel: 86-769-2626-1300
Fax: 86-769-2626-1311
Holtek Semiconductor (USA), Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538, USA
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com
Copyright Ó 2008 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 2.11
47
December 29, 2008