CA3242 Datasheet

CA3242
Quad-Gated Inverting Power Driver For
Interfacing Low-Level Logic to High Current Load
August 1998
Features
Description
• Driven Outputs Capable of Switching 600mA Load
Currents Without Spurious Changes in Output State
The CA3242 quad-gated inverting power driver contains four
gate switches for interfacing low-level logic to inductive and
resistive loads such as: relays, solenoids, AC and DC
motors, heaters, incandescent displays, and vacuum fluorescent displays.
• Inputs Compatible with TTL or 5V CMOS Logic
• Suitable for Resistive or Inductive Loads
• Output Overload Protection
• Power-Frame Construction for Good Heat Dissipation
Applications
• Relays
• Solenoids
Steering diodes in the outputs in conjunction with external
zener diodes protect the IC against voltage transients due to
switching inductive loads.
• AC and DC Motors
• Heaters
To allow for maximum heat transfer from the chip, the four
center leads are directly connected to the die mounting pad.
In free air, junction-to-air thermal resistance (RθJA) is 60oC/W
(typical). This coefficient can be lowered by suitable design
of the PC board to which the CA3242 is soldered.
• Incandescent Displays
• Vacuum Fluorescent Displays
Ordering Information
PART NUMBER
CA3242E
Output overload protection is provided when the load current
(approximately 1.2A) causes the output VCE(sat) to rise
above 1.3V. A built-in time delay, nominally 25µs, is provided
during output turn-on as output drops from VDD to VSAT. That
output will be shut down by its protection network without
affecting the other outputs. The corresponding Input or
Enable must be toggled to reset the output protection circuit.
TEMPERATURE
RANGE
-40oC
to
+105oC
PACKAGE
16 Lead Plastic DIP
Block Diagram
Pinout
CA3242 (PDIP)
TOP VIEW
P
IN D
OUT A 1
16 IN A
CLAMP 2
15 IN B
OUT B 3
14 ENABLE
GND 4
13 GND
GND 5
12 GND
8
OUT D
7
CLAMP
6
OUT C
9
IN C 10
P
VCC 11
GND 12
5
GND
4
GND
3
OUT B
2
CLAMP
1
OUT A
OUT C 6
11 VCC
GND 13
CLAMP 7
10 INC
ENABLE 14
OUT D 8
9 IND
P
IN B 15
P
TRUTH TABLE
ENABLE
IN
OUT
H
H
L
H
L
H
L
X
H
IN A 16
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
2-1
File Number
1561.2
Specifications CA3242
Absolute Maximum Ratings (Note 1)
Thermal Information
Logic Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V
Logic Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V
Output Voltage, VCEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50VDC
Output Sustaining Voltage, VCESUS . . . . . . . . . . . . . . . . . . . . 35VDC
Output Current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1ADC
Thermal Resistance
θJA
θJL
Plastic DIP . . . . . . . . . . . . . . . . . . . . . . 60oC/W
Plastic DIP (to Pins 4, 5, 12, 13) . . . . .
12oC/W
Power Dissipation, PD
Up to 60oC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5W
Above 60oC . . . . . . . . . . . . . . . . . . Derate Linearly at 16.6mW/oC
Up to 90oC w/Heat Sink (PC Board) . . . . . . . . . . . . . . . . . . . 1.5W
Above 90oC w/Heat Sink (PC Board). . Derate Linearly at 25mW/oC
Ambient Temperature Range
Operating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +105oC
Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +150oC
Maximum Junction Temperature, TJ . . . . . . . . . . . . . . . . . . . +150oC
Lead Temperature (During Soldering)
At distance 1/16 inch ± 1/32 inch (1.59 ± 0.79mm) from
case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
At TA = -40oC to +105oC, VCC = 5V Unless Otherwise Specified
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
MAX
UNITS
ICEX
VCE = 50V, VIN = 0.8V
-
100
µA
Output Sustaining Voltage
VCE(SUS)
IC = 100mA, VIN = 0.8V
30
-
V
Collector Emitter Saturation Voltage
VCE(SAT)
IC = 100mA, VIN = 2.4V
-
0.35
V
IC = 400mA, VIN = 2.4V
-
0.6
V
IC = 600mA, VIN = 2.4V
-
0.8
V
-
0.8
V
Output Leakage Current
Input Low Voltage
VIL
Input Low Current
IIL
VIN = 0.8V
-
±10
µA
Input High Voltage
VIH
IC = 600mA
2
-
V
Input High Current
IIH
IC = 700mA, VIN = 4.5V
-
10
µA
Supply Current ON
ICC(ON)
IC = 700mA, VCC = VIH = 5.5V
-
80
mA
Supply Current OFF
ICC(OFF)
-
5
mA
Clamp Diode Leakage Current
IR
VR = 50V
-
100
µA
Clamp Diode Forward Voltage
VF
IF = 1A
-
1.8
V
IF = 1.5A
-
2.5
V
Turn-On Delay
tPHL
-
20
µs
Turn-Off Delay
tPLH
-
30
µs
NOTE:
1. TA = +25oC, Unless Otherwise Specified
2-2
TO B OUT
3
VCC
TO B, C, D
R1
3.7
R2
1.8
R3
1.8
R4
1.8
R5
1.8
Q33
R6
0.56
Q6
Q16
Q11
Q7
A B C D
A
Q8
B
Q18
Q19
Q9 Q10
C
R20
50
Q20
C1
80
D
R22
0.46
II
D9
R23
0.30
Q37
Q34
Q39
2
CLAMP
R21
12
D8
Q38
Q17
2-3
Q4
Q24
(VREF)
Q22
Q1
TO
B, C, D
Q5
ENABLE 14
TO B, C, D
Q23
Q31
Q32
Q12
R11
0.51
R12
0.26
Q15
Q13
D1
Q14
R13
3.04
R15
4.2
D4
Q40
R19
1.8
Q28
D5
Q41
Q27
Q25
Q26
R24
50
Q30
R18
0.5
TO
B, C, D
R8
0.38
R9
2.3
R10
2.0
D3
D6
R25
50
Q35
Q29
R17
1.0
I
OUT A
D2
R7
3.05
(VSAT)
Q21
Q3
IN A 16
R16
60
D7
C2
130
Q42
R29
0.40
Q44
R28
R26
Q36 0.25
C3
130
R30
0.06
0.05
R27
40
Q43
R31
7.5
12, 13
4, 5
GND
NOTE: All resistance values are kΩ, all capacitors are in pF.
FIGURE 1. SCHEMATIC DIAGRAM OF THE CA3242 (SWITCH SECTION A)
R32
7.0
Q45
CA3242
Q2
R14
0.52
OUT B
CA3242
+
P
+
+
P
P
CLAMP
REF.
MOTOR
FWD/REV
ENABLE
PROTECTION
LATCH
LOAD
P
P
INPUT
H-DRIVER
CA3242
FIGURE 3. TYPICAL APPLICATIONS FOR THE CA3242 QUAD
FIGURE 2. LOGIC DIAGRAM FOR EACH OUTPUT
+
P
P
RELAY
P
S1
R1
LATCH - 1
S2
R2
LATCH - 2
S3
R3
LATCH - 3
S4
R4
LATCH - 4
P
+
INC. LITE
P
+
P
FLOATING
SOLENOID
P
P
GROUNDSOLENOID
CA3242
ENABLE
MISC. SWITCHING
APPLICATIONS
FIGURE 5. TYPICAL APPLICATIONS FOR THE CA3242
QUAD DRIVER
FIGURE 4. TYPICAL APPLICATIONS FOR THE CA3242
QUAD DRIVER
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result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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File Number
2-4