isl62771 - ISL62771 - Multiphase PWM Regulator for AMD

DATASHEET
Multiphase PWM Regulator for AMD Fusion™ Mobile
CPUs Using SVI 2.0
ISL62771
Features
The ISL62771 is fully compliant with AMD Fusion SVI 2.0 and
provides a complete solution for microprocessor and graphics
processor core power. The ISL62771 controller supports two
Voltage Regulators (VRs) with three integrated gate drivers. The
Core VR supports 2-, or 1-phase configurations while the
Northbridge VR supports 1-phase operation. The two VRs share a
serial control bus to communicate with the AMD CPU and achieve
lower cost and smaller board area compared with two-chip
solutions.
• Supports AMD SVI 2.0 serial data bus interface
- SVC frequency range 100kHz to 20MHz
• Dual output controller with integrated drivers
• Precision voltage regulation
- 0.5% system accuracy over-temperature
- 0.5V to 1.55V in 6.25mV steps
- Enhanced load line accuracy
The PWM modulator is based on Intersil’s Robust Ripple
Regulator R3™ Technology. Compared to traditional modulators,
the R3 modulator can automatically change switching frequency
for faster transient settling time during load transients and
improved light load efficiency.
• Supports multiple current sensing methods
- Lossless inductor DCR current sensing
- Precision resistor current sensing
• Programmable 1- or 2-phase for the core output
• Adaptive body diode conduction time reduction
The ISL62771 has several other key features. Both outputs
support DCR current sensing with single NTC thermistor for
DCR temperature compensation or accurate resistor current
sensing. Both outputs utilize remote voltage sense, adjustable
switching frequency, OC protection and power-good.
• Superior noise immunity and transient response
Applications
• Programmable VID offset and droop on both outputs
• Output current and voltage telemetry
• Differential remote voltage sensing
• High efficiency across entire load range
• AMD Fusion CPU/GPU and APU Core Power
• Programmable switching frequency for both outputs
• Notebook computers
• Excellent dynamic current balance between phases
• Protection: OCP/WOC, OVP, PGOOD and thermal monitor
• Small footprint 40 Ld 5x5 TQFN package
- Pb-free (RoHS compliant)
Core Performance
100
1.12
90
1.10
VIN = 8V
70
1.08
VIN = 12V
60
VOUT (A)
EFFICIENCY (%)
80
VIN = 19V
50
40
30
10
VIN = 12V
1.02
5
10
15
20
25 30 35
IOUT (A)
40
1
45
50
VIN = 19V
0.98
VOUT CORE = 1.1V
FIGURE 1. EFFICIENCY vs LOAD
March 25, 2015
FN8321.3
VIN = 8V
1.04
1.00
20
0
0
1.06
55
0.96
VOUT CORE = 1.1V
0
5
10
15
20
25
30
35
40
45
50
55
IOUT (A)
FIGURE 2. VOUT vs LOAD
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2012, 2013, 2015. All Rights Reserved
Intersil (and design) and R3 Technology are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL62771
Table of Contents
Simplified Application Circuit for Mid-Power CPUs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Simplified Application Circuit for Low Power CPUs [1+1 Configuration] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Simplified Application Circuit for Low Power CPUs [1+1 Configuration] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Gate Driver Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiphase R3™ Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diode Emulation and Period Stretching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Channel Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Start-up Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Regulation and Load Line Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential Sensing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phase Current Balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dynamic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adaptive Body Diode Conduction Time Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Resistor Configuration Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VR Offset Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CCM Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AMD Serial VID Interface 2.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pre-PWROK Metal VID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SVI Interface Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VID-on-the-Fly Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SVI Data Communication Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SVI Bus Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dynamic Load Line Slope Trim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dynamic Offset Trim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Telemetry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Protection Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overcurrent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current-Balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overvoltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Monitor [NTC, NTC_NB] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fault Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interface Pin Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Key Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Inductor DCR Current-Sensing Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Resistor Current-Sensing Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Load Line Slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Compensator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Monitor Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCB Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
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ISL62771
VDDP
VDD
ENABLE
Simplified Application Circuit for Mid-Power CPUs
VIN
BOOT_NB
Ri
VNB
UGATE_NB
ISUMN_NB
VNB
PHASE_NB
NTC
Cn
LGATE_NB
ISUMP_NB
NB_PH
VNB
NB_PH
IMON_NB
COMP_NB
NTC_NB
FB_NB
VSEN_NB
VR_HOT_L
VNB_SENSE
PWROK
ISL62771
IMON
SVT
µP
THERMAL INDICATOR
SVD
NTC
SVC
VDDIO
COMP
BOOT2
VIN
UGATE2
FB
PHASE2
VSEN
VCORE_SENSE
LGATE2
RTN
PH2
VO2
VCORE
PH1
ISEN1
PH2
ISEN2
BOOT1
VIN
UGATE1
PHASE1
NTC
LGATE1
PH1
VO1
PH1
PH2
ISUMP
PGOOD
Cn
GND PAD
VO2
ISUMN
PGOOD_NB
Ri
VO1
FIGURE 3. TYPICAL APPLICATION CIRCUIT USING DCR SENSING
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ISL62771
NBN
Cn
VDDP
VDD
Ri
ENABLE
Simplified Application Circuit for Low Power CPUs [1+1 Configuration]
VIN
BOOT_NB
UGATE_NB
ISUMN_NB
VNB
PHASE_NB
NTC
NBP
LGATE_NB
ISUMP_NB
NBP
NBN
IMON_NB
COMP_NB
NTC_NB
FB_NB
VSEN_NB
VR_HOT
VNB_SENSE
NTC
PWROK
SVT
µP
THERMAL INDICATOR
ISL62771
SVD
IMON
SVC
*RESISTOR REQUIRED OR ISEN1
WILL PULL HIGH IF LEFT OPEN AND
DISABLE CHANNEL 1.
VDDIO
10k*
ISEN1
+5V
ISEN2
BOOT2
OPEN
UGATE2
OPEN
PHASE2
OPEN
LGATE2
OPEN
COMP
BOOT1
FB
UGATE1
VSEN
VCORE_SENSE
VIN
VCORE
PHASE1
RTN
Cn
CoreP
ISUMN
NTC
ISUMP
CoreP
CoreN
PGOOD
CoreN
GND PAD
Ri
PGOOD_NB
LGATE1
FIGURE 4. TYPICAL APPLICATION CIRCUIT USING RESISTOR SENSING
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March 25, 2015
ISL62771
VDDP
VDD
Ri
VNB
ENABLE
Simplified Application Circuit for Low Power CPUs [1+1 Configuration]
VIN
BOOT_NB
UGATE_NB
ISUMN_NB
VNB
PHASE_NB
NTC
Cn
LGATE_NB
ISUMP_NB
NB_PH
NB_PH
VNB
IMON_NB
COMP_NB
NTC_NB
FB_NB
VSEN_NB
VR_HOT
VNB_SENSE
NTC
PWROK
SVT
µP
THERMAL INDICATOR
IMON
SVD
SVC
VDDIO
*RESISTOR REQUIRED OR ISEN1
WILL PULL HIGH IF LEFT OPEN AND 10k*
DISABLE CHANNEL 1.
+5V
ISL62771
ISEN1
ISEN2
BOOT2
OPEN
UGATE2
OPEN
PHASE2
OPEN
LGATE2
OPEN
COMP
BOOT1
FB
VIN
UGATE1
VCORE
VSEN
PHASE1
VCORE_SENSE
RTN
Cn
PH
ISUMP
PH
VO
PGOOD
ISUMN
NTC
GND PAD
Ri
VO
PGOOD_NB
LGATE1
FIGURE 5. TYPICAL APPLICATION CIRCUIT USING INDUCTOR DCR SENSING
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ISL62771
Block Diagram
VSEN_NB
BOOT_NB
COMP_NB
DRIVER
+
RTN

PHASE_NB
+
_
FB_NB
E/A
VR2
MODULATOR
IDROOP_NB
ISUMP_NB
+
ISUMN_NB
_
UGATE_NB
+
DRIVER
CURRENT
SENSE
LGATE_NB
VDD
PGOOD_NB
OC FAULT
OV FAULT
NB_V
NTC_NB
T_MONITOR
TEMP
MONITOR
NTC
VOLTAGE
A/D
VR_HOT_L
CORE_I
OFFSET
FREQ
SLEWRATE
CONFIG
NB_I
IMON
CURRENT
A/D
IMON_NB
IDROOP_NB
ENABLE
A/D
IDROOP
D/A
DAC2
DAC1
PWROK
DIGITAL
INTERFACE
SVC
VDDP
CORE_I
NB_I
SVD
TELEMETRY
SVT
BOOT2
CORE_V
DRIVER
NB_V
VDDIO
UGATE2
PHASE2
COMP
VSEN
+
RTN

+
VR1
MODULATOR
+
_
FB
E/A
DRIVER
LGATE2
BOOT1
IDROOP
ISUMP
+
ISUMN
_
CURRENT
SENSE
DRIVER
VOLTAGE
A/D
UGATE1
PHASE1
CORE_V
DRIVER
ISEN2
ISEN1
CURRENT
BALANCING
OC FAULT
LGATE1
PGOOD
IBAL FAULT
OV FAULT
GND
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6
FN8321.3
March 25, 2015
ISL62771
Pin Configuration
ISUMN_NB
VSEN_NB
FB_NB
COMP_NB
PGOOD_NB
LGATE_NB
PHASE_NB
UGATE_NB
40
39
38
37
36
35
34
33
32
BOOT_NB
ISUMP_NB
ISL62771
(40 LD TQFN)
TOP VIEW
31
NTC_NB
1
30
BOOT2
IMON_NB
2
29
UGATE2
SVC
3
28
PHASE2
VR_HOT_L
4
27
LGATE2
SVD
5
26
VDDP
VDDIO
6
25
VDD
SVT
7
24
LGATE1
ENABLE
8
23
PHASE1
PWROK
9
22
UGATE1
IMON 10
21
BOOT1
13
14
15
16
17
18
ISEN2
ISEN1
ISUMP
ISUMN
VSEN
RTN
FB
19
20
PGOOD
12
COMP
11
NTC
GND PAD
(BOTTOM)
Pin Descriptions
PIN NUMBER
SYMBOL
1
NTC_NB
2
IMON_NB
3
SVC
4
VR_HOT_L
5
SVD
6
VDDIO
VDDIO is the processor memory interface power rail and this pin serves as the reference to the controller
IC for this processor I/O signal level.
7
SVT
Serial VID Telemetry (SVT) data line input to the CPU from the controller IC. Telemetry and VID-on-the-fly
complete signal provided on from this pin.
8
ENABLE
Enable input. A high level logic on this pin enables both VRs.
9
PWROK
System power-good input. When this pin is high, the SVI 2 interface is active and the I2C protocol is
running. While this pin is low, the SVC and SVD input states determine the pre-PWROK metal VID. This
pin must be low prior to the ISL62771 PGOOD output going high per the AMD SVI 2.0 Controller
Guidelines.
10
IMON
11
NTC
12
ISEN2
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DESCRIPTION
Thermistor input to VR_HOT_L circuit to monitor Northbridge VR temperature.
Northbridge output current monitor. A current proportional to the Northbridge VR output current is
sourced from this pin.
Serial VID clock input from the CPU processor master device.
Thermal indicator signal to AMD CPU. Thermal overload open-drain output indicator active LOW.
Serial VID data bidirectional signal from the CPU processor master device to the VR.
Core output current monitor. A current proportional to the Core VR output current is sourced from this pin.
Thermistor input to VR_HOT_L circuit to monitor Core VR temperature.
7
Individual current sensing for Channel 2 of the Core VR. When ISEN2 is pulled to +5V, the controller
disables Channel 2 and the Core VR runs in single-phase mode.
FN8321.3
March 25, 2015
ISL62771
Pin Descriptions (Continued)
PIN NUMBER
SYMBOL
DESCRIPTION
13
ISEN1
Individual current sensing for Channel 1 of the Core VR. If ISEN2 is tied to +5V, this pin cannot be left
open and must be tied to GND with a 10kΩ resistor. If ISEN1 is tied to +5V, the Core portion of the IC is
shut down.
14
ISUMP
Noninverting input of the transconductance amplifier for current monitor and load line of Core output.
15
ISUMN
Inverting input of the transconductance amplifier for current monitor and load line of Core output.
16
VSEN
Output voltage sense pin for the Core controller. Connect to the +sense pin of the microprocessor die.
17
RTN
Output voltage sense return pin for both Core VR and Northbridge VR. Connect to the -sense pin of the
microprocessor die.
18
FB
19
COMP
Core controller error amplifier output. A resistor from COMP to GND sets the Core VR offset voltage.
20
PGOOD
Open-drain output to indicate the Core portion of the IC is ready to supply regulated voltage. Pull-up
externally to VDD or 3.3V through a resistor.
21
BOOT1
Connect an MLCC capacitor across the BOOT1 and the PHASE1 pins. The boot capacitor is charged,
through an internal boot diode connected from the VDDP pin to the BOOT1 pin, each time the PHASE1
pin drops below VDDP minus the voltage dropped across the internal boot diode.
22
UGATE1
Output of the Phase 1 high-side MOSFET gate driver of the Core VR. Connect the UGATE1 pin to the gate
of the Phase 1 high-side MOSFET(s).
23
PHASE1
Current return path for the Phase 1 high-side MOSFET gate driver of VR1. Connect the PHASE1 pin to the
node consisting of the high-side MOSFET source, the low-side MOSFET drain and the output inductor of
Phase 1.
24
LGATE1
Output of the Phase 1 low-side MOSFET gate driver of the Core VR. Connect the LGATE1 pin to the gate
of the Phase 1 low-side MOSFET(s).
25
VDD
5V bias power. A resistor [2Ω] and a decoupling capacitor should be used from the +5V supply. A high
quality, X7R dielectric MLCC capacitor is recommended.
26
VDDP
Input voltage bias for the internal gate drivers. Connect +5V to the VDDP pin. Decouple with at least 1µF
of capacitance to GND. A high quality, X7R dielectric MLCC capacitor is recommended.
27
LGATE2
Output of the Phase 2 low-side MOSFET gate driver of the Core VR. Connect the LGATE2 pin to the gate
of the Phase 2 low-side MOSFET(s).
28
PHASE2
Current return path for the Phase 2 high-side MOSFET gate driver of the Core VR. Connect the PHASE2
pin to the node consisting of the high-side MOSFET source, the low-side MOSFET drain and the output
inductor of Phase 2.
29
UGATE2
Output of the Phase 2 high-side MOSFET gate driver of the Core VR. Connect the UGATE2 pin to the gate
of the Phase 2 high-side MOSFET(s).
30
BOOT2
Connect an MLCC capacitor across the BOOT2 and PHASE2 pins. The boot capacitor is charged, through
an internal boot diode connected from the VDDP pin to the BOOT2 pin, each time the PHASE2 pin drops
below VDDP minus the voltage dropped across the internal boot diode.
31
BOOT_NB
Boot connection of the Northbridge VR. Connect an MLCC capacitor across the BOOT1_NB and the
PHASE_NB pins. The boot capacitor is charged, through an internal boot diode connected from the VDDP
pin to the BOOT_NB pin, each time the PHASE_NB pin drops below VDDP minus the voltage dropped
across the internal boot diode.
32
UGATE_NB
High-side MOSFET gate driver of the Northbridge VR. Connect the UGATE_NB pin to the gate of the
high-side MOSFET(s) of the Northbridge VR.
33
PHASE_NB
Phase connection of the Northbridge VR. Current return path for the high-side MOSFET gate driver of the
floating internal driver. Connect the PHASE_NB pin to the node consisting of the high-side MOSFET
source, the low-side MOSFET drain and the output inductor of the Northbridge VR.
34
LGATE_NB
Low-side MOSFET gate driver of the Northbridge VR. Connect the LGATE_NB pin to the gate of the low-side
MOSFET(s) of the Northbridge VR.
35
PGOOD_NB
Open-drain output to indicate the Northbridge portion of the IC is ready to supply regulated voltage.
Pull-up externally to VDDP or 3.3V through a resistor.
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Output voltage feedback to the inverting input of the Core controller error amplifier.
8
FN8321.3
March 25, 2015
ISL62771
Pin Descriptions (Continued)
PIN NUMBER
SYMBOL
DESCRIPTION
36
COMP_NB
Northbridge VR error amplifier output. A resistor from COMP_NB to GND sets the Northbridge VR offset
voltage and is used to set the switching frequency for the Core VR and Northbridge VR.
37
FB_NB
38
VSEN_NB
Output voltage sense pin for the Northbridge controller. Connect to the +sense pin of the microprocessor
die.
39
ISUMN_NB
Inverting input of the transconductance amplifier for current monitor and load line of the Northbridge VR.
40
ISUMP_NB
Noninverting input of the transconductance amplifier for current monitor and load line of the Northbridge
VR.
Output voltage feedback to the inverting input of the Northbridge controller error amplifier.
GND (Bottom Pad)
Signal common of the IC. All signals are referenced to the GND pin.
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP.
RANGE (°C)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
ISL62771HRTZ
62771 HRTZ
-10 to +100
40 Ld 5x5 TQFN
L40.5x5
ISL62771IRTZ
62771 IRTZ
-40 to +100
40 Ld 5x5 TQFN
L40.5x5
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials and 100% matte tin
plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL62771. For more information on MSL please see tech brief TB363.
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FN8321.3
March 25, 2015
ISL62771
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VDD, VDDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V
Battery Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +28V
Boot Voltage (BOOT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V
Boot to Phase Voltage (BOOT-PHASE) . . . . . . . . . . . . . . . . -0.3V to +7V (DC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +9V(<10ns)
Phase Voltage (PHASE) . . . . . . . . . . . . . . . . -7V (<20ns Pulse Width, 10µJ)
UGATE Voltage (UGATE) . . . . . . . . . .PHASE - 0.3V (DC) to BOOTPHASE - 5V
. . . . . . . . . . . . . . . . . (<20ns Pulse Width, 10µJ) to BOOT LGATE Voltage
. . . . . . . . . . . . . . . . . . . . . -2.5V (<20ns Pulse Width, 5µJ) to VDD + 0.3V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VDD + 0.3V)
Open-drain Outputs, PGOOD, PGOOD_NB, VR_HOT_L . . . . . . -0.3V to +7V
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
40 Ld TQFN Package (Notes 4, 5) . . . . . . .
33
3
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
Battery Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to 25V
Ambient Temperature
HRTZ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +100°C
IRTZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +100°C
Junction Temperature
HRTZ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -10°C to +125°C
IRTZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications Operating Conditions: VDD = 5V, TA = -40°C to +100°C, fSW = 300kHz, unless otherwise noted. Boldface
limits apply over the operating temperature range, -40°C to +100°C.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
8
11
mA
1
µA
4.5
V
INPUT POWER SUPPLY
+5V Supply Current
IVDD
ENABLE = 1V
ENABLE = 0V
POWER-ON-RESET THRESHOLDS
VDD POR Threshold
VDD_PORr
VDD rising
4.35
VDD_PORf
VDD falling
4.00
HRTZ
%Error (VOUT)
No load; closed loop, active mode range,
VID = 0.75V to 1.55V,
-0.5
VID = 0.25V to 0.74375V
IRTZ
%Error (VOUT)
No load; closed loop, active mode range,
VID = 0.75V to 1.55V
VID = 0.25V to 0.74375V
-12
4.15
V
SYSTEM AND REFERENCES
System Accuracy
+0.5
%
-10
+10
mV
-0.8
+0.8
%
+12
mV
Maximum Output Voltage
VOUT(max)
VID = [00000000]
1.55
V
Minimum Output Voltage
VOUT(min)
VID = [11111111]
0.0
V
CHANNEL FREQUENCY
Nominal Channel Frequency
280
fSW(nom)
300
320
kHz
+0.15
mV
+0.20
mV
AMPLIFIERS
Current-sense Amplifier Input Offset
Error Amp DC Gain
HRTZ
IFB = 0A
-0.15
IRTZ
IFB = 0A
-0.20
Av0
Error Amp Gain-bandwidth Product
GBW
CL = 20pF
119
dB
17
MHz
20
nA
ISEN
Input Bias Current
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FN8321.3
March 25, 2015
ISL62771
Electrical Specifications Operating Conditions: VDD = 5V, TA = -40°C to +100°C, fSW = 300kHz, unless otherwise noted. Boldface
limits apply over the operating temperature range, -40°C to +100°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
0.4
V
POWER-GOOD (PGOOD, PGOOD_NB) AND PROTECTION MONITORS
PGOOD Low Voltage
VOL
IPGOOD = 4mA
PGOOD Leakage Current
IOH
PGOOD = 3.3V
-1
1
PWROK High Threshold
750
VR_HOT_L Pull-down
11
µA
mV
Ω
PWROK Leakage Current
1
µA
VR_HOT_L Leakage Current
1
µA
1.5
Ω
GATE DRIVER
UGATE Pull-up Resistance
RUGPU
200mA source current
1.0
UGATE Source Current
IUGSRC
UGATE - PHASE = 2.5V
2.0
UGATE Sink Resistance
RUGPD
250mA sink current
1.0
UGATE Sink Current
IUGSNK
UGATE - PHASE = 2.5V
2.0
LGATE Pull-up Resistance
RLGPU
250mA source current
1.0
LGATE Source Current
ILGSRC
LGATE - VSSP = 2.5V
2.0
LGATE Sink Resistance
RLGPD
250mA sink current
0.5
LGATE Sink Current
ILGSNK
LGATE - VSSP = 2.5V
4.0
A
UGATE to LGATE Deadtime
tUGFLGR
UGATE falling to LGATE rising, no load
23
ns
LGATE to UGATE Deadtime
tLGFUGR
LGATE falling to UGATE rising, no load
28
ns
A
1.5
Ω
A
1.5
Ω
A
0.9
Ω
PROTECTION
Overvoltage Threshold
OVH
Undervoltage Threshold
OVH
Current Imbalance Threshold
VSEN rising above setpoint for >1µs
275
325
375
mV
VSEN falls below setpoint for >1µs
275
325
375
mV
One ISEN above another ISEN for >1.2ms
9
mV
15
µA
Way Overcurrent Trip Threshold
[IMONx Current Based Detection]
IMONxWOC
All states, IDROOP = 60µA, RIMON = 135kΩ
Overcurrent Trip Threshold
[IMONx Voltage Based Detection]
VIMONx_OCP
All states, IDROOP = 45µA,
IIMONx = 11.25µA, RIMON = 135kΩ
1.485
1.51
1.535
V
1
V
LOGIC THRESHOLDS
ENABLE Input Low
VIL
ENABLE Input High
ENABLE Leakage Current
VIH
HRTZ
1.6
V
VIH
IRTZ
1.65
V
IENABLE
ENABLE = 0V
-1
ENABLE = 1V
SVT Impedance
0
1
µA
18
35
µA
20
MHz
30
%
50
SVC Frequency Range
0.1
SVC, SVD Input Low
VIL
% of VDDIO
SVC, SVD Input High
VIH
% of VDDIO
SVC, SVD Leakage
Ω
70
%
ENABLE = 0V, SVC, SVD = 0V and 1V
-1
1
µA
ENABLE = 1V, SVC, SVD = 1V
-5
1
µA
ENABLE = 1V, SVC, SVD = 0V
-35
-5
µA
-20
THERMAL MONITOR
NTC Source Current
NTC = 0.6V
NTC Thermal Warning Voltage
27
30
33
µA
600
640
680
mV
NTC Thermal Warning Voltage
Hysteresis
20
NTC Thermal Shutdown Voltage
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530
11
580
mV
630
mV
FN8321.3
March 25, 2015
ISL62771
Electrical Specifications Operating Conditions: VDD = 5V, TA = -40°C to +100°C, fSW = 300kHz, unless otherwise noted. Boldface
limits apply over the operating temperature range, -40°C to +100°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
8
10
12
mV/µs
SLEW RATE
VID-on-the-Fly Slew Rate
Soft-start Slew Rate
10
mV/µs
NOTE:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
Gate Driver Timing Diagram
PWM
tLGFUGR
tFU
tRU
1V
UGATE
1V
LGATE
tRL
tFL
tUGFLGR
FIGURE 6. GATE DRIVER TIMING DIAGRAM
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FN8321.3
March 25, 2015
ISL62771
Theory of Operation
VW
Multiphase R3™ Modulator
MASTER CLOCK CIRCUIT
MASTER
CLOCK
COMP
PHASE
VCRM
SEQUENCER
GMVO
COMP
MASTER
CLOCK
CLOCK1
PWM1
CLOCK2
PWM2
VW
MASTER
CLOCK
HYSTERETIC
WINDOW
VCRM
The ISL62771 is a multiphase regulator implementing two voltage
regulators, CORE VR and Northbridge (NB) VR, on one chip
controlled by AMD’s SVI2 protocol. The CORE VR can be
programmed for 1- or 2-phase operation. The Northbridge VR only
supports 1-phase operation. Both regulators use the Intersil
patented R3™ (Robust Ripple Regulator) modulator. The R3™
modulator combines the best features of fixed frequency PWM
and hysteretic PWM while eliminating many of their shortcomings.
Figure 7 conceptually shows the multiphase R3™ modulator
circuit and Figure 8 shows the operation principles.
CLOCK1
CLOCK2
CLOCK3
CLOCK3
PWM3
CRM
VW
SLAVE CIRCUIT 1
VW
CLOCK1
S
R
VCRS1
Q
PWM1
PHASE1
L1
IL1
VO
CO
GM
SLAVE CIRCUIT 2
CLOCK2
S
R
VCRS2
Q
PWM2
PHASE2
L2
IL2
GM
CRS2
SLAVE CIRCUIT 3
VW
CLOCK3
VCRS3
S
R
Q
PWM3
PHASE3
L3
IL3
GM
CRS3
FIGURE 7. R3™ MODULATOR CIRCUIT
Inside the IC, the modulator uses the master clock circuit to
generate the clocks for the slave circuits. The modulator
discharges the ripple capacitor Crm with a current source equal
to gmVo, where gm is a gain factor. Crm voltage VCRM is a
sawtooth waveform traversing between the VW and COMP
voltages. It resets to VW when it hits COMP and generates a
one-shot master clock signal. A phase sequencer distributes the
master clock signal to the slave circuits. In this example, the
CORE VR is in 3-phase mode, the master clock signal is
distributed to the three phases and the Clock 1~3 signals will be
120° out-of-phase. If the Core VR is in 2-phase mode, the master
clock signal is distributed to Phases 1 and 2 and the Clock1 and
Clock2 signals will be 180° out-of-phase. If the Core VR is in
1-phase mode, the master clock signal will be distributed to
Phase 1 only and be the Clock1 signal.
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13
VCRS3
VCRS1
FIGURE 8. R3™ MODULATOR OPERATION PRINCIPLES IN
STEADY STATE
CRS1
VW
VCRS2
Each slave circuit has its own ripple capacitor Crs, whose voltage
mimics the inductor ripple current. A gm amplifier converts the
inductor voltage into a current source to charge and discharge
Crs. The slave circuit turns on its PWM pulse upon receiving the
clock signal and the current source charges Crs. When Crs
voltage VCrs hits VW, the slave circuit turns off the PWM pulse
and the current source discharges Crs.
Since the controller works with Vcrs, which are large amplitude
and noise-free synthesized signals, it achieves lower phase jitter
than conventional hysteretic mode and fixed PWM mode
controllers. Unlike conventional hysteretic mode converters, the
error amplifier allows the ISL62771 to maintain a 0.5% output
voltage accuracy.
Figure 9 shows the operation principles during load insertion
response. The COMP voltage rises during load insertion,
generating the master clock signal more quickly, so the PWM
pulses turn on earlier, increasing the effective switching
frequency. This allows for higher control loop bandwidth than
conventional fixed frequency PWM controllers. The VW voltage
rises as the COMP voltage rises, making the PWM pulses wider.
During load release response, the COMP voltage falls. It takes
the master clock circuit longer to generate the next master clock
signal so the PWM pulse is held off until needed. The VW voltage
falls as the COMP voltage falls, reducing the current PWM pulse
width. This kind of behavior gives the ISL62771 excellent
response speed.
The fact that all the phases share the same VW window voltage,
also ensures excellent dynamic current balance among phases.
FN8321.3
March 25, 2015
ISL62771
Figure 11 shows the operation principle in diode emulation mode
at light load. The load gets incrementally lighter in the three cases
from top to bottom. The PWM on-time is determined by the VW
window size and therefore is the same, making the inductor
current triangle the same in the three cases. The ISL62771 clamps
the ripple capacitor voltage VCRS in DE mode to make it mimic the
inductor current. It takes the COMP voltage longer to hit VCRS,
naturally stretching the switching period. The inductor current
triangles move farther apart such that the inductor current
average value is equal to the load current. The reduced switching
frequency helps increase light-load efficiency.
VW
COMP
VCRM
MASTER
CLOCK
CLOCK1
PWM1
CLOCK2
VW
PWM2
CCM/DCM
BOUNDARY
V CRS
CLOCK3
PWM3
IL
VW
VW LIGHT DCM
V CRS
VCRS1
VCRS3
VCRS2
IL
FIGURE 9. R3™ MODULATOR OPERATION PRINCIPLES IN LOAD
INSERTION RESPONSE
VW
DEEP DCM
V CRS
Diode Emulation and Period Stretching
The ISL62771 can operate in Diode Emulation (DE) mode to
improve light-load efficiency. In DE mode, the low-side MOSFET
conducts when the current is flowing from source-to-drain and
does not allow reverse current, thus emulating a diode. Figure 10
shows that when LGATE is on, the low-side MOSFET carries current,
creating negative voltage on the phase node due to the voltage
drop across the ON-resistance. The ISL62771 monitors the current
by monitoring the phase node voltage. It turns off LGATE when the
phase node voltage reaches zero to prevent the inductor current
from reversing the direction and creating unnecessary power loss.
PHASE
IL
FIGURE 11. PERIOD STRETCHING
Channel Configuration
Individual PWM channels of the Core VR can be disabled by
connecting the ISENx pin of the channel not required to +5V. For
example, placing the controller in a 1+1 configuration as shown
in Figure 3 on page 3 requires ISEN2 of the Core VR to be tied to
+5V. This disables Channel 2 of the Core VR. ISEN1 must be tied
through a 10kΩ resistor to GND to prevent this pin from pulling
high and disabling the channel. Connecting ISEN1 to +5V will
disable the Core VR output.
Power-on Reset
UGATE
LGATE
IL
FIGURE 10. DIODE EMULATION
If the load current is light enough (see Figure 10), the inductor
current reaches and stays at zero before the next phase node
pulse and the regulator is in discontinuous conduction mode
(DCM). If the load current is heavy enough, the inductor current
will never reach 0A and the regulator is in CCM, although the
controller is in DE mode.
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Before the controller has sufficient bias to guarantee proper
operation, the ISL62771 requires a +5V input supply tied to VDD
and VDDP to exceed the VDD rising power-on reset (POR)
threshold. Once this threshold is reached or exceeded, the
ISL62771 has enough bias to check the state of the SVI inputs
once ENABLE is taken high. Hysteresis between the rising and
the falling thresholds assure the ISL62771 does not
inadvertently turn off unless the bias voltage drops substantially
(see “Electrical Specifications” on page 10). Note that VIN must
be present for the controller to drive the output voltage.
FN8321.3
March 25, 2015
ISL62771
1
2
4
3
5
6
7
8
VDD
SVC
SVD
VOTF
SVT
Telemetry
Telemetry
ENABLE
PWROK
METAL_VID
VCORE/ VCORE_NB
V_SVI
PGOOD & PGOOD_NB
Interval 1 to 2: ISL62771 waits to POR.
Interval 2 to 3: SVC and SVD are externally set to pre-Metal VID code.
Interval 3 to 4: ENABLE locks pre-Metal VID code. Both outputs soft-start to this level.
Interval 4 to 5: PGOOD signal goes HIGH, indicating proper operation.
Interval 5 to 6: PGOOD and PGOOD_NB high is detected and PWROK is taken high. The ISL62771 is prepared for SVI commands.
Interval 6 to 7: SVC and SVD data lines communicate change in VID code.
Interval 7 to 8: ISL62771 responds to VID-ON-THE-FLY code change and issues a VOTF for positive VID changes.
Post 8: Telemetry is clocked out of the ISL62771.
FIGURE 12. SVI INTERFACE TIMING DIAGRAM: TYPICAL PRE-PWROK METAL VID START-UP
Start-up Timing
With the controller's VDD POR threshold exceeded and VIN voltage
present, the start-up sequence begins when ENABLE exceeds the
logic high threshold. Figure 13 shows the typical start-up timing of
Core and Northbridge VRs. The ISL62771 uses a digital soft-start
to ramp-up the DAC to the voltage programmed by the Metal VID.
PGOOD is asserted high at the end of the ramp-up. Similar results
occur if ENABLE is tied to VDD, with the soft-start sequence
starting 8ms after VDD crosses the POR threshold.
Voltage Regulation and Load Line
Implementation
After the soft-start sequence, the ISL62771 regulates the output
voltages to the pre-PWROK metal VID programmed, see Table 5.
The ISL62771 controls the no load output voltage to an accuracy
of ±0.5% over the range of 0.75V to 1.55V. A differential amplifier
allows voltage sensing for precise voltage regulation at the
microprocessor die.
RDROOP
VDD
+
VCCSENSE
-
FB
SLEW RATE
ENABLE
VDROOP
VR LOCAL VO
MetalVID
CATCH RESISTOR
IDROOP
VID COMMAND VOLTAGE
+
8ms
SVC
E/A
COMP
DAC
-
DAC
SVD
SVID[7:0]
VDAC
+
RTN
PGOOD
VSSSENSE
+
INTERNAL TO IC
PWROK
VSS
CATCH RESISTOR
VIN
FIGURE 13. TYPICAL SOFT-START WAVEFORMS
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15
FIGURE 14. DIFFERENTIAL SENSING AND LOAD LINE
IMPLEMENTATION
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March 25, 2015
ISL62771
to the RTN pin. These resistors, typically 10Ω~100Ω, provide voltage
feedback if the system is powered up without a processor installed.
As the load current increases from zero, the output voltage
droops from the VID programmed value by an amount
proportional to the load current, to achieve the load line.
The ISL62771 can sense the inductor current through the
intrinsic DC Resistance (DCR) of the inductors, as shown in
Figures 3 and 5, or through resistors in series with the inductors
as shown in Figure 4. In both methods, capacitor Cn voltage
represents the total inductor current. An amplifier converts Cn
voltage into an internal current source with the gain set by
resistor Ri, see Equation 1. This ISUM current is used for load line
implementation, current monitoring on the IMON pins and
overcurrent protection.
V Cn
I sum = ----------Ri
(EQ. 1)
Figure 14 shows the load line implementation. The ISL62771
drives a current source (Idroop) out of the FB pin, as described by
Equation 2.
5
5 V Cn
I droop = --- xI sum = --- x ----------4
4 Ri
(EQ. 2)
When using inductor DCR current sensing, a single NTC element
is used to compensate the positive temperature coefficient of the
copper winding, thus sustaining the load line accuracy with
reduced cost.
Idroop flows through resistor Rdroop and creates a voltage drop as
shown in Equation 3.
V droop = R droop  I droop
(EQ. 3)
Vdroop is the droop voltage required to implement load line.
Changing Rdroop or scaling Idroop can change the load line slope.
Since Isum sets the overcurrent protection level, it is
recommended to first scale Isum based on OCP requirement,
then select an appropriate Rdroop value to obtain the desired
load line slope.
Differential Sensing
Figure 14 also shows the differential voltage sensing scheme.
VCCSENSE and VSSSENSE are the remote voltage sensing signals
from the processor die. A unity gain differential amplifier senses
the VSSSENSE voltage and adds it to the DAC output. The error
amplifier regulates the inverting and non-inverting input voltages
to be equal as shown in Equation 4:
VCC SENSE + V
droop
= V DAC + VSS SENSE
Phase Current Balancing
INTERNAL
TO IC
ISEN2
Cisen
ISEN1
PHASE1
Risen
The VCCSENSE and VSSSENSE signals come from the processor die.
The feedback is an open circuit in the absence of the processor. As
Figure 14 shows, it is recommended to add a “catch” resistor to
feed the VR local output voltage back to the compensator and to
add another “catch” resistor to connect the VR local output ground
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IL2
Rdcr1
L1
Rpcb1
IL1
The ISL62771 monitors individual phase average current by
monitoring the ISEN1 and ISEN2 voltages. Figure 15 shows the
recommended current balancing circuit for DCR sensing. Each
phase node voltage is averaged by a low-pass filter consisting of
Risen and Cisen and is presented to the corresponding ISEN pin.
Risen should be routed to the inductor phase-node pad in order to
eliminate the effect of phase node parasitic PCB DCR.
Equations 6 and 7 give the ISEN pin voltages:
V ISEN1 =  R dcr1 + R pcb1   I L1
(EQ. 6)
V ISEN2 =  R dcr2 + R pcb2   I L2
(EQ. 7)
Where Rdcr1 and Rdcr2 are inductor DCR; Rpcb1 and Rpcb2 are
parasitic PCB DCR between the inductor output side pad and the
output voltage rail; and IL1 and IL2 are inductor average currents.
The ISL62771 adjusts the phase pulse-width relative to the other
phases to make VISEN1 = VISEN2, thus to achieve IL1 = IL2, when
Rdcr1 = Rdcr2 and Rpcb1 = Rpcb2.
Using the same components for L1 and L2 provides a good
match of Rdcr1 and Rdcr2. Board layout determines Rpcb1 and
Rpcb2. It is recommended to have a symmetrical layout for the
power delivery path between each inductor and the output
voltage rail, such that Rpcb1 = Rpcb2.
V2p
PHASE2
Risen
INTERNAL
TO IC
(EQ. 5)
VO
FIGURE 15. CURRENT BALANCING CIRCUIT
ISEN2
VCC SENSE – VSS SENSE = V DAC – R droop  I droop
Rpcb2
Cisen
(EQ. 4)
Rewriting Equation 4 and substituting Equation 3 gives
Equation 5. The exact equation required for load line
implementation.
Rdcr2
L2
PHASE2
Risen
ISEN1
IL2
Risen
Cisen
Rpcb2
Vo
V2n
Risen
PHASE1 V1p
Risen
Risen
C isen
Rdcr2
L2
Rdcr1
L1
IL1
Rpcb1
V1n
Risen
FIGURE 16. DIFFERENTIAL-SENSING CURRENT BALANCING
CIRCUIT
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March 25, 2015
ISL62771
Sometimes it is difficult to implement symmetrical layout. For
the circuit shown in Figure 15, asymmetric layout causes
different Rpcb1 and Rpcb2 values, thus creating a current
imbalance. Figure 16 shows a differential sensing current
balancing circuit recommended for ISL62771. The current
sensing traces should be routed to the inductor pads so they only
pick up the inductor DCR voltage. Each ISEN pin sees the average
voltage of two sources: its own, phase inductor phase-node pad
and the other phase inductor output side pad. Equations 8 and 9
give the ISEN pin voltages:
V ISEN1 = V 1p + V 2n
(EQ. 8)
V ISEN2 = V 1n + V 2p
(EQ. 9)
REP RATE = 10kHz
REP RATE = 25kHz
The ISL62771 will make VISEN1 = VISEN2 as shown in
Equation 10:
V 1p + V 2n = V 1n + V 2p
(EQ. 10)
Rewriting Equation 10 gives Equation 11:
V 1p – V 1n = V 2p – V 2n
(EQ. 11)
Therefore:
R dcr1  I L1 = R dcr2  I L2
(EQ. 12)
REP RATE = 50kHz
Current balancing (IL1 = IL2) is achieved when Rdcr1 = Rdcr2 .
Rpcb1and Rpcb2 do not have any effect.
Since the slave ripple capacitor voltages mimic the inductor
currents, the R3™ modulator can naturally achieve excellent
current balancing during steady state and dynamic operations.
Figure 17 shows the current balancing performance of the
evaluation board with load transient of 12A/51A at different rep
rates. The inductor currents follow the load current dynamic
change with the output capacitors supplying the difference. The
inductor currents can track the load current well at a low
repetition rate, but cannot keep up when the repetition rate gets
into the hundred-kHz range, where it is out of the control loop
bandwidth. The controller achieves excellent current balancing in
all cases installed.
REP RATE = 100kHz
REP RATE = 200kHz
FIGURE 17. CURRENT BALANCING DURING DYNAMIC OPERATION.
CH1: IL1 , CH2: ILOAD, CH3: IL2, CH4: IL3
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March 25, 2015
ISL62771
Modes of Operation
VID transitions, the output voltage decays to the lower VID value
at the slew rate determined by the load.
TABLE 1. CORE VR MODES OF OPERATION
CONFIG.
PSL0_L
AND
PSI1_L
ISEN2
MODE
2-phase Core To Power
VR Config.
Stage
11
2-phase CCM
01
1-phase DE
00
1-phase DE
1-phase Core Tied to 5V
VR Config.
11
1-phase CCM
01
1-phase DE
00
1-phase DE
IMON OCP
THRESHOLD
(V)
1.5
1.5
The Core VR can be configured for 2- or 1-phase operation.
Table 1 shows Core VR configurations and operational modes,
programmed by the ISEN2 pin status and the PSL0_L & PSL1_L
commands via the SVI 2 interface, see Table 8 on page 22.
For a 1-phase configuration, tie the ISEN2 pin to 5V. In this
configuration, only Phase 1 is active.
For 2-phase configurations, the Core VR operates in 2-phase CCM
with PSI0_L and PSI_L both high. If PSI0_L is taken low via the
SVI 2 interface, the Core VR sheds Phase 2 and the Core VR
enters 1-phase DE mode. When both PSI0_L and PSI1_L are
taken low, the Core VR continues to operate in the 1-phase DE
mode.
In a 1-phase configuration, the Core VR operates in 1-phase CCM
and enters 1-phase DE when PSI0_L is taken low and continues
to operate in this mode when both PSI0_l and PSI1_L are taken
low.
The Core VR can be disabled completely by connecting ISEN1 to
+5V.
ISL62771 Northbridge VR operates in 1-phase CCM.
Table 2 shows the Northbridge VR operational modes, which are
programmed by the PSI0_L and PSI1_L bits of the SVI 2
command.
TABLE 2. NORTHBRIDGE VR MODES OF OPERATION
CONFIG.
1-phase NB VR
Config.
PSL0_L and
PSI1_L
MODE
11
1-phase CCM
01
1-phase DE
00
1-phase DE
IMON OCP
THRESHOLD
1.5V
The Northbridge VR operates in 1-phase CCM and enters 1-phase
DE when PSI0_L goes low and remains in this mode of operation
when both PSI0_L and PSI1_L are low.
The R3™ modulator intrinsically has voltage feed-forward. The
output voltage is insensitive to a fast slew rate input voltage
change.
Adaptive Body Diode Conduction Time
Reduction
In DCM, the controller turns off the low-side MOSFET when the
inductor current approaches zero. During on-time of the low-side
MOSFET, phase voltage is negative and the amount is the
MOSFET rDS(ON) voltage drop, which is proportional to the
inductor current. A phase comparator inside the controller
monitors the phase voltage during on-time of the low-side
MOSFET and compares it with a threshold to determine the zero
crossing point of the inductor current. If the inductor current has
not reached zero when the low-side MOSFET turns off, it will flow
through the low-side MOSFET body diode, causing the phase
node to have a larger voltage drop until it decays to zero. If the
inductor current has crossed zero and reversed the direction
when the low-side MOSFET turns off, it will flow through the
high-side MOSFET body diode, causing the phase node to have a
spike until it decays to zero. The controller continues monitoring
the phase voltage after turning off the low-side MOSFET. To
minimize the body diode-related loss, the controller also adjusts
the phase comparator threshold voltage accordingly in iterative
steps such that the low-side MOSFET body diode conducts for
approximately 40ns.
Resistor Configuration Options
The ISL62771 uses the COMP and COMP_NB pins to configure
some functionality within the IC. Resistors from these pins to GND
are read during the first portion of the soft-start sequence. The
following sections outline how to select the resistor values for each
of these pins to correctly program the output voltage offset of each
output and switching frequency used for both VRs.
VR Offset Programming
A positive or negative offset is programmed for the Core VR using
a resistor to ground from the COMP pin and the Northbridge in a
similar manner from the COMP_NB pin. Table 3 provides the
resistor value to select the desired output voltage offset. The 1%
tolerance resistor value shown in the table must be used to
program the corresponding Core or NB output voltage offset. The
MIN and MAX tolerance values provide margin to insure the 1%
tolerance resistor will be read correctly.
The Core and Northbridge VRs have an overcurrent threshold of
1.5V on IMON and IMON_NB respectively and this level does not
vary based on channel configuration. See “Overcurrent” on
page 23 for more details.
Dynamic Operation
Core VR and Northbridge VR behave the same during dynamic
operation. The controller responds to VID-on-the-fly changes by
slewing to the new voltage at a fixed slew rate. During negative
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March 25, 2015
ISL62771
AMD Serial VID Interface 2.0
TABLE 3. COMP AND COMP_NB OUTPUT VOLTAGE OFFSET
SELECTION
5.54
5.62
5.70
-43.75
18.75
7.76
7.87
7.98
-37.5
31.25
The on-board Serial VID Interface 2.0 (SVI 2) circuitry allows the
AMD processor to directly control the Core and Northbridge
voltage reference levels within the ISL62771. Once the PWROK
signal goes high, the IC begins monitoring the SVC and SVD pins
for instructions. The ISL62771 uses a digital-to-analog converter
(DAC) to generate a reference voltage based on the decoded SVI
value. See Figure 12 for a simple SVI interface timing diagram.
11.33
11.5
11.67
-31.25
43.76
Pre-PWROK Metal VID
16.65
16.9
17.15
-25
50
19.3
19.6
19.89
-18.75
37.5
24.53
24.9
25.27
-12.5
25
33.49
34.0
34.51
-6.25
12.5
40.58
41.2
41.81
6.25
0
51.52
52.3
53.08
18.75
18.75
72.10
73.2
74.29
31.25
31.25
93.87
95.3
96.72
43.76
43.76
119.19
121
112.81
50
50
151.69
154
156.31
37.5
37.5
179.27
182
184.73
25
25
206.85
210
213.15
12.5
12.5
0
0
RESISTOR VALUE [kΩ]
COMP_NB
COMP
MIN
1% TOLERANCE
MAX
VCORE OFFSET OFFSET
TOLERANCE
VALUE
TOLERANCE
[mV]
[mV]
OPEN
CCM Switching Frequency
The Core and Northbridge VR switching frequency is set by the
programming resistor on COMP_NB. When the ISL62771 is in
continuous conduction mode (CCM), the switching frequency is
not absolutely constant due to the nature of the R3™ modulator.
As explained in the “Multiphase R3™ Modulator” on page 13, the
effective switching frequency increases during load insertion and
decreases during load release to achieve fast response. Thus, the
switching frequency is relatively constant at steady state.
Variation is expected when the power stage condition, such as
input voltage, output voltage, load, etc. changes. The variation is
usually less than 10% and does not have any significant effect on
output voltage ripple magnitude. Table 4 defines the switching
frequency based on the resistor value used to program the
COMP_NB pin. Use the previous table related to COMP_NB to
determine the correct resistor value in these ranges to program
the desired output offset and switching frequency configuration.
TABLE 4. SWITCHING FREQUENCY SELECTION
FREQUENCY
[kHz]
COMP_NB RANGE
[kΩ]
300
57.6 to OPEN
400
5.62 to 41.2
The controller monitors SVI commands to determine when to
enter power-saving mode, implement dynamic VID changes and
shut down individual outputs.
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Typical motherboard start-up begins with the controller decoding
the SVC and SVD inputs to determine the pre-PWROK Metal VID
setting (see Table 5). Once the ENABLE input exceeds the rising
threshold, the ISL62771 decodes and locks the decoded value
into an on-board hold register.
TABLE 5. PRE-PWROK METAL VID CODES
SVC
SVD
OUTPUT VOLTAGE
(V)
0
0
1.1
0
1
1.0
1
0
0.9
1
1
0.8
The internal DAC circuitry begins to ramp Core and Northbridge
VRs to the decoded pre-PWROK Metal VID output level. The
digital soft-start circuitry ramps the internal reference to the
target gradually at a fixed rate of 10mV/µs. The controlled ramp
of all output voltage planes reduces in-rush current during the
soft-start interval. At the end of the soft-start interval, the PGOOD
and PGOOD_NB outputs transition high, indicating both output
planes are within regulation limits.
If the ENABLE input falls below the enable falling threshold, the
ISL62771 tri-states both outputs. PGOOD and PGOOD_NB are
pulled low with the loss of ENABLE. The Core and Northbridge VR
output voltages decay, based on output capacitance and load
leakage resistance. If bias to VDD falls below the POR level, the
ISL62771 responds in the manner previously described. Once
VDD and ENABLE rise above their respective rising thresholds,
the internal DAC circuitry reacquires a pre-PWROK metal VID
code and the controller soft-starts.
SVI Interface Active
Once the Core and Northbridge VRs have successfully
soft-started and PGOOD and PGOOD_NB signals transition high,
PWROK can be asserted externally to the ISL62771. Once
PWROK is asserted to the IC, SVI instructions can begin as the
controller actively monitors the SVI interface. Details of the SVI
Bus protocol are provided in the “AMD Serial VID Interface 2.0
(SVI2) Specification”. See AMD publication #48022.
Once a VID change command is received, the ISL62771 decodes
the information to determine which VR is affected and the VID
target is determined by the byte combinations in Table 6. The
internal DAC circuitry steps the output voltage of the VR
commanded to the new VID level. During this time, one or more
of the VR outputs could be targeted. In the event either VR is
FN8321.3
March 25, 2015
ISL62771
commanded to power-off by serial VID commands, the PGOOD
signal remains asserted.
If the PWROK input is deasserted, then the controller steps both
the Core and the Northbridge VRs back to the stored pre-PWROK
metal VID level in the holding register from initial soft-start. No
attempt is made to read the SVC and SVD inputs during this time.
If PWROK is reasserted, then the ISL62771 SVI interface waits
for instructions.
If ENABLE goes low during normal operation, all external
MOSFETs are tri-stated and both PGOOD and PGOOD_NB are
pulled low. This event clears the pre-PWROK metal VID code and
forces the controller to check SVC and SVD upon restart, storing
the pre-PWROK metal VID code found on restart.
A POR event on VCC during normal operation shuts down both
regulators and both PGOOD outputs are pulled low. The
pre-PWROK metal VID code is not retained. Loss of VIN during
operation will typically cause the controller to enter a fault
condition on one or both outputs. The controller will shut down
both Core and Northbridge VRs and latch off. The pre-PWROK
metal VID code is not retained during the process of cycling
ENABLE to reset the fault latch and restart the controller.
VID-on-the-Fly Transition
Once PWROK is high, the ISL62771 detects this flag and begins
monitoring the SVC and SVD pins for SVI instructions. The
microprocessor follows the protocol outlined in the following
sections to send instructions for VID-on-the-fly transitions. The
ISL62771 decodes the instruction and acknowledges the new
VID code. For VID codes higher than the current VID level, the
ISL62771 begins stepping the commanded VR outputs to the
new VID target at the fixed slew rate of 10mV/µs. Once the DAC
ramps to the new VID code, a VID-on-the-Fly Complete (VOTFC)
request is sent on the SVI lines.
When the VID codes are lower than the current VID level, the
ISL62771 checks the state of power state bits in the SVI
command. If power state bits are not active, the controller begins
stepping the regulator output to the new VID target. If the power
state bits are active, the controller allows the output voltage to
decay and slowly steps the DAC down with the natural decay of
the output. This allows the controller to quickly recover and move
to a high VID code if commanded. The controller issues a VOTFC
request on the SVI lines once the SVI command is decoded and
prior to reaching the final output voltage.
VOTFC requests do not take priority over telemetry per the AMD
SVI 2 specification.
SVI Data Communication Protocol
The SVI WIRE protocol is based on the I2C bus concept. Three
wires [serial clock (SVC) and serial data (SVD) and telemetry
(SVT)], carry information between the AMD processor (master)
and VR controller (slave) on the bus. The master initiates and
terminates SVI transactions and drives the clock, SVC, during a
transaction. The AMD processor is always the master and the
voltage regulators are the slaves. The slave receives the SVI
transactions and acts accordingly. Mobile SVI WIRE protocol
timing is based on high-speed mode I2C. See AMD publication
#48022 for additional details.
TABLE 6. SERIAL VID CODES
SVID[7:0]
VOLTAGE (V)
SVID[7:0]
VOLTAGE (V)
SVID[7:0]
VOLTAGE (V)
SVID[7:0]
VOLTAGE (V)
0000_0000
1.55000
0010_0000
1.35000
0100_0000
1.15000
0110_0000
0.95000
0000_0001
1.54375
0010_0001
1.34375
0100_0001
1.14375
0110_0001
0.94375
0000_0010
1.53750
0010_0010
1.33750
0100_0010
1.13750
0110_0010
0.93750
0000_0011
1.53125
0010_0011
1.33125
0100_0011
1.13125
0110_0011
0.93125
0000_0100
1.52500
0010_0100
1.32500
0100_0100
1.12500
0110_0100
0.92500
0000_0101
1.51875
0010_0101
1.31875
0100_0101
1.11875
0110_0101
0.91875
0000_0110
1.51250
0010_0110
1.31250
0100_0110
1.11250
0110_0110
0.91250
0000_0111
1.50625
0010_0111
1.30625
0100_0111
1.10625
0110_0111
0.90625
0000_1000
1.50000
0010_1000
1.30000
0100_1000
1.10000
0110_1000
0.90000
0000_1001
1.49375
0010_1001
1.29375
0100_1001
1.09375
0110_1001
0.89375
0000_1010
1.48750
0010_1010
1.28750
0100_1010
1.08750
0110_1010
0.88750
0000_1011
1.48125
0010_1011
1.28125
0100_1011
1.08125
0110_1011
0.88125
0000_1100
1.47500
0010_1100
1.27500
0100_1100
1.07500
0110_1100
0.87500
0000_1101
1.46875
0010_1101
1.26875
0100_1101
1.06875
0110_1101
0.86875
0000_1110
1.46250
0010_1110
1.26250
0100_1110
1.06250
0110_1110
0.86250
0000_1111
1.45625
0010_1111
1.25625
0100_1111
1.05625
0110_1111
0.85625
0001_0000
1.45000
0011_0000
1.25000
0101_0000
1.05000
0111_0000
0.85000
0001_0001
1.44375
0011_0001
1.24375
0101_0001
1.04375
0111_0001
0.84375
0001_0010
1.43750
0011_0010
1.23750
0101_0010
1.03750
0111_0010
0.83750
0001_0011
1.43125
0011_0011
1.23125
0101_0011
1.03125
0111_0011
0.83125
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March 25, 2015
ISL62771
TABLE 6. SERIAL VID CODES (Continued)
SVID[7:0]
VOLTAGE (V)
SVID[7:0]
VOLTAGE (V)
SVID[7:0]
VOLTAGE (V)
SVID[7:0]
VOLTAGE (V)
0001_0100
1.42500
0011_0100
1.22500
0101_0100
1.02500
0111_0100
0.82500
0001_0101
1.41875
0011_0101
1.21875
0101_0101
1.01875
0111_0101
0.81875
0001_0110
1.41250
0011_0110
1.21250
0101_0110
1.01250
0111_0110
0.81250
0001_0111
1.40625
0011_0111
1.20625
0101_0111
1.00625
0111_0111
0.80625
0001_1000
1.40000
0011_1000
1.20000
0101_1000
1.00000
0111_1000
0.80000
0001_1001
1.39375
0011_1001
1.19375
0101_1001
0.99375
0111_1001
0.79375
0001_1010
1.38750
0011_1010
1.18750
0101_1010
0.98750
0111_1010
0.78750
0001_1011
1.38125
0011_1011
1.18125
0101_1011
0.98125
0111_1011
0.78125
0001_1100
1.37500
0011_1100
1.17500
0101_1100
0.97500
0111_1100
0.77500
0001_1101
1.36875
0011_1101
1.16875
0101_1101
0.96875
0111_1101
0.76875
0001_1110
1.36250
0011_1110
1.16250
0101_1110
0.96250
0111_1110
0.76250
0001_1111
1.35625
0011_1111
1.15625
0101_1111
0.95625
0111_1111
0.75625
1000_0000
0.75000
1010_0000
0.55000*
1100_0000
0.35000*
1110_0000
0.15000*
1000_0001
0.74375
1010_0001
0.54375*
1100_0001
0.34375*
1110_0001
0.14375*
1000_0010
0.73750
1010_0010
0.53750*
1100_0010
0.33750*
1110_0010
0.13750*
1000_0011
0.73125
1010_0011
0.53125*
1100_0011
0.33125*
1110_0011
0.13125*
1000_0100
0.72500
1010_0100
0.52500*
1100_0100
0.32500*
1110_0100
0.12500*
1000_0101
0.71875
1010_0101
0.51875*
1100_0101
0.31875*
1110_0101
0.11875*
1000_0110
0.71250
1010_0110
0.51250*
1100_0110
0.31250*
1110_0110
0.11250*
1000_0111
0.70625
1010_0111
0.50625*
1100_0111
0.30625*
1110_0111
0.10625*
1000_1000
0.70000
1010_1000
0.50000*
1100_1000
0.30000*
1110_1000
0.10000*
1000_1001
0.69375
1010_1001
0.49375*
1100_1001
0.29375*
1110_1001
0.09375*
1000_1010
0.68750
1010_1010
0.48750*
1100_1010
0.28750*
1110_1010
0.08750*
1000_1011
0.68125
1010_1011
0.48125*
1100_1011
0.28125*
1110_1011
0.08125*
1000_1100
0.67500
1010_1100
0.47500*
1100_1100
0.27500*
1110_1100
0.07500*
1000_1101
0.66875
1010_1101
0.46875*
1100_1101
0.26875*
1110_1101
0.06875*
1000_1110
0.66250
1010_1110
0.46250*
1100_1110
0.26250*
1110_1110
0.06250*
1000_1111
0.65625
1010_1111
0.45625*
1100_1111
0.25625*
1110_1111
0.05625*
1001_0000
0.65000
1011_0000
0.45000*
1101_0000
0.25000*
1111_0000
0.05000*
1001_0001
0.64375
1011_0001
0.44375*
1101_0001
0.24375*
1111_0001
0.04375*
1001_0010
0.63750
1011_0010
0.43750*
1101_0010
0.23750*
1111_0010
0.03750*
1001_0011
0.63125
1011_0011
0.43125*
1101_0011
0.23125*
1111_0011
0.03125*
1001_0100
0.62500
1011_0100
0.42500*
1101_0100
0.22500*
1111_0100
0.02500*
1001_0101
0.61875
1011_0101
0.41875*
1101_0101
0.21875*
1111_0101
0.01875*
1001_0110
0.61250
1011_0110
0.41250*
1101_0110
0.21250*
1111_0110
0.01250*
1001_0111
0.60625
1011_0111
0.40625*
1101_0111*
0.20625*
1111_0111
0.00625*
1001_1000
0.60000*
1011_1000
0.40000*
1101_1000
0.20000*
1111_1000
OFF*
1001_1001
0.59375*
1011_1001
0.39375*
1101_1001
0.19375*
1111_1001
OFF*
1001_1010
0.58750*
1011_1010
0.38750*
1101_1010
0.18750*
1111_1010
OFF*
1001_1011
0.58125*
1011_1011
0.38125*
1101_1011
0.18125*
1111_1011
OFF*
1001_1100
0.57500*
1011_1100
0.37500*
1101_1100
0.17500*
1111_1100
OFF*
1001_1101
0.56875*
1011_1101
0.36875*
1101_1101
0.16875*
1111_1101
OFF*
1001_1110
0.56250*
1011_1110
0.36250*
1101_1110
0.16250*
1111_1110
OFF*
1001_1111
0.55625*
1011_1111
0.35625*
1101_1111
0.15625*
1111_1111
OFF*
NOTE: *Indicates a VID not required for AMD Family 10h processors. Loosened AMD requirements at these levels.
Submit Document Feedback
21
FN8321.3
March 25, 2015
1
SVC
2
3
4
5
6
7
8
9
10
VID
bit [0]
VID bits [7:1]
11
12
13
14
16
15
17
18
19
PSI1_L
PSI0_L
ISL62771
20
21
22
23
24
25
26
27
SVD
START
FIGURE 18. SVD PACKET STRUCTURE
SVI Bus Protocol
The AMD processor bus protocol is compliant with SMBus send
byte protocol for VID transactions. The AMD SVD packet structure
is shown in Figure 18. The description of what each bit of the
three bytes that make up the SVI command are shown in Table 7.
During a transaction, the processor sends the start sequence
followed by each of the three bytes, which end with an optional
acknowledge bit. The ISL62771 does not drive the SVD line
during the ACK bit. Finally, the processor sends the stop
sequence. After the ISL62771 has detected the stop, it can then
proceed with the commanded action from the transaction.
TABLE 7. SVD DATA PACKET
BITS
1:5
For the 1-Phase Northbridge VR, when PSI0_L is asserted,
Channel 1 enters diode emulation mode to boost efficiency.
When PSI0_L and PSI1_L are asserted low, the Northbridge VR
continues to operate in this fashion.
It is possible for the processor to assert or deassert PSI0_L and
PSI1_L out of order. PSI0_L takes priority over PSI1_L. If PSI0_L
is deasserted while PSI1_L is still asserted, the ISL62771 will
return the selected VR back full channel CCM operation.
TABLE 8. PSI0_L, PSI1_L AND TFN DEFINITION
FUNCTION
BIT
DESCRIPTION
PSI0_L
10
Power State Indicate level 0. When this signal is
asserted (active Low) the processor is in a low
enough power state for the VR controller to take
action to boost efficiency by dropping phases and/or
entering 1-Phase DE.
PSI1_L
20
Power State Indicate level 1. When this signal is
asserted (active Low) the processor is in a low
enough power state for the VR controller to take
action to boost efficiency by dropping phases and
entering 1-Phase DE.
TFN
21
Telemetry Functionality. This is an active high signal
that allows the processor to control the telemetry
functionality of the VR.
DESCRIPTION
Always 11000b
6
Core domain selector bit, if set then the following data byte
contains VID, power state, telemetry control, load line trim and
offset trim apply to the Core VR.
7
Northbridge domain selector bit, if set then the following data
byte contains VID, power state, telemetry control, load line trim
and offset trim apply to the Northbridge VR.
8
Always 0b
9
Acknowledge Bit
10
PSI0_L
Dynamic Load Line Slope Trim
11:17 VID Code bits [7:1]
18
Acknowledge Bit
19
VID Code bit [0]
20
PSI1_L
21
TFN (Telemetry Functionality)
LOAD LINE
SLOPE TRIM [2:0]
25:26 Offset Trim [1:0]
Acknowledge Bit
Power States
SVI2 defines two power state indicator levels, see Table 8. As
processor current consumption reduces the power state indicator
level changes to improve VR efficiency under low power
conditions.
For the Core VR operating in 2-phase mode, when PSI0_L is
asserted, Channel 2 is tri-stated and Channel 1 enters diode
emulation mode to boost efficiency. When PSI0_L and PSI1_L
are asserted low, the Core VR continues to operate in this mode.
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The ISL62771 supports the SVI2 ability for the processor to
manipulate the load line slope of the Core and Northbridge VRs
independently using the serial VID interface. The slope
manipulation applies to the initial load line slope. A load line
slope trim will typically coincide with a VOTF change. See Table 9
for more information about the load line slope trim feature of the
ISL62771.
TABLE 9. LOAD LINE SLOPE TRIM DEFINITION
22:24 Load Line Slope Trim
27
ACK
ACK
ACK
22
DESCRIPTION
000
Disable LL
001
-40% mΩ Change
010
-20% mΩ Change
011
No Change
100
+20% mΩ Change
101
+40% mΩ Change
110
+60% mΩ Change
111
+80% mΩ Change
FN8321.3
March 25, 2015
ISL62771
Dynamic Offset Trim
Protection Features
The ISL62771 supports the SVI2 ability for the processor to
manipulate the output voltage offset of the Core and Northbridge
VRs. This offset is in addition to any output voltage offset set via
the COMP resistor reader. The dynamic offset trim can disable
the COMP resistor programmed offset of either output when
“Disable All Offset” is selected.
Core VR and Northbridge VR both provide overcurrent,
current-balance, undervoltage and overvoltage fault protections.
The controller also provides over-temperature protection. The
following discussion is based on Core VR and also applies to the
Northbridge VR.
TABLE 10. OFFSET TRIM DEFINITION
OFFSET TRIM
[1:0]
DESCRIPTION
00
Disable All Offset
01
-25mV Change
10
0mV Change
11
+25mV Change
Telemetry
The ISL62771 can provide voltage and current information
through the telemetry system outlined by the AMD SVI2
specification. The telemetry data is transmitted through the SVC
and SVT lines of the SVI 2 interface.
Current telemetry is based on a voltage generated across a
133kΩ resistor placed from the IMON pin to GND. The current
flowing out of the IMON pin is proportional to the load current in
the VR. The Isum current defined in the “Voltage Regulation and
Load Line Implementation” on page 15 provides the base
conversion from the load current to the internal amplifier created
Isum current. The Isum current is then divided down by a factor of
4 to create the IMON current, which flows out of the IMON pin.
The Isum current will measure 35µA when the load current is at
full load based on a droop current designed for 45µA at the same
load current. The difference between the Isum current and the
droop current is provided in Equation 2. The IMON current will
measure 11.25µA at full load current for the VR and the IMON
voltage will be 1.2V. The load percentage, which is reported by
the IC is based on this voltage. When the load is 25% of the full
load, the voltage on the IMON pin will be 25% of 1.2V or 0.3V.
The SVI interface allows the selection of no telemetry, voltage
only, or voltage and current telemetry on either or both of the VR
outputs. The TFN bit along with the Core and Northbridge domain
selector bits are used by the processor to change the
functionality of telemetry, see Table 11 for more information.
TABLE 11. TFN TRUTH TABLE
TFN, CORE, NB
BITS [21,6,7]
DESCRIPTION
1,0,1
Telemetry is in voltage and current mode. Therefore,
voltage and current are sent for VDD and VDDNB
domains by the controller.
1,0,0
Telemetry is in voltage mode only. Only the voltage of
VDD and VDDNB domains is sent by the controller.
1,1,0
Telemetry is disabled.
1,1,1
Reserved
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23
Overcurrent
The IMON voltage provides a means of determining the load
current at any moment in time. The overcurrent protection (OCP)
circuitry monitors the IMON voltage to determine when a fault
occurs. Based on the previous description in the“Voltage
Regulation and Load Line Implementation” on page 15, the
current, which flows out of the IMON pin, is proportional to the
ISUM current. The ISUM current is created from the sensed voltage
across Cn, which is a measure of the load current based upon the
sensing element selected. The IMON current is generated
internally and is 1/4 of the ISUM current. The EDC or IDDspike
current value for the AMD CPU load is used to set the maximum
current level for droop and the IMON voltage of 1.2V, which
indicates 100% loading for telemetry. The ISUM current level at
maximum load, or IDDspike is 36µA and this translates to an IMON
current level of 9µA. The IMON resistor is 133kΩ and the 9µA
flowing through the IMON resistor results in a 1.2V level at
maximum loading of the VR.
The overcurrent threshold is 1.5V on the IMON pin. Based on a
1.2V IMON voltage equating to 100% loading, the additional 0.3V
provided above this level equates to a 25% increase in load current
before an OCP fault is detected. The EDC or IDDspike current is
used to set the 1.2V on IMON for full load current. So the OCP level
is 1.25x the EDC or IDDspike current level. This additional margin
above the EDC or IDDspike current allows the AMD CPU to enter
and exit the IDDspike performance mode without issue unless the
load current is out of line with the IDDspike expectation, thus the
need for overcurrent protection.
When the voltage on the IMON pin meets the overcurrent
threshold of 1.5V, this triggers an OCP event. Within 2µs of
detecting an OCP event, the controller asserts VR_HOT_L low to
communicate to the AMD CPU to throttle back. A fault timer
begins counting while IMON is at or above the 1.5V threshold. The
fault timer lasts 7.5µs to 11µs and then flags an OCP fault. The
controller then tri-states the active channels and goes into
shutdown. PGOOD is taken low and a fault flag from this VR is sent
to the other VR and it is shutdown within 10µs. If the IMON voltage
drops below the 1.5V threshold prior to the fault timer count
finishing, the fault timer is cleared and VR_HOT_L is taken high.
The ISL62771 also features a way-overcurrent [WOC] feature,
which immediately takes the controller into shutdown. This
protection is also referred to as fast overcurrent protection for
short-circuit protection. If the IMON current reaches 15µA, WOC is
triggered. Active channels are tri-stated and the controller is
placed in shutdown and PGOOD is pulled low. There is no fault
timer on the WOC fault, the controller takes immediate action. The
other controller output is also shutdown within 10µs.
FN8321.3
March 25, 2015
ISL62771
Current-Balance
The controller monitors the ISENx pin voltages to determine
current-balance protection. If the ISENx pin voltage difference is
greater than 9mV for 1ms, the controller will declare a fault and
latch off.
INTERNAL TO
ISL62771
+V
Undervoltage
Rp
MONITOR
+
-
If the VSEN voltage exceeds the output voltage VID value plus any
programmed offsets by +325mV, the controller declares an
overvoltage fault. The controller deasserts PGOOD and turns on the
low-side power MOSFETs. The low-side power MOSFETs remain on
until the output voltage is pulled down below the VID set value. Once
the output voltage is below this level, the lower gate is tri-stated. If
the output voltage rises above the overvoltage threshold again, the
protection process is repeated. when all power MOSFETs are turned
off. This behavior provides the maximum amount of protection
against shorted high-side power MOSFETs while preventing output
ringing below ground.
Thermal Monitor [NTC, NTC_NB]
The ISL62771 features two thermal monitors, which use an
external resistor network that includes an NTC thermistor to
monitor motherboard temperature and alert the AMD CPU of a
thermal issue. Figure 19 shows the basic thermal monitor circuit
on the Core VR NTC pin. The Northbridge VR features the same
thermal monitor. The controller drives a 30µA current out of the
NTC pin and monitors the voltage at the pin. The current flowing
out of the NTC pin creates a voltage that is compared to a
warning threshold of 640mV. When the voltage at the NTC pin
falls to this warning threshold or below, the controller asserts
VR_HOT_L to alert the AMD CPU to throttle back load current to
stabilize the motherboard temperature. A thermal fault counter
begins counting toward a minimum shutdown time of 100µs.
The thermal fault counter is an up/down counter, so if the
voltage at the NTC pin rises above the warning threshold, it will
count down and extend the time for a thermal fault to occur. The
warning threshold does have 20mV of hysteresis.
If the voltage at the NTC pin continues to fall down to the
shutdown threshold of 580mV or below, the controller goes into
shutdown and triggers a thermal fault. The PGOOD pin is pulled
low and tri-states the power MOSFETs. A fault on either side will
shutdown both VRs.
RNTC
Rs
WARNING SHUTDOWN
580mV
640mV
FIGURE 19. CIRCUITRY ASSOCIATED WITH THE THERMAL MONITOR
FEATURE OF THE ISL62771
As the board temperature rises, the NTC thermistor resistance
decreases and the voltage at the NTC pin drops. When the
voltage on the NTC pin drops below the over-temperature trip
threshold, then VR_HOT is pulled low. The VR_HOT signal is used
to change the CPU operation and decrease power consumption.
With the reduction in power consumption by the CPU, the board
temperature decreases and the NTC thermistor voltage rises.
Once the over-temperature threshold is tripped and VR_HOT is
taken low, the over-temperature threshold changes to the reset
level. The addition of hysteresis to the over-temperature
threshold prevents nuisance trips. Once both pin voltages exceed
the over-temperature reset threshold, the pull-down on VR_HOT
is released. The signal changes state and the CPU resumes
normal operation. The over-temperature threshold returns to the
trip level.
Table 12 summarizes the fault protections.
TABLE 12. FAULT PROTECTION SUMMARY
FAULT TYPE
Overcurrent
Phase Current
Unbalance
Way-Overcurrent
(1.5xOC)
FAULT DURATION
BEFORE
PROTECTION
PROTECTION
ACTION
FAULT
RESET
7.5µs to 11.5µs PWM tri-state,
PGOOD latched
1ms
low
Immediately
Undervoltage
-325mV
PGOOD latched
low.
PWM tri-state.
Overvoltage
+325mV
PGOOD latched
low.
Actively pulls the
output voltage to
below VID value,
then tri-state.
NTC Thermal
24
R
NTC
VNTC
Overvoltage
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VR_HOT_L
30µA
If the VSEN voltage falls below the output voltage VID value plus
any programmed offsets by -325mV, the controller declares an
undervoltage fault. The controller deasserts PGOOD and
tri-states the power MOSFETs.
100µs min
ENABLE
toggle or
VDD toggle
PGOOD latched
low.
PWM tri-state.
FN8321.3
March 25, 2015
ISL62771
Fault Recovery
All of the previously described fault conditions can be reset by
bringing ENABLE low or by bringing VDD below the POR
threshold. When ENABLE and VDD return to their high operating
levels, the controller resets the faults and soft-start occurs.
Interface Pin Protection
The SVC and SVD pins feature protection diodes, which must be
considered when removing power to VDD and VDDIO, but leaving
it applied to these pins. Figure 20 shows the basic protection on
the pins. If SVC and/or SVD are powered but VDD is not, leakage
current will flow from these pins to VDD.
INTERNAL TO
ISL62771
Figure 21 shows the inductor DCR current-sensing network for a
2-phase solution. An inductor current flows through the DCR and
creates a voltage drop. Each inductor has two resistors in Rsum
and Ro connected to the pads to accurately sense the inductor
current by sensing the DCR voltage drop. The Rsum and Ro
resistors are connected in a summing network as shown and feed
the total current information to the NTC network (consisting of
Rntcs, Rntc and Rp) and capacitor Cn. Rntc is a negative
temperature coefficient (NTC) thermistor, used to temperature
compensate the inductor DCR change.
The inductor output side pads are electrically shorted in the
schematic but have some parasitic impedance in actual board
layout, which is why one cannot simply short them together for the
current-sensing summing network. It is recommended to use
1Ω~10ΩRo to create quality signals. Since Ro value is much smaller
than the rest of the current sensing circuit, the following analysis
ignores it.
The summed inductor current information is presented to the
capacitor Cn. Equations 13 through 17 describe the frequency
domain relationship between inductor total current Io(s) and Cn
voltage VCn(s):
VDD
SVC, SVD
GND
FIGURE 20. PROTECTION DEVICES ON THE SVC AND SVD PINS
Key Component Selection
Inductor DCR Current-Sensing Network
PHASE1 PHASE2
RSUM
RSUM
ISUM+


R ntcnet

DCR
V Cn  s  =  ------------------------------------------  -------------  I o  s   A cs  s 
N 
R sum

 R ntcnet + -------------
N
(EQ. 13)
 R ntcs + R ntc   R p
R ntcnet = ---------------------------------------------------R ntcs + R ntc + R p
(EQ. 14)
s
1 + ------L
A cs  s  = ----------------------s
1 + ------------ sns
(EQ. 15)
DCR
 L = ------------L
(EQ. 16)
1
 sns = -------------------------------------------------------R sum
R ntcnet  --------------N
------------------------------------------  C n
R sum
R ntcnet + --------------N
(EQ. 17)
Where N is the number of phases.
L
L
RNTCS
+
RP
DCR
DCR
RNTC
CNVCN
RI
RO
RO
IO
FIGURE 21. DCR CURRENT-SENSING NETWORK
ISUM-
Transfer function Acs(s) always has unity gain at DC. The inductor
DCR value increases as the winding temperature increases,
giving higher reading of the inductor DC current. The NTC Rntc
value decrease as its temperature decreases. Proper selection of
Rsum, Rntcs, Rp and Rntc parameters ensures that VCn
represents the inductor total DC current over the temperature
range of interest.
There are many sets of parameters that can properly
temperature-compensate the DCR change. Since the NTC network
and the Rsum resistors form a voltage divider, Vcn is always a
fraction of the inductor DCR voltage. It is recommended to have a
higher ratio of Vcn to the inductor DCR voltage so the droop circuit
has a higher signal level to work with.
A typical set of parameters that provide good temperature
compensation are: Rsum = 3.65kΩ, Rp = 11kΩ, Rntcs = 2.61kΩ
and Rntc = 10kΩ (ERT-J1VR103J). The NTC network parameters
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25
FN8321.3
March 25, 2015
ISL62771
may need to be fine-tuned on actual boards. One can apply full
load DC current and record the output voltage reading
immediately; then record the output voltage reading again when
the board has reached the thermal steady state. A good NTC
network can limit the output voltage drift to within 2mV. It is
recommended to follow the Intersil evaluation board layout and
current sensing network parameters to minimize engineering
time.
VCn(s) also needs to represent real-time Io(s) for the controller to
achieve good transient response. Transfer function Acs(s) has a
pole sns and a zero L. One needs to match L and sns so
Acs(s) is unity gain at all frequencies. By forcing L equal to sns
and solving for the solution, Equation 18 gives Cn value.
io
Vo
FIGURE 24. LOAD TRANSIENT RESPONSE WHEN Cn IS TOO LARGE
io
(EQ. 18)
L
C n = --------------------------------------------------------------R sum
R ntcnet  --------------N
------------------------------------------  DCR
R sum
R ntcnet + --------------N
iL
Vo
For example, given N = 2, Rsum = 3.65kΩ, Rp = 11kΩ,
Rntcs = 2.61kΩ, Rntc = 10kΩ, DCR = 0.88mΩ and L = 0.36µH,
Equation 18 gives Cn = 0.294µF.
Assuming the compensator design is correct, Figure 22 shows the
expected load transient response waveforms if Cn is correctly
selected. When the load current Icore has a square change, the
output voltage Vcore also has a square response.
If Cn value is too large or too small, VCn(s) does not accurately
represent real-time Io(s) and worsens the transient response.
Figure 23 shows the load transient response when Cn is too
small. Vcore sags excessively upon load insertion and may create
a system failure. Figure 24 shows the transient response when
Cn is too large. Vcore is sluggish in drooping to its final value.
There is excessive overshoot if load insertion occurs during this
time, which may negatively affect the CPU reliability.
RING
BACK
FIGURE 25. OUTPUT VOLTAGE RING-BACK PROBLEM
ISUM+
R ntcs
Vcn
C n.2
Rp
R ntc
+
C n.1
Rn
OPTIONAL
ISUM-
Ri
R ip
Cip
io
OPTIONAL
FIGURE 26. OPTIONAL CIRCUITS FOR RING-BACK REDUCTION
Vo
FIGURE 22. DESIRED LOAD TRANSIENT RESPONSE WAVEFORMS
io
Vo
FIGURE 23. LOAD TRANSIENT RESPONSE WHEN Cn IS TOO SMALL
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26
Figure 25 shows the output voltage ring-back problem during
load transient response. The load current io has a fast step
change, but the inductor current iL cannot accurately follow.
Instead, iL responds in first-order system fashion due to the
nature of the current loop. The ESR and ESL effect of the output
capacitors makes the output voltage Vo dip quickly upon load
current change. However, the controller regulates Vo according to
the droop current idroop, which is a real-time representation of iL;
therefore, it pulls Vo back to the level dictated by iL, causing the
ring-back problem. This phenomenon is not observed when the
output capacitor has very low ESR and ESL, as is the case with all
ceramic capacitors.
Figure 26 shows two optional circuits for reduction of the
ring-back. Cn is the capacitor used to match the inductor time
constant. It usually takes the parallel of two (or more) capacitors
to get the desired value. Figure 26 shows that two capacitors
(Cn.1 and Cn.2) are in parallel. Resistor Rn is an optional
FN8321.3
March 25, 2015
ISL62771
component to reduce the Vo ring-back. At steady state,
Cn.1 + Cn.2 provides the desired Cn capacitance. At the beginning
of io change, the effective capacitance is less because Rn
increases the impedance of the Cn.1 branch. As Figure 23 shows,
Vo tends to dip when Cn is too small and this effect reduces the
Vo ring-back. This effect is more pronounced when Cn.1 is much
larger than Cn.2. It is also more pronounced when Rn is bigger.
However, the presence of Rn increases the ripple of the Vn signal
if Cn.2 is too small. It is recommended to keep Cn.2 greater than
2200pF. Rn value usually is a few ohms. Cn.1, Cn.2 and Rn values
should be determined through tuning the load transient response
waveforms on an actual board.
Rip and Cip form an R-C branch in parallel with Ri, providing a lower
impedance path than Ri at the beginning of io change. Rip and Cip
do not have any effect at steady state. Through proper selection of
Rip and Cip values, idroop can resemble io rather than iL and Vo will
not ring back. The recommended value for Rip is 100Ω. Cip should
be determined through tuning the load transient response
waveforms on an actual board. The recommended range for Cip is
100pF~2000pF. However, it should be noted that the Rip -Cip branch
may distort the idroop waveform. Instead of being triangular as the
real inductor current, idroop may have sharp spikes, which may
adversely affect idroop average value detection and therefore may
affect OCP accuracy. User discretion is advised.
Resistor Current-Sensing Network
PHASE1 PHASE2
L
L
DCR
DCR
RSUM
ISUM+
+
RSEN
VCN
-
1
A Rsen  s  = ----------------------s
1 + ------------ sns
1
 Rsen = ----------------------------R sum
---------------  C n
N
(EQ. 19)
(EQ. 20)
(EQ. 21)
Transfer function ARsen(s) always has unity gain at DC.
Current-sensing resistor Rsen value does not have significant
variation over-temperature, so there is no need for the NTC
network.
The recommended values are Rsum = 1kΩ and Cn = 5600pF.
Overcurrent Protection
Refer to Equation 2 on page 16 and Figures 21, 25 and 27;
resistor Ri sets the Isum current, which is proportional to droop
current and IMON current. Tables 1 and 2 show the internal OCP
threshold based on the IMON pin voltage. Since the Ri resistor
impacts both the droop current and the IMON current, fine
adjustments to Idroop will require changing the Rcomp resistor.
For example, the OCP threshold is 1.5V on the IMON pin, which
equates to an IMON current of 11.25µA using a 133kΩ IMON
resistor. The corresponding ISUM current is 45µA, which results
in an Idroop of 56.25µA. At full load current, Iomax, the ISUM
current is 36µA and the resulting Idroop is 45µA. The ratio of the
ISUM current at OCP relative to full load is 1.25. Therefore, the
OCP current trip level is 25% higher than the full load current.
CN
RI
ISUM-
RO
IO
FIGURE 27. RESISTOR CURRENT-SENSING NETWORK
Figure 27 shows the resistor current-sensing network for a
2-phase solution. Each inductor has a series current sensing
resistor, Rsen. Rsum and Ro are connected to the Rsen pads to
accurately capture the inductor current information. The Rsum
and Ro resistors are connected to capacitor Cn. Rsum and Cn
form a filter for noise attenuation. Equations 19 through 21 give
the VCn(s) expression.
27


R ntcnet

DCR
V Cn =  ------------------------------------------  -------------  I o
N 
R sum

 R ntcnet + -------------
N
(EQ. 22)
Substitution of Equation 22 into Equation 2 gives Equation 23:
RO
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R sen
V Cn  s  = -------------  I o  s   A Rsen  s 
N
For inductor DCR sensing, Equation 22 gives the DC relationship
of Vcn(s) and Io(s):
RSUM
RSEN
.
R ntcnet
DCR
5 1
I droop = ---  -----  ------------------------------------------  -------------  I o
R sum
N
4 Ri
R ntcnet + --------------N
(EQ. 23)
Therefore:
R ntcnet  DCR  I o
5
R i = ---  ---------------------------------------------------------------------------------R sum
4
N   R ntcnet + ---------------  I droop

N 
(EQ. 24)
Substitution of Equation 14 and application of the OCP condition
in Equation 24 gives Equation 25:
 R ntcs + R ntc   R p
----------------------------------------------------  DCR  I omax
R ntcs + R ntc + R p
5
R i = ---  ----------------------------------------------------------------------------------------------------------------------------4
  R ntcs + R ntc   R p R sum
N   ---------------------------------------------------- + ---------------  I droopmax
N 
 R ntcs + R ntc + R p
(EQ. 25)
FN8321.3
March 25, 2015
ISL62771
Where Iomax is the full load current and Idroopmax is the
corresponding droop current. For example, given N = 2,
Rsum = 3.65kΩ, Rp = 11kΩ, Rntcs = 2.61kΩ, Rntc = 10kΩ,
DCR = 0.88mΩ, Iomax = 50A and Idroopmax = 45µA. Equation 25
gives Ri = 466Ω.
For resistor sensing, Equation 26 gives the DC relationship of
Vcn(s) and Io(s).
R sen
V Cn = -------------  I o
N
Compensator
Figure 22 shows the desired load transient response waveforms.
Figure 28 shows the equivalent circuit of a voltage regulator (VR)
with the droop function. A VR is equivalent to a voltage source
(= VID) and output impedance Zout(s). If Zout(s) is equal to the
load line slope LL, i.e., a constant output impedance, then in the
entire frequency range, Vo will have a square response when Io
has a square change.
(EQ. 26)
i
Zout(s) = LL
o
Substitution of Equation 26 into Equation 2 gives Equation 27:
5 1 R sen
I droop = ---  -----  -------------  I o
N
4 Ri
(EQ. 27)
VR
VID
V
o
LOAD
Therefore:
5 R sen  I o
R i = ---  --------------------------4 N  I droop
(EQ. 28)
Substitution of Equation 28 and application of the OCP condition
in Equation 24 gives Equation 29:
5 R sen  I omax
R i = ---  -------------------------------------4 N  I droopmax
(EQ. 29)
Where Iomax is the full load current and Idroopmax is the
corresponding droop current. For example, given N = 2,
Rsen = 1mΩ, Iomax = 50A and Idroopmax = 45µA, Equation 29
gives Ri = 694Ω.
Load Line Slope
See Figure 14 for load line implementation.
For inductor DCR sensing, substitution of Equation 23 into
Equation 3 gives the load line slope expression in Equation 30:
V droop
R ntcnet
5 R droop
DCR
LL = ------------------- = ---  -------------------  ------------------------------------------  ------------4
Io
Ri
R sum
N
R ntcnet + --------------N
(EQ. 30)
Intersil provides a Microsoft Excel-based spreadsheet to help
design the compensator and the current sensing network so that
VR achieves constant output impedance as a stable system.
A VR with active droop function is a dual-loop system consisting of
a voltage loop and a droop loop, which is a current loop. However,
neither loop alone is sufficient to describe the entire system. The
spreadsheet shows two loop gain transfer functions, T1(s) and
T2(s), that describe the entire system. Figure 29 conceptually
shows T1(s) measurement set up and Figure 30 conceptually
shows T2(s) measurement set up. The VR senses the inductor
current, multiplies it by a gain of the load line slope, adds it on top
of the sensed output voltage and then feeds it to the compensator.
T1 is measured after the summing node and T2 is measured in the
voltage loop before the summing node. The spreadsheet gives
both T1(s) and T2(s) plots. However, only T2(s) can actually be
measured on an ISL62771 regulator.
.
Q1
VIN
GATE
DRIVER
Q2
(EQ. 31)
LOAD LINE SLOPE

20
EA
MOD.
(EQ. 32)
One can use the full-load condition to calculate Rdroop. For
example, given Iomax = 50A, Idroopmax = 45µA and LL = 2.1mΩ,
Equation 32 gives Rdroop = 2.33kΩ.
It is recommended to start with the Rdroop value calculated by
Equation 32 and fine-tune it on the actual board to get accurate
load line slope. One should record the output voltage readings at
no load and at full load for load line slope calculation. Reading
the output voltage at lighter load instead of full load will increase
the measurement error.
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28
iO
COUT
Substitution of Equation 24 and rewriting Equation 30, or
substitution of Equation 28 and rewriting Equation 31, gives the
same result as in Equation 32:
Io
R droop = ----------------  LL
I droop
VO
L
For resistor sensing, substitution of Equation 27 into Equation 3
gives the load line slope expression in Equation 31:
V droop
5 R sen  R droop
LL = ------------------- = ---  --------------------------------------4
Io
N  Ri
FIGURE 28. VOLTAGE REGULATOR EQUIVALENT CIRCUIT
COMP
+
VID
+
+
ISOLATION
TRANSFORMER
CHANNEL B
LOOP GAIN =
CHANNEL A
CHANNEL A
NETWORK
ANALYZER
CHANNEL
EXCITATION OUTPUT
FIGURE 29. LOOP GAIN T1(s) MEASUREMENT SET UP
T1(s) is the total loop gain of the voltage loop and the droop loop.
It always has a higher crossover frequency than T2(s), therefore
has a higher impact on system stability.
FN8321.3
March 25, 2015
ISL62771
T2(s) is the voltage loop gain with closed droop loop, thus having
a higher impact on output voltage response.
Design the compensator to get stable T1(s) and T2(s) with sufficient
phase margin and an output impedance equal to or smaller than
the load line slope.
INTERNAL TO
ISL62771
+V
30µA
L
GATE
DRIVER
NTC
Q2
MONITOR
IO
CO
330kΩ
8.45kΩ
LOAD LINE SLOPE
+
COMP
Rs
FIGURE 31. THERMAL MONITOR FEATURE OF THE ISL62771
+
VID
ISOLATION
TRANSFORMER
CHANNEL B
CHANNEL A
CHANNEL A
NETWORK
ANALYZER
CHANNEL B
EXCITATION OUTPUT
FIGURE 30. LOOP GAIN T2(s) MEASUREMENT SET-UP
Current Balancing
Refer to Figure 15 through 21 for information on current
balancing. The ISL62771 achieves current balancing through
matching the ISEN pin voltages. Risen and Cisen form filters to
remove the switching ripple of the phase node voltages. It is
recommended to use a rather long Risen, Cisen time constant,
such that the ISEN voltages have minimal ripple and represent
the DC current flowing through the inductors. Recommended
values are Rs = 10kΩ and Cs = 0.22µF.
Thermal Monitor Component Selection
The ISL62771 features two pins, NTC and NTC_NB, which are
used to monitor motherboard temperature and alert the AMD
CPU if a thermal issue arises. The basic function of this circuitry
is outlined in the “Thermal Monitor [NTC, NTC_NB]” on page 24.
Figure 31 shows the basic configuration of the NTC resistor, RNTC
and offset resistor, RS, used to generate the warning and
shutdown voltages at the NTC pin.
As the board temperature rises, the NTC thermistor resistance
decreases and the voltage at the NTC pin drops. When the
voltage on the NTC pin drops below the thermal warning
threshold of 0.64V, then VR_HOT_L is pulled low. When the AMD
CPU detects VR_HOT_L has gone low, it will begin throttling back
load current on both outputs to reduce the board temperature.
If the board temperature continues to rise, the NTC thermistor
resistance will drop further and the voltage at the NTC pin could
drop below the thermal shutdown threshold of 0.58V. Once this
threshold is reached, the ISL62771 shuts down both Core and
Northbridge VRs indicating a thermal fault has occurred prior to
the thermal fault counter triggering a fault.
Selection of the NTC thermistor can vary depending on how the
resistor network is configured. The equivalent resistance at the
typical thermal warning threshold voltage of 0.64V is defined in
Equation 33.
0.64V
---------------- = 21.3k
30A
29
(EQ. 33)
The equivalent resistance at the typical thermal shutdown
threshold voltage of 0.58V required to shutdown both outputs is
defined in Equation 34.
0.58V
---------------- = 19.3k
30A
(EQ. 34)
The NTC thermistor value correlates to the resistance change
between the warning and shutdown thresholds and the required
temperature change. If the warning level is designed to occur at a
board temperature of +100°C and the thermal shutdown level at
a board temperature of +105°C, then the resistance change of
the thermistor can be calculated. For example, a Panasonic NTC
thermistor with B = 4700 has a resistance ratio of 0.03939 of its
nominal value at +100°C and 0.03308 of its nominal value at
+105°C. Taking the required resistance change between the
thermal warning threshold and the shutdown threshold and
dividing it by the change in resistance ratio of the NTC thermistor
at the two temperatures of interest, the required resistance of
the NTC is defined in Equation 35.
 21.3k – 19.3k 
------------------------------------------------------ = 317k
 0.03939 – 0.03308 
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WARNING SHUTDOWN
580mV
640mV
20
EA
MOD.
RNTC
+
-
LOOP GAIN =
R
VO
Q1
VIN
VR_HOT_L
(EQ. 35)
FN8321.3
March 25, 2015
ISL62771
The closest standard thermistor to the value calculated with
B = 4700 is 330kΩ. The NTC thermistor part number is
ERTJ0EV334J. The actual resistance change of this standard
thermistor value between the warning threshold and the
shutdown threshold is calculated in Equation 36.
 330k  0.03939  –  330k  0.03308  = 2.082k
(EQ. 36)
Since the NTC thermistor resistance at +105°C is less than the
required resistance from Equation 34, additional resistance in
series with the thermistor is required to make up the difference.
A standard resistor, 1% tolerance, added in series with the
thermistor will increase the voltage seen at the NTC pin. The
additional resistance required is calculated in Equation 37.
19.3k – 10.916k = 8.384k
When placing MOSFETs, try to keep the source of the upper
MOSFETs and the drain of the lower MOSFETs as close as
thermally possible (see Figure 32). Input high-frequency
capacitors should be placed close to the drain of the upper
MOSFETs and the source of the lower MOSFETs. Place the output
inductor and output capacitors between the MOSFETs and the
load. High-frequency output decoupling capacitors (ceramic)
should be placed as close as possible to the decoupling target
(microprocessor), making use of the shortest connection paths to
any internal planes. Place the components in such a way that the
area under the IC has less noise traces with high dV/dt and di/dt,
such as gate signals and phase node signals.
(EQ. 37)
The closest standard 1% tolerance resistor is 8.45kΩ.
The NTC thermistor is placed in a hot spot on the board, typically
near the upper MOSFET of Channel 1 of the respective output.
The standard resistor is placed next to the controller.
Layout Guidelines
VIAS TO
GROUND
PLANE
GND
VOUT
INDUCTOR
PHASE
NODE
HIGH-SIDE
MOSFETS
VIN
OUTPUT
CAPACITORS
SCHOTTKY
DIODE
LOW-SIDE
MOSFETS
INPUT
CAPACITORS
PCB Layout Considerations
POWER AND SIGNAL LAYERS PLACEMENT ON THE PCB
As a general rule, power layers should be close together, either
on the top or bottom of the board, with the weak analog or logic
signal layers on the opposite side of the board. The ground-plane
layer should be adjacent to the signal layer to provide shielding.
FIGURE 32. TYPICAL POWER COMPONENT PLACEMENT
Table 13 shows layout considerations for the ISL62771
controller by pin.
COMPONENT PLACEMENT
There are two sets of critical components in a DC/DC converter;
the power components and the small signal components. The
power components are the most critical because they switch
large amount of energy. The small signal components connect to
sensitive nodes or supply critical bypassing current and signal
coupling.
The power components should be placed first and these include
MOSFETs, input and output capacitors and the inductor. It is
important to have a symmetrical layout for each power train,
preferably with the controller located equidistant from each
power train. Symmetrical layout allows heat to be dissipated
equally across all power trains. Keeping the distance between
the power train and the control IC short helps keep the gate drive
traces short. These drive signals include the LGATE, UGATE,
PGND, PHASE and BOOT.
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30
FN8321.3
March 25, 2015
ISL62771
TABLE 13. LAYOUT CONSIDERATIONS FOR THE ISL62771 CONTROLLER
ISL62771 PIN
SYMBOL
LAYOUT GUIDELINES
BOTTOM PAD
GND
1
NTC_NB
2
IMON_NB
3
SVC
4
VR_HOT_L
5
SVD
Use good signal integrity practices and follow AMD recommendations.
6
VDDIO
Use good signal integrity practices and follow AMD recommendations.
7
SVT
Use good signal integrity practices and follow AMD recommendations.
8
ENABLE
Use good signal integrity practices.
9
PWROK
Use good signal integrity practices and follow AMD recommendations.
10
IMON
11
NTC
The NTC thermistor must be placed close to the thermal source that is monitored to determine Core thermal
throttling. Placement at the hottest spot of the Core VR is recommended. Additional standard resistors in the
resistor network on this pin should be placed near the IC.
12
ISEN2
13
ISEN1
Each ISEN pin has a capacitor (Cisen) decoupling it to VSUMN and then through another capacitor (Cvsumn) to
GND. Place Cisen capacitors as close as possible to the controller and keep the following loops small:
Connect this ground pad to the ground plane through a low impedance path. A minimum of 5 vias are
recommended to connect this pad to the internal ground plane layers of the PCB.
The NTC thermistor must be placed close to the thermal source that is monitored to determine Northbridge
thermal throttling. Placement at the hottest spot of the Northbridge VR is recommended. Additional standard
resistors in the resistor network on this pin should be placed near the IC.
Place the IMON_NB resistor close to this pin and make/keep a tight GND connection.
Use good signal integrity practices and follow AMD recommendations.
Follow AMD recommendations. Placement of the pull-up resistor near the IC is recommended.
Place the IMON resistor close to this pin and make/keep a tight GND connection.
1. Any ISEN pin to another ISEN pin
2. Any ISEN pin to GND
The red traces in the following drawing show the loops to be minimized.
PHASE2
VO
L2
RO
RISEN
ISEN2
CISEN PHASE1
RISEN
ISEN1
GND
31
RO
VSUMN
CISEN
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L1
CVSUMN
FN8321.3
March 25, 2015
ISL62771
TABLE 13. LAYOUT CONSIDERATIONS FOR THE ISL62771 CONTROLLER (Continued)
ISL62771 PIN
SYMBOL
LAYOUT GUIDELINES
14
ISUMP
15
ISUMN
Place the current sensing circuit in general proximity of the controller.
Place capacitor Cn very close to the controller.
Place the NTC thermistor next to Core VR Channel 1 inductor so it senses the inductor temperature correctly.
Each phase of the power stage sends a pair of VSUMP and VSUMN signals to the controller. Run these two
signals traces in parallel fashion with decent width (>20mil).
IMPORTANT: Sense the inductor current by routing the sensing circuit to the inductor pads. If possible, route the
traces on a different layer from the inductor pad layer and use vias to connect the traces to the center of the
pads. If no via is allowed on the pad, consider routing the traces into the pads from the inside of the inductor.
The following drawings show the two preferred ways of routing current sensing traces.
INDUCTOR
INDUCTOR
VIAS
CURRENT-SENSING TRACES
CURRENT-SENSING TRACES
16
VSEN
17
RTN
18
FB
19
COMP
20
PGOOD
No special consideration.
21
BOOT1
Use a wide trace width (>30mil). Avoid routing any sensitive analog signal traces close to or crossing over this
trace.
22
UGATE1
23
PHASE1
These two signals should be routed together in parallel. Each trace should have sufficient width (>30mil). Avoid
routing these signals near sensitive analog signal traces or crossing over them. Routing PHASE1 to the Core VR
Channel 1 high-side MOSFET source pin instead of a general connection to PHASE1 copper is recommended for
better performance.
24
LGATE1
Use sufficient trace width (>30mil). Avoid routing this signal near any sensitive analog signal traces or crossing
over them.
25
VDD
A high quality, X7R dielectric MLCC capacitor is recommended to decouple this pin to GND. Place the capacitor
in close proximity to the pin with the filter resistor nearby the IC.
26
VDDP
A high quality, X7R dielectric MLCC capacitor is recommended to decouple this pin to GND. Place the capacitor
in close proximity to the pin.
27
LGATE2
Use sufficient trace width (>30mil). Avoid routing this signal near any sensitive analog signal traces or crossing
over them.
28
PHASE2
29
UGATE2
These two signals should be routed together in parallel. Each trace should have sufficient width (>30mil). Avoid
routing these signals near sensitive analog signal traces or crossing over them. Routing PHASE2 to the Core VR
Channel 2 high-side MOSFET source pin instead of a general connection to PHASE2 copper is recommended for
better performance.
30
BOOT2
Use a wide trace width (>30mil). Avoid routing any sensitive analog signal traces close to or crossing over this
trace.
31
BOOT_NB
Use a wide trace width (>30mil). Avoid routing any sensitive analog signal traces close to or crossing over this
trace.
32
UGATE_NB
33
PHASE_NB
These two signals should be routed together in parallel. Each trace should have sufficient width (>30mil). Avoid
routing these signals near sensitive analog signal traces or crossing over them. Routing PHASE_NB to the
Northbridge VR high-side MOSFET source pin instead of a general connection to PHASE_NB copper is
recommended for better performance.
34
LGATE_NB
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Place the filter on these pins in close proximity to the controller for good coupling.
Place the compensation components in general proximity of the controller.
32
Use sufficient trace width (>30mil). Avoid routing this signal near any sensitive analog signal traces or crossing
over them.
FN8321.3
March 25, 2015
ISL62771
TABLE 13. LAYOUT CONSIDERATIONS FOR THE ISL62771 CONTROLLER (Continued)
ISL62771 PIN
SYMBOL
LAYOUT GUIDELINES
35
PGOOD_NB
No special consideration.
36
COMP_NB
Place the compensation components in general proximity of the controller.
37
FB_NB
38
VSEN_NB
Place the filter on this pin in close proximity to the controller for good coupling.
39
ISUMN_NB
40
ISUMP_NB
Place the current sensing circuit in general proximity of the controller.
Place capacitor Cn very close to the controller.
Place the NTC thermistor next to Northbridge VR Channel 1 inductor so it senses the inductor temperature
correctly. Each phase of the power stage sends a pair of VSUMP and VSUMN signals to the controller. Run these
two signals traces in parallel fashion with decent width (>20mil).
IMPORTANT: Sense the inductor current by routing the sensing circuit to the inductor pads. If possible, route the
traces on a different layer from the inductor pad layer and use vias to connect the traces to the center of the
pads. If no via is allowed on the pad, consider routing the traces into the pads from the inside of the inductor.
The following drawings show the two preferred ways of routing current sensing traces.
INDUCTOR
INDUCTOR
VIAS
CURRENT-SENSING TRACES
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33
CURRENT-SENSING TRACES
FN8321.3
March 25, 2015
ISL62771
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
CHANGE
March 25, 2015
FN8321.3
On page 1 under Features, added "SVC Frequency Range 100kHz to 20MHz" below "Supports AMD SVI 2.0 serial
data bus interface”
Electrical Spec Table On page 11: “LOGIC THRESHOLDS” section, added “SVC Frequency Range” with limits of
0.1MHz to 20MHz.
Updated the L40.5x5 Package Outline Drawing on page 35 to the latest revision:
Rev 1 to Rev 2 changes are by adding tolerance +/- values to Top view and Side View.
September 12, 2013
FN8321.2
Ordering information table on page 9: Changed IRTZ part temperature from -40°C to +85°C to -40°C to
+100°C.
Page 14, Channel Configuration Section, removed “as will connecting ISEN1_NB to +5V will disable the
Northbridge VR output.”
Changed temperature -40°C to +85°C to -40°C to +100°C throughout the datasheet.
December 18, 2012
FN8321.1
Changed AGND symbols to GND symbols in Figures 3 thru 5 and Pin 12/13 drawing in the Layout Guidelines
table. The IC has a single GND connection which all signals are referenced.
November 19, 2012
FN8321.1
Typo on page 9 in the pin description for COMP_NB pin. Changed "slew rate" to "switching frequency".
The part description in all other places indicated that the slew rate is fixed and the switching frequency is set by
the COMP_NB resistor.
Corrected part marking in “Ordering Information” on page 9.
June 13, 2012
FN8321.0
Initial Release
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
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34
FN8321.3
March 25, 2015
ISL62771
Package Outline Drawing
L40.5x5
40 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 7/14
5.00 ± 0.05
4x3.60
A
B
36x0.40
6
PIN #1 INDEX AREA
(4X)
3.50
5.00 ± 0.05
6
PIN 1
INDEX AREA
0.15
40x0.4 ± 0.1
TOP VIEW
BOTTOM VIEW
0.20
b
4
0.10 M C A B
PACKAGE OUTLINE
0.40
0.750 ± 0.10
3.50
5.00
0.050
SEE DETAIL “X”
SIDE VIEW
// 0.10 C
C
BASE PLANE
SEATING PLANE
0.08 C
(36x0.40)
0.2 REF
(40x0.20)
C
(40x0.60)
5
0.00 MIN
0.05 MAX
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance: Decimal ± 0.05
4.
Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.27mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
7.
JEDEC reference drawing: MO-220WHHE-1
either a mold or mark feature.
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35
FN8321.3
March 25, 2015