GAL20RA10 Data Sheet - Lattice Semiconductor

GAL®20RA10 Device Datasheet
June 2010
All Devices Discontinued!
Product Change Notification (PCN) #09-10 has been issued to discontinue all devices in
this data sheet.
The original datasheet pages have not been modified and do not reflect those changes.
Please refer to the table below for reference PCN and current product status.
Product Line
GAL20RA10
Ordering Part Number
GAL20RA10B-10LP
GAL20RA10B-15LP
GAL20RA10B-20LP
GAL20RA10B-30LP
GAL20RA10B-20LPI
GAL20RA10B-7LJ
GAL20RA10B-10LJ
GAL20RA10B-15LJ
GAL20RA10B-20LJ
GAL20RA10B-30LJ
GAL20RA10B-20LJI
Product Status
Reference PCN
Discontinued
PCN#09-10
5555 N.E. Moore Ct. z Hillsboro, Oregon 97124-6421 z Phone (503) 268-8000 z FAX (503) 268-8347
Internet: http://www.latticesemi.com
GAL20RA10
High-Speed Asynchronous E2CMOS PLD
Generic Array Logic™
Features
Functional Block Diagram
• HIGH PERFORMANCE E2CMOS ® TECHNOLOGY
— 7.5 ns Maximum Propagation Delay
— Fmax = 83.3 MHz
— 9 ns Maximum from Clock Input to Data Output
— TTL Compatible 8 mA Outputs
— UltraMOS® Advanced CMOS Technology
PL
8
I
I/O/Q
OLMC
8
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• 50% to 75% REDUCTION IN POWER FROM BIPOLAR
— 75mA Typical Icc
I
• ACTIVE PULL-UPS ON ALL PINS
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
8
• E CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100 ms)
— 20 Year Data Retention
PROGRAMMABLE
AND-ARRAY
(80X40)
I
2
I
I
• TEN OUTPUT LOGIC MACROCELLS
— Independent Programmable Clocks
— Independent Asynchronous Reset and Preset
— Registered or Combinatorial with Polarity
— Full Function and Parametric Compatibility with
PAL20RA10
I
I
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
— 100% Functional Testability
8
8
8
8
8
I
• APPLICATIONS INCLUDE:
— State Machine Control
— Standard Logic Consolidation
— Multiple Clock Logic Designs
8
I
8
I
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
Description
OE
The GAL20RA10 combines a high performance CMOS process
with electrically erasable (E2) floating gate technology to provide
the highest speed performance available in the PLD market. Lattice
Semiconductor’s E2CMOS circuitry achieves power levels as low
as 75mA typical ICC which represents a substantial savings in power
when compared to bipolar counterparts. E2 technology offers high
speed (<100ms) erase times providing the ability to reprogram,
reconfigure or test the devices quickly and efficiently.
Pin Configuration
DIP
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. The GAL20RA10 is a direct parametric compatible CMOS
replacement for the PAL20RA10 device.
I/O/Q
PL
28
I/O/Q
NC
2
Vcc
I
4
I
PL
I
PLCC
25
I
I
7
NC
I
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacturing. Therefore, Lattice
Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
9
GAL20RA10
Top View
23
I
11
I/O/Q
OE
I/O/Q
19
18
16
NC
14
I
I
12
GND
I
Vcc
I/O/Q
I/O/Q
I/O/Q
I
I/O/Q
I
GAL
20RA10
6
I/O/Q
18
I
NC
21
24
I
I
26
5
1
I
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
I/O/Q
I/O/Q
I
I/O/Q
I/O/Q
I
I/O/Q
I/O/Q
I
GND
I/O/Q
12
13
OE
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
20ra10_02
1
July 1997
Specifications GAL20RA10
GAL20RA10 Ordering Information
Commercial Grade Specifications
Tpd (ns)
Tsu (ns)
7.5
10
Icc (mA)
3
9
100
GAL20RA10B-7LJ
28-Lead PLCC
4
11
100
GAL20RA10B-10LP
24-Pin Plastic DIP
100
GAL20RA10B-10LJ
28-Lead PLCC
100
GAL20RA10B-15LP
24-Pin Plastic DIP
7
15
Ordering #
Package
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15
Tco (ns)
20
10
30
20
20
30
100
GAL20RA10B-15LJ
28-Lead PLCC
100
GAL20RA10B-20LP
24-Pin Plastic DIP
100
GAL20RA10B-20LJ
28-Lead PLCC
100
GAL20RA10B-30LP
24-Pin Plastic DIP
100
GAL20RA10B-30LJ
28-Lead PLCC
Industrial Grade Specifications
Tpd (ns)
Tsu (ns)
Tco (ns)
Icc (mA)
Ordering #
Package
20
10
20
120
GAL20RA10B-20LPI
24-Pin Plastic DIP
120
GAL20RA10B-20LJI
28-Lead PLCC
Part Number Description
XXXXXXXX _ XX
X X X
GAL20RA10B Device Name
Grade
Speed (ns)
L = Low Power
Power
Blank = Commercial
I = Industrial
Package P = Plastic DIP
J = PLCC
2
Specifications GAL20RA10
Output Logic Macrocell (OLMC)
Asynchronous Reset and Preset
Each GAL20RA10 macrocell has an independent asynchronous
reset and preset control product term. The reset and preset product
terms are level sensitive, and will hold the flip-flop in the reset or
preset state while the product term is active independent of the clock
or D-inputs. It should be noted that the reset and preset term alter the state of the flip-flop whose output is inverted by the output
buffer. A reset of the flip-flop will result in the output pin becoming
a logic high and a preset will result in a logic low.
The GAL20RA10 has 10 dedicated input pins and 10 programmable I/O pins, which can be either inputs, outputs, or dynamic I/
O. Each pin has a unique path to the logic array. All macrocells
have the same type and number of data and control product terms,
allowing the user to exchange I/O pin assignments without restriction.
RESET PRESET
FUNCTION
0
0
Registered function of data product term
1
0
Reset register to "0" (device pin = "1")
0
1
Preset register to "1" (device pin = "0")
1
1
Register-bypass (combinatorial output)
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The GAL20RA10 OLMC consists of 10 D flip-flops with individual asynchronous programmable reset, preset and clock product
terms. The sum of four product terms and an Exclusive-OR provide a programmable polarity D-input to each flip-flop. An output
enable term combined with the dedicated output enable pin provides tri-state control of each output. Each OLMC has a flip-flop
bypass, allowing any combination of registered or combinatorial
outputs.
Independent Programmable Clocks
Combinatorial Control
An independent clock control product term is provided for each
GAL20RA10 macrocell. Data is clocked into the flip-flop on the
active edge of the clock product term. The use of individual clock
control product terms allow up to ten separate clocks. These clocks
can be derived from any pin or combination of pins and/or feedback
from other flip-flops. Multiple clock sources allow a number of
asynchronous register functions to be combined into a single
GAL20RA10. This allows the designer to combine discrete logic
functions into a single device.
The register in each GAL20RA10 macrocell may be bypassed by
asserting both the reset and preset product terms. While both
product terms are active the flip-flop is bypassed and the D- input
is presented directly to the inverting output buffer. This provides
the designer the ability to dynamically configure any macrocell as
a combinatorial output, or to fix the macrocell as combinatorial only
by forcing both reset and preset product terms active. Some logic
compilers will configure macrocells as registered or combinatorial
based on the logic equations, others require the designer to force
the reset and preset product terms active for combinatorial
macrocells.
Programmable Polarity
The polarity of the D-input to each macrocell flip-flop is individually
programmable to be active high or low. This is accomplished with
a programmable Exclusive-OR gate on the D-input of each flipflop. The polarity of the pin is active low when XOR bit is programmed (or zero) and is active high when XOR bit is erased (or
one). Because of the inverted output buffer, the XOR gate output
node is opposite polarity from the pin. It should be noted that the
programmable polarity only affects the data latched into the flip-flop
on the active edge of the clock product term. The reset, preset and
preload will alter the state of the flip-flop independent of the state
of programmable polarity bit. The ability to program the active polarity of the D-inputs can be used to reduce the total number of
product terms used, by allowing the DeMorganization of the logic
functions. This logic reduction is accomplished by the logic compiler, and does not require the designer to define the polarity.
Parallel Flip-Flop Preload
The flip-flops of a GAL20RA10 can be reset or preset from the
I/O pins by applying a logic low to the preload pin (pin 1 on DIP
package / pin 2 on PLCC package) and applying the desired logic
level to each I/O pin. The I/O pins must remain valid for the preload
setup and hold time. All 10 flip-flops are reset or preset during
preload, independent of all other OLMC inputs.
A logic low on an I/O pin during preload will preset the flip-flop, a
logic high will reset the flip-flop. The output of any flip-flop to be
preloaded must be disabled. Enabling the output during preload
will maintain the current logic state. It should be noted that the
preload alters the state of the flip-flop whose output is inverted by
the output buffer. A reset of the flip-flop will result in the output pin
becoming a logic high and a preset will result in a logic low. Note
that the common output enable pin will disable all 10 outputs of the
GAL20RA10 when held high.
Output Enable
The output of each GAL20RA10 macrocell is controlled by the
“AND’ing” of an independent output enable product term and a
common active low output enable pin (pin 13 on DIP package / pin
16 on PLCC package). The output is enabled while the output enable product term is active and the output enable pin is low. This
output control structure allows several output enable alternatives.
3
Specifications GAL20RA10
Output Logic Macrocell Diagram
PL
OE
AR
PL
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PD
Q
D
AP
0
1
XOR (n)
Output Logic Macrocell Configuration (Registered With Polarity)
PL
OE
PL
AR
PD
D
Q
AP
XOR (n)
Output Logic Macrocell Configuration (Combinatorial With Polarity)
OE
XOR (n)
4
Specifications GAL20RA10
GAL20RA10 Logic Diagram
DIP (PLCC) Package Pinouts
1 (2)
PL
0
4
8
12
16
20
24
28
32
36
0
OLMC
280
23 (27)
XOR - 3200
2 (3)
320
OLMC
22 (26)
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600
XOR - 3201
3 (4)
640
OLMC
920
21 (25)
XOR - 3202
4 (5)
960
OLMC
1240
20 (24)
XOR - 3203
5 (6)
1280
OLMC
1560
19 (23)
XOR - 3204
6 (7)
1600
OLMC
1880
18 (21)
XOR - 3205
7 (9)
1920
OLMC
2200
17 (20)
XOR - 3206
8 (10)
2240
OLMC
2520
16 (19)
XOR - 3207
9 (11)
2560
OLMC
2840
15 (18)
XOR - 3208
10 (12)
2880
OLMC
3160
14 (17)
XOR - 3209
11 (13)
13 (16)
OE
64-USER ELECTRONIC SIGNATURE FUSES
3210, 3211, ....
.... 3272, 3273
Byte7 Byte6 ....
.... Byte1 Byte0
MSB
LSB
5
Specifications GAL20RA10B
Absolute Maximum Ratings(1)
Recommended Operating Conditions
Supply voltage VCC ....................................... -0.5 to +7V
Input voltage applied ........................... -2.5 to VCC +1.0V
Off-state output voltage applied .......... -2.5 to VCC +1.0V
Storage Temperature ................................. -65 to 150°C
Ambient Temperature with
Power Applied ......................................... -55 to 125°C
Commercial Devices:
Ambient Temperature (TA) ............................. 0 to +75°C
Supply voltage (VCC)
with Respect to Ground ..................... +4.75 to +5.25V
Industrial Devices:
Ambient Temperature (TA) ..........................-40 to +85°C
Supply voltage (VCC)
with Respect to Ground ..................... +4.50 to +5.50V
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1.Stresses above those listed under the “Absolute Maximum
Ratings” may cause permanent damage to the device. These
are stress only ratings and functional operation of the device at
these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming, follow the programming specifications).
DC Electrical Characteristics
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL
VIL
VIH
IIL1
IIH
VOL
VOH
IOL
IOH
IOS2
MIN.
TYP.3
MAX.
UNITS
Input Low Voltage
Vss – 0.5
—
0.8
V
Input High Voltage
2.0
—
Vcc+1
V
PARAMETER
CONDITION
Input or I/O Low Leakage Current
0V ≤ VIN ≤ VIL (MAX.)
—
—
-100
µA
Input or I/O High Leakage Current
3.5V ≤ VIN ≤ VCC
—
—
10
µA
Output Low Voltage
IOL = MAX. Vin = VIL or VIH
—
—
0.5
V
Output High Voltage
IOH = MAX. Vin = VIL or VIH
2.4
—
—
V
Low Level Output Current
—
—
8
mA
High Level Output Current
—
—
-3.2
mA
-50
—
-135
mA
L -7/-10/-15/-20/-30
—
75
100
mA
L -20
—
75
120
mA
Output Short Circuit Current
COMMERCIAL
ICC
Operating Power
Supply Current
INDUSTRIAL
ICC
Operating Power
Supply Current
VCC = 5V VOUT = 0.5V TA = 25°C
VIL = 0.5V VIH = 3.0V
ftoggle = 15MHz Outputs Open
VIL = 0.5V
VIH = 3.0V
ftoggle = 15MHz Outputs Open
1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Characterized but not 100% tested.
3) Typical values are at Vcc = 5V and TA = 25 °C
6
Specifications GAL20RA10B
AC Switching Characteristics
Over Recommended Operating Conditions
PARAM.
TEST
COND1.
COM
COM
COM / IND
COM
-7
-10
-15
-20
-30
DESCRIPTION
UNITS
MIN.
MAX. MIN.
MAX. MIN.
MAX. MIN.
MAX. MIN.
MAX.
A
Input or I/O to Combinatorial Output
2
7.5
2
10
—
15
—
20
—
30
ns
A
Clock to Output Delay
2
9
2
11
—
15
—
20
—
30
ns
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tpd
tco
tsu
th
COM
fmax
3
twh
twl
ten/tdis
ten/tdis
tar/tap
tarw/tapw
tarr/tapr
twp
tsp
thp
—
Setup Time, Input or Fdbk before Clk↑
3
—
4
—
7
—
10
—
20
—
ns
—
Hold Time, Input or Fdbk after Clk↑
2
—
3
—
3
—
3
—
10
—
ns
A
Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)
83.3
—
66.7
—
45.0
—
33.3
—
20.0
—
MHz
A
Maximum Clock Frequency with
No Feedback
83.3
—
71.4
—
50.0
—
41.7
—
25.0
—
MHz
—
Clock Pulse Duration, High
6
—
7
—
10
—
12
—
20
—
ns
—
Clock Pulse Duration, Low
6
—
7
—
10
—
12
—
20
—
ns
B,C
I or I/O to Output Enabled / Disabled
—
7.5
—
10
—
15
—
20
—
30
ns
B,C
OE to Output Enabled / Disabled
—
5
—
9
—
12
—
15
—
20
ns
A
Input or I/O to Async. Reset / Preset
—
9
—
11
—
15
—
20
—
30
ns
—
Async. Reset / Preset Pulse Duration
6
—
10
—
15
—
20
—
20
—
ns
—
Async. Reset / Preset Recovery Time
7
—
7
—
10
—
12
—
20
—
ns
—
Preload Pulse Duration
8
—
10
—
15
—
20
—
30
—
ns
—
Preload Setup Time
5
—
7
—
10
—
15
—
25
—
ns
—
Preload Hold Time
5
—
7
—
10
—
15
—
25
—
ns
1) Refer to Switching Test Conditions section.
2) Refer to fmax Descriptions section.
Capacitance (TA = 25°C, f = 1.0 MHz)
SYMBOL
PARAMETER
MAXIMUM*
UNITS
TEST CONDITIONS
CI
Input Capacitance
8
pF
VCC = 5.0V, VI = 2.0V
CI/O
I/O Capacitance
10
pF
VCC = 5.0V, VI/O = 2.0V
*Characterized but not 100% tested.
7
Specifications GAL20RA10
Switching Waveforms
INPUT or
I/O FEEDBACK
INPUT or
I/O FEEDBACK
VALID INPUT
VALID INPUT
t su
t pd
COMBINATORIAL
OUTPUT
th
VALID CLOCK
CLK
VALID CLOCK
t co
REGISTERED
OUTPUT
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Combinatorial Output
Registered Output
INPUT or
I/O FEEDBACK
t dis
t en
INPUT or
I/O FEEDBACK
VALID INPUT
OUTPUT
t ar
Q-OUTPUT OF
REGISTER
Input or I/O to Output Enable/Disable
t wl
t wh
REGISTERED
OUTPUT PIN
CLK
t ap
Q-OUTPUT OF
REGISTER
Clock Width
twp
REGISTERED
OUTPUT PIN
PL
tsp
thp
Asynchronous Reset and Preset
ALL I/O
PINS
INPUT or
I/O FEEDBACK
DRIVING AP or AR
Parallel Preload
VALID INPUT
tapw/arw
tapr/arr
CLK
OE
Asynchronous Reset and Preset Recovery
t dis
t en
OUTPUT
OE to Enable / Disable
8
Specifications GAL20RA10
fmax Descriptions
CLK
CLK
LOGIC
ARRAY
REGISTER
LOGIC
ARRAY
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REGISTER
tsu
tco
fmax with No Feedback
fmax with External Feedback 1/(tsu+tco)
Note: fmax with no feedback may be less
than 1/(twh + twl). This is to allow for a
clock duty cycle of other than 50%.
Note: fmax with external feedback is calculated from measured tsu and tco.
Switching Test Conditions
Input Pulse Levels
Input Rise and
Fall Times
GND to 3.0V
-7/-10
2ns 10% – 90%
-15/-20/-30
3ns 10% – 90%
Input Timing Reference Levels
1.5V
Output Timing Reference Levels
1.5V
Output Load
+5V
R1
See Figure
FROM OUTPUT (O/Q)
UNDER TEST
TEST POINT
3-state levels are measured 0.5V from steady-state active
level.
R2
C L*
Output Load Conditions (see figure)
Test Condition
A
B
C
Active High
Active Low
Active High
Active Low
R1
R2
CL
470Ω
∞
470Ω
∞
470Ω
390Ω
390Ω
390Ω
390Ω
390Ω
50pF
50pF
50pF
5pF
5pF
*C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
9
Specifications GAL20RA10
Electronic Signature
Device Programming
An electronic signature word is provided in every GAL20RA10
device. It contains 64 bits of reprogrammable memory that contains user defined data. Some uses include user ID codes, revision numbers, pattern identification or inventory control codes. The
signature data is always available to the user independent of the
state of the security cell.
GAL devices are programmed using a Lattice Semiconductorapproved Logic Programmer, available from a number of manufacturers (see the the GAL Development Tools section). Complete
programming of the device takes only a few seconds. Erasing of
the device is transparent to the user, and is done automatically as
part of the programming cycle.
NOTE: The electronic signature bits if programmed to any value
other then zero(0) will alter the checksum of the device.
Input Buffers
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GAL20RA10 devices are designed with TTL level compatible input buffers. These buffers have a characteristically high impedance
and present a much lighter load to the driving logic than traditional
bipolar devices.
Security Cell
A security cell is provided in every GAL20RA10 device as a deterrent to unauthorized copying of the device pattern. Once programmed, this cell prevents further read access of the device
pattern information. This cell can be only be reset by reprogramming the device. The original pattern can never be examined once
this cell is programmed. The Electronic Signature is always available regardless of the security cell state.
GAL20RA10 input buffers have active pull-ups within their input
structure. As a result, unused inputs and I/Os will float to a TTL
“high” (logical “1”). Lattice Semiconductor recommends that all unused inputs and tri-stated I/O pins be connected to another active
input, Vcc, or GND. Doing this will tend to improve noise immunity and reduce Icc for the device.
Latch-Up Protection
Typical Input Pull-up Characteristic
I n p u t C u r r e n t (u A )
GAL20RA10 devices are designed with an on-board charge pump
to negatively bias the substrate. The negative bias is of sufficient
magnitude to prevent input undershoots from causing the circuitry
to latch. Additionally, outputs are designed with n-channel pullups
instead of the traditional p-channel pullups to eliminate any possibility of SCR induced latching.
0
-20
-40
-60
0
1.0
2.0
3.0
In p u t V o lt ag e ( V o lt s)
10
4.0
5.0
Specifications GAL20RA10
Power-Up Reset
Vcc
Vcc (min.)
t su
t wl
CLK
t pr
INTERNAL REGISTER
Q - OUTPUT
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Internal Register
Reset to Logic "0"
FEEDBACK/EXTERNAL
OUTPUT REGISTER
Device Pin
Reset to Logic "1"
Circuitry within the GAL20RA10 provides a reset signal to all registers during power-up. All internal registers will have their Q
outputs set low after a specified time (tpr, 1µs MAX). As a result,
the state on the registered output pins (if they are enabled) will
be high on power-up, because of the inverting buffer on the output
pins. This feature can greatly simplify state machine design by
providing a known state on power-up. The timing diagram for
power-up is shown to the right. Because of the asynchronous
nature of system power-up, some conditions must be met to
provide a valid power-up reset of the GAL20RA10. First, the Vcc
rise must be monotonic. Second, the clock input must be at a static
TTL level as shown in the diagram during power up. The registers will reset within a maximum of 1µs. As in normal system operation, avoid clocking the device until all input and feedback path
setup times have been met. The clock must also meet the minimum pulse width requirements.
Input/Output Equivalent Schematics
PIN
PIN
Feedback
Active Pull-up
Circuit
Vcc
Active Pull-up
Circuit
(Vref Typical = 3.2V)
Vcc
Vref
Tri-State
Control
Vcc
Vcc
(Vref Typical = 3.2V)
Vref
ESD
Protection
Circuit
Data
Output
PIN
PIN
ESD
Protection
Circuit
Feedback
(To Input Buffer)
Typical Input
Typical Output
11
Specifications GAL20RA10
GAL20RA10B-7/-10: Typical AC and DC Characteristic Diagrams
Normalized Tpd vs Vcc
1.4
1.1
1
0.9
1.1
1
0.9
1.2
1
0.8
A
D LL
IS
C DE
O
N VIC
TI
N ES
U
ED
0.8
4.50
Normalized Tsu
Normalized Tco
1.2
0.8
4.50
4.75
Supply Voltage (V)
5.25
0.6
4.50
5.50
0.8
1
0.9
0.8
1.2
1
0.8
-55
125
100
Temperature (deg. C)
Temperature (deg. C)
Delta Tpd vs # of Outputs
Switching
Delta Tco vs # of Outputs
Switching
0
0
Delta Tco (ns)
Delta Tpd (ns)
75
50
25
0
-25
Temperature (deg. C)
-0.5
-1
-1.5
-0.5
-1
-1.5
-2
2
3
4
5
6
7
8
9
10
1
Number of Outputs Switching
2
3
4
5
6
7
8
9
10
Number of Outputs Switching
Delta Tpd vs Output
Loading
Delta Tco vs Output
Loading
8
8
6
RISE
4
FALL
Delta Tco (ns)
Delta Tpd (ns)
1.4
0.6
-55
125
100
75
50
0
25
-25
0.7
-55
0.7
1.1
2
0
-2
6
RISE
4
FALL
2
0
-2
-4
-4
0
50
100
0
150
50
100
Output Loading (pF)
Output Loading (pF)
12
100
0.9
1.2
75
1
5.50
1.6
Normalized Tsu
Normalized Tco
1.1
5.25
Normalized Tsu vs Temp
1.3
1.2
5.00
Supply Voltage (V)
Normalized Tco vs Temp
1.3
1
4.75
Supply Voltage (V)
Normalized Tpd vs Temp
Normalized Tpd
5.00
50
5.50
0
5.25
25
5.00
-25
4.75
150
125
1.2
Normalized Tpd
Normalized Tsu vs Vcc
Normalized Tco vs Vcc
Specifications GAL20RA10
GAL20RA10B-7/-10: Typical AC and DC Characteristic Diagrams
Voh vs Ioh
5
0.8
4
0.6
0.4
0.2
Voh vs Ioh
4
3.75
Voh (V)
1
Voh (V)
Vol (V)
Vol vs Iol
3
2
3.25
1
0
3
0.00
A
D LL
IS
C DE
O
N VIC
TI
N ES
U
ED
0
3.5
10
20
30
40
0
10
20
Iol (mA)
50
60
70
80
1
0.9
1.3
1.40
1.2
1.30
1.1
1
0.9
0.8
Supply Voltage (V)
125
100
75
5.50
25
5.25
-25
5.00
-55
0.7
4.75
Temperature (deg. C)
0
10
20
Iik (mA)
Delta Icc (mA)
10
8
6
4
30
40
50
60
70
2
80
0
0.20 0.70 1.20 1.70 2.20 2.70 3.20 3.70
Vin (V)
90
-2.00
-1.50
-1.00
Vik (V)
13
3.00
4.00
-0.50
1.20
1.10
1.00
0.90
0.80
0
25
50
Frequency (MHz)
Input Clamp (Vik)
Delta Icc vs Vin (1 input)
2.00
Normalized Icc vs Freq.
Normalized Icc
Normalized Icc
1.1
1.00
Ioh(mA)
Normalized Icc vs Temp
1.2
Normalized Icc
40
Ioh(mA)
Normalized Icc vs Vcc
0.8
4.50
30
0
0
0.00
75
Specifications GAL20RA10
GAL20RA10B-15/-20/-30: Typical AC and DC Characteristic Diagrams
Normalized Tpd vs Vcc
1.6
Normalized Tco
1.1
PT L->H
1
RISE
1.05
FALL
1
0.95
1.4
1.2
1
0.8
0.6
A
D LL
IS
C DE
O
N VIC
TI
N ES
U
ED
0.9
Normalized Tsu
1.1
PT H->L
4.75
Supply Voltage (V)
5.25
0.4
4.50
5.50
0.9
0.8
1
0.9
0.8
1
0.9
0.8
0.7
-55
125
Temperature (deg. C)
Delta Tco vs # of Outputs
Switching
0
Delta Tco (ns)
0
Delta Tpd (ns)
1.1
Temperature (deg. C)
Delta Tpd vs # of Outputs
Switching
-0.2
-0.4
-0.6
-0.8
RISE
-1
FALL
-1.2
-0.2
-0.4
-0.6
-0.8
RISE
-1
FALL
-1.2
1
2
3
4
5
6
7
8
9
10
1
Number of Outputs Switching
12
10
Delta Tco (ns)
FALL
6
4
2
0
-2
-4
50
100
150
200
3
4
5
6
7
8
9
10
Delta Tco vs Output
Loading
RISE
8
2
Number of Outputs Switching
Delta Tpd vs Output
Loading
Delta Tpd (ns)
90
75
50
25
0
-25
Temperature (deg. C)
0
1.2
0.6
-55
125
90
75
50
25
0
-25
0.7
-55
0.7
FALL
1.1
1.3
250
14
12
10
8
6
4
2
0
-2
-4
RISE
FALL
0
300
50
100
150
200
250
Output Loading (pF)
Output Loading (pF)
14
90
1
5.50
1.4
RISE
1.2
Normalized Tsu
Normalized Tco
PT L->H
1.1
5.25
Normalized Tsu vs Temp
1.3
PT H->L
5.00
Supply Voltage (V)
Normalized Tco vs Temp
1.3
1.2
4.75
Supply Voltage (V)
Normalized Tpd vs Temp
Normalized Tpd
5.00
75
5.50
50
5.25
0
5.00
25
4.75
0.9
4.50
-25
0.8
4.50
300
125
1.2
Normalized Tpd
Normalized Tsu vs Vcc
Normalized Tco vs Vcc
Specifications GAL20RA10
GAL20RA10B-15/-20/-30: Typical AC and DC Characteristic Diagrams
Voh vs Ioh
5
4
2
1.5
1
Voh vs Ioh
3.75
3.625
Voh (V)
3
2.5
Voh (V)
Vol (V)
Vol vs Iol
3
2
3.375
1
A
D LL
IS
C DE
O
N VIC
TI
N ES
U
ED
0.5
3.5
0
0.00
20.00
40.00
60.00
0
0.00
80.00
Iol (mA)
1.00
0.90
1.1
1
0.9
Supply Voltage (V)
125
100
75
50
0
25
5.50
-25
5.25
-55
0.8
5.00
Temperature (deg. C)
Delta Icc vs Vin (1 input)
0
10
4
Iik (mA)
20
3
2
30
40
50
60
70
1
80
0
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
Vin (V)
90
-2.00
-1.00
Vik (V)
15
1.30
1.20
1.10
1.00
0.90
0.80
0
25
50
Frequency (MHz)
Input Clamp (Vik)
5
4.00
1.40
Normalized Icc
Normalized Icc
Normalized Icc
1.10
3.00
Normalized Icc vs Freq.
1.2
4.75
2.00
Ioh(mA)
Normalized Icc vs Temp
1.20
0.80
4.50
1.00
Ioh(mA)
Normalized Icc vs Vcc
Delta Icc (mA)
3.25
0.00
10.00 20.00 30.00 40.00 50.00 60.00
0.00
75