NTE4569B Integrated Circuit CMOS, Programmable Divide−By−”N” Dual 4−Bit BCD/Binary Counter Description: The NTE4569B is a programmable divide−by−N dual 4−bit binary or BCD down counter in a 16−Lead DIP type package constructed with MOS P−channel and N−channel enhancement mode devices (complementary MOS) in a monolithic structure. This device has been designed for use with a 4569B phase comparator/counter in frequency synthesizers, phase−locked loops, and other frequency division applications requiring low power dissipation and/or high noise immunity. Features: D 9.5Mhz Typical Counting Rate at 10V for Any Division Ratio Greater Than 1 D Speed−Up Circuitry for Zero Detection and Preset Enable D Each 4−Bit Counter Can Divide Independently in BCD or Binary Mode D Quiescent Current = 5.0nA/Package (Typ) at 5Vdc Absolute Maximum Ratings: (Voltages Referenced to VSS, Note 1) DC Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to +18.0V Input Voltage (All Inputs), Vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to VDD + 0.5V DC Current Drain (Per Pin), I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA Operating Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55 to +125°C Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65 to +150°C Note 1. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation it is recommended that Vin and Vout be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Electrical Characteristics: (Note 2) Parameter Output Voltage Vin = VDD or 0 Symbol “0” Level VOL “1” Level VOH Vin = 0 or VDD Input Voltage (Note 4) “0” Level (VO = 4.5 or 0.5Vdc) VIL −555C +255C +1255C VDD Vdc 5.0 Min Max Min Typ Max Min Max − 0.05 − 0 0.05 − 0.05 Unit Vdc 10 − 0.05 − 0 0.05 − 0.05 Vdc 15 − 0.05 − 0 0.05 − 0.05 Vdc 5.0 4.95 − 4.95 5.0 − 4.95 − Vdc 10 9.95 − 9.95 10 − 9.95 − Vdc 15 14.95 − 14.95 15 − 14.95 − Vdc 5.0 − 1.5 − 2.25 1.5 − 1.5 Vdc (VO = 9.0 or 1.0Vdc) 10 − 3.0 − 4.50 3.0 − 3.0 Vdc (VO = 13.5 or 1.5Vdc) 15 − 4.0 − 6.75 4.0 − 4.0 Vdc (VO = 0.5 or 4.5Vdc) “1” Level VIH 5.0 3.5 − 3.5 2.75 − 3.5 − Vdc (VO = 1.0 or 9.0Vdc) 10 7.0 − 7.0 5.50 − 7.0 − Vdc (VO = 1.5 or 13.5Vdc) 15 11.0 − 11.0 8.25 − 11.0 − Vdc Output Drive Current (VOH = 2.5Vdc) Source IOH 5.0 −3.0 − −2.4 −4.2 − −1.7 − mAdc (VOH = 4.6Vdc) 5.0 −0.64 − −0.51 −0.88 − −0.36 − mAdc (VOH = 9.5Vdc) 10 −1.6 − −1.3 −2.25 − −0.9 − mAdc (VOH = 13.5Vdc) 15 −4.2 − −3.4 −0.88 − −2.4 − mAdc 5.0 0.64 − 0.51 0.88 − 0.36 − mAdc (VOL = 0.5Vdc) 10 1.6 − 1.3 2.25 − 0.9 − mAdc (VOL = 1.5Vdc) 15 4.2 − 3.4 8.8 − 2.4 − mAdc (VOL = 0.4Vdc) Sink IOL Input Current Iin 15 − ±0.1 − ±0.00001 ±0.1 − ±0.1 μAdc Input Capacitance (VIN = 0) Cin − − − − 5.0 7.5 − − pF Quiescent Current (Per Package) IDD 5.0 − 50 − 0.005 50 − 150 μAdc 10 − 100 − 0.010 100 − 300 μAdc 15 − 200 − 0.015 200 − 600 μAdc Total Supply Current (Dynamic plus Quiescent, Per Package, CL = 50pF on All Outputs, All Buffers Switching Note 3, Note 5) IT 5.0 IT = (0.58μA/kHz) f + IDD μAdc 10 IT = (1.20μA/kHz) f + IDD μAdc 15 IT = (1.95μA/kHz) f + IDD μAdc Note 2. Data labeled “Typ” is not to be used for design purposes but is intended as an indication of the device’s potential performance. Note 3. The formulas given are for the typical characteristics only at +25°C. Note 4. Noise immunity specified for worst−case input combination. Noise margin for both “1” and “0” = 1.0Vdc min @ VDD = 5Vdc 2.0Vdc min @ VDD = 10Vdc 2.5Vdc min @ VDD = 15Vdc Note 5. To calculate total supply current at loads other than 50pF: IT(CL) = IT(50pF) + 1 x 10−3 (CL −50) VDDf where: IT is in μA (per package), CL in pF, VDD in volts and f in kHz is input frequency. Switching Characteristics: (CL = 50pF, TA = +25°C, Note 2) Parameter Output Rise Time Symbol tTLH, Output Fall Time tTHL Turn−On Delay Time PEout tPLH Q Output Turn−Off Delay Time PEout tPHL Q Output Circuit Pulse Width tWH Clock Pulse Frequency (Note 4) fcl Clock Pulse Rise and Fall Time tTLH, tTHL VDD Vdc 5.0 10 15 5.0 10 15 Min − − − − − − Typ 100 50 40 100 50 40 Max 200 100 80 200 100 80 Unit ns ns ns ns ns ns 5.0 10 15 5.0 10 15 − − − − − − 420 175 125 675 285 200 700 300 250 1200 500 400 ns ns ns ns ns ns 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 − − − − − − 300 150 115 − − − 380 600 ns 150 300 ns 100 200 ns 530 1000 ns 225 400 ns 155 300 ns 100 − ns 45 − ns 30 − ns 3.5 2.1 MHz 9.5 5.7 MHz 13.0 7.8 MHz No Limit μs μs μs Note 2. Data labeled “Typ” is not to be used for design purposes but is intended as an indication of the device’s potential performance. Note 3. The formulas given are for the typical characteristics only at +25°C. Note 4. This implies that zero detection and preset enable is done while the clock is running at the specified frequency. Operating Characteristics: The NTE4569B includes a high speed Johnson counter followed by a BCD/binary 4−bit synchronous counter. The use of an encoder allows the Johnson counter to be programmed (i.e. preset) in BCD or binary code through inputs DPA2, DPA3, and DPA4. The BCD/binary counter can be programmed through inputs DPA1, DPA2, DPA3, and DPA4. For each counter a divide ratio of 10 (BCD count) or 16 (binary count) can be chosen independently by inputs CTLA and CTLB respectively. When one of those inputs is set to high, the divide ratio of the corresponding counter is 10 (BCD); when it i set low, the division ratio is 16 (binary). A Cascade Feedback input (Pin7), a Q output (Pin15) and a Preset Enable output (Pin1) made it possible to cascade a 4568B, NTE4522B and NTE4526B with this device. CF, Q an PEout of NTE4569B must be respectively connected to “0”, C and PE of the following counter. Operating Characteristics (Cont’d): When NTE4569B is used alone, CF must be connected to VDD. One pulse will appear on output PEout every N clock periods (N being the value programmed on the DP inputs). Both counters included in NTE4569B and eventually all the counters which are cascaded, should normally be preset at the programmed values during the clock period where they all reach the count zero. For best speed performance, preset is started as soon as count 1 is detected. As a consequence, it is not possible to program a frequency division ratio of one. However, it is possible to program a division ratio of 11 (i.e. DPA1 . . . DPA4 = 1,0,0,0 and DPB1 . . . DPB4 = 1,0,0,0), or a division ratio of 101 if another counter is cascaded with the NTE4569B. This high speed configuration makes it possible to guarantee a maximum clock pulse frequency of 5.7Mhz for a 10V VDD supply for any division ratio greater than one. Due to the presence of the early zero detection, the circuit must be used in the two least significant digit positions. Because all the circuitry i static, there is no minimum frequency specification for the Clock Input, C (Pin9). Pin Connection Diagram Zero Detect 1 16 VDD 15 Q 14 DPB4 CTLA 2 DPA1 3 13 DPB3 DPA2 4 DPA3 5 12 DPB2 DPA4 6 Cascade Feedback 7 11 DPB1 10 CTLB 9 Clock VSS 8 16 9 1 8 .870 (22.0) Max .260 (6.6) Max .200 (5.08) Max .100 (2.54) .700 (17.78) .099 (2.5) Min