PO100HSTL180A Differential LVDS/LVPECL/HSTL to LVTTL Translator www.potatosemi.com & LVTTL/LVCMOS to Differential HSTL Translator High Frequency Noise Canncellation Translator DESCRIPTION: FEATURES: • Patented Technology • Differential LVDS/LVPECL/HSTL to LVTTL Translator - Operating frequency up to 1GHz with 2pf load - Operating frequency up to 800MHz with 5pf load - Operating frequency up to 450MHz with 15pf load - Very low output pin to pin skew < 150ps - Propagation delay < 1.8ns max with 15pf load • LVTTL/LVCMOS to Differential HSTL Translator - Operating frequency up to 1.65GHz with 5pf load - Operating frequency up to 500MHz with 15pf load - Very low output pin to pin skew < 100ps - Propagation delay < 1.4ns max with 15pf load • 2.4V to 3.6V power supply • Industrial temperature range: –40°C to 85°C • Available in 14-pin 150ml SOIC package Pin Configuration NC R RE DE D GND GND 14 3 12 13 4 11 5 10 7 8 6 The PO100HSTL180A is a low-skew, The small outline 14 pin package and the low skew design to make it ideal for applications which require the translation of a clock or a data signal. Logic Block Diagram 1 2 Potato Semiconductor’s PO100HSTL180A is designed for world top performance using submicron CMOS technology to achieve 1GHz LVTTL output frequency with less than 1.8ns propagation delay and 1.65GHz HSTL output frequency with less than 1.4ns propagation delay. 9 VCC VCC A B Z Y NC D DE RE R 9 5 10 4 3 12 2 11 Y Z A B Pin Description RECEIVER INPUTS RECEIVER OUTPUT VID = VA– VB RE R 10 mV 10 mV < VID < 10 mV L L H –10 mV VID VID L L L H X H Z D DE L H Open X H ? Open Potato Semiconductor Corporation DRIVER INPUTS 1 DRIVER OUTPUTS Y Z L H H L H L Z Z H H L 01/01/10 PO100HSTL180A Differential LVDS/LVPECL/HSTL to LVTTL Translator www.potatosemi.com & LVTTL/LVCMOS to Differential HSTL Translator High Frequency Noise Canncellation Translator Maximum Ratings Description Max Unit Storage Temperature -65 to 150 °C Operation Temperature -40 to 85 °C Operation Voltage -0.5 to +4.6 V Input Voltage -0.5 to Vcc V Output Voltage -0.5 to Vcc+0.5 V Note: stresses greater than listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability specification is not implied. Pin Characteristics Symbol Parameter Test Conditions CIN Input Capacitance RPULLDOWN Input A Pulldown Resistor RPULLUP Minimum Input B Pullup Resistor Typical 4 Maximum 88 Units pF K 88 K DC Electrical Characteristics Symbol Description VOH Output High voltage VOL Test Conditions Min Typ Max Unit Vcc=3V Vin=VIH or VIL, IOH= -12mA 2.4 3 - V Output Low voltage Vcc=3V Vin=VIH or VIL, IOH=12mA - 0.3 0.5 V VIH Input High voltage Guaranteed Logic HIGH Level (Input Pin) 2 - Vcc V VIL Input Low voltage Guaranteed Logic LOW Level (Input Pin) -0.5 - 0.8 V IIH Input High current Vcc = 3.6V and Vin = Vcc - - 1 uA IIL Input Low current Vcc = 3.6V and Vin = 0V - - -1 uA VIK Clamp diode voltage Vcc = Min. And IIN = -18mA -0.7 -1.2 - V Notes: 1. 2. 3. 4. 5. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. Typical values are at Vcc = 3.3V, 25 °C ambient. This parameter is guaranteed but not tested. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. VoH = Vcc – 0.6V at rated current Potato Semiconductor Corporation 2 01/01/10 PO100HSTL180A Differential LVDS/LVPECL/HSTL to LVTTL Translator www.potatosemi.com & LVTTL/LVCMOS to Differential HSTL Translator High Frequency Noise Canncellation Translator Power Supply Characteristics Symbol IccQ Description Quiescent Power Supply Current Test Conditions (1) Min Typ Max Unit Vcc=Max, Vin=Vcc or GND - 0.1 30 uA Notes: 1. 2. 3. 4. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. Typical values are at Vcc = 3.3V, 25•C ambient. This parameter is guaranteed but not tested. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. Receiver Switching Characteristics Symbol tPD Description Test Conditions (1) M ax Unit CL = 15pF 1.8 ns Propagation Delay D to Output pair tPZH or tPZL Output Enable Time CL = 15pF 2.5 ns tPHZ or tPLZ Output Disable Time CL = 15pF 2.5 ns 0.8V – 2.0V Output Pin to Pin Skew (Same Package) CL = 15pF, 125MHz 0.8 150 ns ps Output Skew (Different Package) CL = 15pF, 125MHz 300 ps MHz MHz tr/tf tsk(o) tsk(pp) Rise/Fall Time fmax fmax Input Frequency CL =15pF Input Frequency CL = 5pF 450 250 800 300 fmax Input Frequency CL = 2pF 1000 400 MHz Notes: 1. See test circuits and waveforms. 2. tpLH, tpHL, tsk(p), and tsk(o) are production tested. All other parameters guaranteed but not production tested. 3. Airflow of 1m/s is recommended for frequencies above 133MHz Test Circuit Vcc 50Ohm Pulse Generator V+ V+ V- V- D.U.T 15pF to 2pF 50Ohm Potato Semiconductor Corporation 3 01/01/10 PO100HSTL180A Differential LVDS/LVPECL/HSTL to LVTTL Translator www.potatosemi.com & LVTTL/LVCMOS to Differential HSTL Translator High Frequency Noise Canncellation Translator Test Waveforms FIGURE 1. LVDS/ PECL/ ECL/ HSTL /DIFFERENTIAL INPUT WAVEFORM DEFINITIONS VCC VCC= 3.3V VIH VPP VPP RANGE 0V-VCC VIL VEE=0.0V VEE FIGURE 2. LVTTL OUTPUT tr,tf, VO FIGURE 3. Propogation Delay, Output pulse skew, and output-to-output skew for D to output INPUT CLOCK VPP TPLH TPD TPHL OUTPUT CLOCK VO tSK(O) ANOTHER OUTPUT CLOCK Potato Semiconductor Corporation 4 01/01/10 PO100HSTL180A Differential LVDS/LVPECL/HSTL to LVTTL Translator www.potatosemi.com & LVTTL/LVCMOS to Differential HSTL Translator High Frequency Noise Canncellation Translator Driver Switching Characteristics Symbol Description Test Conditions (1) Typ M ax Unit Propagation Delay D to Output pair CL = 15pF 1.4 ns tPZH or tPZL Output Enable Time CL = 15pF 2.5 ns tPHZ or tPLZ Output Disable Time CL = 15pF 2.5 ns Rise/Fall Time 0.8V – 2.0V ns ps tPD tr/tf tsk(o) tsk(pp) fmax fmax Output Pin to Pin Skew (Same Package) CL = 15pF, 125MHz 0.8 100 Output Skew (Different Package) CL = 15pF, 125MHz 250 ps Input Frequency CL =15pF MHz Input Frequency CL = 5pF 500 250 1.65 300 GHz Notes: 1. See test circuits and waveforms. 2. tpLH, tpHL, tsk(p), and tsk(o) are production tested. All other parameters guaranteed but not production tested. 3. Airflow of 1m/s is recommended for frequencies above 133MHz Test Circuit Vcc Pulse Generator 15pF to 2pF D.U.T 15pF to 2pF 50Ohm Potato Semiconductor Corporation 5 01/01/10 PO100HSTL180A Differential LVDS/LVPECL/HSTL to LVTTL Translator www.potatosemi.com & LVTTL/LVCMOS to Differential HSTL Translator High Frequency Noise Canncellation Translator Test Waveforms FIGURE 1. LVTTL/LVCMOS INPUT WAVEFORM DEFINITION 3V 1.5V Input 0V FIGURE 2. HSTL OUTPUT tr,tf, 20-80% VO FIGURE 3. Propogation Delay, Output pulse skew, and output-to-output skew for D to output pair INPUT CLOCK TPLH TPD TPHL OUTPUT CLOCK VO tSK(O) ANOTHER OUTPUT CLOCK Potato Semiconductor Corporation 6 01/01/10 PO100HSTL180A Differential LVDS/LVPECL/HSTL to LVTTL Translator www.potatosemi.com & LVTTL/LVCMOS to Differential HSTL Translator High Frequency Noise Canncellation Translator Packaging Mechanical Drawing: 14 pin 150mil SOIC 0.244 6.20 0.228 5.80 0.010 0.007 0.050 1.27 0.016 0.40 0.25 0.17 X.XX Denotes dimensions in inches X.XX X.XX Denotes dimensions in millimenters X.XX IC Ordering Information Ordering Code Top-Marking Package TA PO100HSTL180ASU for Tube 14-pin SOIC Pb-free & Green PO100HSTL180AS -40°C to 85°C PO100HSTL180ASR for Tape & Reel 14-pin SOIC Pb-free & Green PO100HSTL180AS -40°C to 85°C IC Package Information PACKAGE CODE S PACKAGE TYPE SOIC 14 TAPE WIDTH (mm) 16 Potato Semiconductor Corporation TAPE PITCH (mm) 8 PIN 1 LOCATION TAPE TRAILER LENGTH QTY PER REEL TAPE LEADER LENGTH QTY PER TUBE Top Left Corner 39 (12”) 3000 64 (20”) 55 7 01/01/10