PO100HSTL22A 02/13/07 Dual LVTTL/LVCMOS to Differential HSTL Translator DESCRIPTION: FEATURES: • Patented Technology • HSTL differential outputs • LVTTL/LVCMOS to Differential HSTL Translator • Operating frequency up to 1.65GHz with 5pf load • Operating frequency up to 500MHz with 15pf load • Very low output pin to pin skew < 100ps • Propagation delay < 1.4ns max with 15pf load • 1.65V to 3.6V power supply • Industrial temperature range: –40°C to 85°C • Available in 8-pin SOIC package • Available in 8-pin TSSOP package Pin Configuration Potato Semiconductor’s PO100HSTL22A is designed for world top performance using submicron CMOS technology to achieve 1.65GHz HSTL output frequency with less than 1.4ns propagation delay. The PO100HSTL22A is a low-skew, LVTTL/LVCMOS to Differential HSTL Translator. The small outline 8 pin package and the low skew design to make it ideal for applications which require the translation of a clock or a data signal. Logic Block Diagram Q0 Q0 1 8 VCC Q0 2 7 D0 Q0 D0 HSTL Q1 3 6 D1 5 GND Q1 Q1 4 LVTTL/ LVCMOS D1 Q1 Pin Description PIN Qn, Qn D0, D1 VCC GND FUNCTION HSTL Differential Outputs LVTTL/LVCMOS Inputs Positive Supply Ground 1 Copyright © Potato Semiconductor Corporation PO100HSTL22A 02/13/07 Dual LVTTL/LVCMOS to Differential HSTL Translator Maximum Ratings Description Max Unit Storage Temperature -65 to 150 °C Operation Temperature -40 to 85 °C Operation Voltage -0.5 to +4.6 V Input Voltage -0.5 to +5.5 V Output Voltage -0.5 to Vcc+0.5 V Note: stresses greater than listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability specification is not implied. DC Electrical Characteristics Symbol Description VOH Output High voltage VOL Test Conditions Min Typ Max Unit Vcc=3V Vin=VIH or VIL, IOH= -12mA 2.4 3 - V Output Low voltage Vcc=3V Vin=VIH or VIL, IOH=12mA - 0.3 0.5 V VIH Input High voltage Guaranteed Logic HIGH Level (Input Pin) 2 - Vcc V VIL Input Low voltage Guaranteed Logic LOW Level (Input Pin) -0.5 - 0.8 V IIH Input High current Vcc = 3.6V and Vin = 5.5V - - 1 uA IIL Input Low current Vcc = 3.6V and Vin = 0V - - -1 uA VIK Clamp diode voltage Vcc = Min. And IIN = -18mA -0.7 -1.2 - V Notes: 1. 2. 3. 4. 5. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. Typical values are at Vcc = 3.3V, 25 °C ambient. This parameter is guaranteed but not tested. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. VoH = Vcc – 0.6V at rated current 2 Copyright © Potato Semiconductor Corporation PO100HSTL22A 04/03/07 Dual LVTTL/LVCMOS to Differential HSTL Translator Power Supply Characteristics Symbol IccQ Description Quiescent Power Supply Current Test Conditions (1) Min Typ Max Unit Vcc=Max, Vin=Vcc or GND - 0.1 30 uA Notes: 1. 2. 3. 4. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. Typical values are at Vcc = 3.3V, 25°C ambient. This parameter is guaranteed but not tested. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. Switching Characteristics Symbol Description Test Conditions (1) Typ M ax Unit tPD Propagation Delay D to Output pair CL = 15pF 1.4 ns tr/tf Rise/Fall Time 0.8V – 2.0V Output Pin to Pin Skew (Same Package) CL = 15pF, 125MHz 0.8 100 ns ps Output Skew (Different Package) CL = 15pF, 125MHz 250 ps Random Clock Jitter (RMS) CL = 15pF, 125MHz tsk(o) tsk(pp) tJITTER fmax fmax Input Frequency CL =15pF Input Frequency CL = 5pF ps 1.6 500 250 1.65 300 MHz GHz Notes: 1. See test circuits and waveforms. 2. tpLH, tpHL, tsk(p), and tsk(o) are production tested. All other parameters guaranteed but not production tested. 3. Airflow of 1m/s is recommended for frequencies above 133MHz Test Circuit Vcc Pulse Generator 15pF to 2pF D.U.T 50Ω 15pF to 2pF 3 Copyright © Potato Semiconductor Corporation PO100HSTL22A 02/13/07 Dual LVTTL/LVCMOS to Differential HSTL Translator Test Waveforms FIGURE 1. LVTTL/LVCMOS INPUT WAVEFORM DEFINITION 3V 1.5V Input 0V FIGURE 2. HSTL OUTPUT tr,tf, 20-80% VO FIGURE 3. Propogation Delay, Output pulse skew, and output-to-output skew for D to output pair INPUT CLOCK TPLH TPD TPHL OUTPUT CLOCK VO tSK(O) ANOTHER OUTPUT CLOCK 4 Copyright © Potato Semiconductor Corporation PO100HSTL22A Dual LVTTL/LVCMOS to Differential HSTL Translator 02/13/07 Packaging Mechanical Drawing: 8 pin SOIC 8 0-8˚ .149 .157 3.78 3.99 .0099 .0196 0.25 x 45˚ 0.50 .016 .050 0.40 1.27 .2284 .2440 5.80 6.20 1 .189 .196 4.80 5.00 .053 .068 .016 .026 0.406 0.660 .0075 .0098 1.35 1.75 0.19 0.25 SEATING PLANE REF .050 BSC 1.27 .0040 0.10 .0098 0.25 .013 0.330 .020 0.508 X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS Packaging Mechanical Drawing: 8 pin TSSOP 8 SEATING PLANE X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS 5 Copyright © Potato Semiconductor Corporation PO100HSTL22A 02/13/07 Dual LVTTL/LVCMOS to Differential HSTL Translator Ordering Information Ordering Code Package Top-Marking TA PO100HSTL22ASU 8 pin SOIC Tube Pb-free & Green PO100HSTL22AS -40°C to 85°C PO100HSTL22ASR 8 pin SOIC Tape and reel Pb-free & Green PO100HSTL22AS -40°C to 85°C PO100HSTL22ATU 8 pin TSSOP Tube Pb-free & Green PO100HSTL22TS -40°C to 85°C PO100HSTL22ATR 8 pin TSSOP Tape and reel Pb-free & Green PO100HSTL22TS -40°C to 85°C 6 Copyright © Potato Semiconductor Corporation