PO54G373A, PO74G373A www.potatosemi.com OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS 54 & 74 Series Noise Cancellation GHz Logic FEATURES: DESCRIPTION: . Patented technology . Operating frequency up to 1.125GHz with 2pf load . Operating frequency up to 700MHz with 5pf load . Operating frequency up to 350MHz with 15pf load . Operating frequency up to 100MHz with 50pf load . VCC Operates from 1.65V to 3.6V . Propagation delay < 1.8ns max with 15pf load . Low input capacitance: 4pf typical . Available in 20pin TSSOP package . Available in 20pin Ceramic Dual Flatpack . Available in 20pin Leadless Ceramic Chip Carrier Potato Semiconductor’s PO74G373A is designed for world top performance using submicron CMOS technology to achieve higher than 1.125GHz TTL /CMOS output frequency with less than 1.8ns propagation delay. This dual Octal transparent D-type latches are designed for 1.65-V to 3.6-V VCC operation. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of these devices as translators in a mixed 3.3V/5V system environment. 20 3 18 2 19 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q LE 8Q 1 2D 2Q 3Q 3D 4D Pin Description OE L L L H INPUTS LE D H H H L X Potato Semiconductor Corporation L X X 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13 8D 7D 7Q 6Q 6D Logic Block Diagram OUTPUT Q H 4 4Q GND LE 5Q 5D OE 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND 1D 1Q OE VCC Pin Configuration OE LE L 1D Q0 Z 1 11 3 C1 1D 2 1Q To Seven Other Channels 1 01/01/10 PO54G373A, PO74G373A www.potatosemi.com OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS 54 & 74 Series Noise Cancellation GHz Logic Maximum Ratings Description Max Unit Storage Temperature -65 to 150 °C Operation Temperature -55 to 125 °C Operation Voltage -0.5 to +4.6 V Input Voltage -0.5 to +5.5 V Output Voltage -0.5 to Vcc+0.5 V Note: stresses greater than listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability specification is not implied. DC Electrical Characteristics Symbol Description VOH Output High voltage VOL Test Conditions Min Typ Max Unit Vcc=3V Vin=VIH or VIL, IOH= -12mA 2.4 3 - V Output Low voltage Vcc=3V Vin=VIH or VIL, IOH=12mA - 0.3 0.5 V VIH Input High voltage Guaranteed Logic HIGH Level (Input Pin) 2 - 5.5 V VIL Input Low voltage Guaranteed Logic LOW Level (Input Pin) -0.5 - 0.8 V IIH Input High current Vcc = 3.6V and Vin = 5.5V - - 1 uA IIL Input Low current Vcc = 3.6V and Vin = 0V - - -1 uA VIK Clamp diode voltage Vcc = Min. And IIN = -18mA - -0.7 -1.2 V Notes: 1. 2. 3. 4. 5. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. Typical values are at Vcc = 3.3V, 25 °C ambient. This parameter is guaranteed but not tested. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. VoH = Vcc – 0.6V at rated current Potato Semiconductor Corporation 2 01/01/10 PO54G373A, PO74G373A www.potatosemi.com OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS 54 & 74 Series Noise Cancellation GHz Logic Power Supply Characteristics Symbol IccQ Description Quiescent Power Supply Current Test Conditions (1) Min Typ Max Unit Vcc=Max, Vin=Vcc or GND - 0.1 30 uA Notes: 1. 2. 3. 4. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. Typical values are at Vcc = 3.3V, 25°C ambient. This parameter is guaranteed but not tested. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. Capacitance Parameters (1) Description Cin Cout Test Conditions Typ Input Capacitance Vin = 0V Output Capacitance Vout = 0V 4 6 Unit pF pF Notes: 1 This parameter is determined by device characterization but not production tested. Switching Characteristics Symbol tsu th tpd Description Test Conditions (1) Setup time before LE Hold time, data after LE Propagation Delay D to Q Propagation Delay LE to Q M ax - CL = 15pF Min Unit 0.5 ns 0.5 1.8 2.0 ns ns ns tPZH or tPZL Output Enable Time CL = 15pF 2.5 ns tPHZ or tPLZ Output Disable Time CL = 15pF 2.5 ns tr/tf Rise/Fall Time 0.8V – 2.0V - ns fmax Input Frequency CL= 50pF 100 MHz fmax Input Frequency CL= 15pF 350 MHz fmax Input Frequency CL= 5pF 700 MHz fmax Input Frequency CL= 2pF 1125 MHz 0.8 - Notes: 1. See test circuits and waveforms. 2. tPLH, tPHL, tsu, and th are production tested. All other parameters guaranteed but not production tested. 3. Airflow of 1m/s is recommended for frequencies above 500MHz Potato Semiconductor Corporation 3 01/01/10 PO54G373A, PO74G373A www.potatosemi.com OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS 54 & 74 Series Noise Cancellation GHz Logic Test Waveforms Timing Input tw tsu VI VM Input VM 0V Data Input VM tPLH tPHL Output 0V tPHL VM Output VI VM VM VOH VOL tPLH VM VM VOH VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 0V th VM VM VI 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION Input VI VM Output Control Output Waveform 1 S1 at V LOAD (see Note B) Output Waveform 2 S1 at GND (see Note B) VM VI VM tPZL tPLZ VM tPZH 0V VLOAD/2 VOL + V VOL tPHZ VM VOH - V VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING Test Circuit Vcc Pulse Generator 50Ohm Potato Semiconductor Corporation D.U.T 50pF to 2pF 4 01/01/10 PO54G373A, PO74G373A www.potatosemi.com OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS 54 & 74 Series Noise Cancellation GHz Logic Packaging Mechanical Drawing: 20 pin TSSOP 20 .169 .177 1 .252 .260 6.4 6.6 .0256 BSC 0.65 4.3 4.5 .047 1.20 Max .007 0.19 .012 0.30 .018 .030 0.45 0.75 SEATING PLANE .002 0.05 .006 0.15 .238 .269 6.1 6.7 .004 0.09 .008 0.20 X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS Packaging Mechanical Drawing: 20pin Leadless Ceramic Chip Carrier Potato Semiconductor Corporation 5 01/01/10 PO54G373A, PO74G373A www.potatosemi.com OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS 54 & 74 Series Noise Cancellation GHz Logic Packaging Mechanical Drawing: 20pin Ceramic Dual Flatpack 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 3 2 1 13 12 4 18 5 17 6 16 0.358 (9,09) 7 0.307 (7,80) 15 8 14 0.358 (9,09) 0.342 (8,69) 9 10 11 12 X.XX Denotes dimensions in inches X.XX X.XX Denotes dimensions in millimenters X.XX 13 Ordering Information Ordering Code Package Top-Marking TA 20pin TSSOP Pb-free & Green POTATO74G373AT -40 C to 85 C PO74G373ATR for Tape & Reel 20pin TSSOP Pb-free & Green POTATO74G373AT -40 C to 85 C PO54G373ALU for Tube 20pin Leadless Ceramic Chip Carrier 20pin Ceramic Dual Flatpack Pb-free & Green POTATO54G373AL -55 C to 125 C Pb-free & Green POTATO54G373AF -55 C to 125 C PO74G373ATU for Tube PO54G373AFU for Tube IC Package Information PACKAGE CODE PACKAGE TYPE T TSSOP 20 TAPE WIDTH (mm) 16 TAPE PITCH (mm) 8 PIN 1 LOCATION TAPE TRAILER LENGTH QTY PER REEL TAPE LEADER LENGTH QTY PER TUBE Top Left Corner 39 (12”) 3000 64 (20”) 74 L LCCC 20 N/A N/A N/A N/A N/A N/A 55 F CFP 20 N/A N/A N/A N/A N/A N/A 85 Potato Semiconductor Corporation 6 01/01/10