Datasheet

PI6CDBL401B
4-Output Low Power PCIE GEN1-2-3 Buffer
Features
Description
ÎÎ4x 100MHz low power HCSL or LVDS compatible outputs
The PI6CDBL401B is a 4-output low power buffer for 100MHz
PCIe Gen1, Gen2 and Gen3 applications with integrated output
terminations providing Zo=100Ω. The device has 4 output enables for clock management, and 3 selectable SMBus addresses.
ÎÎPCIe 3.0, 2.0 and 1.0 compliant
ÎÎProgrammable output amplitude and slew rate
ÎÎSupply voltage of 3.3V +/-10%
ÎÎIndustrial ambient operation temperature
Applications
ÎÎAvailable in lead-free package: 32-TQFN
ÎÎPCIe 3.0/2.0/1.0 clock distribution
Block Diagram
OE(3:0)#
4
CLK(3:0)
CLK_IN
ZDB PLL
CLK_IN#
SADR_tri
HIBW_BYPM_LOBW#
CKPWRGD_PD#
CONTROL
LOGIC
SDATA_3.3
SCLK_3.3
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PI6CDBL401B
4-Output Low Power PCIE GEN1-2-3 Buffer
VDDO1.8
GND
CLK3
CLK3#
OE3#
GND
CKPWRGD_PD#
SADR_tri
Pin Configuration
32 31 30 29 28 27 26 25
HIBW_BYPM_LOBW#
1
24 OE2#
FB_DNC
2
23 CLK2#
FB_DNC#
3
22 CLK2
VDDR3.3
4
CLK_IN
5
CLK_IN#
6
19 CLK1#
GNDR
7
18 CLK1
GNDDIG
8
21 VDDA3.3
PI6CDBL401B
20 GNDA
17 OE1#
VDDO1.8
GND
CLK0#
CLK0
OE0#
SDATA_3.3
SCLK_3.3
VDDDIG3.3
9 10 11 12 13 14 15 16
SMBus Address Selection Table
State of SADR on first application of CKPWRGD_PD#
SADR
Address
+ Read / Write bit
0
1101011
1/0
M
1101100
1/0
1
1101101
1/0
Power Management Table
CLKx
CKPWRGD_PD#
CLK_IN
SMBus OEx bit
OEx# Pin
True O/P
Comp. O/P
PLL
0
x
x
x
Low
Low
Off
1
Running
0
x
Low
Low
On1
1
Running
1
0
Running
Running
On1
1
Running
x
1
Low
Low
On1
1. If bypass mode is selected, the PLL will be off, and outputs will be running
Power Connections
PLL Operating Mode
HiBW_BypM_LoBW# MODE
Byte1 [7:6] Byte1 [4:3]
Readback Control
0
PLL Lo BW
00, 10
00, 10
M
Bypass
01
01
1
PLL Hi BW
11
11
Pin Number
VDD
GND
Description
4
7
Input receiver analog
9
8
Digital Power
16, 25
15, 26, 30
DIF outputs
21
20
PLL Analog
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PI6CDBL401B
4-Output Low Power PCIE GEN1-2-3 Buffer
Pin Descriptions
Pin#
Pin Name
Type
Description
1
HIBW_BYPM_
LOBW#
Input
Trilevel input to select High BW, Bypass or Low BW mode. See PLL Operating
Mode Table for Details.
2
FB_DNC
Output
True clock of differential feedback. The feedback output and feedback input are
connected internally on this pin. Do not connect anything to this pin.
3
FB_DNC#
Output
Complement clock of differential feedback. The feedback output and feedback
input are connected internally on this pin. Do not connect anything to this pin.
4
VDDR3.3
Power
3.3V power for differential input clock (receiver). This VDD should be treated as
an Analog power rail and filtered appropriately.
5
CLK_IN
Input
True Input for differential reference clock.
6
CLK_IN#
Input
Complementary Input for differential reference clock.
7
GNDR
Power
Analog Ground pin for the differential input (receiver)
8
GNDDIG
Power
Ground pin for digital circuitry
9
VDDDIG3.3
Power
3.3V digital power (dirty power)
10
SCLK_3.3
Input
Clock pin of SMBus circuitry, 3.3V tolerant.
11
SDATA_3.3
Input/Output
Data pin for SMBus circuitry, 3.3V tolerant.
12
OE0#
Input
Active low input for enabling DIF pair 0. This pin has an internal pull-down. 1
=disable outputs, 0 = enable outputs
13
CLK0
Output
Differential true clock output
14
CLK0#
Output
Differential Complementary clock output
15
GND
Power
Ground pin.
16
VDDO1.8
Power
Power supply for outputs, nominally 1.8V range from 1.05V~3.3V.
17
OE1#
Input
Active low input for enabling DIF pair 1. This pin has an internal pull-down. 1
=disable outputs, 0 = enable outputs
18
CLK1
Output
Differential true clock output
19
CLK1#
Output
Differential Complementary clock output
20
GNDA
Power
Ground pin for the PLL core.
21
VDDA3.3
Power
3.3Vpower for the PLL core.
22
CLK2
Output
Differential true clock output
23
CLK2#
Output
Differential Complementary clock output
24
OE2#
Input
Active low input for enabling DIF pair 2. This pin has an internal pull-down. 1
=disable outputs, 0 = enable outputs
25
VDDO1.8
Power
Power supply for outputs, nominally 1.8V range from 1.05V~3.3V.
26
GND
Power
Ground pin.
27
CLK3
Output
Differential true clock output
28
CLK3#
Output
Differential Complementary clock output
29
OE3#
Input
Active low input for enabling DIF pair 3. This pin has an internal pull-down. 1
=disable outputs, 0 = enable outputs
30
GND
Power
Ground pin.
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PI6CDBL401B
4-Output Low Power PCIE GEN1-2-3 Buffer
Pin Descriptions Cont...
Pin#
Pin Name
Type
Description
31
CKPWRGD_PD#
Input
Input notifies device to sample latched inputs and start up on first high assertion. Low enters Power Down Mode, subsequent high assertions exit Power Down
Mode. This pin has internal pull-up resistor.
32
SADR_tri
Input
Tri-level latch to select SMBus Address. See SMBus Address Selection Table.
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PI6CDBL401B
4-Output Low Power PCIE GEN1-2-3 Buffer
Maximum Ratings
(Above which useful life may be impaired. For user guidelines, not tested.)
Supply Voltage to Ground Potential.......................................................4.6V
All Inputs and Output......................................................-0.5V toVDD+0.5V
Ambient Operating Temperature............................................ -40 to +85°C
Storage Temperature........................................................... –65°C to +150°C
Junction Temperature........................................................................... 125°C
Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any
other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
Soldering Temperature.......................................................................... 260°C
ESD Protection (Input)............................................................2000V(HBM)
Electrical Characteristics–Clock Input Parameters (TA = -40~85oC; VDD = 3.3V+/-10%; VDDO =
1.8V+/-10%, See Test Loads for Loading Conditions)
Symbol
Parameters
Condition
Min.
Type
Max.
Units
VIHDIF
Input High Voltage - CLK_IN1
600
800
1150
mV
VILDIF
Input Low Voltage - CLK_IN1,3
(single-ended measurement)
VSS 300
0
300
mV
VCOM
Input Common Mode Voltage CLK_IN1
Common Mode Input Voltage
300
725
mV
VSWING
Input Amplitude - CLK_IN1
Peak to Peak value (VIHDIF - VILDIF)
300
1450
mV
dv/dt
Input Slew Rate - CLK_IN1,2
Measured differentially
0.4
IIN
Input Leakage Current1
VIN = VDD , VIN = GND
-5
5
uA
dtin
Input Duty Cycle1
Measurement from differential wavefrom
45
55
%
JDIFIn
Input Jitter - Cycle to Cycle
Differential Measurement
0
150
ps
1
Differential inputs
(single-ended measurement)
Differential inputs
V/ns
Note:
1. Guaranteed by design and characterization, not 100% tested in production.
2. Slew rate measured through +/-75mV window centered around differential zero
3. The device can be driven from a single ended clock by driving the true clock and biasing the complement clock input to the VBIAS, where VBIAS is (VIHHIGH - VIHLOW)/2
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PI6CDBL401B
4-Output Low Power PCIE GEN1-2-3 Buffer
Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions
(TA = -40~85oC; VDD = 3.3V+/-10%; VDDO = 1.8V+/-10%, See Test Loads for Loading Conditions)
Symbol
Parameters
VDDX
VDDO
TA
Condition
Min.
Type
Max.
Units
Supply Voltage1
Supply voltage for core, analog
3.0
3.3
3.6
V
Supply Voltage
Supply voltage outputs
1.65
1.8
2.0
V
-40
25
85
°C
1
Ambient Operating
Temperature1
VIH
Input High Voltage1
Single-ended inputs, except SMBus, SADR_tri
0.65 VDD
VDD +0.3
V
VIM
Input Mid Voltage
SADR_tri
0.4 VDD
0.6 VDD
V
VIL
Input Low Voltage
Single-ended inputs, except SMBus, SADR_tri
-0.3
0.35 VDD
V
Single-ended inputs, except SADR_tri
0.5 VDD
0.6 VDD
V
Single-ended inputs, except SADR_tri
0.4 VDD
0.5 VDD
V
0.2 VDD
V
VT+
VT-
1
1
Schmitt Trigger Postive
Going Threshold Voltage1
Schmitt Trigger Negative
Going Threshold Voltage1
VH
Hysteresis Voltage1
VT+ - VT-
0.05 VDD
VOH
Output High Voltage1
Single-ended outputs, except SMBus. IOH =
-2mA
VDD
-0.45
VOL
Outputt Low Voltage1
Single-ended outputs, except SMBus. IOL =
-2mA
Single-ended inputs, VIN = GND, VIN = VDD
(exclude XTAL_IN pin)
IIN
VIN = 0 V; Inputs with internal pull-up resistors
IINP
VIN = VDD; Inputs with internal pull-down
resistors
fin
Input Frequency1
Lpin
Pin Inductance
Cout
0.45
V
-5
5
uA
-200
200
uA
26
MHz
7
nH
5
pF
6
pF
0.6
1
ms
31.500
33
kHz
3
clocks
300
us
Single-ended inputs
Input Current1
CIN
V
XTAL, or XTAL_IN
23
25
1
Capacitance1
tSTAB
Clock output Stabilization1, 2
f MODIN
Input SS Modulation
Frequency1
tLATOE#
OE# Latency1, 3
tDRVPD
Tdrive_PD#1, 3
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Control Inputs
1.5
Output pin capacitance
From VDD Power-Up and after input clock
stabilization or de-assertion of CKPWRGD_
PD# to 1st clock
Allowable Frequency
(Triangular Modulation)
CLK start after OE# assertion
CLK stop after OE# deassertion
CLK output enable after
CKPWRGD_PD# de-assertion
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PI6CDBL401B
4-Output Low Power PCIE GEN1-2-3 Buffer
Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions Cont...
Symbol
Parameters
Condition
tF
Fall time1, 2
tR
Rise time
VILSMB
SMBus Input Low Voltage
VIHSMB
SMBus Input High Voltage
VOLSMB
SMBus Output Low Voltage
@ IPULLUP
IPULLUP
SMBus Sink Current1
@ VOL
4
VDDSMB
Nominal Bus Voltage1
3.3V bus voltage
2.7
tRSMB
SCLK/SDATA Rise Time
tFSMB
SCLK/SDATA Fall Time
f MAXSMB
SMBus Operating Frequency
1, 2
Min.
Type
Max.
Units
Control inputs
5
ns
Control inputs
5
ns
0.8
V
3.6
V
0.4
V
1
2.1
1
1
1
1
1, 5
mA
3.6
V
(Max VIL - 0.15) to (Min VIH + 0.15)
1000
ns
(Min VIH + 0.15) to (Max VIL - 0.15)
300
ns
Maximum SMBus operating frequency
400
kHz
Note:
1. Guaranteed by design and characterization, not 100% tested in production.
2. Control input must be monotonic from 20% to 80% of input swing. Input Frequency Capacitance
3. Time from deassertion until outputs are >200 mV
4. The differential input clock must be running for the SMBus to be active
Electrical Characteristics–CLK 0.7V Low Power HCSL Outputs (TA = -40~85oC; VDD = 3.3V+/-10%;
VDDO = 1.8V+/-10%, See Test Loads for Loading Conditions)
Symbol
Trf
Parameters
Slew rate
1,2,3
Condition
Min.
Type
Max.
Units
Scope averaging on 2.0V/ns setting @100MHz
output
1
2
3
V/ns
Scope averaging on 3.0V/ns setting @100MHz
output
2
3
4.5
V/ns
7
20
%
660
880
mV
-150
150
mV
1150
mV
ΔTrf
Slew rate matching1,2,4
Slew rate matching, Scope averaging on
VHIGH
Voltage High
VLOW
Voltage Low1,7
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope averaging
on)
Vmax
Max Voltage1
Measurement on single ended signal using
Vmin
Min Voltage
absolute value. (Scope averaging off)
-300
mV
Vswing
Vswing
Scope averaging off
300
mV
Vcross_abs
Crossing Voltage (abs)1,5,7
Scope averaging off
250
Δ-Vcross
Crossing Voltage (var)1,6
Scope averaging off
1,7
1
1,2,7
550
mV
140
mV
Note:
1. Guaranteed by design and characterization, not 100% tested in production.
2. Measured from differential waveform
3. Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around differential 0V.
4. Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point
where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations.
5. Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock rising and
Clock# falling).
6. The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross absolute) allowed. The intent is to
limit Vcross induced modulation by setting Δ-Vcross to be smaller than Vcross absolute.
7. At default SMBus settings.
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PI6CDBL401B
4-Output Low Power PCIE GEN1-2-3 Buffer
Electrical Characteristics–Current Consumption (TA = -40~85oC; VDD = 3.3V+/-10%; VDDO = 1.8V+/10%, See Test Loads for Loading Conditions)
Symbol
IDDAOP
IDDOP
IDDAPD
IDDPD
Parameters
Condition
Operating Supply Current1
Powerdown Current1,2
Min.
Type
Max.
Units
VDDA+VDDR, PLL Mode, @100MHz
37
45
mA
VDD1.8, All outputs active @100MHz
52
60
mA
VDDA+VDDR, PLL Mode, @100MHz
1
mA
VDD1.8, Outputs Low
1.8
mA
Note:
1. Guaranteed by design and characterization, not 100% tested in production.
2. Input clock stopped.
Electrical Characteristics–Output Duty Cycle, Jitter, Skew and PLL Characterisitics (TA =
-40~85oC; VDD = 3.3V+/-10%; VDDO = 1.8V+/-10%, See Test Loads for Loading Conditions)
Symbol
Parameters
tDC
Duty Cycle1
tDCD
Duty Cycle Distortion
tpdBYP
tpdPLL
1,3
Skew, Input to Output1,4
tskew
Skew, Output to Output
tjcyc-cyc
Jitter, Cycle to cycle
1,2
Condition
Min.
Measured differentially, PLL Mode
45
Measured differentially, Bypass [email protected]
-1
Bypass Mode, VT = 50%
PLL Mode VT = 50%
VT = 50%
Type
Max.
Units
55
%
1
%
2500
4500
ps
-250
250
ps
50
ps
50
ps
25
ps
0
25
PLL mode @100MHz output
1,2
Additive Jitter in Bypass Mode @100MHz
output
0.1
Note:
1. Guaranteed by design and characterization, not 100% tested in production.
2. Measured from differential waveform
3. Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.
4. All outputs at default slew rate
5. The MIN/TYP/MAX values of each BW setting track each other, i.e., Low BW MAX will never occur with Hi BW MIN.
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PI6CDBL401B
4-Output Low Power PCIE GEN1-2-3 Buffer
Electrical Characteristics–Phase Jitter Parameters (TA = -40~85oC; VDD = 3.3V+/-10%; VDDO =
1.8V+/-10%, See Test Loads for Loading Conditions)
Type
INDUSTRY
LIMIT
Units
PCIe Gen 11,2,3
34
86
PCIe Gen 2 Low Band 10kHz < f < 1.5MHz1,2
0.9
3
PCIe Gen 2 High Band 1.5MHz < f < Nyquist
(50MHz)1,2
2.2
3.1
tjphPCIeG3
PCIe Gen 3 (PLL BW of 2-4MHz, CDR = 10MHz)1,2,4
0.5
1
tjphSGMII
125MHz, 1.5MHz to 20MHz, -20dB/decade rollover <
1.5MHz, -40db/decade rolloff > 10MHz1,6
1.9
NA
tjphPCIeG1
PCIe Gen 11,2,3
0.6
N/A
PCIe Gen 2 Low Band 10kHz < f < 1.5MHz1,2,5
0.1
N/A
PCIe Gen 2 High Band 1.5MHz < f < Nyquist
(50MHz)1,2,5
0.05
N/A
tjphPCIeG3
PCIe Gen 3 (PLL BW of 2-4MHz, CDR = 10MHz)1,2,4,5
0.05
N/A
tjphSGMII
125MHz, 1.5MHz to 10MHz, -20dB/decade rollover <
1.5MHz, -40db/decade rolloff > 10MHz1,6
0.15
N/A
Symbol
Parameters
tjphPCIeG1
tjphPCIeG2
tjphPCIeG2
Phase Jitter, PLL
Mode
Additive Phase
Jitter,
Bypass Mode
Condition
Min.
ps
(p-p)
ps
(rms)
ps
(rms)
ps
(rms)
ps
(rms)
ps
(p-p)
ps
(rms)
ps
(rms)
ps
(rms)
ps
(rms)
Note:
1. Applies to all outputs, with device driven by 9FG432AKLF or equivalent.
2. See http://www.pcisig.com for complete specs
3. Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
4. Subject to final ratification by PCI SIG.
5. For RMS figures, additive jitter is calculated by solving the following equation: Additive jitter = SQRT[(total jitter)^2 - (input jitter)^2]
6. Applies to all differential outputs
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PI6CDBL401B
4-Output Low Power PCIE GEN1-2-3 Buffer
Test Loads
Low-Power HCSL Differential Output Test Load
5 inches
Rs
Zo=100Ω
Rs
2pF
2pF
Device
Driving LVDS
RO
3.3V
Driving LVDS
R7a
R7b
R8a
R8b
Cc
Rs
Zo
Cc
Rs
Device
LVDS Clock
input
R
Driving LVDS inputs with the PI6CDBL401B
Value
Component
Receiver has termination
Receiver does not have termination
R7a, R7b
10K Ω
140 Ω
R8a, R8b
5.6K Ω
75 Ω
Cc
0.1 uF
0.1 uF
1.2 volts
1.2 volts
Vcm
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PI6CDBL401B
4-Output Low Power PCIE GEN1-2-3 Buffer
Serial Data Interface (SMBus)
This part is a slave only device that supports blocks read and block write protocol using a single 7-bit address and read/write bit as
shown below.
Read and write block transfers can be stopped after any complete byte transfer by issuing STOP.
Address Assignment
Refer to SMBus Address Selection Table.
Data Protocol
(Write)
1 bit
8 bits
1
8 bits
1
8 bits
1
8 bits
1
Start bit
Slave
Addr: D4
Ack
Register
offset
Ack
Byte
Count=N
Ack
Data
Byte 0
Ack
…
8 bits
1
1 bit
Data
Byte N-1
Ack
Stop bit
(Read)
1 bit
Start bit
8 bits
1
8 bits
1
1
8 bits
1
8 bits
1
Slave
Register
Repeat
Slave
Byte
Ack
Ack
Ack
Ack
Addr: D4
offset
start Addr: D5
Count=N
8 bits
1
8 bits
1
Data
Data Byte NOT
Ack …
Byte 0
N-1
Ack
1 bit
Stop
bit
Note:
1. Register offset for indicating the starting register for indexed block write and indexed block read. Byte Count in write mode cannot be 0.
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PI6CDBL401B
4-Output Low Power PCIE GEN1-2-3 Buffer
SMBus Table: Output Enable Register
1
Byte 0
Name
Control Function
Type
7
Reserved
6
OE3
Output Enable
RW
Low
Enabled
1
5
OE2
Output Enable
RW
Low
Enabled
1
4
Reserved
3
OE1
2
Reserved
1
OE0
0
Reserved
0
1
Default
1
1
Output Enable
RW
Low
Enabled
1
1
Output Enable
RW
Low
Enabled
1
1
1. A low on these bits will overide the OE# pin and force the differential output Low.
SMBus Table: PLL Operating Mode and Output Amplitude Control Register
Byte 1
Name
Control Function
Type
7
PLLMODERB1
PLL Mode Readback Bit 1
R
6
PLLMODERB0
PLL Mode Readback Bit 0
5
PLLMODE_
SWCNTRL
Enable SW control of PLL Mode
4
PLLMODE1
PLL Mode Control Bit 1
RW1
3
PLLMODE0
PLL Mode Control Bit 0
RW1
2
Reserved
1
AMPLITUDE
1
0
AMPLITUDE
0
0
1
Default
Latch
See PLL Operating Mode Table
R
RW
Latch
Values in
B1[7:6]
set PLL Mode
Values in B1[4:3]
set PLL Mode
See PLL Operating Mode Table
0
0
0
1
RW
00 = 0.6V
01 = 0.7V
1
RW
10= 0.8V
11 = 0.9V
0
0
1
Default
Controls Output Amplitude
1. B1[5] must be set to a 1 for these bits to have any effect on the part.
SMBus Table: DIF Slew Rate Control Register
Byte 2
Name
Control Function
Type
7
Reserved
6
SLEWRATESEL DIF3
Slew Rate Selection
RW
2 V/ns
3 V/ns
1
5
SLEWRATESEL DIF2
Slew Rate Selection
RW
2 V/ns
3 V/ns
1
4
Reserved
3
SLEWRATESEL DIF1
2
Reserved
1
1
Slew Rate Selection
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RW
2 V/ns
3 V/ns
1
1
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PI6CDBL401B
4-Output Low Power PCIE GEN1-2-3 Buffer
SMBus Table: DIF Slew Rate Control Register Cont...
Byte 2
Name
Control Function
Type
0
1
Default
1
SLEWRATESEL DIF0
Slew Rate Selection
RW
2 V/ns
3 V/ns
1
0
Reserved
1
SMBus Table: Frequency Select Control Register
Byte 3
Name
Control Function
Type
7
Reserved
1
6
Reserved
1
5
Reserved
0
4
Reserved
0
3
Reserved
0
2
Reserved
1
1
Reserved
1
0
Reserved
1
0
1
Default
Byte 4 is Reserved and reads back 'hFF
SMBus Table: Revision and Vendor ID Register
Byte 5
Name
Control Function
Type
7
RID3
6
RID2
5
RID1
4
RID0
R
0
3
VID3
R
0
2
VID2
R
0
1
VID1
R
0
0
VID0
R
0
0
R
R
Revision ID
R
VENDOR ID
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15-0071
13
1
Default
0
A rev = 0000
0
0
www.pericom.com06/05/15
PI6CDBL401B
4-Output Low Power PCIE GEN1-2-3 Buffer
SMBus Table: Device Type/Device ID
Byte 6
Name
Control Function
7
Device Type1
6
Device Type0
5
Device ID5
R
0
4
Device ID4
R
0
3
Device ID3
2
Device ID2
1
Device ID1
R
0
0
Device ID0
R
0
Device Type
Type
0
R
00 = FGV, 01 = DBV,
0
R
10 = DMV, 11= Reserved
1
R
Device ID
R
1
000100 binary or 04 hex
Default
0
1
SMBus Table: Byte Count Register
Byte 7
Name
Control Function
7
Reserved
0
6
Reserved
0
5
Reserved
0
4
Reserved
0
3
Reserved
0
2
Reserved
0
1
Reserved
0
0
Reserved
0
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15-0071
Type
14
0
1
Default
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PI6CDBL401B
4-Output Low Power PCIE GEN1-2-3 Buffer
Thermal Characteristics
Symbol
Parameter
Condition
θJA
Thermal Resistance Junction to Ambient
Still air
θJA
Thermal Resistance Junction to Case
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15
Min.
Type
Max.
Units
44.7
°C/W
21.7
°C/W
www.pericom.com06/05/15
PI6CDBL401B
4-Output Low Power PCIE GEN1-2-3 Buffer
Packaging Mechanical : TQFN (ZH32)
Notes:
1. All dimensions are in mm. Angles in degrees.
2. Coplanarity applies to the exposed pad as well as the terminals.
3. Refer JEDEC MO-220
4. Recommended land pattern is for reference only.
5. Thermal pad soldering area (mesh stencile design is recommended)
DATE: 06/30/11
DESCRIPTION: 32-contact, Thin Quad Flat No-Lead (TQFN)
PACKAGE CODE: ZH32
DOCUMENT CONTROL #: PD-2070
REVISION: B
11-0147
Note: For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php
Ordering Information(1-3)
Ordering Code
Package Code
Package Description
PI6CDBL401BZHIE
ZH
32-contact, Thin Quad Flat No-Lead (TQFN)
PI6CDBL401BZHIEX
ZH
32-contact, Thin Quad Flat No-Lead (TQFN), Tape & Reel
Notes:
1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
2. E = Pb-free and Green
3. Adding an X suffix = Tape/Reel
Pericom Semiconductor Corporation • 1-800-435-2336
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