PRELIMINARY TECHNICAL DATA = Evaluation Board AD1555/AD1556 24-Bit ⌺-⌬ ADC Preliminary Technical Data EVAL-AD1555/56EB FEATURES : On-Board Reference, Oscillator, Control Logic and Buffers Easy interface to printer port of PC PC Software for Control and Data Analysis Stand Alone Capability to ease design Analog and Digital Prototype Area The EVAL-AD1555/56EB is ideal for use either as a standalone evaluation board to interface with a customer application or with any compatible PC using the parallel printer port. GENERAL DESCRIPTION The EVAL-AD1555/56EB is an evaluation board for the AD1555 and AD1556 24-bit ⌺-⌬ ADC chip-set. The AD1555/AD1556 chip-set can convert a high dynamic range input signal, operates from +5V and -5V supplies and uses a serial interface. The AD1555/AD1556 evaluation board is designed to demonstrate the ADC's performance and operation. A full description of the AD1555/AD1556 is available in the AD1555/AD1556 data sheet and should be consulted when utilizing this evaluation board. Software is provided to allow simple demonstration and evaluation of the AD1555/AD1556 chip-set. On-board components include an AD780 3V ultra low noise bandgap reference, a crystal oscillator, and digital control logic. The board has both a Centronics male connector to interface with PC printer port and a 50-pin connector for stand-alone operation. FUNCTIONAL BLOCK DIAGRAM SJ3 +5V SJ2 - 5V SJ1 +5V +5V oscillator Ref AD1555 Ain PGA Σ ∆ mod FPG A 25-WAY D-Type connector AD1556 Tin PGA_M OD 50-Way connector REV. PrD Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 PRELIMINARY TECHNICAL DATA EVAL-AD1555/AD1556 TABLE II. JUMPER DESCRIPTION OPERATING THE EVAL-AD1555/56EB The EVAL-AD1555/56EB is a two-layer board carefully laid out and tested to demonstrate the specific high dynamic performance of the chip-set. Figure 4 shows the schematics of the evaluation board. The layout of the board is given in the next four figures : Figure 5 shows the Top side silk-screen. Figure 6 shows the Top layer. Figure 7 shows the Bottom side silk-screen. Figure 8 shows the Bottom layer. The available test points are listed in Table I and a description of each selectable jumper is listed in Table II. The component list is provided in Table III. Jumper SW1 JP1 Power Supplies and Grounding : The EVAL-AD1555/56EB has three power supply blocks: a single +5V supply Vcc (SJ1) for the evaluation board digital section, another +5V or +3.3V supply VL (SJ2) for the digital supply of AD1555 only and a +/-5V supply (SJ3) for the analog section of AD1555. The evaluation board ground plane is separated into three sections: a DGND plane for the AD1556 and the digital interface circuitry, a LGND plane for the digital section of AD1555 and an analog AGND plane for the AD1555, its analog input and external reference circuitry. To facilitate grounding connections of test equipment and attain high performance the board was designed with a good isolation barrier between the AD1555 and the rest of the digital functions. This isolation barrier is not required in applications where the analog and digital ground are not tied together externally. That is achieved using optocouplers and high value resistors. The analog ground and AD1555 digital ground can be tied together close to the AD1555 using JP2 which is the optimal configuration. Analog inputs : Fully differential signals could be applied on either AIN and TIN inputs through SMB plugs. The analog input ranges have to be compatible with the PGA gain settings used as described in the AD1555/AD1556 datasheet. The modulator section of the AD1555 can be separately evaluated using the PGA_MOD SMB plug. TABLE I. EVAL-AD1555/56EB Test Points Test Point TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 Available Signal REFIN (3V) DGND ( FPGA ) DGND ( AD1556 ) CB0 CB1 CB2 CB3 CB4 MDATA MCLKOUT MFLG JP2 Function To get all the software functionality, SW1 should be in the position where the identification dot on the core of the switch is visible. When SW1 is in the other position ( the switch hole is hidden ), the AD1556 could be controlled externally using the 50-pin connector P2. ( see chapter using the EVAL-AD1555/56EB in customized system for details ). JP1 controls the input signal applied to the AD1555 modulator input MODIN. In position A, the PGA output is applied to MODIN. In position B, the signal on PGA_MOD SMB plug is applied to MODIN. JP2 allows LGND and AGND to be tied together close to the AD1555 which is generally the preferred configuration. RUNNING THE EVAL-AD1555/56EB SOFTWARE Software Description : The EVAL-AD1555/56EB comes with software for analyzing the AD1555/AD1556 chip-set. This software allows comprehensive control and evaluation of the AD1555/AD1556 chipset or the AD1555 and the AD1556 separately. The frontend PC software has only one screen shown in Figure 1. This screen is partitioned into five windows which allows the user to select the configuration, launch the sampling sequence, perform computation on the output signal and display the results. The choices for display are Time domain response, Spectral response and histogram chart. Different measurements as Dynamic range, equivalent input noise, Total Harmonic Distortion (THD) and DC offset can be done. Figure 1 describes the steps to follow for proper software operation. Software Installation : The EVAL-AD1555/56EB software runs under Windows95. It requires a minimum of 7MB hard-disk space available and a display with a minimum resolution of 800 by 600. Due to the real-time operation, it is recommended that other programs be closed when using the EVAL-AD1555/56EB software. The EVAL-AD1555/56EB software installation process is: - Run Setup.exe using the EVAL-AD1555/56EB disk 1 and follow the instructions. The files can be stored in any directory at the user convenience using the destination folder field. The default folder is C:\Program Files\Ad1555_56. - Run AD1555_56.exe to launch the software. It will open the window in figure 1. - If the window in figure 1 exceeds the actual screen, the display resolution needs to be increased by opening Start>Settings>Control Panel>Display then settings> 800*600 for desktop area >apply>OK. –2– REV. PrD PRELIMINARY TECHNICAL DATA EVAL-AD1555/AD1556 - The software uses a special font which can be installed using Start>Settings>Control Panel>Fonts>File>install new fonts> then select ADILogo Regular in the working directory then OK. - To operate the software, follow the 5 steps described in figure 1. Using the EVAL-AD1555/56B in the customized system : The EVAL-AD1555/56EB is also designed to ease the evaluation and the design of the AD1555 and the AD1556 in the customized system. The useful interface signals can be connected to the customized system using the connector P2. The switch SW1 in the position where the identification dot of the switch is hidden changes the configuration of U1 as follows : - The AD1556 CLKIN at 1.024MHz is supplied by U1 ( exact division by 8 of U5 oscillator ). - U1 transmits the AD1556 MCLK output ( 256kHz ) to the AD1555 MCLK with the appropriate phase ( one inversion is done by U1 in order to cancel the U9 inversion). - U1 output pins PGA0-4, CS*, R/W*, DINM1, BW0-2, H/S*, RSEL, CSEL, PWRDN, RESET, SYNC, SCLKOUT, TDATA are Hi-Z . This configuration allows the control of these signals by the customized system. The AD1555 and AD1556 clock are still generated by the EVAL-AD1555/56EB. TABLE III. Component List. Integrated Circuits U1 FPGA EPM7128ELC84-15. U2 AD1556AS. U3 AD1555AP. U4 reference AD780AN. U5 Oscillator 8.192MHz. U6 Buffer 74HC245. U7 Invertor 74HC04. U8,U9 Optocoupler HCPL2630. Capacitors C1-C6,C8-C9,C11-C12, C14-C16,C22-C24,C27, C29-C31,C33,C34 C7,C10,C13,C17-C18, C21,C25,C26,C28 C20 REV. PrD 100nF Ceramic Capacitors. 10F Tantalum Capacitors. 22F Tantalum Capacitor 6.3v. –3– Resistors R6,R10-R15 R1-R5 R8,R9 R17,R21,R22 R18-R20 R16 47.5K⍀ Resistor. 13K⍀ Resistor. 4.7K⍀ Resistor. 2K⍀ Resistor. 402⍀ Resistor. 10⍀ Resistor. Sockets P2 P1 JP2 PB1 SW1,JP1 SMB1-SMB5 50pin Male ribbon cable connector. 25pin DB-25 connector. 2 Position Male jumper strip. SMT push-button. Slide Switch. SMB Connector. PRELIMINARY TECHNICAL DATA EVAL-AD1555/AD1556 Step 1 Start execution: click on the double-arrows icon to start execution. Step 2 Configuration menu: Selects Configuration, Signal input, PGA gain setting, AD1556 filter selection, power controls, interface settings. Display window : displays either Time domain or Frequency domain or Histogram and/or performance values such as dynamic range, equivalent input noise level, THD and DC offset. Step 5 Display menu : selects Time/Frequency domain or histogram, controls display parameters ( scales, zoom, cursor...), and controls outputs ( save to file or print ). Step 4 Computation menu : COMPUTE launches the specified computation data process before display, allowing windowing, software filtering or measurements computation if desired. Compute sequence should be done again after changes into computation, sampling, configuration menus. F3 is the key command for "compute". Step 3 Sampling menu : after the desired samples number is selected, SAMPLE launches a sampling sequence. When complete, "Successful" will appear in the status window. If not, verify the configuration and the hardware setup. When the configuration or sampling menu is modified, a sampling sequence should be done again. F2 is the key command for "sample". "Continuous" allows continuous running sampling and computing (F4 is the key command key for "continuous"). "Average" allows the averaging between successive sampling. Figure 1. Software main screen. –4– REV. PrD PRELIMINARY TECHNICAL DATA EVAL-AD1555/AD1556 Measurements display : This window displays the measurements. When a signal approximately at least 10 times higher than the noise floor is detected, the THD is measured otherwise, the dynamic range and equivalent input noise are displayed. Measurement enable : This button enables the measurements computation when on. 50 Hz or 60 Hz rejection filter can be used before noise computation. The number of harmonics uses in the THD computation is selectable. Figure 2. Frequency domain screen with measurements. REV. PrD –5– PRELIMINARY TECHNICAL DATA EVAL-AD1555/AD1556 Status Register display : This window displays each bit of the AD1556 status register. The displayed value is the status register value corresponding to the data value marked with the cursor in the time domain display. Status enable : This button enables the AD1556 Status register reading. This feature is only available in time domain. Figure 3. Time domain screen with AD1556 Status register content. –6– REV. PrD DB25 P1 AGND 1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 13 C34 .1uF 3 7 1 TRIM 2.5/3vSEL VOUT DGND 3 2 1 JUMP M1M0 C0 C1 DIN A8 SCLK C2 RWLOAD C3 CSS RGND AD780 TEMP N/C N/C U4 2 +VIN GND 4 19 1 2 3 4 5 6 7 8 9 MCLKIN CSEL MCLKOUT CLK56 SYNC TDATA PWRDN RESET ERROR* DINM1 RSEL R/W* CS DRDY DOUT SCLKOUT HS BW2 BW1 BW0 CB4 CB3 CB2 CB1 CB0 A8 5 TP1 4.7K R8 VCC C11 .1uF DGND SW1 R9 4.7K C10 10uF DGND VCC 2 4 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 HEADER 25X2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 P2 MFLG DGND MDATA 1 3 DGND 8.192MHz GND +5v OUT U5 CLKIN83 30 31 RST 37 M1M0 C26 PB1 36 CSS 10uF RWLOAD 35 34 SCLK 33 DIN DGND 65 MCLKIN U6 8 DRDY 18 9 DOUT B0 A0 17 64 MDATA B1 A1 16 TP2 25 MFLG B2 A2 S6 15 77 ERROR* B3 A3 S7DGND 14 1 B4 A4 S5 13 2 B5 A5 S4 12 84 DGND B6 A6 S3 11 39 B7 A7 6 46 E 79 74HC245 DIR REFIN AGND AGND 8 6 C24 .1uF VCC CLKIN C15 .1uF C27 .1uF VCC DGND VCC C28 10uF C30 .1uF CLKIN MANUAL RST M1M0 CSSWRST R/W*LOAD SCLK DIN MCLKIN DRDY DOUT MDATA MFLG ERROR* GLOBALCLEAR GLOBALOE1 GLOBALOE2 NC NC NC NC U1 FPGA_84 R6 CS* R/W* SCLKOUT DINM1 BW2 BW1 BW0 H/S* RSEL I/O OUTEST RESET CSEL PWRDN SYNC TDATA MCLKOUT CLK56 S3 S4 S5 S6 S7 CB0 CB1 CB2 CB3 CB4 5 4 10 80 12 14 15 11 81 73 74 76 71 75 69 70 63 67 50 49 48 44 45 C21 10uF V+ C0 C1 C2 C3 TEST 47.5K C18 10uF AGND SMB4 TIN_P AGND TP12 RESET CSEL PWRDN SYNC TDATA MCLKOUT CLK56 S3 S4 S5 S6 S7 CS R/W* SCLKOUT DINM1 BW2 BW1 BW0 HS RSEL SMB5 TIN_N C23 .1uF V- VCC CB4 CB3 CB2 CB1 CB0 13K 13K 13K 13K 13K DGND TP3 C12 .1uF C29 .1uF R12 R13 TP6 R14 PGA0 PGA1 PGA2 PGA3 PGA4 CS* R/W* SCLK DIN DRDY ERROR* DOUT U2 VCC AD1556 REFIN C14 .1uF TP8 5 6 7 8 2 28 C31 .1uF TP7 C13 10uF AIN+ AINTIN+ TINPGAOUT MODIN MDATA TDATA PWRDN CSEL BW0 BW1 BW2 RESET NC NC RSEL H/S* MFLG SYNC CLK56 MCLKIN 47.5K 47.5K 47.5K 47.5K 47.5K R11 TP5 SMB1 PGA_MODE TP4 3 2 JP1 1 R10 B A C17 10uF C9 .1uF VL LGND C16 .1uF C8 .1uF SMB2 AIN_P 2 CB0 3 CB1 4 CB2 5 CB3 6 CB4 16 CS 17 R/W* SCLKOUT 13 DINM1 19 15 DRDY ERROR* 20 14 DOUT R5 R4 R3 R2 R1 SMB3 AIN_N C22 .1uF C7 10uF DGND C6 .1uF 25 REFIN C5 .1uF 24 23 C19 22uF RGND REFCAP2 REFCAP1 C4 .1uF AD1555 U3 36 30 26 29 7 8 9 25 27 28 18 10 +VA 3 LGND RSEL HS U7B JP2 AGND VCC 4 7 2K 2 LGND U9A VL 2 1 402 V- SJ1 DGND 402 47.5K R15 R19 VL 2 1 U8B Date: File: A Size Title 1 10 R16 6 SJ3 MFLG AGND V6 U7D U7F 74HC04 U9B U7E 74HC04 A YU7C 74HC04 3 4 HCPL2630 10 6 12 74HC04 8 AD1555 Evaluation Board 2 V+ TP11 R22 MDATA MCLKOUT DGND LGND Revision 11 5 13 9 ' Sheet of 21-Feb-2002 0277, Drawn By: C:\ANALOG PROJECTS\AD1555REVDEVAL\AD1555REVD.Ddb Number R21 TP10 DGND 402 TP9 HCPL2630 7 VCC 2K U8A HCPL2630 LGND 3 4 2K SJ2 LGND R20 C33 .1uF LGND R18 VCC C20 22uF RGND C32 22uF HCPL2630 DGND VL LGND TEST V+ 74HC04 U7A 20 16 19 9 4 3 74HC04 MCLK R17 1 -VA LGND VL TEST -VA TP13 MDATA TDATA PWRDN CSEL BW0 BW1 BW2 RESET V- 26 21 C25 10uF 82 72 59 47 42 32 19 7 78 66 53 43 38 26 13 3 21 20 18 17 16 GND GND GND GND GND GND GND GND VCC VCC VCC VCC VCC VCC VCC VCC PGA0 PGA1 PGA2 PGA3 PGA4 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 40 41 51 52 54 55 56 57 58 60 61 62 68 22 23 24 27 28 29 22 27 1 CB0 CB1 CB2 CB3 CB4 MFLG MCLK MDATA 10 11 12 13 14 15 18 17 +VA -VA 2 C3 .1uF DGND DGND DGND DGND 34 24 23 12 2 AGND3 AGND2 AGND1 1 8 5 1 C2 .1uF 33 21 1 43 42 41 40 39 38 31 32 35 37 NC NC NC CB0 CB1 CB2 CB3 CB4 MFLG SYNC CLKIN MCLK NC 44 22 11 VCC VCC VCC 2 8 5 C1 .1uF 1 –7– 3 REV. PrD 1 Figure 4. Schematics. 2 V+ PRELIMINARY TECHNICAL DATA EVAL-AD1555/AD1556 PRELIMINARY TECHNICAL DATA EVAL-AD1555/AD1556 Figure 5. Top side silk-screen ( not to scale). Figure 6. Top layer ( not to scale). –8– REV. PrD PRELIMINARY TECHNICAL DATA EVAL-AD1555/AD1556 Figure 7. Bottom side silk-screen ( not to scale). Figure 8. Bottom layer ( not to scale). REV. PrD –9–