PI90LVB16

PI90LVB16
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
3V Bus LVDS 1-to-6
Clock Buffer/Bus Transceiver
Features
General Description
•
•
•
•
•
•
•
•
•
•
PI90LVB16 is a six-channel LVTTL clock distribution driver with 50
picosecond channel-to-channel skew. It translates one BLVDS
(Bus Low-Voltage Differential Signaling) input signal into six LVTTLcompatible output signals for distribution to adjacent chips on the
same board. The PI90LVB16 accepts BLVDS (300mV typical) differential input levels, and translates them to 3V CMOS output levels.
The 160MHz PI90LVB16 can be the master clock, driving inputs of
other clock I/O pins in a multipoint environment. It can also drive
the BLVDS backplane with a separate channel acting as a return/
source LVTTL clock source. The master/slave clock selection of the
driving source is controlled by the CrdCLKIN and the DE pins. An
output enable pin OE, when high, forces all CLKOUT pins high.
A backplane clock distribution network must be able to drive many
transmission line stubs. The Bus LVDS feature of the PI90LVB16 is
ideal for driving data transfers in large, high-performance backplane
system applications. The device can be used as a source synchronous driver to distribute clock signals within data and telecommunications systems.
Master/Slave clock selection in a backplane application
160 MHz operation (typical)
100ps duty cycle distortion (typical)
50ps channel to channel skew (typical)
3.3V power supply design
Glitch-free power on at CLKI/O pins
Low Power design (16mA @ 3.3V static)
Accepts small swing (300mV typical) differential signal levels
Industrial temperature operating range (–40°C to +85°C)
Packaging: (Pb-free & Green available)
— 24-pin TSSOP (L)
Receive Mode Truth Table
Driver Mode Truth Table
Input
Input
Output
OE
DE
CrdCLKIN CLKI/O+
L
L
L
L
L
H
CLKI/O–
CLKOUT
L
H
L
H
H
H
L
H
L
L
L
H
H
H
L
H
H
L
H
H
H
X
Z
Z
H
Output
CrdCLKIN
(CLKI/O+)–(CLKI/O–)
CLKOUT
H
X
X
H
L
H
X
VID ≥ 0.07V
H
L
H
X
VID ≤ –0.07V
L
OE DE
L = Low Logic State; H = High Logic State; X = Irrelevant
Z = High Impedance
Function Diagram
CLKOUT0
CLKOUT1
OE
CLKI/0+
CLKI/0–
R
MUX
Delay
CLKOUT5
D
DE
CrdCLKIN
08-0295
1
PS8536C
11/11/08
PI90LVB16
3V Bus LVDS 1-to-6
Clock Buffer/Bus Transceiver
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
Connection Diagram
GND
1
24
VCC
OE
2
23
CLKOUT0
GND
NC
3
22
VCCA
4
21
CLKOUT1
20
VCC
19
CLKOUT2
GNDA
5
CLKI/0+
6
CLKI/0–
7
18
GND
GNDA
8
17
CLKOUT3
CrdCLKIN
24-Pin
L
9
16
VCC
NC
10
15
CLKOUT4
DE
11
14
GND
GND
12
13
CLKOUT5
TSSOP Package Pin Description
Pin Name
Pin #
Type
CLKI/O+
6
I/O
True (Positive) side of the differential clock input.
CLKI/O–
7
I/O
Complementary (Negative) side of the differential clock input.
OE
2
I
OE; this pin is active Low. When High, this pin forces all CLKOUT pin High. When Low,
CLKOUT pins logic state is determined by either the CrdCLKIN or VID at the CLKI/O
pins with respect to the logic level at the DE pin. This pin has a weak pullup device to
VCC. If OE is floating, then all CLKOUT pins will be High.
DE
11
I
DE; this pin is active Low. When Low, this pin enables the CardCLKIN signal to the
CLKI/O pins and CLKOUT. When High the Driver is 3- State, the CLKI/O pins are
inputs and determine the state of the CLKOUT pins. This pin has a weak pullup device to
VCC. If DE is floating, then all CLKI/O pins are 3- State.
CLKOUT
13,15,17,19,21,23
O
Six Buffered clock (CMOS) outputs.
CrdCLKIN
9
I
Input clock from Card (CMOS level or TTL level).
VCC
16,20,24
Power
GND
1,12,14,18,22
VCCA
4
GNDA
5,8
NC
3,10
08-0295
De s cription
VCC; Analog VCCA (Internally separate from VCC, connect externally or use separate
power supplies). No special power sequencing required. Either VCCA or VCC can be
applied first, or simultaneously apply both power supplies.
Ground GND
Power
Analog VCCA (Internally separate from VCC, connect externally or use separate power
supplies). No special power sequencing required. Either VCCA or VCC can be applied
first, or simultaneously apply both power supplies.
Ground Analog Ground (Internally separate from Ground must be connected externally.
No Connects.
2
PS8536C
11/11/08
PI90LVB16
3V Bus LVDS 1-to-6
Clock
Buffer/Bus
Transceiver
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
Absolute Maximum Ratings(1)
Supply Voltage Range, VCC ..................................................................................... –0.3V to +4V
Enable Input Voltage (DE, OE, CrdCLKIN) .............................................. –0.3V to +4V
Voltage (CLKOUT)
............................................................... –0.3V to (VCC + 0.3V)
Voltage (CLKI/O±)
............................................................... –0.3V to (VCC + 0.3V)
Driver Short Circuit Current ....................................................................... momentary
Receiver Short Circuit Current .................................................................. momentary
Maximum Package Power Dissipation at +25°C
TSSOP Package
................................................................................... 1500mW
Derate TSSOP Package ..................................................... 8.2mW/°C above +25°C
θJA ........................................................................................................................................... 95°C/W
θJC ........................................................................................................................................... 30°C/W
Storage Temperature Range ............................................................. –65°C to +150°C
Lead Temperature Range (Soldering, 4s) ........................................................... 260°C
ESD Ratings: HBM(2) .................................................................................................................. 9kV
CLKOUT(0–5) .......................................................................................................................... ≥ 2kV
CDM(2) .................................................................................................................................. >1000V
Machine Model(2) ............................................................................................................... >200V
Recommended Operating Conditions
Min.
Supply Voltage (VCC)
+3.0
CrdCLKIN, DE, OE Input Voltage
0
Operating Free Air Temperature (TA) –40
08-0295
Typ.
+3.3
24
Max
+3.6
VCC
+85
3
Units
V
V
°C
PS8536C
11/11/08
PI90LVB16
3V Bus LVDS 1-to-6
Clock Buffer/Bus Transceiver
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
DC Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specificed(3,4)
Symbol
Parame te r
Conditions
Pin
VTH
Input Threshold High
VTL
Input Threshold Low
VCMR
Common Mode Voltage
VID = 250mV peak- to- peak
Range(5)
IIN
Input Current
VIN = OV to VCC, DE = VCC, OE = VCC,
Other Input = 1.2V ±50mV
VOH1R
Output High Voltage
VOH2R
M in.
Typ.
M a x.
25
75
mV
–70
CLKI/O+,
CLKI/O–
–3 5
⏐VID⏐/2
–10
±5
VID =250mV, IOH = –1.0mA
VCC –0.2
2. 9
Output High Voltage
VID =250mV, IOH = –6mA
VCC –0.6
2. 5
VOL1R
Output Low Voltage
IOL =1.0mA, VID = –250mV
VOL2R
Output Low Voltage
IOL =6mA, VID = –250mV
IODHR
IODLR
Units
CLKOUT Dynamic
Output Current(6)
+10
μA
V
0. 1
0
0.22
0.4
–16
–2 4
–34
14
25
37. 5
mA
VID = –250mV, VOUT = 1V
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
Input High Current
IIL
Input Low Current
VIN = GND or 0.4V
IINCRD
Input Current
VIN = 0V to VCC, OE = VCC
CrdCLKIN
–5
VCL
Input Voltage Clamp
IOUT = –1.5mA
OE, DE,
CrdCLKIN
–0.8
ICC
No Load Supply
Current
Outputs Enabled,
No VID Applied
OE = DE = 0V,
CrdCLKIN = VCC or GND,
CLKI/O(±) = Open
CLKOUT (0:5) = Open Circuit
ICC1
No Load Supply
Current
Outputs Enabled,
VID over Common
Voltage Range
OE = GND, DE = VCC,
CrdCLKIN = VCC or GND,
VID = 250mV (0.125V VCM 2.275V)
CLKOUT(0:5) = Open Circuit
ICCD
Driver Loaded Supply
Current
08-0295
V
0.04
CLKOUT
VID = +250mV, VOUT = VCC–1V
2.8 –
⏐VID⏐/2
DE, OE,
CrdCLKIN
VIN = VCC or 2.4V
2.0
VCC
GND
0 .8
–6
4
6
–20
11
+20
V
OE, DE
μA
5
V
10
DE = OE = 0V,
CrdCLKIN = VCC or GND,
RL = 37.5Ω between CLKI/O+
and CLKI/O–, CLKOUT (0:5) = Open Circuit
4
VCC
6
16
mA
21
PS8536C
11/11/08
PI90LVB16
3V Bus LVDS 1-to-6
Clock
Buffer/Bus
Transceiver
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
DC Electrical Characteristics (continued)
Over Supply Voltage and Operating Temperature ranges, unless otherwise specificed(3,4)
Symbol
Parame te r
VOD
Driver Output Differential
Voltage
ΔVOD
Driver VOD Magnitude
Change
VOS
Driver Offset Voltage
ΔVOS
Driver Offset Voltage
Multitude Change
VOHD
Driver Output High
VOLD
Driver Output Low
IOS1D
Driver Differential Short
Circuit Current(6)
IOS2D
Driver Differential Short
Circuit Current to VCC(6)
IOS3D
IOS4D
Driver Differential Short
Circuit Current to GND(6)
IOS5D
Power Off Leakage
Current
IOFF
Conditions
Pin
M in.
Typ.
M ax.
250
350
45 0
Units
mV
RL = 37.5Ω, Figure 5
DE = 0V
1.1
CrdCLKIN = VCC or GND,
VOD = 0V, (outputs shorted together), DE = 0V
CLKI/O+,
CLKI/O–
0.8
2
20
1.25
1.5
V
1
20
mV
1.4
1.8
V
1.05
± 13
± 17
CrdCLKIN = GND, DE = 0V, CLKI/O+ = VCC
11
17
CrdCLKIN = VCC, DE = 0V, CLKI/O– = VCC
10
17
CrdCLKIN = VCC, DE = 0V, CLKI/O+ = 0V
–15
–17
CrdCLKIN = GND, DE = 0V, CLKI/O– = 0V
–15
–17
VCC = 0V or Open, VAPPLIED = 3.6V
mA
± 20
μA
Units
Switching Characteristics
Differential Receiver Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specificed(7,8)
Symbol
Parame te r
Conditions
M in.
Typ.(1)
M ax.
tPHLDR
Differential Propagation Delay High to Low. CLKI/O to CLKOUT
1.3
2.6
3. 8
tPLHDR
Differential Propagation Delay Low to High. CLKI/O to CLKOUT
1.3
2. 6
3.8
tSK1R
Duty Cycle Distortion(10) pulse skew, ⎪tPLH – tPHL⎪
5
400
5
80
tSK2R
Channel- to- Channel Skew; Same
tSK3R
Part- to- Part Skew(12)
Low- to- High(9),
Edge(11)
C L = 15 p F
VID = 250mV
Figures 1 & 2
Transition Time
(20% to 80%)
1.0
1.4
2.4
tTHLR
Transition Time High- to- Low(9), (80% to 20%)
1.0
1. 3
2.4
1.0
2.1
3.2
1.0
2.1
3.2
100
160
Propagation Delay Low- to- High (OE to CLKOUT)
tPHLOER
Propagation Delay High- to- Low (OE to CLKOUT)
fMAX
C L = 15 p F
Figures 3 & 4
Maximum Operating Frequency(15)
08-0295
5
ps
TBD
tTLHR
tPLHOER
ns
ns
MHz
PS8536C
11/11/08
PI90LVB16
3V Bus LVDS 1-to-6
Clock Buffer/Bus Transceiver
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
Switching Characteristics
Differential Driver Timing Requuirements
(Over supply voltage and operating temperature ranges, unless otherwise specificed(7,8)
Symbol
Parame te r
Conditions
tPHLDD
Differential Propagation Delay High to Low. CrdCLKIN to CLKI/O
tPLHDD
Differential Propagation Delay Low to High. CrdCLKIN to CLKI/O
tPHLCrd
CrdCLKIN to CLKOUT Propagation Delay High to Low
tPLHCrd
CrdCLKIN to CLKOUT Propagation Delay Low to High
tSK1D
Differential Skew ⎪tPLH – tPHL⎪(13)
tSK2D
Differential Part- to- Part Skew(14)
Differential Transition
Time(9),
(20% to 80%)
tTHLD
Differential Transition
Time(9),
(80% to 20%)
tPHZD
Transition Time Low to 3- State. DE to CLKI/O
tPLZD
Transition Time Low to 3- State. DE to CLKI/O
tPZHD
Transition Time 3- State- to- High. DE to CLKI/O
tPZLD
Transition Time 3- State- to- Low. DE to CLKI/O
fMAX
Maximum Operating Frequency(15)
tTLHD
CL = 15pF
RL = 37.5Ω
Figures 6 & 7
CL = 15pF
Figures 8 & 9
M in.
Typ.(1)
1.0
1.5
2 .2
1.0
1.3
2 .2
2.0
2 .8
4 .5
2.0
2 .8
4 .5
M ax. Units
600
CL = 15pF
Figures 6 & 7
ns
ps
TBD
0. 2
0.35
0.65
0. 2
0.35
0.65
2.6
VIN = 0V to VCC
CL = 15pF
RL = 37.5Ω
Figures 10 & 11
ns
2.6
4.3
3.6
100
160
MHz
Notes:
1. “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. These ratings
are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of
device operation.
2. ESD Rating: ESD qualification is performed per the following: HBM (1.5kΩ, 100pF), Machine Model (250V, 0Ω), IEC 1000-4-2. All VCC
pins connected together, all ground pins connected together.
3. Current into device pins are defined as positive. Current out of device pins defined as negative. All voltages are referenced to ground except
VID, VOD, VTH, and VTL
4. All typicals are given for: VCC = +3.3V and TA = +25°C.
5. The VCMR range is reduced for larger VID. Example: If VID=400 mV, then VCMR is 2V to 2.2VAVID up to ⎪VCC-0V⎪ may be applied
between the CLKI/O+ and CLKI/O– inputs, with the Common Mode set to VCC/2.
6. Only one output should be momentarily shorted at a time. Do not exceed package power dissipation rating.
7. CL includes probe and fixture capacitance.
8. Generator waveform for all tests unless otherwise specified: f = 25 MHz, Zo = 50Ω, tr = 1ns, tf = 1ns (10%–90%). To ensure fastest
propagation delay and minimum skew, clock input edge rates should not be slower than 1ns/V; control signals not slower than 3ns/V.
In general, the faster the input edge rate, the better the AC performance,
9. All device output transition times are based on characterization measurements and are guaranteed by design.
10. tSKIR is the difference in receiver propagation delay ⎪tPLH-tPHL⎪ of one device, and is the duty cycle distortion of the output at any given
temperature and VCC. The propagation delay specification is a device-to-device worst case over process, voltage and temperature.
11. tSK2R is the difference in receiver propagation delay between channels in the same device of any outputs switching in the same direction.
This parameter is guaranteed by design and characterization.
12. tSK3R part-to-part skew, is the difference in receiver propagation delay between devices of any outputs switching in the same direction.
This specification applies to devices over recommended operating temperature and voltage ranges, and across process distribution. tSK3R is
defined as Max-Min differential propagation delay. This parameter is guaranteed by design and characterization.
13. tSK1D is the difference in driver propagation delay ⎪tPLH-tPHL⎪and is the duty cycle distortion of the CLKI/O outputs.
14. tSK2D part-to-part skew, is the difference in driver propagation delay between devices of any outputs switching in the same direction. This
specification applies to devices over recommended operating temperature and voltage ranges, and across process distribution. tSK2D is
defined as Max-Min differential propagation delay.
15. Generator input conditions: trtf < 1ns, 50% duty cycle, differential (1.10V to 1.35V pk-pk). Output Criteria: 60%/40% duty cycle,
VOL(max) 0.4V, VOH(min) 2.7V, Load - 7pF (stray plus probes).
08-0295
6
PS8536C
11/11/08
PI90LVB16
3V Bus LVDS 1-to-6
Clock
Buffer/Bus
Transceiver
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
Parameter Measurement Information
CLKI/0+
Generator
CLKI/0–
D.U.T.
CLKOUT
CL
50:
Figure 1. Receiver Propagation Delay and Transition Time Test Circuit
+1.35V
CLKI/0–
VID = 250mV
+1.10V
CLKI/0+
tPLHDR
tPHLDR
80%
VCC/2
CLKOUT
VOH
80%
VCC/2
20%
20%
tTLHR
VOL
tTHLR
Generator waveform for all test unless otherwise specificed: f = 25MHz, 50% Duty Cycle, Z0 = 50:, tTHL = 1ns
Figure 2. Receiver Propagation Delay and Transition Time Waveforms
08-0295
7
PS8536C
11/11/08
PI90LVB16
3V Bus LVDS 1-to-6
Clock Buffer/Bus Transceiver
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
Parameter Measurement Information
Test
Point
Generator
OE
507
Test
Point
0.95V
–
1.2V
CLKOUT
+
0.95V
CL
Figure 3. Output Enable (OE) Test Circuit
OE
VCC
50%
50%
0V
tPHLOER
CLKOUT
S1– = 0.95V
S1+ = 1.2V
tPLHOER
VOH
50%
50%
VOL
CLKOUT
VOH
S1– = 0.95V
S1+ = 1.2V
Figure 4. Output Enable (OE) Delay Waveforms
08-0295
8
PS8536C
11/11/08
PI90LVB16
3V Bus LVDS 1-to-6
Clock
Buffer/Bus
Transceiver
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
Parameter Measurement Information
RL/2 = 18.757
2V
VOS
D
0.8V
VOD
RL/2 = 18.757
DE
Figure 5. Differential Driver DC Test
CL
D
CrdCLKIN
RL
CL
DE
Figure 6. Driver Propagation Delay Test Circuit
VCC
50%
0V
CrdCLKIN
tPLHCrd
tPHLCrd
CLKI/0–
VOH
0 Differential
CLKI/0+
VOL
tPHLDR
80%
VDIFF= [CLKI/)+] – [CLKI/)–]
80%
0 Differential
20%
20%
tTHLDD
tTLHDD
Figure 7. Driver Propagation Delay and Transition Time Waveforms
08-0295
9
PS8536C
11/11/08
PI90LVB16
3V Bus LVDS 1-to-6
Clock Buffer/Bus Transceiver
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
Parameter Measurement Information
CrdCLKIN
Generator
D.U.T.
CLKOUT
CL
507
Figure 8. CrdCLKIN Propagation Delay Time Test Circuit
VCC
CLKIN
50%
50%
0V
VOH
CLKOUT
50%
50%
VOL
tPLHCrd
tPHLCrd
Figure 9. CrdCLKIN Propagation Delay Time Waveforms
08-0295
10
PS8536C
11/11/08
PI90LVB16
3V Bus LVDS 1-to-6
Clock
Buffer/Bus
Transceiver
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
Parameter Measurement Information
CL
VCC
CrdCLKIN
RL/2
1.2V
D
0V
RL/2
CL
Pulse
Generator
DE
507
Figure 10. Driver 3-State Test Circuit
VCC
DE
50%
0V
tPLZD
CLKI/O+ (CrdCLKIN - L)
CLKI/O– (CrdCLKIN - H)
tPZLD
1.2V
50%
50%
VOL
tPZhD
tPHZD
VOH
CLKI/O+ (CrdCLKIN -H)
CLKI/O– (CrdCLKIN - L)
50%
50%
1.2V
Figure 11. Driver 3-State Waveforms
08-0295
11
PS8536C
11/11/08
PI90LVB16
3V Bus LVDS 1-to-6
Clock Buffer/Bus Transceiver
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
24-Pin TSSOP (L) Package
DOCUMENT CONTROL NO.
PD - 1312
24
REVISION: E
DATE: 03/09/05
.169
.177
4.3
4.5
.004
.008
1
.303
.311
7.7
7.9
0.45
0.75
1
.047
1.20
Max
.007
.012
0.19
0.30
.0256
BSC
0.65
.002
.006
SEATING
PLANE
0.09
0.20
.018
.030
.252
BSC
6.4
0.05
0.15
Pericom Semiconductor Corporation
3545 N. 1st Street, San Jose, CA 95134
1-800-435-2335 • www.pericom.com
Note:
1. Package Outline Exclusive of Mold Flash and Metal Burr
2. Controlling dimentions in millimeters
3. Ref: JEDEC MO-153F/AD
DESCRIPTION: 24-Pin, 173-Mil Wide, TSSOP
PACKAGE CODE: L
Ordering Information
Orde ring Code
Package Code
Package Type
Ope rating Range
PI90LVB16LE
L
Pb- free & Green, 24- pin TSSOP
–40°C to 85°C
Pericom Semiconductor Corporation • 1-800-435-2336 • http://www.pericom.com
08-0295
12
PS8536C
11/11/08