PT7C4908R/S
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2
I C Bus Real-time Clock Module
I2C Bus Real-time Clock Module
Product Features
Product Description
The PT7C4908R/S are I2C™-compatible real-time
clocks (RTCs) with a microprocessor supervisor,
optional trickle charger, backup power source, and NV
RAM controller. The PT7C4908R/S provide a
switchover to battery power, and time and date
indication. The NV RAM is 31 bytes of static RAM that
are available for scratchpad storage. The PT7C4908R/S
are controlled through a 2-wire serial bus.
The real-time clock/calendar provides seconds,
minutes, hours, day, date, month, and year information.
The date is automatically adjusted for months with fewer
than 31 days, including corrections for leap year up to
the year 2100. The clock operates in either the 24-hour
or 12-hour format with an AM/PM indicator. A
time/date-programmable ALARM output completes the
features list for the real-time clock section of the
PT7C4908. The alarm function can also be used in a
polled mode by periodically reading the alarm out status
bit in the minutes register.
A built-in μP supervisor with an open-drain reset
ensures the μP powers up in a known state. A reset
threshold is available for 3V or 3.3V supplies. The piezo
transducer output, PZT, is register selectable for one of
four frequencies, can be turned on and off through a
register bit, or selected to go on when the /ALM, alarm
output, goes active.
The PT7C4908 are available in a 16-pin TSSOP
package and operate over the -40°C to +85°C
temperature range.
RTC Counts Seconds, Minutes, Hours, Date of the
Month, Month, Day of the Week, and Year, with
Leap Year Compensation Valid Up to 2100
31 Bytes of RAM for Scratchpad Data Storage
Uses Standard 32.768kHz, 6pF or 12pF Load,
Watch Crystal
Programmable Time/Date, Open-Drain ALARM
Output (Status Can also Be Polled)
Oscillator Compensation on Chip
-Digitally controlled trim capacitors in oscillator
-Digitally frequency adjustment settings to 190ppm
OUT Pin for SRAM Power
μP Reset Output
Manual Reset Input with Push-Button Switch
Debounce
Independent Power-Fail and Reset Comparators
400kHz 2-Wire Interface
Single-Byte or Multiple-Byte (Burst Mode) Data
Transfer for Read or Write of Clock Registers or
RAM
Bus Timeout to Prevent Lockup of Malfunctioning
Bus Interface
Dual Power-Supply Pins for Primary and Backup
Power
Programmable Trickle Charger
Uses Less than 1μA Timekeeping Current at 3.0V
Operating voltages of 3V and 3.3V
Point-of-Sale Equipment
Lead free and Green Package: 16-pin TSSOP
Programmable Logic Controller
Handheld Instruments
Medical Instrumentation
Table 1 Function Comparison Table
Reset
Operation
Part No
Threshold
Voltage
PT7C4908R
2.63V
3.0V
PT7C4908S
2.93V
3.3V
Application
Trickle
Charger
Yes
Yes
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I C Bus Real-time Clock Module
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Pin Assignment
Pin Description
Pin no.
Pin
Type
1
BATT
I
2
NC
-
3
OUT
O
4
PFI
I
5
/MR
I
6
7
8
9
10
11
12
13
14
15
16
GND
X1
X2
SDA
SCL
/ALM
PZT
/PFO
/RESET
RESET
VCC
I
O
I/O
I
O
O
O
O
O
I
Description
Backup Battery Input. When VCC falls below the reset threshold and VBATT, OUT
connects to BATT. Connect BATT to GND if no backup battery supply is used.
No connected.
Supply Output for CMOS RAM or Other ICs Requiring Use of Backup Battery
Power. Bypass to GND with at least a 0.1μF capacitor.
Power-Fail Comparator Input. For monitoring external power supplies.
Manual Reset Input. The active-low input has an internal pullup resistor. Internal
debouncing circuitry ensures noise immunity. Leave open if unused.
Ground
32.768kHz Crystal Pin; Oscillator Input
32.768kHz Crystal Pin; Oscillator Output
Serial Data Line. Data input/output connection for the 2-wire serial interface.
Serial Clock Line. Clock input connection for the 2-wire serial interface.
Alarm Output. Open drain, active low.
Piezo Transducer Output. Push-pull Piezo transducer output.
Power-Fail Comparator Output. Push-pull active low.
Open-Drain, Active-Low Reset Output
Push-Pull, Active-High Reset Output. Complement of /RESET.
Main Supply Input. Bypass to GND with at least a 0.01μF capacitor.
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Function Block
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Maximum Ratings
Storage Temperature…………………………………………..- 65oC to +150oC
Ambient Temperature with Power Applied……………………-40 oC to +85 oC
BATT or Vcc………………………………………………………- 0.3 to +6.0V
OUT, ALM, SCL, SDA, PFO, RESET. …………………………… - 0.3 to +6.0V
All other Pins…………………………….………………..- 0.3 to (VSUP + 0.3V)
(Where VSUP is greater of VBATT or VCC)
Input Current Vcc………………………………………………………500mA
Input Current BATT……………………………………………………100mA
Input Current GND……………………………………………………….20mA
Output Current OUT……………………………………………………450mA
Output Current(All other optputs)…………………………………………20mA
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended
periods may affect reliability.
Power Dissipation (TA = +70°C)……………………………………… 727mW
(QSOP-20 package)
DC Electrical Characteristics
TA = -40 to +85°C, VCC = VCC(MIN) to VCC(MAX), unless otherwise noted. Typical values are at TA = +25°C.) (Notes 1, 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
PT7C4908R (Note 3)
2.7
3.3
Operating Voltage Range
VCC
PT7C4908S (Note 3)
3.0
3.6
PT7C4908R (Note 4)
2.0
3.6
Operating Voltage Range
VBATT
BATT
PT7C4908S (Note 4)
2.0
3.6
VBATT = 2V,
0.30
0.75
VCC = 0V
Crystal failVBATT = 3V,
BATT Current (Note 5)
IBATT
0.32
0.95
circuit disabled
VCC = 0V
VBATT = 3.6V,
0.34
1.1
VCC = 0V
VBATT = 2V,
0.32
0.75
VCC = 0V
VBATT = 3V,
Crystal fail0.34
0.95
Timekeeping Current (Note 5)
IBATT
VCC = 0V
circuit enabled
VBATT = 3.6V,
0.36
1.1
VCC = 0V
VCC = 3.3V,
20
140
VBATT = 0V
Active Supply Current (Note
PZT disabled,
ICCA
6)
crystal-disabled
VCC = 3.6V,
22
150
VBATT = 0V
VCC = 3.3V,
7
9
VBATT = 0V
PZT disabled,
Standby Current (Note 5)
ICCS
crystal-disabled
VCC = 3.6V,
7
9
VBATT = 0V
VCC = 3.3V,
6
18
VBATT = 0V
Crystal failStandby Current (Note 5)
ICCS
circuit enabled
VCC = 3.6V,
6
25
VBATT = 0V
Trickle-Charge Diode Voltage
1.2
Drop (Two Diodes)
R1
1.7
Trickle Charge Resistors
R2
2.8
R3
5.0
To be continued.
12-07-0001
PT0308-1
4
UNITS
V
V
µA
µA
µA
µA
µA
V
kΩ
07/04/12
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I C Bus Real-time Clock Module
2
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Continued.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
VBATT = 3.0V, VCC = 0V,
IOUT = 80mA
VBATT = 2.0V, VCC = 0V,
IOUT = 40mA
VCC = 3.0V, VBATT = 0V,
IOUT = 100mA
VCC = 2.7V, VBATT = 0V,
IOUT = 50mA
VBATT
-0.15
VBATT
-0.1
VCC 0.15
VCC –
0.1
VBATT
- 0.1
VBATT
- 0.05
VCC 0.1
VCC 0.05
MAX
UNITS
-
V
OUT
OUT in Battery-Backup Mode
(Note 4)
VOUT
OUT in VCC Mode (Note 4)
VOUT
V
-
VBATT to VCC Switch over
Threshold
VTRU
Power-up (VCC < VRST) switch from
VBATT to VCC (Note 7)
-
VBATT
+ 0.05
-
V
VCC to VBATT Switchover
Threshold
VTRD
Power-down (VCC < VRST) switch from
VCC to VBATT (Note 7)
-
VBATT
- 0.05
-
V
VIL
-
-
-
0.3
×VCC
-
0.7
×VCC
MANUAL RESET INPUT
/MR Input Threshold
VIH
/MR Internal Pullup Resistance
/MR Minimum Pulse Width
/MR Glitch Immunity
/MR to Reset Delay
POWER-FAIL INPUT AND POWER-FAIL OUTPUT
PFI Input Threshold
VPFT
PFI Input Current
-
PFI to PFO Delay
-
PFI Hysteresis
VPFH
/PFO Output Voltage High
VOH
/PFO Output Voltage Low
VOL
-
-
V
(Note 8)
(Note 8)
1
-
50
200
50
350
kΩ
µs
ns
ns
VCC = VCC(MIN)
1.19
1.27
1.31
V
-
-100
+2
+100
nA
PFI rising
0.06
0.2
2.2
PFI falling
2.4
5
12
0.9
×VCC
30
-
mV
-
-
V
-
-
0.2
V
Sink current
5
-
18
Source current
5
-
20
Sink current
6
-
20
Source current
6.5
-
25
(Note 8)
PFI rising
ISOURCE = 200µA,
PFI = VCC = VCC(MIN)
ISINK= 1.2mA, VBATT= 2V,
PFI = VCC = 0V
µs
PZT OUTPUT
PZT Output Short-Circuit
Current (VCC Must Be > VRST
for PZT to Be Active)
PT7C4908R
IPZT
PT7C4908S
PZT Frequency 1
PZTf1
-
-
1024
-
Hz
PZT Frequency 2
PZTf2
-
-
2048
-
Hz
PZT Frequency 3
PZTf3
-
-
4096
-
Hz
PZT Frequency 4
PZTf4
-
-
8192
-
Hz
PZT Off-Leakage Current
IOLKG
-
-1
-
+1
µA
To be continued.
12-07-0001
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I C Bus Real-time Clock Module
2
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Continued.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
-
-
0.2
-
-
0.25
-1
-
+1
2.80
2.50
-
2.93
2.63
10
3.00
2.70
-
mV
-
10
50
µs
140
200
280
ms
-
-
0.2
V
-1
-
+1
µA
0.8
×VCC
-
-
ALARM OUTPUT
/ALM Output Low Voltage
/ALM Off-Leakage Current
VOL
IOLKG
VBATT = 2.0V, VCC = 0V,
IOL = 3mA
VCC = 2.7V, IOL = 5mA,
VBATT = 0V
-
V
µA
RESET FUNCTION
Reset Active Timeout Period
tRP
PT7C4909S/10S
PT7C4909R/10R
VCC falling from VRST(MAX) to VRST(MIN)
at 10V/ms, measured from the
beginning of VCC falling to RESET
asserting high
-
/RESET Output Low Voltage
VOL
Reset asserted
/RESET Off-Leakage Current
ILKG
Reset Threshold
VRST
VRST Hysteresis
VHYST
VCC Falling Reset Delay
IOL = 1.6mA, VBATT =
2.0V,
VCC = 0V
-
IOH = 20µA,
VCC = 1.0V,
VBATT = 0V
RESET Output High Voltage
VOH
Reset asserted
IOH = 1mA,
VCC = 2V,
VBATT = 0V
RESET Output Low Voltage
VOL
VCC = VCC(MIN), IOL = 1.6mA
2-WIRE DIGITAL INPUTS (SCL, SDA) (VCC(MIN)< VCC < VCC(MAX))
V
V
0.9
×VCC
-
-
-
0.032
0.1
V
Input High Voltage
VIH
-
0.7
×VCC
-
-
V
Input Low Voltage
VIL
-
-
-
0.3
×VCC
V
Input Hysteresis
VHYS
-
-
0.05
×VCC
-
V
VIN= GND or VCC
(Note 8)
-1
-
-
+1
10
µA
pF
IOL = 4mA, VCC = VCC(MIN)
-
-
0.4
V
Input Leakage Current
Input Capacitance
Output Low Voltage
VOL
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AC Characteristics
(VCC = VCC(MIN) to VCC(MAX), TA = -40°C to +85°C, unless otherwise noted.) (Notes 2)
PARAMETER
SYMBOL
CONDITIONS
2-WIRE BUS TIMING
SCL Clock Frequency
fSCL
(Note 9)
Bus Timeout
tTIMEOUT
-
MIN
TYP
MAX
UNITS
0.32
1
-
400.00
2
kHz
s
Bus Free Time Between
STOP and START Condition
tBUF
-
1.3
-
-
µs
Hold Time After (Repeated)
START Condition; After This
Period, the First Clock Is
Generated
tHD:STA
-
0.6
-
-
µs
Repeated START Condition
Setup Time
STOP Condition Setup Time
Data Hold Time
Data Setup Time
SCL Low to Data Out Valid
SCL Low Period
SCL High Period
tSU:STA
-
0.6
-
-
µs
tSU:STO
tHD:DAT
tSU:DAT
tVD:DAT
tLOW
tHIGH
(Notes 10, 11)
(Note 8)
-
0.6
0
100
50
1.3
0.6
-
0.9
-
µs
µs
ns
ns
µs
µs
SCL/SDA Rise Time
tR
(Note 12)
20 +
0.1*CB
-
300
ns
SCL/SDA Fall Time
(Receiving)
tF
(Notes 12, 13)
20 +
0.1*CB
-
300
ns
tF
(Notes 12, 13)
20 +
0.1*CB
-
250
ns
tSP
(Note 8)
-
-
50
ns
CB
-
-
-
400
pF
SCL/SDA Fall Time
(Transmitting)
Pulse Width of Spike
Suppressed
Capacitive Load of Each Bus
Line
Note 1: VRST is the reset threshold for VCC.
Note 2: All parameters are 100% tested at TA = +85°C. Limits over temperature are guaranteed by design and not production
tested.
Note 3: 2-wire serial interface is operational for VCC > VRST.
Note 4: See the Function Details section (BATT function).
Note 5: IBATT and ICCS are specified with SDA and SCLK pulled high, OUT floating, and /CE_OUT floating.
Note 6: 2-wire serial interface operating at 400kHz, SDA pulled high.
Note 7: For OUT switch over to BATT, VCC must fall below VRST and VBATT. For OUT switchover to VCC, VCC must be above
VRST or above VBATT.
Note 8: Guaranteed by design. Not production tested.
Note 9: Due to the 2-wire bus timeout feature, there is a minimum specification on the SCL clock frequency based on a 31-byte
burst-mode transaction to RAM. See the Timeout Feature section.
Note 10: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V IH min of the SCL
signal) in order to bridge the undefined region of the falling edge of SCL.
Note 11: The maximum tHD:DAT only has to be met if the device does not stretch the LOW period (t LOW) of the SCL signal.
Note 12: CB = total capacitance of one bus line in pF.
Note 13: The maximum tF for the SDA and SCL bus lines is specified at 300ns. The maximum fall time for the SDA output stage
tF is specified at 250ns. This allows series protection resistors to be connected between the SDA/SCL pins and the SDA/SCL bus
lines without exceeding the maximum specified tF.
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Function Description
Overview of Functions
The PT7C4908R/S contain eight 8-bit timekeeping registers, two burst address registers, a trickle charge register, a control register,
a configuration register, an alarm configuration register, and seven alarm threshold
registers, all controlled through a 2-wire serial interface. Refer to PT7C4908 block diagram.
The OUT pin supplies voltage for CMOS RAM or other ICs requiring the use of backup battery power. When VCC rises above the
reset threshold (VRST) or above VBATT, OUT is connected to VCC. When VCC falls below VRST and VBATT, BATT is connected to
OUT. If enabled, an on-board trickle charger charges BATT from VCC.
BATT can act as a backup supply from either a battery or SuperCap™.
There are two reset outputs, /RESET and RESET. They become active while VCC is below the reset threshold(VRST) or while
manual reset (/MR) is held low, and for tRP after /MR goes high, VCC rises above the reset threshold. Reset thresholds are available
for 3V and 3.3V applications. /MR is internally pulled high and contains debounce circuitry to accommodate a manual pushbutton
reset switch.
A power-fail comparator is available to monitor other system voltages through PFI and report the status through /PFO. If the
PT7C4909/PT7C4910 are in reset, /PFO is low; otherwise, it is high as long as PFI is greater than 1.27V (typ).
The piezo transducer drive output (PZT) has register selectable frequencies of 1.024kHz, 2.048kHz, 4.096kHz, or 8.192kHz. This
output can be selected to become active when the alarm is triggered or can be independently controlled through the configuration
register. When activated, the PZT outputs a frequency with an attention-getting 1Hz duty cycle of 50% on and 50% off.
An on-chip crystal oscillator maintaining circuit, for use with a 32.768kHz crystal, provides the clock for timekeeping functions.
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Registers
1.
Register Address Definition
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Figure 1 Register Address Definition
\
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2.
Hex Register Address/Description
Table 2. Hex Register Address/Description
WRITE
READ
DESCRIPTION
(HEX)
(HEX)
80
81
Seconds
82
83
Minutes
84
85
Hours
86
87
Date
88
89
Month
8A
8B
Day
8C
8D
Year
8E
8F
Control
90
91
Trickle charger
92
93
Century
94
95
Alarm configuration
—
97
Test configuration*
9A
9B
Configuration
9C
9D
Seconds alarm threshold
9E
9F
Minutes alarm threshold
A0
A1
Hours alarm threshold
A2
A3
Date alarm threshold
A4
A5
Month alarm threshold
A6
A7
Day alarm threshold
A8
A9
Year alarm threshold
B0
-Test register1(write-only)
B2
-Test register2(write-only)
B8
B9
Digital offset adjust
BC
BD
Oscillator capacitor adjust
BE
BF
Clock burst
C0
C1
RAM 0
C2
C3
RAM 1
C4
C5
RAM 2
C6
C7
RAM 3
C8
C9
RAM 4
CA
CB
RAM 5
CC
CD
RAM 6
CE
CF
RAM 7
D0
D1
RAM 8
D2
D3
RAM 9
D4
D5
RAM 10
D6
D7
RAM 11
D8
D9
RAM 12
DA
DB
RAM 13
DC
DD
RAM 14
To be continued.
12-07-0001
POR CONTENTS (HEX)
00
00
00
01
01
01
70
00
00
19
00
07
00
7F
7F
BF
3F
1F
00
FF
N/A
N/A
00
CC
N/A
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
POR CONTENTS
(BCD)
00
00
00
01
01
01
70
00
00
19
00
07
00
7F
7F
BF
3F
1F
00
FF
N/A
N/A
00
CC
N/A
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
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Continued.
WRITE
(HEX)
DE
E0
E2
E4
E6
E8
EA
EC
EE
F0
F2
F4
F6
F8
FA
FC
FE
READ
(HEX)
DF
E1
E3
E5
E7
E9
EB
ED
EF
F1
F3
F5
F7
F9
FB
FD
FF
DESCRIPTION
POR CONTENTS (HEX)
POR CONTENTS (BCD)
RAM 15
RAM 16
RAM 17
RAM 18
RAM 19
RAM 20
RAM 21
RAM 22
RAM 23
RAM 24
RAM 25
RAM 26
RAM 27
RAM 28
RAM 29
RAM 30
RAM Burst
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
N/A
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
N/A
Crystal Selection
A 32.768kHz crystal is connected to the PT7C4908 through pins 9 and 10 (X1 and X2). The crystal selected for use should have a
specified load capacitance (CL) of 6pF or 12pF where the capacitive load is included in the PT7C4908. When designing the PC
board, keep the crystal as close to the X1 and X2 pins as possible. Keep the trace lengths short and small and place a guard ring
around the crystal and connect the ring to GND to reduce capacitive loading and prevent unwanted noise pickup. Keep all signals
out from beneath the crystal and the X1 and X2 pins to prevent noise coupling. Finally, an additional local ground plane on an
adjacent PC board layer can be added under the crystal to shield it from unwanted pickup from traces on other layers of the board.
This plane should be isolated from the regular PC board ground plane, should be no larger than the perimeter of the guard ring,
and connected to the GND pin of the PT7C4908. Ensure that this ground plane does not contribute to significant capacitance
between signal line and ground on the connections that run from X1 and X2 to the crystal.
Some crystal manufacturers and part numbers for their SMT, 32.768kHz watch crystals that require 6pF or 12pF loads are listed in
Table 3. In addition, these manufacturers offer other package options depending upon the specific application considerations.
Table 3 Crystal Manufacturers and Part Numbers
MANUFACTURER
PART
TEMP RANGE
(°C)
Caliber Electronics
AWS2A-32.768KHz, AWS2B32.768KHz
-20 to +70
CL (pF)
12
6
+25°C FREQUENCY
TOLERANCE (ppm)
±20
ECS INC International
ECS-.327-6.0-17
-10 to +60
12
6
±20
Fox Electronics
FSM327
-40 to +85
12
6
±20
M-tron
SX2010/ SX2020
-20 to +75
12
6
±20
Raltron
RSE-32.768-6-C-T
-10 to +60
12
6
±20
Timekeeping accuracy of the PT7C4908 is dependent on the frequency stability of the external crystal. To determine frequency
stability, use the following equations:
∆f = f * k * (T0 - T)2
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where:
∆f = change in frequency from +25°C (Hz)
f = nominal crystal frequency (Hz)
k = parabolic curvature constant (-0.035 ±0.005ppm/°C2 for 32.768kHz watch crystals)
T0 = turnover temperature (+25°C ±5°C for 32.768kHz watch crystals)
T = temperature of interest (°C)
For example: What is the worst-case change in oscillator frequency from +25°C ambient to +45°C ambient?
∆fdrift = 32.768Hz * (-0.04ppm/°C)2 * (20°C - 45°C)2 = -0.8192Hz
What is the worst-case timekeeping error per second?
1) Error due to temperature drift:
∆tdrift = {[1 / [(f + ∆ fdrift) / 32,768]] - 1s}/1s = {[1 / [(32.768Hz - 0.8192Hz) / 32.768]] - 1s}/1s = 0.000025s/s
2) Error due to +25°C initial crystal tolerance of ±20ppm:
∆finitial = 32.768Hz * (-20ppm) = -0.65536Hz
∆tinitial = {[1 / [(f + ∆ finitial) / 32.768]] - 1}/1s
∆tinitial = {[1 / [(32.768 - 0.65536)/32.768]] - 1} /1s = 0.000020s/s
3) Total timekeeping error per second:
∆ttotal = ∆ tdrift + ∆tinitial
∆ ttotal = 0.000025s / s + 0.000020s / s = 0.000045s/s
After 1 month that translates to:
∆t = (31day) * (24hr/day) * (60min/hr) * (60s/min) * (0.000045s/s) = 120.158s
Total worst-case timekeeping error at the end of 1 month at +45°C is approximately 120s or 2min (assumes negligible parasitic
layout capacitance).
Table 4. Acceptable Quartz Crystal Parameters
PARAMETER
Frequency
Equivalent series resistance
(ESR)
SYMBOL
f
MIN
-
TYP
32.768
MAX
-
UNITS
kHz
RS
-
-
60
kΩ
Parallel load capacitance
CL
Q factor
Q
40,000
6
12
-
-
pF
-
Figure 2 Recommended Layout for Crystal
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Control Register (Write Protect Bit)
Bit 7 of the control register is the write protect bit. The lower 7 bits (bits 0–6) are forced to zero and always read a zero when read.
Before any write operation to the clock or RAM, bit 7 must be zero. When high, the write protect bit prevents a write operation to
any other register.
Hours Register (AM-PM/12-24 Mode)
Bit 7 of the hours register is defined as the 12-hour or 24-hour mode select bit. When high, the 12-hour mode is selected. In the
12-hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20h–23h).
Clock Burst
Addressing the clock burst register specifies burst mode operation. In this mode, the first seven clock/calendar registers and the
control register can be consecutively read or written starting with bit 7 of address BEh for a write and BFh for a read. If the write
protect bit is set high when a write clock/calendar burst mode is specified, no data transfer occurs to any of the seven
clock/calendar registers or the control register. When writing to the clock registers in the burst mode, all eight registers must be
written in order for the data to be transferred. In addition, the WP bit in the control register must be set to zero prior to a clock
burst write.
RAM
The static RAM is 31 bytes addressed consecutively in the RAM address space. Even address/commands (C0h–FCh) are used for
writes, and odd address/commands (C1h–FDh) are used for reads. The contents of the RAM are static and remain valid for VOUT
down to 1.5V (TYP).
RAM Burst
Addressing the RAM burst register specifies burst mode operation. In this mode, the 31 RAM registers can be consecutively read
or written starting with bit 7 of address FEh for a write and FFh for a read. When writing to RAM in burst mode, it is not
necessary to write all 31 bytes for the data to transfer. Each byte that is written to is transferred to RAM regardless of whether all
31 bytes are written.
Trickle Charger Register
The trickle charge register controls the trickle charger characteristics of the PT7C4908. The trickle charger functional schematic
(Figure 3) shows the basic components of the trickle charger. Table 6 details the bit settings for trickle charger control. Trickle
charge selection (TCS) bits D7–D4 control the selection of the trickle charger. In order to prevent accidental enabling, only a
pattern of 1010 enables the trickle charger. All other patterns disable the trickle charger. The PT7C4908 powers up with the trickle
charger disabled. The diode select (DS) bits (D3–D2) select whether two diodes or no diodes are connected between VCC and
BATT. If DS is 10, no diode is selected; if DS is 01, two diodes are selected. If DS is 00 or 11, the trickle charger is disabled
independent of the state of the TCS bits. The RS bits (D1–D0) select the resistor that is connected between VCC and BATT. If
both RS bits are set to zero, the trickle charger is disabled, regardless of any other bit states in the trickle charger register. RS bits
set to 10 select a 1.7K, 01 selects 2.9K, and 11 select 5K.
Diode and resistor selection is determined by the user, according to the maximum current desired for the battery or Super Cap
charging. The maximum charging current can be calculated as shown in the following example. Assume that a system power
supply of 3V is applied to VCC and a SuperCap is connected to BATT. Also assume that the trickle charger has been enabled with
no diode and resistor R1 between VCC and BATT. The maximum current IMAX would therefore be calculated as follows:
IMAX = 3.0V/R1 ≈ 3.0V/1.7kΩ ≈ 1.76mA
As the Super Cap charges, the voltage difference between VCC and VBATT decreases, and therefore the charge current decreases.
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Figure 3 Trickle charger functional schematic
Table 5 Trickle Charger Register Control
D7
D6
D5
D4
D3
D2
TCS
TCS
TCS TCS
DS
DS
0
0
×
×
×
×
1
1
×
×
×
×
×
×
×
×
×
×
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
D1
RS
×
×
0
1
0
1
1
0
1
D0
RS
×
×
0
0
1
1
0
1
1
ACTION
Trickle charger disabled
Trickle charger disabled
Trickle charger disabled
No diode selected, 1.7k selected
No diode selected, 2.9k selected
No diode selected, 5k selected
Two diode selected, 1.7k selected
Two diode selected, 2.9k selected
Two diode selected, 5k selected
OUT Function
OUT is an output supply voltage for external devices. When VCC rises above the reset threshold or is greater than VBATT, OUT
connects to VCC. When VCC falls below VRST and VBATT, OUT connects to BATT. There is a typical VTRU - VTRD hysteresis
associated with the switching between VCC and BATT if BATT < VRST and typically VHYST of hysteresis if BATT > VRST. Connect
at least a 0.1μF capacitor from OUT to ground (GND). Switching from VCC to BATT uses a break-before-make switch; a capacitor
from OUT to GND prevents loss of power needed for clock data and RAM during switchover.
Oscillator Start Time
The PT7C4909/4910 oscillator typically takes 300ms to settle to its optimum operating power level after startup. To ensure the
oscillator is operating, the system software should validate this by reading the seconds register. Any reading with more than 0s,
from the POR value of 0s, is a validation that the oscillator is operating.
Power-On Reset (POR)
The PT7C4908 contain an integral POR circuit that ensures all registers are reset to a known state on power-up. On initial powerup, once VOUT rises above 0.75V (typ), the POR circuit releases the registers for normal operation. Should VOUT dip to less
than 1.5V (typ), the contents of the PT7C4908 registers can no longer be guaranteed.
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Table 6 I/O and IC sections powered from VCC and BATT
PIN
NAME
X1
X2
BATT
POWER=V
Enabled
Enabled
N/A
Enabled
Enabled
N/A
VCC<VRST
COMMENTS
-
OUT
(> of VCC or BATT if VCC< VRESET)
OUT
N/A
N/A
-
Power output pin
Manual Reset Input
Power-Fail Input
Ground
/MR
PFI
GND
Enabled
Enabled
N/A
Disabled
Disabled
N/A
Input ignored
Input ignored
-
Power pin
Active Low, Open-Drain Reset Output
(-OD)
/RESET
Enabled
Enabled
Pulled low
-
RESET
/PFO
/ALM
PZT
SDA
SCL
VCC
-
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
N/A
Enabled
Enabled
Enabled
Enabled
Disabled
Disabled
Disabled
N/A
Disabled
Pulled to VCC
Pulled low
High impedance
-
Power pin
-
-
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Disabled in BATT
-
Supply = OUT
Supply = OUT
Supply = OUT
Supply = OUT
Supply = OUT
Supply = OUT
Supply = VCC
Supply = VCC
Supply = VCC
Supply = OUT
-
Enabled
Disabled
-
Supply = OUT
DESCRIPTION
Crystal Oscillator I/O
Crystal Oscillator I/O
Backup Power-Supply Input
Active High, Push/Pull Reset Output
Power-Fail Output
Alarm Output
Piezo Output
2-Wire Bus Data I/O
2-Wire Bus Clock
Main Power-Supply Input
Trickle Charge
FEATURES
Crystal Oscillator
RAM
Timekeeping Registers
Control Registers
Alarm Registers
Power-Fail Comparator
RESET Comparator
Internal Reference
Power Switchover
Piezo Dividers/Select Register
Trickle Charge
CC
VCC<VRST
COMMENTS
Power pin
Alarm Generation Registers
The alarm function generates an ALARM when the contents of the SEC, MIN, HR, DATE, MONTH, DAY, or YEAR registers
match the respective alarm threshold registers. Also, the generation of the ALARM is programmable through the alarm
configuration register. The alarm configuration register can be written to with an address of 94H or it can be read with an address
of 95H. The alarm configuration register definition is shown in Figure 1 (register address definition). Placing a 1 in the appropriate
bit enables the /ALM and the alarm out status bit when the selected alarm threshold register contents match the respective
timekeeping register contents. For example, writing 0000 0001 to the alarm configuration register causes the alarm pin to get
triggered every minute (each time the contents of the seconds timekeeping register match the contents of the seconds alarm
threshold register). Writing 0000 0010 causes the alarm to go on every hour (each time the contents of the minutes timekeeping
register match the contents of the minutes alarm threshold register). Writing a 0100 1111 to the alarm configuration register,
therefore, causes the alarm to be triggered on a specific second, of a specific minute, of a specific hour, of a specific date, of a
specific year. The alarm output stays low until it is ―cleared‖ by reading or writing to the alarm configuration register or by
reading or writing to any of the alarm threshold registers.
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Minutes Register (Alarm Out Status)
An alarm out status bit is available if it is desired to use the alarm function as a polled alarm instead of connecting directly to the
/ALM output pin. Bit D7 in the minutes timekeeping register contains the status of the /ALM output with a 1 indicating the alarm
function has triggered and zero indicating no triggered alarm.
Manual Reset Input
Many microprocessor-based products require manual reset capability, allowing the operator, a test technician, or external logic
circuitry to initiate a reset. With the PT7C4908, a logic low on /MR asserts reset. Reset remains asserted while /MR is low, and for
tRP (Figure 4) after it returns high. /MR has an internal pull-up resistor of typically 50kΩ, so it can be left open if it is not used.
Internal debounce circuitry requires a minimum low time on the /MR input of 1μs with 100ns (typ) minimum glitch immunity.
Figure 4 Manual Reset Timing
Reset Outputs
A μP’s reset input starts the μP in a known state. When /RESET and RESET are active, all control inputs (/MR, /CE_IN, and the
2-wire interface) are disabled. The PT7C4908 μP supervisory circuit asserts a reset to prevent code-execution errors during powerup, power-down, and brownout conditions. /RESET, opendrain active low, and RESET (push-pull active high) are guaranteed to
be active for 0V < VCC < VRST, provided VOUT is greater than 1V. Once VCC exceeds the reset threshold, an internal timer keeps
/RESET and RESET active for the reset timeout period (tRP); after this interval, /RESET becomes inactive (high) and RESET
becomes inactive (low). If a brownout condition occurs (V CC dips below the reset threshold), RESET and /RESET become active.
Each time RESET and /RESET are asserted, they are held active for the reset timeout period.
The PT7C4908R is optimized to monitor 3.0V ±10% power supplies. Except when /MR is asserted, reset does not occur until VCC
falls below 2.7V (3.0V - 10%), but is guaranteed to occur before the power supply falls below +2.5V.
The PT7C4908S is optimized to monitor 3.3V ±10% power supplies. Except when /MR is asserted, reset does not occur until VCC
falls below 3.0V (3.0V is just above 3.3V - 10%), but is guaranteed to occur before the power supply falls below 2.8V.
Negative-Going VCC Transients
The PT7C4909/4910 are relatively immune to short duration negative transients (glitches) while issuing resets to the μP during
power-up, power-down, and brownout conditions. Therefore, resetting the μP when VCC experiences only small glitches is usually
not recommended.
Maximum transient duration vs. reset comparator overdrive shows the maximum pulse period that can occur on VCC for which
reset pulses are NOT generated. The graph was produced using negative-going VCC pulses, starting at 3.6V and ending below the
reset threshold by the magnitude indicated (reset comparator overdrive). The graph shows the typical maximum pulse width a
negative-going VCC transient can have without causing a reset. As the amplitude of the transient increases (i.e., goes farther below
the reset threshold), the maximum allowable pulse width decreases. Typically, a VCC transient that goes 60mV below the reset
threshold and lasts for 60μs or less does not cause a reset pulse to be issued. A capacitor of at least 0.1μF mounted close to the VCC
pin provides additional transient immunity.
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Interfacing to Microprocessors with Bidirectional Reset Pins
Microprocessors with bidirectional reset pins, such as the Motorola 68HC11 series, can contend with the PT7C4909/4910 /RESET
or RESET outputs. If, for example, the RESET output is driven high and the μP wants to pull it low, indeterminate logic levels
may result. To correct this, connect a 4.7kΩ resistor between the RESET output and the μP reset I/O. Buffer the RESET output to
other system components. The positive voltage supply for the RESET pin is VCC. If VCC drops, then so does the VOH of this pin.
Power-Fail Comparator
The PT7C4908 PFI is compared to an internal reference. If the PFI voltage is less than the power-fail threshold(VPFT), /PFO goes
low. The power-fail comparator is intended for use as an under voltage detector to signal a failing power supply and can monitor
either positive or negative supplies using a voltage-divider to PFI. However, the comparator does not need to be dedicated to this
function because it is completely separate from the rest of the circuitry.
Any time VCC < VRST, /PFO is forced low, regardless of the state of PFI. Any time VCC > VRST and /RESET is active low (during
the reset timeout period), /PFO is forced high, regardless of the state of PFI. If the comparator is unused, connect PFI to VCC and
leave /PFO floating. Figure 5 shows PFI and /PFO timing.
Figure 5 PFI and /PFO Timing
Piezo Transducer Output Drive
The push-pull, piezo transducer drive output, PZT, is selectable through the configuration register for frequencies of 1.024kHz,
2.048kHz, 4.096kHz, or 8.192kHz (Table 6). Bits D0 and D1 control which frequency outputs to PZT. If in battery backup mode
(when VCC falls below the reset threshold and below VBATT), the PZT output is disabled to high impedance to prevent battery drain
from the backup battery on the BATT pin.
Table 7 lists the piezo transducer control bits.
Bit D3, the PZT SEL bit, selects whether the /ALM, alarm output, controls when the selected PZT frequency is gated to PZT or
whether control is given to the PZT CNTL bit, bit D2. If D3 = 1, then the /ALM controls gating of the selected PZT frequency to
PZT. When the alarm is triggered, the selected frequency stays on PZT until the alarm is cleared by writing to or reading from the
alarm configuration register. If D3 = 0, then the PZT CNTL bit, D2, determines when and for how long the selected frequency
appears at PZT. Bit D2, the PZT CNTL bit, controls whether the selected frequency is gated to PZT, provided D3 = 0. D2 = 1
gates the selected frequency to PZT and D2 = 0 inhibits the selected frequency (PZT remains low).
Anytime a frequency is selected to be gated through to the PZT output, it is modulated by a 1Hz square wave. The PZT output
then turns on for 0.5s and off for 0.5s. Since the human ear is particularly sensitive to changes in condition, switching a sound on
and off makes it more noticeable than a continuous sound of the same frequency.
The PZT output swings between VCC and GND through the output stage’s on-resistance, ROUT_PZT. To allow flexibility of the PZT
output to work with many different types of piezo buzzers, ROUT_PZT is designed to be as low as practical. To minimize peak
currents into the piezo buzzer, an external current-limiting resistor Rs may be required. Ipeak is now equal to VCC / (Rs +
ROUT_PZT). Rs can be adjusted to reduce the sound amplitude from the external piezo buzzer. The value of Rs varies for each
application and should be chosen at the prototype design stage with the piezo buzzer installed in a cavity approximating its final
housing. The typical value of ROUT_PZT is calculated from VOUT / IPZT, where IPZT is the average of the sink and source currents.
Figure 6 is the piezo transducer functional diagram.
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Table 7 Piezo Transducer Selectable Frequencies
D1(PZT FREQ)
0
0
1
1
Table 8 1Hz MODULATION ENABLE
EN_1Hz
0(Default)
1
Table 9 Piezo Transducer Control Bits
D3(PZT SEL)
D2(PZT CNTL)
0
0
0
1
1
0
1
1
D0(PZT FREQ)
0
1
0
1
PZT TYPICAL FREQUENCY (kHz)
1.024
2.048
32.768
8.192
Square wave output at PZT
PZT output square wave with 1Hz modulation
PZT output square wave without 1Hz modulation
CONDITION
PZT CNTL bit, D2, has control
PZT CNTL bit, D2, has control
/ALM has control, D2 is ignored; assume alarm triggered
/ALM has control, D2 is ignored; assume alarm cleared by
reading the alarm configuration register
PZT
Low
Selected frequency
Selected frequency
Low
PT7C4908R/S
Test Configuration Register
Figure 6 Piezo Transducer Functional Diagram
This is a read-only register.
Test Register
The block implements an I2C interface controller, which can operate at a maximum frequency of 400KHz. It fully supports the
four types of I2C transfer (single write, single read, burst write and burst read) as defined in the spec. Besides, this block also
incorporates a test block, which implements four test modes that can be entered by first writing 0xFF to TEST REG1(address
0xB0) and then writing a specific value to TEST REG2(address 0xB2) through I2C interface.
Table 10 The four test modes and their entries by i2c write transfers list:
Test mode
Purpose of the test mode
Reset all the RTC relevant registers and all the DFFs in the digital clock
Test reset 1
division chain
Generate a test clock to replace the 16kHz clock input of the digital clock
Test clock 1
division chain
Generate a test clock to replace the 128Hz pulse generated in the middle of
Test clock 2
the digital clock division chain
Test clock 3
Generate a test clock for all the timekeeping registers
Generate a test clock to replace the 1Hz pulse generated by the digital clock
Test clock 4
division chain
12-07-0001
TEST REG 1
TEST REG 2
0XFF
0XB0
0XFF
0XA1
0XFF
0XA2
0XFF
0XA3
0XFF
0XA4
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Offset Adjust
1. Digital adjust
This block incorporates a digital clock division chain and a clock precision adjustment function. The digital clock division chain
receives the 16KHz clock from the oscillator as input, and, through a series of DFFs, generates a 1Hz-periodic pulse to update the
second counter in timekeeping registers. In order to speed up the clock division cycle during test, the input 16KHz clock and the
128Hz pulse in the middle of the clock division chain can be replaced by test_clock1 and test_clock2 generated by the test block in
i2c control block (see the above table).
The precision of the clock generated by the division chain can be set ahead or behind through the clock precision adjustment
function, if a proper adjustment data is set in register DOFFSET (0xB8). The binary encoded settings in the seven bits from F6 to
F0 are used to set the precision of the clock generated from the 32768Hz oscillator up to ±189.1×10-6 in the forward (ahead) or
reverse(behind) direction, in units of ±3.05×10-6. The adjustment happens once every 20 seconds (at ―00‖,‖20‖ and ―40‖ seconds).
The adjustment amount and adjustment value are listed in the table below:
Adjustment data
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Adjustment amount
(ppm)
Decimal
Hexadecimal
F6
F5
F4
F3
F2
F1
F0
-189.10
+63
3F h
0
1
1
1
1
1
1
-186.05
+62
3E h
0
1
1
1
1
1
0
-183.00
+61
3D h
0
1
1
1
1
0
1
1
0
0
0
0
1
1
1
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0
0
0
0
1
1
1
0
0
0
0
0
1
1
1
0
0
0
0
0
1
1
1
0
0
0
0
0
1
1
1
04 h
03 h
02 h
01 h
00 h
7F h
7E h
7D h
+4
+3
+2
+1
0
-1
-2
-3
-9.15
-6.10
-3.05
OFF
OFF
+3.05
+6.10
+9.15
+183.00
-60
44 h
1
0
0
0
1
0
0
+186.05
-61
43 h
1
0
0
0
0
1
1
+189.10
-62
42 h
1
0
0
0
0
1
0
OFF
-63
41 h
1
0
0
0
0
0
1
OFF
-64
40 h
1
0
0
0
0
0
0
The adjustment is carried out in this way: Assume DOFFSET is set to 02h, then every 20 seconds an additional cycle of 16KHz
will be added to all the clock signals in the division chain. If 03h is set, two additional cycles of 16KHz will be added every 20
seconds, etc. Assume DOFFSET is set to 7Fh, then every 20 seconds a cycle of 16KHz will be removed from all the clock signals
in the division chain. If 7Eh is set, then two cycles of 16KHz will be removed every 20 seconds, etc.
2. Analogy adjust
The crystal load capacitance (CL) include in IC can be configured by the OSCILLATOR CAP ADJUST register, the register
address is 1011, 1100. The default value is 1100, 1100. The D7~D4 bit 1100H correspond 12pF C X1 paralleled connected to X1,
and D3~D0 bit 1100H correspond 12pF CX2 paralleled connected to X2, and the total CL is 6pF.
bit 4
bit 3
bit 2
bit 1
bit 0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
1
0
1
0
12
13
14
15
bit 5
12
13
14
15
Bit6
6pF (Default)
6.5pF
7pF
7.5pF
bit 7
Details are listed in the below table:
Adjustment data
Total CL
CX1
CX2
0pF
0
0
0.5pF
1
1
1pF
2
2
1
1
1
1
0
0
1
1
0
1
0
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
1
1
1
1
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Reading / Writing Data via the I2C Bus Interface
1. 2-wire Interface
The PT7C4908 uses a bidirectional 2-wire serial interface. The two lines are SDA and SCL. Both lines must be connected to a
positive supply through individual pull up resistors. Data transfers can only be initiated when the bus is not busy (both SDA and
SCL are high). When VCC is less than VRST, communication with the serial bus is terminated and inactive to prevent erroneous
communication from the microprocessor. Figure 7 is the 2-wire bus timing diagram.
Figure 7 2 Wire Bus Timing Diagram
2. Timeout Feature
The purpose of the bus timeout is to reset the serial bus interface and change the SDA line from an output to an input, which
releases the SDA line from being held low. This is necessary when the PT7C4908 is transmitting data and become stuck at logic
low. If the SDA line is stuck low, any other device on the bus is not able to communicate. The logic above, shown in Figure 8, is
intended to illustrate the timeout feature. If an I 2C transaction takes more than 1s (minimum timout period), a timeout condition
occurs. When a timeout condition is observed, the I2C interface resets to the IDLE state and waits for a new I2C transaction. In
order to complete the 31-byte burst read/write from the RAM before an I2C timeout, the minimum SCL frequency must be
0.32kHz. A valid start condition sets Time_Out_CLR = 1 and the counting begins. A valid stop condition returns Time_Out_CLR
= 0 and disables the up/down counter.
Figure 9 shows the normal 2-wire bus operation.
Figure 10 illustrates what happens when the SDA line is stuck low for two clock cycles of 1Hz_CLK during a valid bus
transaction. Depending on when the actual valid bus transaction begins relative to the 1Hz CLK, the timeout period is either t1 =
2s or t2 = 1s.
Figure 8 Timeout Simplified Functional Diagram
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Figure 9 Normal 2-Wire Bus Operation
Figure 10 Timeout 2-Wire Bus Operation
3. BIT Transfer
One data bit is transferred for each clock pulse. The data on SDA must remain stable during the high portion of the clock pulse
as changes in data during this time are interpreted as control signals (Figure 11).
Figure 11 Bit Transfer
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4. Starting and Stopping Conditions
Both SDA and SCL remain high when the bus is not busy. A high-to-low transition of SDA, while SCL is high, is defined as the
START (S) condition. A low-to-high transition of the data line while SCL is high is defined as the STOP (P) condition (Figure
12).
Figure 12 Start and Stop Conditions
5. Acknowledge
The number of data bytes between the START and STOP conditions for the transmitter and receiver are unlimited. Each 8-bit
byte is followed by an acknowledge bit. The acknowledge bit is a high-level signal put on SDA by the transmitter, during which
time the master generates an extra acknowledge-related clock pulse. A slave receiver that is addressed must generate an
acknowledge after each byte it receives. Also, a master receiver must generate an acknowledge after each byte it receives that
has been clocked out of the slave transmitter.
The device that acknowledges must pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable
low during the high period of the acknowledge clock pulse (setup and hold times must also be met). A master receiver must
signal an end of the data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the
slave. In this case, the transmitter must leave SDA high to enable the master to generate a STOP condition.
6. Slave Address Byte
Before any data is transmitted on the bus, the device that should respond is addressed first. The first byte sent after the start (S)
procedure is the address byte. The PT7C4908 acts as a slave transmitter/receiver. Therefore, SCL is only an input clock signal
and SDA is a bidirectional data line. The slave address for the PT7C4908 is shown in Figure 13.
Figure 13 2-Wire Slave Address Byte
7. Address/Command Byte
The command byte is shown in Figure 14. The MSB (bit 7) must be a logic 1. If it is zero, writes to the PT7C4909/ 4910 are
disabled. Bit 6 specifies clock/calendar data if logic 0 or RAM data if logic 1. Bits 1 through 5 specify the designated registers to
be input or output, and the LSB (bit 0) specifies a write operation (input) if logic 0 or a read operation (output) if logic 1. The
command byte is always input starting with the MSB (bit 7).
Figure 14 Address/Command Byte
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8. Reading from the Timekeeping Registers
The timekeeping registers (seconds, minutes, hours, date, month, day, and year) can be read either with a single read or a burst
read. The century register can only be read with a single read. Since the real-time clock runs continuously and a read takes a
finite amount of time, there is the possibility that the clock counters could change during a read operation, thereby reporting
inaccurate timekeeping data. In the PT7C4908, each clock register’s data is buffered by a latch. Clock register data is latched by
the 2-wire bus read command (on the falling edge of SCL when the slave acknowledge bit is sent after the address/command
byte has been sent by the master to read a timekeeping register). Collision-detection circuitry ensures that this does not happen
coincident with a seconds counter update to ensure accurate time data is being read. This avoids time data changes during a read
operation. The clock counters continue to count and keep accurate time during the read operation.
If single reads are to be used to read each of the timekeeping registers individually, then it is necessary to do some error
checking on the receiving end. The potential for error is the case when the seconds counter increments before all the other
registers are read out. For example, suppose a carry of 13:59:59 to 14:00:00 occurs during single read operations of the
timekeeping registers. Then, the net data could become 14:59:59, which is erroneous real-time data. To prevent this with singleread operations, read the seconds register first (initial seconds) and store this value for future comparison. When the remaining
timekeeping registers have been read out, read the seconds register again (final seconds). If the initial seconds value is 59, check
that the final seconds value is still 59; if not, repeat the entire single-read process for the timekeeping registers. A comparison of
the initial seconds value with the final seconds value can indicate if there was a bus delay problem in reading the timekeeping
data (difference should always be 1s or less). Using a 100kHz bus speed, sequential single reads would take under 2.5ms to read
all seven of the timekeeping registers, plus a second read of the seconds register.
The most accurate way to read the timekeeping registers is to do a burst read. In the burst read, the main timekeeping registers
(seconds, minutes, hours, date, month, day, year) and the control register are read sequentially, in the order listed with the
seconds register first. They must be all read out as a group of eight registers, with 8 bits each, for proper execution of the burst
read function. All seven timekeeping registers are latched upon the receipt of the burst read command. Worst-case errors that
can occur between the actual time and the read time is 1s, assuming the entire burst
read is done in less than 1s.
9. Reading from the Timekeeping Registers
The time and date can be set by writing to the timekeeping registers (seconds, minutes, hours, date, month, day, year, and
century). To avoid changing the current time by an incomplete write operation, the current time value is buffered from being
written directly to the timekeeping registers. The timekeeping registers continue to count, and on the next rising edge of the 1Hz
seconds clock, the new data is loaded into the timekeeping registers. The new value will be incremented on the next rising of the
1Hz seconds clock. Collision-detection circuitry ensures that this does not happen coincident with a seconds register update to
ensure accurate time data is being written. This avoids time data changes during a write operation. An incomplete write
operation aborts the time update procedure and the contents of the input buffer are discarded.
If single write operations are to be used to write to each of the timekeeping registers, then error checking is needed. If the
seconds register is to be updated, update it first and then read it back and store its value as the initial seconds. Update the
remaining timekeeping registers and then read the seconds register again (final seconds). If initial seconds were 59, ensure they
are still 59. If initial seconds were not 59, ensure that final seconds are within 1s of initial seconds. If the seconds register is not
to be written to, then read the seconds register first and save it as initial seconds. Write to the required timekeeping registers and
then read the seconds register again (final seconds). If initial seconds were 59, ensure they are still 59. If initial seconds were not
59, ensure that final seconds are within 1s of initial seconds.
Although both single writes and burst writes are possible, the most accurate way to write to the timekeeping registers is to do a
burst write. In the burst write, the main timekeeping registers (seconds, minutes, hours, date, month, day, year) and the control
register are written to sequentially. They must be all written to as a group of eight registers, with 8 bytes each, for proper
execution of the burst write function. All seven timekeeping registers are simultaneously loaded into the input buffer at the end
of the 2-wire bus write operation. The worst-case error that can occur between the actual time and the write time update is 1s.
Figure 15 shows PT7C4908 data transfer.
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Figure 15 PT7C4909/PT7C4910 Data Transfer
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Application Circuit
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Mechanical Information
LE(Lead free and Green TSSOP-16)
PKG. DIMENSIONS(MM)
SYMBOL
MIN
MAX
A
1.10
A1
0.02
0.15
A2
0.80
1.00
b
0.19
0.30
c
0.09
0.20
D
4.90
5.10
E
4.30
4.50
E1
6.25
6.55
e
0.65 BSC
L
0.50
0.70
θ
1°
7°
Note:
1) Ref : JEDEC MO-153F/AD
Ordering Information
Part Number
PT7C4908RLE
PT7C4908SLE
Package Code
L
L
Package
Lead free and Green 16-Pin TSSOP
Lead free and Green 16-Pin TSSOP
Note:
E = Pb-free and Green
Adding X Suffix= Tape/Reel
Pericom Semiconductor Corporation 1-800-435-2336 www.pericom.com
Pericom reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply
the best possible product. Pericom does not assume any responsibility for use of any circuitry described other than the circuitry embodied in Pericom product.
The company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom.
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