PI74AVC16835

PI74AVC16835
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
18-Bit Universal Bus Driver
with 3-State Outputs
Product Features
Product Description
• Very high-speed, low-noise universal bus driver with
embedded resistor outputs
• Meets PC133 SDRAM Registered DIMM specification
• Implements output impedance control for low-noise and
heavy-load applications
• Fast Propagation Delay:
2.5ns max. for 50pF test load
• VCC = 3.3V or 2.5V or 1.8V
• Packaging (Pb-free and Green available):
– 56-pin, 240 mil wide plastic TSSOP (A)
Data flow from A to Y is controlled by Output Enable (OE). The device
operates in the transparent mode when LE is HIGH. The A data is
latched if CLK is held at a high or low logic level. If LE is LOW, the
A-bus is stored in the latch/flip-flop on the low-to-high transition of
CLK. When OE is HIGH, the outputs are in the high-impedance state.
The PI74AVC16835 bus driver is designed to drive an array of 133
MHz synchronous memory chips, with minimal undershoot/
overshoot noise, and to meet the input signal rise/fall time requirement
of memory chips.
The output drivers of this part have an embedded series-resistor. For
DIMM module design, no external series termination resistors near
the buffer drivers or any other termination resistors are required. This
feature simplifies DIMM module layout design, and results in cost
savings.
Product Pin Configuration
1
2
56
55
GND
3
4
5
54
53
52
A1
6
7
8
51
50
49
A3
9
10
48
47
A5
11
12
Y8
13
46
45
44
GND
Y7
Y9
14
15
16
43
42
41
A9
17
18
40
A12
39
GND
19
20
21
38
37
36
A13
22
23
24
35
34
VDD
33
A17
32
31
GND
Y18
25
26
OE
27
30
CLK
LE
28
29
LE
NC
NC
Y1
GND
Y2
Y3
VDD
Y4
Y5
Y6
GND
Y10
Y11
Y12
GND
Y13
Y14
Y15
VDD
Y16
Y17
GND
09-0003
NC
GND
A2
VDD
A4
A6
A7
A8
A10
A11
A14
A15
A16
A18
1
PS8373G
10/27/09
PI74AVC16835
18-Bit Universal Bus Driver
with 3-State Outputs
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
Truth Table(1)
Logic Block Diagram
Inputs
OE
CLK
LE
A1
27
30
28
54
1D
C1
3
Y1
OE
LE
CLK
A
Outputs Y
H
X
X
X
Z
L
H
X
L
L
L
H
X
H
H
L
L
↑
L
L
L
L
↑
H
H
L
L
H
X
Yo(2)
L
L
L
X
Yo(3)
Notes:
1 H = High Signal Level
L = Low Signal Level
Z = High Impedance
↑ = Transition LOW-to-HIGH
X = Irrelevant
2. Output level before the indicated steady-state input
conditions were established, provided that CLK is HIGH
before LE goes LOW.
3. Output level before the indicated steady-state input
conditions were established.
CLK
TO 17 OTHER CHANNELS
Product Pin Description
Pin Name
OE
LE
CLK
A
Y
GND
VCC
09-0003
Description
Output Enable Input (Active LOW)
Latch Enable
Clock Input
Data Input
Data Output
Ground
Power
2
PS8373G
10/27/09
PI74AVC16835
18-Bit Universal Bus Driver
with 3-State Outputs
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ............................................................................................................. –65°C to +150°C
Ambient Temperature with Power Applied .............................................................................. –40°C to +85°C
Supply Voltage Range, VCC .................................................................................................................................................................................... –0.5V to +4.6V
Input Voltage Range, VI(1) ....................................................................................................................................................................................... –0.5V to +4.6V
Voltage range applied to any output in the high-impedance or power-off state, VO(1) ..............–0.5V to +4.6V
Voltage range applied to any output in the high or low state, VO(1,2) .................................. –0.5V to VCC +0.5V
Input clamp current, IIK (VI <0) ............................................................................................................... –50mA
Output clamp current, IOK (VO <0) ...........................................................................................................–50mA
Continuous output current, IO ................................................................................................................ ±50mA
Continuous current through each VCC or GND ..................................................................................... ±100mA
Package thermal impedance, θJA(3): A (TSSOP) package ..................................................................... 81°C/W
Notes:
Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
1. Input and output negative voltage ratings may be exceeded if the input and output current ratings are observed.
2. Output positive voltage rating may be exceeded up to 4.6V maximum if the output current rating is observed.
3. Package thermal impedance is calculated in accordance with JESD 51.
09-0003
3
PS8373G
10/27/09
PI74AVC16835
18-Bit Universal Bus Driver
with 3-State Outputs
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
Recommended Operating Conditions(1)
Parame te rs
VCC
De s cription
Te s t Conditions
M in.
M a x.
Operating
1. 6 5
3. 6
Data Retention Only
1. 2
VCC = 1.2V
VCC
Supply Voltage
VCC = 1.65V to 1.95V
VIH
0.65 x VCC
High- level Input Voltage
VCC = 2.3V to 2.7V
VCC = 3V to 3.6V
1. 7
2
VCC = 1.2V
GND
VCC = 1.65V to 1.95V
VIL
V
0.35 x VCC
Low- level Input Voltage
VIN
Input Voltage
VOUT
Output Voltage
IOHS
Units
High- level Output Current (2)
VCC = 2.3V to 2.7V
0. 7
VCC = 3V to 3.6V
0. 8
0
3.6
Active State
0
VCC
3- State
0
3.6
VCC = 1.65V to 1.95V
-4
VCC = 2.3V to 2.7V
-8
VCC = 3V to 3.6V
- 12
mA
IOLS
Δt/Δv
TA
Low- level Output Current (2)
Input transition rise or fall rate
VCC = 1.65V to 1.95V
4
VCC = 2.3V to 2.7V
8
VCC = 3V to 3.6V
12
VCC = 1.65V to 3.6V
5
ns/V
85
°C
Operating Free- Air Temperature
- 40
Notes:
1. Unused control inputs must be held HIGH or LOW to prevent them from floating.
2. Dynamic drive is greater than standard output drive of IOH = –24mA and IOL = 24mA
09-0003
4
PS8373G
10/27/09
PI74AVC16835
18-Bit Universal Bus Driver
with 3-State Outputs
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
DC Electrical Characteristics (Over the Operating Range, TA = –40°C to +85°C, VCC = 3.3V ± 10%)
Parame te rs
VOH
VOL
II
Control Inputs
Te s t Conditions
VCC(1)
M in.
Typ.(2)
1.65 to 3.6
VCC - 0.2
M ax. Units
IOHS = –100μA
VIH or VIL
IOHS = –4mA
VIH = 1.07V
1.65
1.2
IOHS = –8mA
VIH = 1.7V
2.3
1.75
IOHS = –12mA
VIH = 2V
3.0
2.3
IOLS = 100μA
VIH or VIL
1.65 to 3.6
0.2
IOLS = 4mA
VIL = 0.57V
1.65
0.4 5
IOLS = 8mA
VIL = 0.7V
2. 3
0.5 5
IOLS = 12mA
VIL = 0.8V
3. 0
0.7
3. 6
2.5
0
±10
3.6
±10
3 .6
40
V
VI = VCC or GND
IOFF
VI = 0 or 3.6V
IOZ(3)
VO = VCC or GND
ICC
VI = VCC or GND
OE = VCC
IO = 0
2.5
4.5
3.3
4.5
2.5
4.0
3.3
4.0
2.5
6. 5
3.3
6. 5
μA
Control Inputs
VI = VCC or GND
CI
Data Input
CO
Outputs
pF
VO = VCC or GND
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are measured at +25°C.
3. For I/O ports, the IOZ includes the input leakage current.
Timing Requirements over Operating Range
Parame te rs
De s cription
VCC = 1.8 V
± 0.15V
M in.
M a x.
VCC = 2.5V
± 0.2V
M in.
M in.
fCLOCK
Clock Frequency
tW Pulse
Duration
LE High
2.0
1.2
1.0
CLK High or Low
2.0
1.2
1.0
Data before CLK↑
1.4
1.2
1.0
Data before LE↓, CLK High or Low
1.4
1.2
1.0
Data after CLK↑
1.0
0.8
0.6
Data after LE↓, CLK High or Low
1. 0
0.8
0.6
tSU Setup time
tH Hold time
09-0003
150
M a x.
VCC = 3.3V
± 0.3V
5
150
Units
M a x.
150
MHz
ns
PS8373G
10/27/09
PI74AVC16835
18-Bit Universal Bus Driver
with 3-State Outputs
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
Switching Characteristics Over Recommended Operating Free-Air Temperature Range
Unless otherwise noted, see Figures 3 through 5.
Parame te r
From
(Input)
To
(Output)
VCC = 1.8V
± 0.15V
M in.
fmax
tpd
VCC = 2.5V
± 0.2V
M a x.
M in.
150
M a x.
150
VCC = 3.3V(1)
± 0.3V
M in.
M a x.
150
MHz
A
1.0
4. 5
0. 8
3 .0
0 .7
2 .4
LE
1.0
5.0
0.8
3 .3
0 .7
2 .5
1.0
4. 5
0. 8
3 .0
0 .7
2 .5
CLK
Y
Units
ten
OE
1.5
5.5
1.0
4 .5
1.0
4 .0
tDIS
OE
1.5
5.0
1.0
4 .5
1.0
4 .0
ns
Notes:
1. Load at 50pF and 500Ω.
Operating Characteristics, TA = 25°C
Parame te rs
Outputs Enabled
Cpd Power dissipation capacitance
Outputs Disabled
09-0003
Te s t
Conditions
VCC = 1.8V
VCC = 2.5V
VCC = 3.3V
Typ.
Typ.
Typ.
C L = 0,
f = 10 MHz
45
48
52
23
25
28
6
Units
pF
PS8373G
10/27/09
PI74AVC16835
18-Bit Universal Bus Driver
with 3-State Outputs
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
Parameter Measurement Information (VCC = 1.8V ±0.15V)
2 x VCC
R1
1K7
From Output
Under Test
TEST
Open
GND
tpd
tPLZ/tPZL
tPHZ/tPZH
1k7
CL=30pF
S1
Ope n
2 x VCC
GND
Load Circuit
Timing
Input
VCC/2
tsu
Data
Input
VCC/2
tW
VCC
0V
Input
VCC/2
VCC
0V
(Low-level
enabling)
tPLH
tPLH
VCC/2
tPZL
Output
Waveform 1
S1 at 2 x VSS
VDD/2
Vcc/2
VCC
Output
Control
0V
Output
0V
Voltage Waveforms
Pulse Duration
VDD
VDD/2
VCC
VCC/2
th
Voltage Waveforms
Setup and Hold Times
Input
VCC/2
tPLZ
VCC/2
tPZH
Output
Waveform 2
S1 at GND
VDD
Vcc/2
VDD
Voltage Waveforms
Propagation Delay Times
VCC/2
0V
VCC
VOL +0.15V
VOL
tPHZ
VCC/2
VOH
VOH –0.15V
0V
Voltage Waveforms
Enable and Disable Times
Notes:
• CL includes probe and jig capacitance.
• Waveform 1 is for an output with internal conditions such that the output is LOW except when disabled by the output control.
• Waveform 2 is for an output with internal conditions such that the output is HIGH except when disabled by the output control.
• All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tr ≤2ns, tr ≤2ns.
• The outputs are measured one at a time with one transition per measurement.
• tPLZ and tPHZ are the same as tdis.
• tPZL and tPZH are the same as ten.
• tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
09-0003
7
PS8373G
10/27/09
PI74AVC16835
18-Bit Universal Bus Driver
with 3-State Outputs
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
Parameter Measurement Information (VCC = 2.5V ±0.2V)
5007
From Output
Under Test
S1
2 x VCC
Open
GND
TEST
tpd
tPLZ/tPZL
tPHZ/tPZH
5007
CL=30pF
S1
Ope n
2 x VCC
GND
Load Circuit
tW
Timing
Input
VCC
VCC/2
tsu
Data
Input
VCC/2
Input
0V
th
0V
(Low-level
enabling)
Output
Waveform 1
S1 at 2 x VSS
VCC
Vcc/2
Vcc/2
0V
tPLH
tPLH
Output
Vcc/2
0V
VCC
Output
Control
Voltage Waveforms
Setup and Hold Times
Input
VCC
VCC/2
Voltage Waveforms
Pulse Duration
VCC
VCC/2
VCC/2
VCC/2
tPZL
tPLZ
VCC/2
tPZH
VOH
Output
Waveform 2
S1 at GND
Vcc/2
VOL
Voltage Waveforms
Propagation Delay Times
VCC/2
0V
VCC
VOL +0.15V
VOL
tPHZ
VCC/2
VOH
VOH –0.15V
0V
Voltage Waveforms
Enable and Disable Times
Notes:
• CL includes probe and jig capacitance.
• Waveform 1 is for an output with internal conditions such that the output is LOW except when disabled by the output control.
• Waveform 2 is for an output with internal conditions such that the output is HIGH except when disabled by the output control.
• All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tr ≤2ns, tr ≤2ns.
• The outputs are measured one at a time with one transition per measurement.
• tPLZ and tPHZ are the same as tdis.
• tPZL and tPZH are the same as ten.
• tPLH and tPHL are the same as tpd.
Figure 4. Load Circuit and Voltage Waveforms
09-0003
8
PS8373G
10/27/09
PI74AVC16835
18-Bit Universal Bus Driver
with 3-State Outputs
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
Parameter Measurement Information (VCC = 3.3V ±0.3V)
5007
From Output
Under Test
2 x VCC
Open
GND
S1
TEST
tpd
tPLZ/tPZL
tPHZ/tPZH
5007
CL=50pF
S1
Ope n
2 x VCC
GND
Load Circuit
tW
Timing
Input
VCC
VCC/2
tsu
Data
Input
VCC/2
Input
0V
th
0V
(Low-level
enabling)
Output
Waveform 1
S1 at 2 x VSS
VCC
Vcc/2
Vcc/2
0V
tPLH
tPLH
Output
Vcc/2
0V
VCC
Output
Control
Voltage Waveforms
Setup and Hold Times
Input
VCC
VCC/2
Voltage Waveforms
Pulse Duration
VCC
VCC/2
VCC/2
VCC/2
tPZL
tPLZ
VCC/2
tPZH
VOH
Output
Waveform 2
S1 at GND
Vcc/2
VOL
Voltage Waveforms
Propagation Delay Times
VCC/2
0V
VCC
VOL +0.3V
VOL
tPHZ
VCC/2
VOH
VOH –0.3V
0V
Voltage Waveforms
Enable and Disable Times
Notes:
• CL includes probe and jig capacitance.
• Waveform 1 is for an output with internal conditions such that the output is LOW except when disabled by the output control.
• Waveform 2 is for an output with internal conditions such that the output is HIGH except when disabled by the output control.
• All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tr ≤2ns, tr ≤2ns.
• The outputs are measured one at a time with one transition per measurement.
• tPLZ and tPHZ are the same as tdis.
• tPZL and tPZH are the same as ten.
• tPLH and tPHL are the same as tpd.
Figure 5. Load Circuit and Voltage Waveforms
09-0003
9
PS8373G
10/27/09
PI74AVC16835
18-Bit Universal Bus Driver
with 3-State Outputs
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
'$7(
1RWHV
&RQWUROOLQJGLPHQVLRQVLQPLOOLPHWHUV
5HI-('(&02)((
3DFNDJH2XWOLQH([FOXVLYHRI0ROG)ODVKDQG0HWDO%XUU
'(6&5,37,21SLQPLOZLGH76623
3$&.$*(&2'($
'2&80(17&21752/3'
5(9,6,210
06-0736
Notes:
• For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php
Ordering Information
Ordering Code
PI74AVC16835AE
Package Code
A
Package Type
Pb-free & Green, 56-pin TSSOP
Notes:
• Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
• E = Pb-free & Green
• Adding an X suffix = Tape/Reel
Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com
09-0003
10
PS8373G
10/27/09