PT8211 16-Bit Digital to Analog Converter DESCRIPTION PT8211 is a dual channel, 16 bit Digital-to-Analog Converter IC utilizing CMOS technology specially designed for the digital audio applications. The internal conversion architecture is based on a R-2R resister ladder network, internal circuit is well matched and a 16 bit dynamic range is achieved even in whole supply voltage range. PT8211 also enhanced the performance of timing responsibility in digital serial bus, in a company with the fast switching R-2R network that make 8X oversampling audio signal is also supported. PT8211 can be supported wide range of sample frequency; it is compatible with TDA1311 by functionally. Its digital input timing format is Least Significant Bit Justified (LSBJ), or so called Japanese input format. Digital code format is two’s complement and MSB first. PT8211 is available in 8-pin SOP or DIP. FEATURES • • • • • • • • CMOS technology Support 3.3V bus input level Low power consumption Two audio channel output in the same chip 16-bit dynamic range Low total harmonic distortion No phase shift between both output channel Available in 8 pins, SOP or DIP APPLICATIONS • • • • Digital audio equipment CD ROM/VCD Multimedia sound card MPEG decoder card BLOCK DIAGRAM Tel: 886-66296288‧Fax: 886-29174598‧ http://www.princeton.com.tw‧2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan PT8211 APPLICATION CIRCUIT AND NOTE To further suppress residual noise, we suggest placing an additional low pass filter after the analog output of PT8211. Please refer to the circuit diagram below. This is a simple second-order analog post filter. If low noise output is very important for your circuit design we suggest using a regulated power supply. V1.6 2 February 2012 PT8211 ORDER INFORMATION Valid Part Number PT8211-S PT8211 Package Type 8 Pins, SOP, 150mil 8 Pins, DIP, 300mil Top Code PT8211-S PT8211 PIN CONFIGURATION PIN DESCRIPTION Pin Name BCK WS DIN GND VDD LCH NC RCH V1.6 I/O I I I Power O O Description Serial Bit Clock Input Word Select Clock Input Pin Data Input Pin Ground Positive Power Supply Left Channel Output No Connection Right Channel Output 3 Pin No. 1 2 3 4 5 6 7 8 February 2012 PT8211 FUNCTION DESCRIPTION The serial bus input data format of PT8211 is Japanese or called LSBJ (Least Significant Bit Justified) format. Each valid DIN data will be shifted to the input register in the rising edge of the BCK, only the first 16bit data ( from MSB) is valid if the input data length is more than 16bits, other data bit will be truncated. The clock frequency of the BCK could run up to 20MHz and supported to 8× over-sampling in 48KHz WS clock rate. Both left and right data words are time multiplexed. Please refer to the diagrams for timing and input signal formats. Figure 1. Japanese Input Signal Format Figure 2. Timing and Input Signal Formats The DIN data must be the 2’s complementary format and the MSB (Most Significant Bit) must be the first. When the Word Select (WS) clock in the Low level, the DIN data will be shifted to the right input register. likewise, the DIN data will be shifted to the left input register when WS clock in the High level. The buffered DIN data then feeding to the DAC after both input register are all settled down, this can eliminated the phase shift happened between two channel output. DAC output is generated by a 16 bit R-2R resistor ladder network. This signal is driven to the Right/Left Channel (RCH/LCH) via the buffer operational amplifier. V1.6 4 February 2012 PT8211 ABSOLUTE MAXIMUM RATINGS Parameter Power supply voltage Input voltage Operating temperature Storage temperature Symbol VDD VI Topr Tstg Rating -0.3 ~ 7.0 -0.3 ~ VDD+0.3 -40 ~ +85 -65 ~ +150 Unit V V ℃ ℃ DC CHARACTERISTICS (Test Conditions: Ta=25℃, VDD=5.0V, unless otherwise specified) Parameter Symbol Condition Power supply voltage VDD THD<1% Operating current Is VDD=5V Digital input high level (see Note) VIH Digital input low level (see Note) VIL Min 3 10 1.8 GND Typ 5 13 2.2 1.2 Max. 6 18 Vcc 1.8 Unit V mA V V Note: Digital input level will change due to supply voltage. TIMING CHARACTERISTICS (Please refer to the Figure 1) Parameter Bit clock frequency Word clock frequency Input data rate H Level time Rise time Fall time Symbol Fbck Fws Fdin tH tR tF Condition BCK WS DIN Min 25 Typ - Max 18.4 384 18.4 Unit MHz KHz Mbits/s ns ns ns 20 20 ANALOG AUDIO CHARACTERISTICS (Unless otherwise specified, Test Condition: Ta=25℃, VDD=5V) Parameter Symbol Condition Maximum output level VO 1KHz, 0dB FS Total harmonic distortion THD 1KHz, -10dB FS 1KHz,-60dB FS Monotonicity Mt Dynamic range DR Data=0000H Signal to noise ratio S/N No clock input CTa Both Output Channel Cross talk CTd Digital in to Analog out Phase shift Pd Both Output Channel V1.6 5 Min. 2.2 0.08 - Typ 2.5 0.13 0.1 3 85 89 80 75 - 89 93 95 89 80 0 Max. 2.7 0.3 0.2 6 16 97 92 0.2 Unit VPP % % Bit dB dB dB μs February 2012 PT8211 PACKAGE INFORMATION 8 PINS, SOP, 150MIL Symbol A A1 A2 b c e D E E1 L θ Dimensions(MM) Nom. 1.27 BSC - Min. 1.35 0.10 1.25 0.31 0.17 4.80 5.80 3.80 0.40 0° Max. 1.75 0.25 1.65 0.51 0.25 5.00 6.20 4.00 1.27 8° Note: Refer to JEDEC MS-012 AA V1.6 6 February 2012 PT8211 8 PINS, DIP, 300MIL Symbol A A1 A2 b b2 D E E1 e eB L Dimension(Inch) Nom. 0.130 0.018 0.060 0.365 0.310 0.250 0.100 BSC 0.130 Min. 0.015 0.115 0.014 0.045 0.355 0.300 0.240 0.300 0.115 Max. 0.21 0.195 0.022 0.070 0.400 0.325 0.280 0.430 0.150 Notes: 1. Refer to JEDEC MS-001, Variation BA 2. All dimensions are in Inch V1.6 7 February 2012 PT8211 IMPORTANT NOTICE Princeton Technology Corporation (PTC) reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and to discontinue any product without notice at any time. PTC cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a PTC product. No circuit patent licenses are implied. Princeton Technology Corp. 2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan Tel: 886-2-66296288 Fax: 886-2-29174598 http://www.princeton.com.tw V1.6 8 February 2012