Datasheet μPD46184095B μPD46184185B 18M-BIT DDR II SRAM SEPARATE I/O 2-WORD BURST OPERATION R10DS0115EJ0200 Rev.2.00 Nov 09, 2012 Description The μPD46184095B is a 2,097,152-word by 9-bit and the μPD46184185B is a 1,048,576-word by 18-bit synchronous double data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. The μPD46184095B and μPD46184185B integrate unique synchronous peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (K and K#) are latched on the positive edge of K and K#. These products are suitable for application which require synchronous operation, high speed, low voltage, high density and wide bit configuration. These products are packaged in 165-pin PLASTIC BGA. Features • 1.8 ± 0.1 V power supply • 165-pin PLASTIC BGA (13 x 15) • HSTL interface • PLL circuitry for wide output data valid window and future frequency scaling • Separate independent read and write data ports • DDR read or write operation initiated each cycle • Pipelined double data rate operation • Separate data input/output bus • Two-tick burst for low DDR transaction size • Two input clocks (K and K#) for precise DDR timing at clock rising edges only • Two output clocks (C and C#) for precise flight time and clock skew matching-clock and data delivered together to receiving device • Internally self-timed write control • Clock-stop capability. Normal operation is restored in 20 μs after clock is resumed. • User programmable impedance output (35 to 70 Ω) • Fast clock cycle time : 3.3 ns (300 MHz), 4.0 ns (250 MHz) • Simple control logic for easy depth expansion • JTAG 1149.1 compatible test access port R10DS0115EJ0200 Rev.2.00 Nov 09, 2012 Page 1 of 34 μPD46184095B, μPD46184185B Ordering Information Part No. μPD46184095BF1-E33-EQ1-A μPD46184095BF1-E40-EQ1-A μPD46184185BF1-E33-EQ1-A μPD46184185BF1-E40-EQ1-A μPD46184095BF1-E33Y-EQ1-A μPD46184095BF1-E40Y-EQ1-A μPD46184185BF1-E33Y-EQ1-A μPD46184185BF1-E40Y-EQ1-A μPD46184095BF1-E33-EQ1 μPD46184095BF1-E40-EQ1 μPD46184185BF1-E33-EQ1 μPD46184185BF1-E40-EQ1 μPD46184095BF1-E33Y-EQ1 μPD46184095BF1-E40Y-EQ1 μPD46184185BF1-E33Y-EQ1 μPD46184185BF1-E40Y-EQ1 R10DS0115EJ0200 Rev.2.00 Nov 09, 2012 Organization (word x bit) 2M x 9 1M x 18 2M x 9 1M x 18 2M x 9 1M x 18 2M x 9 1M x 18 Clock frequency Core Supply Voltage Operating Ambient Temperature 3.3ns 300MHz 1.8 ± 0.1 TA = 0 to 70°C 4.0ns 250MHz Cycle time Package 165-pin PLASTIC 3.3ns 300MHz BGA 4.0ns 250MHz (13 x 15) 3.3ns 300MHz 4.0ns 250MHz 3.3ns 300MHz 1.8 ± 0.1 TA = −40 to 85°C Lead-free 1.8 ± 0.1 TA = 0 to 70°C 165-pin 4.0ns 250MHz 3.3ns 300MHz 4.0ns 250MHz PLASTIC 3.3ns 300MHz BGA 4.0ns 250MHz 3.3ns 300MHz 4.0ns 250MHz 3.3ns 300MHz 4.0ns 250MHz (13 x 15) 1.8 ± 0.1 TA = −40 to 85°C Lead Page 2 of 34 μPD46184095B, μPD46184185B Pin Arrangement 165-pin PLASTIC BGA (13 x 15) (Top View) [μPD46184095B] 2M x 9 1 2 3 4 5 6 7 8 9 10 11 A CQ# VSS/72M A R, W# NC K# NC/144M LD# A VSS/36M CQ B NC NC NC A NC/288M K BW0# A NC NC Q4 C NC NC NC VSS A A A VSS NC NC D4 D NC D5 NC VSS VSS VSS VSS VSS NC NC NC E NC NC Q5 VDDQ VSS VSS VSS VDDQ NC D3 Q3 F NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC G NC D6 Q6 VDDQ VDD VSS VDD VDDQ NC NC NC H DLL# VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC NC VDDQ VDD VSS VDD VDDQ NC Q2 D2 K NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC L NC Q7 D7 VDDQ VSS VSS VSS VDDQ NC NC Q1 M NC NC NC VSS VSS VSS VSS VSS NC NC D1 N NC D8 NC VSS A A A VSS NC NC NC P NC NC Q8 A A C A A NC D0 Q0 R TDO TCK A A A C# A A A TMS TDI A D0 to D8 Q0 to Q8 LD# R, W# BW0# K, K# C, C# CQ, CQ# ZQ DLL# Remarks 1. 2. 3. : Address inputs : Data inputs : Data outputs : Synchronous load : Read Write input : Byte Write data select : Input clock : Output clock : Echo clock : Output impedance matching : PLL disable TMS TDI TCK TDO VREF VDD VDDQ VSS NC NC/xxM : IEEE 1149.1 Test input : IEEE 1149.1 Test input : IEEE 1149.1 Clock input : IEEE 1149.1 Test output : HSTL input reference input : Power Supply : Power Supply : Ground : No connection : Expansion address for xxMb ×××# indicates active LOW. Refer to Package Dimensions for the index mark. 2A, 7A, 10A and 5B are expansion addresses : 10A for 36Mb : 10A and 2A for 72Mb : 10A, 2A and 7A for 144Mb : 10A, 2A, 7A and 5B for 288Mb 2A and 10A of this product can also be used as NC. R10DS0115EJ0200 Rev.2.00 Nov 09, 2012 Page 3 of 34 μPD46184095B, μPD46184185B Pin Arrangement 165-pin PLASTIC BGA (13 x 15) (Top View) [μPD46184185B] 1M x 18 1 2 3 4 5 6 7 8 9 10 11 R, W# BW1# K# NC/288M LD# A VSS/72M CQ A CQ# B NC Q9 D9 A NC K BW0# A NC NC Q8 C NC NC D10 VSS A A A VSS NC Q7 D8 D NC D11 Q10 VSS VSS VSS VSS VSS NC NC D7 E NC NC Q11 VDDQ VSS VSS VSS VDDQ NC D6 Q6 F NC Q12 D12 VDDQ VDD VSS VDD VDDQ NC NC Q5 G NC D13 Q13 VDDQ VDD VSS VDD VDDQ NC NC D5 H DLL# VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC D14 VDDQ VDD VSS VDD VDDQ NC Q4 D4 K NC NC Q14 VDDQ VDD VSS VDD VDDQ NC D3 Q3 L NC Q15 D15 VDDQ VSS VSS VSS VDDQ NC NC Q2 M NC NC D16 VSS VSS VSS VSS VSS NC Q1 D2 N NC D17 Q16 VSS A A A VSS NC NC D1 P NC NC Q17 A A C A A NC D0 Q0 R TDO TCK A A A C# A A A TMS TDI VSS/144M NC/36M A D0 to D17 Q0 to Q17 LD# R, W# BW0#, BW1# K, K# C, C# CQ, CQ# ZQ DLL# Remarks 1. : Address inputs : Data inputs : Data outputs : Synchronous load : Read Write input : Byte Write data select : Input clock : Output clock : Echo clock : Output impedance matching : PLL disable TMS TDI TCK TDO VREF VDD VDDQ VSS NC NC/xxM : IEEE 1149.1 Test input : IEEE 1149.1 Test input : IEEE 1149.1 Clock input : IEEE 1149.1 Test output : HSTL input reference input : Power Supply : Power Supply : Ground : No connection : Expansion address for xxMb ×××# indicates active LOW. 2. Refer to Package Dimensions for the index mark. 3. 2A, 3A, 7A and 10A are expansion addresses : 3A for 36Mb : 3A and 10A for 72Mb : 3A,10A and 2A for 144Mb : 3A, 10A, 2A and 7A for 288Mb 2A and 10A of this product can also be used as NC. R10DS0115EJ0200 Rev.2.00 Nov 09, 2012 Page 4 of 34 μPD46184095B, μPD46184185B Pin Description (1/2) Symbol Type A Input D0 to Dxx Input Q0 to Qxx Output LD# Input R, W# Input BWx# Input K, K# Input C, C# Input Description Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the rising edge of K. All transactions operate on a burst of two words (one clock period of bus activity). These inputs are ignored when device is deselected, i.e., NOP (LD# = HIGH). Synchronous Data Inputs: Input data must meet setup and hold times around the rising edges of K and K# during WRITE operations. See Pin Arrangement for ball site location of individual signals. X9 device uses D0 to D8. X18 device uses D0 to D17. Synchronous Data Outputs: Output data is synchronized to the respective C and C# or to K and K# rising edges if C and C# are tied HIGH. Data is output in synchronization with C and C# (or K and K#), depending on the LD# and R, W# command. See Pin Arrangement for ball site location of individual signals. X9 device uses Q0 to Q8. x18 device uses Q0 to Q17. Synchronous Load: This input is brought LOW when a bus cycle sequence is to be defined. This definition includes address and read/write direction. All transactions operate on a burst of 2 data (one clock period of bus activity). Synchronous Read/Write Input: When LD# is LOW, this input designates the access type (READ when R, W# is HIGH, WRITE when R, W# is LOW) for the loaded address. R, W# must meet the setup and hold times around the rising edge of K. Synchronous Byte Writes: When LOW these inputs cause their respective byte to be registered and written during WRITE cycles. These signals must meet setup and hold times around the rising edges of K and K# for each of the two rising edges comprising the WRITE cycle. See Pin Arrangement for signal to data relationships. X9 device uses BW0#. x18 device uses BW0#, BW1#. See Byte Write Operation for relation between BWx# and Dxx. Input Clock: This input clock pair registers address and control inputs on the rising edge of K, and registers data on the rising edge of K and the rising edge of K#. K# is ideally 180 degrees out of phase with K. All synchronous inputs must meet setup and hold times around the clock rising edges. Output Clock: This clock pair provides a user controlled means of tuning device output data. The rising edge of C# is used as the output timing reference for first output data. The rising edge of C is used as the output reference for second output data. Ideally, #C is 180 degrees out of phase with C. When use of K and K# as the reference instead of C and C#, then fixed C and C# to HIGH. Operation cannot be guaranteed unless C and C# are fixed to HIGH (i.e. toggle of C and C#) R10DS0115EJ0200 Rev.2.00 Nov 09, 2012 Page 5 of 34 μPD46184095B, μPD46184185B (2/2) Symbol CQ, CQ# Type Output ZQ Input DLL# Input TMS TDI TCK Input TDO Output VREF − VDD Supply VDDQ Supply VSS NC − Input Supply Description Synchronous Echo Clock Outputs. The rising edges of these outputs are tightly matched to the synchronous data outputs and can be used as a data valid indication. These signals run freely and do not stop when Q tristates. If C and C# are stopped (if K and K# are stopped in the single clock mode), CQ and CQ# will also stop. Output Impedance Matching Input: This input is used to tune the device outputs to the system data bus impedance. Q, CQ and CQ# output impedance are set to 0.2 x RQ, where RQ is a resistor from this bump to ground. The output impedance can be minimized by directly connect ZQ to VDDQ. This pin cannot be connected directly to GND or left unconnected. The output impedance is adjusted every 20 μs upon power-up to account for drifts in supply voltage and temperature. After replacement for a resistor, the new output impedance is reset by implementing power-on sequence. PLL Disable: When debugging the system or board, the operation can be performed at a clock frequency slower than TKHKH (MAX.) without the PLL circuit being used, if DLL# = LOW. The AC/DC characteristics cannot be guaranteed. For normal operation, DLL# must be HIGH and it can be connected to VDDQ through a 10 kΩ or less resistor. IEEE 1149.1 Test Inputs: 1.8 V I/O level. These balls may be left Not Connected if the JTAG function is not used in the circuit. IEEE 1149.1 Clock Input: 1.8 V I/O level. This pin must be tied to VSS if the JTAG function is not used in the circuit. IEEE 1149.1 Test Output: 1.8 V I/O level. When providing any external voltage to TDO signal, it is recommended to pull up to VDD. HSTL Input Reference Voltage: Nominally VDDQ/2. Provides a reference voltage for the input buffers. Power Supply: 1.8 V nominal. See Recommended DC Operating Conditions and DC Characteristics for range. Power Supply: Isolated Output Buffer Supply. Nominally 1.5 V. 1.8 V is also permissible. See Recommended DC Operating Conditions and DC Characteristics for range. Power Supply: Ground No Connect: These signals are not connected internally. R10DS0115EJ0200 Rev.2.00 Nov 09, 2012 Page 6 of 34 μPD46184095B, μPD46184185B Block Diagram [μPD46184095B] 20 ADDRESS LD# ADDRESS R, W# 20 REGISTRY & LOGIC K K# R, W# BW0# 18 OUTPUT BUFFER LD# ARRAY 18 MUX OUTPUT SELECT & LOGIC MEMORY OUTPUT REGISTER REGISTRY 20 2 x 18 SENSE AMPS 18 WRITE DRIVER DATA WRITE REGISTER D0 to D8 9 9 Q0 to Q8 2 CQ, CQ# K K K# K C, C# OR K, K# [μPD46184185B] 19 ADDRESS LD# ADDRESS R, W# 19 REGISTRY & LOGIC K K# R, W# BW0# ARRAY 36 MUX LD# 36 OUTPUT BUFFER & LOGIC MEMORY OUTPUT SELECT REGISTRY 19 2 x 36 OUTPUT REGISTER 36 SENSE AMPS D0 to D17 DATA WRITE DRIVER 18 WRITE REGISTER BW1# 18 Q0 to Q17 2 CQ, CQ# K K# R10DS0115EJ0200 Rev.2.00 Nov 09, 2012 K K C, C# OR K, K# Page 7 of 34 μPD46184095B, μPD46184185B Power-On Sequence in DDR II SRAM DDR II SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. The following timing charts show the recommended power-on sequence. The following power-up supply voltage application is recommended: VSS, VDD, VDDQ, VREF, then VIN. VDD and VDDQ can be applied simultaneously, as long as VDDQ does not exceed VDD by more than 0.5 V during power-up. The following power-down supply voltage removal sequence is recommended: VIN, VREF, VDDQ, VDD, VSS. VDD and VDDQ can be removed simultaneously, as long as VDDQ does not exceed VDD by more than 0.5 V during power-down. Power-On Sequence Apply power and tie DLL# to HIGH. Apply VDDQ before VREF or at the same time as VREF. Provide stable clock for more than 20 μs to lock the PLL. Continuous min.4 NOP(LD# = high) cycles are required after PLL lock up is done. PLL Constraints The PLL uses K clock as its synchronizing input and the input should have low phase jitter which is specified as TKC var. The PLL can cover 120 MHz as the lowest frequency. If the input clock is unstable and the PLL is enabled, then the PLL may lock onto an undesired clock frequency. Power-On Waveforms VDD/VDDQ VDD/VDDQ Stable (< ±0.1 V DC per 50 ns) DLL# Fix HIGH (or tied to VDDQ) Clock Unstable Clock 20 μs or more Stable Clock 4 Times NOP Normal Operation Start LD# R10DS0115EJ0200 Rev.2.00 Nov 09, 2012 Page 8 of 34 μPD46184095B, μPD46184185B Truth Table Operation WRITE cycle LD# R, W# L L CLK D or Q L→H Data in Load address, input write data on Input data D(A+0) D(A+1) consecutive K and K# rising edge Input clock K(t+1) ↑ K#(t+1) ↑ READ cycle L H L→H Data out Load address, read data on Output data Q(A+0) Q(A+1) consecutive C and C# rising edge Output clock C#(t+1) ↑ C(t+2) ↑ NOP (No operation) H × L→H D = ×, Q = High-Z Clock stop × × Stopped Previous state Remarks 1. H : HIGH, L : LOW, × : don’t care, ↑ : rising edge. 2. Data inputs are registered at K and K# rising edges. Data outputs are delivered at C and C# rising edges except if C and C# are HIGH then Data outputs are delivered at K and K# rising edges. 3. All control inputs in the truth table must meet setup/hold times around the rising edge (LOW to HIGH) of K. All control inputs are registered during the rising edge of K. 4. This device contains circuitry that ensure the outputs to be in high impedance during power-up. 5. Refer to state diagram and timing diagrams for clarification. 6. It is recommended that K = K# = C = C# when clock is stopped. This is not essential but permits most rapid restart by overcoming transmission line charging symmetrically. R10DS0115EJ0200 Rev.2.00 Nov 09, 2012 Page 9 of 34 μPD46184095B, μPD46184185B Byte Write Operation [μPD46184095B] Operation K K# BW0# Write D0 to D8 L→H − 0 − L→H 0 Write nothing L→H − 1 − L→H 1 Remarks 1. H : HIGH, L : LOW, → : rising edge. 2. Assumes a WRITE cycle was initiated. BW0# can be altered for any portion of the BURST WRITE operation provided that the setup and hold requirements are satisfied. [μPD46184185B] Operation K# BW0# BW1# L→H − 0 0 − L→H 0 0 Write D0 to D8 L→H − 0 1 − L→H 0 1 Write D9 to D17 L→H − 1 0 − L→H 1 0 Write nothing L→H − 1 1 − L→H 1 1 Write D0 to D17 K Remarks 1. H : HIGH, L : LOW, → : rising edge. 2. Assumes a WRITE cycle was initiated. BW0# and BW1# can be altered for any portion of the BURST WRITE operation provided that the setup and hold requirements are satisfied. R10DS0115EJ0200 Rev.2.00 Nov 09, 2012 Page 10 of 34 μPD46184095B, μPD46184185B Bus Cycle State Diagram LOAD NEW ADDRESS Count = 0 Load, Count = 2 Load, Count = 2 Write Read READ DOUBLE Count = Count + 2 WRITE DOUBLE Count = Count + 2 NOP, Count = 2 NOP, Count = 2 Load NOP NOP Power UP Supply voltage provided Remark State machine control timing sequence is controlled by K. R10DS0115EJ0200 Rev.2.00 Nov 09, 2012 Page 11 of 34 μPD46184095B, μPD46184185B Electrical Characteristics Absolute Maximum Ratings Parameter Rating Unit VDD −0.5 to +2.5 V VDDQ −0.5 to VDD V Input voltage VIN −0.5 to VDD+0.5 (2.5 V MAX.) V Input / Output voltage VI/O −0.5 to VDDQ+0.5 (2.5 V MAX.) V Operating ambient temperature TA 0 to 70 °C −40 to 85 °C −55 to +125 °C Supply voltage Output supply voltage Symbol Conditions (E** series) (E**Y series) Storage temperature Tstg Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended DC Operating Conditions (TA = 0 to 70°C, TA = −40 to 85°C) Parameter MIN. TYP. MAX. Unit VDD 1.7 1.8 1.9 V Output supply voltage VDDQ 1.4 VDD V 1 Input HIGH voltage VIH (DC) VREF +0.1 VDDQ+0.3 V 1, 2 Input LOW voltage VIL (DC) −0.3 VREF −0.1 V 1, 2 Clock input voltage VIN −0.3 VDDQ+0.3 V 1, 2 Reference voltage VREF 0.68 0.95 V Supply voltage Symbol Conditions Note Notes 1. During normal operation, VDDQ must not exceed VDD. 2. Power-up: VIH ≤ VDDQ + 0.3 V and VDD ≤ 1.7 V and VDDQ ≤ 1.4 V for t ≤ 200 ms Recommended AC Operating Conditions (TA = 0 to 70°C, TA = −40 to 85°C) Parameter Symbol Input HIGH voltage VIH (AC) Input LOW voltage VIL (AC) Conditions MIN. MAX. VREF +0.2 VREF −0.2 Unit Note V 1 V 1 Note 1. Overshoot: VIH (AC) ≤ VDD + 0.7 V (2.5 V MAX.) for t ≤ TKHKH/2 Undershoot: VIL (AC) ≥ −0.5 V for t ≤ TKHKH/2 Control input signals may not have pulse widths less than TKHKL (MIN.) or operate at cycle rates less than TKHKH (MIN.). R10DS0115EJ0200 Rev.2.00 Nov 09, 2012 Page 12 of 34 μPD46184095B, μPD46184185B DC Characteristics 1 (TA = 0 to 70°C, VDD = 1.8 ± 0.1 V) Parameter Symbol Test condition MIN. MAX. x9 Unit x18 Input leakage current ILI −2 +2 μA I/O leakage current ILO −2 +2 μA Operating supply current IDD (Read cycle / Write cycle) Standby supply current VIN ≤ VIL or VIN ≥ VIH, Note -E33 500 530 Cycle = MAX. -E40 450 480 VIN ≤ VIL or VIN ≥ VIH, -E33 390 400 -E40 380 380 mA II/O = 0 mA, ISB1 (NOP) mA II/O = 0 mA, Cycle = MAX. Inputs static Output HIGH voltage VOH(Low) VOH Output LOW voltage VOL(Low) VOL Notes 1. 2. 3. 4. |IOH| ≤ 0.1 mA Note1 IOL ≤ 0.1 mA Note2 VDDQ−0.2 VDDQ V 3, 4 VDDQ/2−0.12 VDDQ/2+0.12 V 3, 4 VSS 0.2 V 3, 4 VDDQ/2−0.12 VDDQ/2+0.12 V 3, 4 Outputs are impedance-controlled. | IOH | = (VDDQ/2)/(RQ/5) ±15% for values of 175 Ω ≤ RQ ≤ 350 Ω. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) ±15% for values of 175 Ω ≤ RQ ≤ 350 Ω. AC load current is higher than the shown DC values. HSTL outputs meet JEDEC HSTL Class I standards. R10DS0115EJ0200 Rev.2.00 Nov 09, 2012 Page 13 of 34 μPD46184095B, μPD46184185B DC Characteristics 2 (TA = −40 to 85°C, VDD = 1.8 ± 0.1 V) Parameter Symbol Test condition MIN. MAX. x9 Unit x18 Input leakage current ILI −2 +2 μA I/O leakage current ILO −2 +2 μA Operating supply current IDD (Read cycle / Write cycle) Standby supply current VIN ≤ VIL or VIN ≥ VIH, Note -E33Y 650 680 Cycle = MAX. -E40Y 600 630 VIN ≤ VIL or VIN ≥ VIH, -E33Y 510 530 -E40Y 490 500 mA II/O = 0 mA, ISB1 (NOP) mA II/O = 0 mA, Cycle = MAX. Inputs static Output HIGH voltage VOH(Low) VOH Output LOW voltage VOL(Low) VOL Notes 1. 2. 3. 4. |IOH| ≤ 0.1 mA Note1 IOL ≤ 0.1 mA Note2 VDDQ−0.2 VDDQ V 3, 4 VDDQ/2−0.12 VDDQ/2+0.12 V 3, 4 VSS 0.2 V 3, 4 VDDQ/2−0.12 VDDQ/2+0.12 V 3, 4 Outputs are impedance-controlled. | IOH | = (VDDQ/2)/(RQ/5) ±15% for values of 175 Ω ≤ RQ ≤ 350 Ω. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) ±15% for values of 175 Ω ≤ RQ ≤ 350 Ω. AC load current is higher than the shown DC values. HSTL outputs meet JEDEC HSTL Class I standards. R10DS0115EJ0200 Rev.2.00 Nov 09, 2012 Page 14 of 34 μPD46184095B, μPD46184185B Capacitance (TA = 25°C, f = 1 MHz) Parameter Input capacitance Symbol Test conditions MIN. MAX. Unit CIN VIN = 0 V 5 pF CI/O VI/O = 0 V 7 pF Cclk Vclk = 0 V 6 pF (Address, Control) Input / Output capacitance (D, Q, CQ, CQ#) Clock Input capacitance Remark These parameters are periodically sampled and not 100% tested. Thermal Characteristics Parameter Thermal resistance Symbol θ ja Substrate 4-layer from junction to ambient air 8-layer Thermal characterization parameter Ψ jt 4-layer from junction to the top center of the package surface Thermal resistance 8-layer θ jc Airflow TYP. Unit 0 m/s 16.5 °C/W 1 m/s 13.2 °C/W 0 m/s 15.5 °C/W 1 m/s 12.6 °C/W 0 m/s 0.07 °C/W 1 m/s 0.13 °C/W 0 m/s 0.06 °C/W 1 m/s 0.12 °C/W 3.86 °C/W from junction to case R10DS0115EJ0200 Rev.2.00 Nov 09, 2012 Page 15 of 34 μPD46184095B, μPD46184185B AC Characteristics (TA = 0 to 70°C, TA = −40 to 85°C, VDD = 1.8 ± 0.1 V) AC Test Conditions (VDD = 1.8 ± 0.1 V, VDDQ = 1.4 V to VDD) Input waveform (Rise / Fall time ≤ 0.3 ns) 1.25 V 0.75 V Test Points 0.75 V 0.25 V Output waveform Test Points VDDQ / 2 VDDQ / 2 Output load condition Figure 1. External load at test VDDQ / 2 0.75 V 50 Ω VREF ZO = 50 Ω SRAM 250 Ω ZQ R10DS0115EJ0200 Rev.2.00 Nov 09, 2012 Page 16 of 34 μPD46184095B, μPD46184185B Read and Write Cycle Parameter Symbol -E33,-E33Y (300 MHz) -E40,-E40Y (250 MHz) Unit Note MIN. MAX. MIN. MAX. 3.3 8.4 4.0 8.4 ns 1 0.2 2 Clock Average Clock cycle time (K, K#, C, C#) Clock phase jitter (K, K#, C, C#) Clock HIGH time (K, K#, C, C#) Clock LOW time (K, K#, C, C#) Clock HIGH to Clock# HIGH (K → K#, C → C#) Clock# HIGH to Clock HIGH (K# → K, C# → C) Clock to data clock (K → C, K# → C#) PLL lock time (K, C) K static to PLL reset TKHKH TKC var TKHKL TKLKH TKHK#H 0.2 1.32 1.32 1.49 1.6 1.6 1.8 ns ns ns ns TK#HKH 1.49 1.8 ns TKHCH 0 TKC lock TKC reset 20 30 20 30 μs ns 3 4 TCQHCQ#H 1.24 1.55 ns 5 TCQ#HCQH 1.24 1.55 ns 5 1.45 0 1.8 ns Output Times CQ HIGH to CQ# HIGH (CQ → CQ#) CQ# HIGH to CQ HIGH (CQ# → CQ) C, C# HIGH to output valid C, C# HIGH to output hold C, C# HIGH to echo clock valid C, C# HIGH to echo clock hold CQ, CQ# HIGH to output valid CQ, CQ# HIGH to output hold C HIGH to output High-Z C HIGH to output Low-Z TCHQV TCHQX TCHCQV TCHCQX TCQHQV TCQHQX TCHQZ TCHQX1 0.45 −0.45 −0.45 ns ns ns ns ns ns ns ns TAVKH TIVKH 0.4 0.4 0.5 0.5 ns ns 7 7 TDVKH 0.3 0.35 ns 7 TKHAX TKHIX 0.4 0.4 0.5 0.5 ns ns 7 7 TKHDX 0.3 0.35 ns 7 −0.45 0.45 −0.45 0.45 −0.45 0.45 −0.45 0.27 −0.27 0.3 −0.3 0.45 0.45 6 6 Setup Times Address valid to K rising edge Synchronous load input (LD#), read write input (R, W#) valid to K rising edge Data inputs and write data select inputs (BWx#) valid to K, K# rising edge Hold Times K rising edge to address hold K rising edge to synchronous load input (LD#), read write input (R, W#) hold K, K# rising edge to data inputs and write data select inputs (BWx#) hold R10DS0115EJ0200 Rev.2.00 Nov 09, 2012 Page 17 of 34 μPD46184095B, μPD46184185B Notes 1. When debugging the system or board, these products can operate at a clock frequency slower than TKHKH (MAX.) without the PLL circuit being used, if DLL# = LOW. Read latency (RL) is changed to 1.0 clock cycle in this operation. The AC/DC characteristics cannot be guaranteed, however. 2. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. TKC var (MAX.) indicates a peak-to-peak value. 3. VDD slew rate must be less than 0.1 V DC per 50 ns for PLL lock retention. PLL lock time begins once VDD and input clock are stable. It is recommended that the device is kept NOP (LD# = HIGH) during these cycles. 4. K input is monitored for this operation. See below for the timing. K or TKC reset K TKC reset 5. Guaranteed by design. 6. Echo clock is very tightly controlled to data valid / data hold. By design, there is a ± 0.1 ns variation from echo clock to data. The data sheet parameters reflect tester guardbands and test setup variations. 7. This is a synchronous device. All addresses, data and control lines must meet the specified setup and hold times for all latching clock edges. Remarks 1. This parameter is sampled. 2. Test conditions as specified with the output loading as shown in AC Test Conditions unless otherwise noted. 3. Control input signals may not be operated with pulse widths less than TKHKL (MIN.). 4. If C, C# are tied HIGH, K, K# become the references for C, C# timing parameters. 5. VDDQ is 1.5 V DC. R10DS0115EJ0200 Rev.2.00 Nov 09, 2012 Page 18 of 34 μPD46184095B, μPD46184185B Read and Write Timing NOP READ (burst of 2) 1 2 READ (burst of 2) 3 WRITE (burst of 2) WRITE (burst of 2) 4 5 READ (burst of 2) 6 NOP 7 8 K TKHKL TKLKH TKHKH TKHK#H TK#HKH K# LD# TKHIX TIVKH R, W# A0 Address A1 A2 TDVKH TAVKH TKHAX Data in Data out Q00 Qx2 A4 A3 Q01 TKHDX D20 D21 Q10 Q11 TCHQX1 TDVKH TKHDX D30 D31 Q40 TCHQZ TCHQX TCQHQV Q41 TCQHQX TCHQX TCHQV TCHQV CQ TCHCQX TCHCQV TCQHCQ#H TCQ#HCQH CQ# TKHCH TCHCQX TCHCQV C TKHKL TKLKH TKHKH TKHK#H TK#HKH TKHCH C# Remarks 1. Q01 refers to output from address A0+0. Q02 refers to output from the next internal burst address following A0, i.e., A0+1. 2. Outputs are disabled (high impedance) 2.5 clock cycles after the last READ (LD# = LOW, R, W# = HIGH) is input in the sequences of [READ]-[NOP] and [READ]-[WRITE]. 3. In this example, if address A4 = A3, data Q41 = D31 and Q42 = D32. Write data is forwarded immediately as read results. R10DS0115EJ0200 Rev.2.00 Nov 09, 2012 Page 19 of 34 μPD46184095B, μPD46184185B Application Example D ZQ CQ# CQ Q A LD# R, W# BWx# C/C# K/K# SRAM#1 SRAM Controller Vt R= 250 Ω D ZQ CQ# CQ Q A LD# R, W# BWx# C/C# K/K# ... SRAM#4 R= 250 Ω R Data In Data Out R Address Vt R LD# Vt R, W# BW# ... SRAM#1 CQ/CQ# SRAM#4 CQ/CQ# Vt R Vt R Source CLK/CLK# Return CLK/CLK# Vt R R = 50 Ω Vt = Vref Remark AC Characteristics are defined at the condition of SRAM outputs, CQ, CQ# and Q with termination. R10DS0115EJ0200 Rev.2.00 Nov 09, 2012 Page 20 of 34 μPD46184095B, μPD46184185B JTAG Specification These products support a limited set of JTAG functions as in IEEE standard 1149.1. Test Access Port (TAP) Pins Pin name Pin assignments Description TCK 2R TMS 10R TDI 11R Test Data Input. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP controller state machine and the instruction that is currently loaded in the TAP instruction. TDO 1R Test Data Output. This is the output side of the serial registers placed between TDI and TDO. Output changes in response to the falling edge of TCK. Test Clock Input. All input are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. Test Mode Select. This is the command input for the TAP controller state machine. Remark The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held HIGH for five rising edges of TCK. The TAP controller state is also reset on the SRAM POWER-UP. JTAG DC Characteristics (TA = 0 to 70°C, VDD = 1.8 ± 0.1 V, unless otherwise noted) Parameter Symbol Conditions MIN. MAX. Unit JTAG Input leakage current ILI 0 V ≤ VIN ≤ VDD −5.0 +5.0 μA JTAG I/O leakage current ILO 0 V ≤ VIN ≤ VDDQ, −5.0 +5.0 μA Outputs disabled JTAG input HIGH voltage VIH 1.3 VDD+0.3 V JTAG input LOW voltage VIL −0.3 +0.5 V JTAG output HIGH voltage JTAG output LOW voltage R10DS0115EJ0200 Rev.2.00 Nov 09, 2012 VOH1 | IOHC | = 100 μA 1.6 V VOH2 | IOHT | = 2 mA 1.4 V VOL1 IOLC = 100 μA 0.2 V VOL2 IOLT = 2 mA 0.4 V Page 21 of 34 μPD46184095B, μPD46184185B JTAG AC Test Conditions Input waveform (Rise / Fall time ≤ 1 ns) 1.8 V 0.9 V Test Points 0.9 V 0.9 V Test Points 0.9 V 0V Output waveform Output load Figure 2. External load at test VTT = 0.9 V 50 Ω ZO = 50 Ω TDO 20 pF R10DS0115EJ0200 Rev.2.00 Nov 09, 2012 Page 22 of 34 μPD46184095B, μPD46184185B JTAG AC Characteristics (TA = 0 to 70°C) Parameter Symbol Conditions MIN. MAX. Unit Clock Clock cycle time tTHTH 50 ns Clock frequency fTF Clock HIGH time tTHTL 20 20 MHz ns Clock LOW time tTLTH 20 ns TCK LOW to TDO unknown tTLOX 0 TCK LOW to TDO valid tTLOV Output time ns 10 ns Setup time TMS setup time tMVTH 5 ns TDI valid to TCK HIGH tDVTH 5 ns tCS 5 ns TMS hold time tTHMX 5 ns TCK HIGH to TDI invalid tTHDX 5 ns tCH 5 ns Capture setup time Hold time Capture hold time JTAG Timing Diagram tTHTH TCK tMVTH tTHTL tTLTH TMS tTHMX tDVTH TDI tTHDX tTLOX tTLOV TDO R10DS0115EJ0200 Rev.2.00 Nov 09, 2012 Page 23 of 34 μPD46184095B, μPD46184185B Scan Register Definition (1) Register name Description Instruction register The instruction register holds the instructions that are executed by the TAP controller when it is moved into the run-test/idle or the various data register state. The register can be loaded when it is placed between the TDI and TDO pins. The instruction register is automatically preloaded with the IDCODE instruction at power-up whenever the controller is placed in test-logic-reset state. Bypass register The bypass register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAMs TAP to another device in the scan chain with as little delay as possible. ID register The ID Register is a 32 bit register that is loaded with a device and vendor specific 32 bit code when the controller is put in capture-DR state with the IDCODE command loaded in the instruction register. The register is then placed between the TDI and TDO pins when the controller is moved into shift-DR state. Boundary register The boundary register, under the control of the TAP controller, is loaded with the contents of the RAMs I/O ring when the controller is in capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to shift-DR state. Several TAP instructions can be used to activate the boundary register. The Scan Exit Order tables describe which device bump connects to each boundary register location. The first column defines the bit’s position in the boundary register. The second column is the name of the input or I/O at the bump and the third column is the bump number. Scan Register Definition (2) Register name Bit size Unit Instruction register 3 bit Bypass register 1 bit ID register 32 bit Boundary register 107 bit ID Register Definition Part number Organization ID [31:28] vendor revision no. ID [27:12] part no. ID [11:1] vendor ID no. ID [0] fix bit μPD46184095B 2M x 9 XXXX 0000 0000 0101 0101 00000010000 1 μPD46184185B 1M x 18 XXXX 0000 0000 0001 1001 00000010000 1 R10DS0115EJ0200 Rev.2.00 Nov 09, 2012 Page 24 of 34 μPD46184095B, μPD46184185B SCAN Exit Order Bit Signal name no. x9 x18 Bump Bit Signal name ID no. x9 x18 Bump Bit Signal name ID no. x9 x18 NC Bump ID 1 C# 6R 37 NC 10D 73 2C 2 C 6P 38 NC 9E 74 Q5 Q11 3E 3 A 6N 39 NC Q7 10C 75 D5 D11 2D 4 A 7P 40 NC D7 11D 76 NC 2E 5 A 7N 41 NC 9C 77 NC 1E 6 A 7R 42 NC 9D 78 NC Q12 2F 7 A 8R 43 Q4 Q8 11B 79 NC D12 3F 8 A 8P 44 D4 D8 11C 80 NC 1G 9 A 9R 45 NC 9B 81 NC 1F 10 Q0 11P 46 NC 10B 82 Q6 Q13 3G 11 D0 10P 47 CQ 11A 83 D6 D13 2G 12 NC 10N 48 – Internal 84 NC 1J 13 NC 9P 49 A 9A 85 NC 2J 14 NC Q1 10M 50 A 8B 86 NC Q14 3K 15 NC D1 11N 51 A 7C 87 NC D14 3J 16 NC 9M 52 A 6C 88 NC 2K 17 NC 9N 53 LD# 8A 89 NC 1K 18 Q1 Q2 11L 54 NC 7A 90 Q7 Q15 2L 19 D1 D2 11M 55 BW0# 7B 91 D7 D15 3L 20 NC 9L 56 K 6B 92 NC 1M 21 NC 10L 57 K# 6A 93 NC 1L NC 5B 94 NC Q16 3N 5A 95 NC D16 3M 22 NC Q3 11K 58 23 NC D3 10K 59 NC BW1# 24 NC 9J 60 R, W# 4A 96 NC 1N 25 NC 9K 61 A 5C 97 NC 2M A 4B 98 Q8 Q17 3P 3A 99 D8 D17 2N 26 Q2 Q4 10J 62 27 D2 D4 11J 63 A NC 28 ZQ 11H 64 DLL# 1H 100 NC 2P 29 NC 10G 65 CQ# 1A 101 NC 1P 30 NC 9G 66 NC Q9 2B 102 A 3R NC D9 3B 103 A 4R 31 NC Q5 11F 67 32 NC D5 11G 68 NC 1C 104 A 4P NC 1B 105 A 5P 33 NC 9F 69 34 NC 10F 70 NC Q10 3D 106 A 5N NC D10 3C 107 A 5R 35 Q3 Q6 11E 71 36 D3 D6 10E 72 R10DS0115EJ0200 Rev.2.00 Nov 09, 2012 NC 1D Page 25 of 34 μPD46184095B, μPD46184185B JTAG Instructions Instructions Description EXTEST The EXTEST instruction allows circuitry external to the component package to be tested. Boundary-scan register cells at output pins are used to apply test vectors, while those at input pins capture test results. Typically, the first test vector to be applied using the EXTEST instruction will be shifted into the boundary scan register using the PRELOAD instruction. Thus, during the update-IR state of EXTEST, the output drive is turned on and the PRELOAD data is driven onto the output pins. IDCODE The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in capture-DR mode and places the ID register between the TDI and TDO pins in shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the test-logic-reset state. BYPASS When the BYPASS instruction is loaded in the instruction register, the bypass register is placed between TDI and TDO. This occurs when the TAP controller is moved to the shiftDR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. SAMPLE / PRELOAD SAMPLE / PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the instruction register, moving the TAP controller into the capture-DR state loads the data in the RAMs input and Q pins into the boundary scan register. Because the RAM clock(s) are independent from the TAP clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e., in a metastable state). Although allowing the TAP to sample metastable input will not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data capture setup plus hold time (tCS plus tCH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the boundary scan register. Moving the controller to shift-DR state then places the boundary scan register between the TDI and TDO pins. SAMPLE-Z If the SAMPLE-Z instruction is loaded in the instruction register, all RAM Q pins are forced to an inactive drive state (high impedance) and the boundary register is connected between TDI and TDO when the TAP controller is moved to the shift-DR state. JTAG Instruction Coding IR2 IR1 IR0 Instruction 0 0 0 EXTEST Note 0 0 1 IDCODE 0 1 0 SAMPLE-Z 1 0 1 1 RESERVED 2 1 0 0 SAMPLE / PRELOAD 1 0 1 RESERVED 2 1 1 0 RESERVED 2 1 1 1 BYPASS Notes 1. TRISTATE all Q pins and CAPTURE the pad values into a SERIAL SCAN LATCH. 2. Do not use this instruction code because the vendor uses it to evaluate this product. R10DS0115EJ0200 Rev.2.00 Nov 09, 2012 Page 26 of 34 μPD46184095B, μPD46184185B Output Pin States of CQ, CQ# and Q Instructions Control-Register Status Output Pin Status CQ,CQ# Q 0 Update High-Z 1 Update Update 0 SRAM SRAM 1 SRAM SRAM SAMPLE-Z 0 High-Z High-Z 1 High-Z High-Z SAMPLE 0 SRAM SRAM 1 SRAM SRAM 0 SRAM SRAM 1 SRAM SRAM EXTEST IDCODE BYPASS Remark The output pin statuses during each instruction vary according to the Control-Register status (value of Boundary Scan Boundary Scan Register Register, bit no. 48). CAPTURE Register There are three statuses: Update : Contents of the “Update Register” are output to the SRAM : Contents of the SRAM internal output “SRAM Output” are output to the output pin (DDR Pad). SRAM Output Update Register output pin (DDR Pad). Update High-Z :The output pin (DDR Pad) becomes high impedance by controlling of the “High-Z JTAG ctrl”. The Control-Register status is set during Update-DR at the DDR Pad SRAM High-Z SRAM Output Driver EXTEST or SAMPLE instruction. High-Z JTAG ctrl R10DS0115EJ0200 Rev.2.00 Nov 09, 2012 Page 27 of 34 μPD46184095B, μPD46184185B Boundary Scan Register Status of Output Pins CQ, CQ# and Q Instructions SRAM Status Boundary Scan Register Status CQ,CQ# Q READ (Low-Z) Pad Pad NOP (High-Z) Pad Pad READ (Low-Z) − − NOP (High-Z) − − SAMPLE-Z READ (Low-Z) Pad Pad NOP (High-Z) Pad Pad SAMPLE READ (Low-Z) Internal Internal NOP (High-Z) Internal Pad READ (Low-Z) − − NOP (High-Z) − − EXTEST IDCODE BYPASS Remark The Boundary Scan Register statuses during execution each Note No definition No definition Boundary Scan Register instruction vary according to the instruction code and SRAM CAPTURE Register operation mode. There are two statuses: Internal Pad : Contents of the output pin (DDR Pad) are captured in the “CAPTURE Register” in the Boundary Scan Update Register Pad SRAM Output Register. Internal : Contents of the SRAM internal output “SRAM Output” are captured in the “CAPTURE Register” in the Boundary Scan Register. DDR Pad SRAM Output Driver High-Z JTAG ctrl R10DS0115EJ0200 Rev.2.00 Nov 09, 2012 Page 28 of 34 μPD46184095B, μPD46184185B TAP Controller State Diagram 1 Test-Logic-Reset 0 1 0 1 1 Select-IR-Scan Select-DR-Scan Run-Test / Idle 0 0 1 1 Capture-IR Capture-DR 0 0 0 Shift-DR 0 Shift-IR 1 1 1 1 Exit1-DR Exit1-IR 0 0 0 Pause-DR 0 Pause-IR 1 1 0 0 Exit2-DR Exit2-IR 1 1 Update-DR 1 Update-IR 0 1 0 Disabling the Test Access Port It is possible to use this device without utilizing the TAP. To disable the TAP Controller without interfering with normal operation of the device, TCK must be tied to VSS to preclude mid level inputs. TDI and TMS may be left open but fix them to VDD via a resistor of about 1 kΩ when the TAP controller is not used. TDO should be left unconnected also when the TAP controller is not used. R10DS0115EJ0200 Rev.2.00 Nov 09, 2012 Page 29 of 34 New Instruction μPD46184095B, μPD46184185B Run-Test/Idle Update-IR Exit1-IR Shift-IR Exit2-IR IDCODE Pause-IR Exit1-IR Shift-IR R10DS0115EJ0200 Rev.2.00 Nov 09, 2012 Select-IR-Scan Run-Test/Idle Instruction Register state TDI Controller state TMS Test-Logic-Reset TDO Output Inactive Select-DR-Scan TCK Test Logic Operation (Instruction Scan) Capture-IR Page 30 of 34 IDCODE μPD46184095B, μPD46184185B Test-Logic-Reset Select-IR-Scan Select-DR-Scan Run-Test/Idle Update-DR Exit1-DR Shift-DR Exit2-DR Instruction Pause-DR Exit1-DR Shift-DR Capture-DR R10DS0115EJ0200 Rev.2.00 Nov 09, 2012 Instruction Register state TDI Controller state TMS TCK Test Logic (Data Scan) Run-Test/Idle TDO Output Inactive Select-DR-Scan Page 31 of 34 μPD46184095B, μPD46184185B Package Dimensions 165-PIN PLASTIC BGA(13x15) ZD w S B E ZE B 11 10 9 8 7 6 5 4 3 2 1 A D R P N M L K J H G F E D C B A w S A INDEX MARK A y1 (UNIT:mm) A2 S S y e S b x A1 M S AB ITEM D DIMENSIONS 13.00±0.10 E 15.00±0.10 w 0.30 A 1.35±0.11 A1 0.37±0.05 A2 0.98 e 1.00 b +0.10 0.50 −0.05 x 0.10 y 0.15 y1 0.25 ZD 1.50 ZE 0.50 T165F1-100-EQ1 R10DS0115EJ0200 Rev.2.00 Nov 09, 2012 Page 32 of 34 μPD46184095B, μPD46184185B Recommended Soldering Condition Please consult with our sales offices for soldering conditions of these products. Types of Surface Mount Devices μPD46184095BF1-EQ1 : 165-pin PLASTIC BGA (13 x 15) μPD46184185BF1-EQ1 : 165-pin PLASTIC BGA (13 x 15) Quality Grade • A quality grade of the products is “Standard”. • Anti-radioactive design is not implemented in the products. • Semiconductor devices have the possibility of unexpected defects by affection of cosmic ray that reach to the ground and so forth. R10DS0115EJ0200 Rev.2.00 Nov 09, 2012 Page 33 of 34 μPD46184095B, μPD46184185B Revision History Rev. Rev.1.00 Rev.2.00 Date ’12.06.01 ’12.11.09 Page ALL Description Summary New Data Sheet Addition : -E33,-E33Y series, Lead series Deletion : -E50,-E50Y series All trademarks and registered trademarks are the property of their respective owners. C - 34