SONY CXK77K36R320GB-4

SONY
CXK77K36R320GB
32Mb LW R-R HSTL High Speed Synchronous SRAM (1Mb x 36)
3/33/4
Preliminary
Description
The CXK77K36R320GB is a high speed CMOS synchronous static RAM with common I/O pins, organized as 1,048,576 words
by 36 bits. This synchronous SRAM integrates input registers, high speed RAM, output registers, and a one-deep write buffer
onto a single monolithic IC. Register - Register (R-R) read operations and Late Write (LW) write operations are supported, providing a high-performance user interface.
All address and control input signals except G (Output Enable) and ZZ (Sleep Mode) are registered on the rising edge of the K
differential input clock.
During read operations, output data is driven valid from the rising edge of K, one full clock cycle after the address is registered.
During write operations, input data is registered on the rising edge of K, one full clock cycle after the address is registered.
Sleep (power down) capability is provided via the ZZ input signal.
Output drivers are series terminated, and output impedance is programmable via the ZQ input pin. By connecting an external
control resistor RQ between ZQ and VSS, the impedance of the output drivers can be precisely controlled.
333 MHz operation is obtained from a single 2.5V power supply. JTAG boundary scan interface is provided using a subset of
IEEE standard 1149.1 protocol.
Features
•
3 Speed Bins
Cycle Time / Access Time
-3
3.0ns / 1.6ns
-33
3.3ns / 1.6ns
-4
4.0ns / 2.0ns
• Single 2.5V power supply (VDD): 2.5V ± 5%
Note: 1.8V VDD is also supported. Please contact Sony Memory Marketing Department for further information.
• Dedicated output supply voltage (VDDQ): 1.5V ± 0.1V
Note: 1.8V VDDQ is also supported. Please contact Sony Memory Marketing Department for further information.
• HSTL-compatible I/O interface with dedicated input reference voltage (VREF): 0.75V typical
• Register - Register (R-R) read protocol
• Late Write (LW) write protocol
• Full read/write coherency
• Byte Write capability
• Differential input clocks (K/K)
• Asynchronous output enable (G)
• Sleep (power down) mode via dedicated mode pin (ZZ)
• Programmable output driver impedance
• JTAG boundary scan (subset of IEEE standard 1149.1)
• 119 pin (7x17), 1.27mm pitch, 14mm x 22mm Ball Grid Array (BGA) package
32Mb LW R-R, rev 0.6
1 / 22
March 16, 2004
SONY®
Preliminary
CXK77K36R320GB
1Mb x 36 Pin Assignment (Top View)
1
2
3
4
5
6
7
A
VDDQ
SA
SA
NC
SA
SA
VDDQ
B
NC
SA
SA
SA
(32M)
SA
SA
NC
C
NC
SA
SA
VDD
SA
SA
NC
D
DQc
DQc
V SS
ZQ
V SS
DQb
DQb
E
DQc
DQc
V SS
SS
V SS
DQb
DQb
F
VDDQ
DQc
V SS
G
V SS
DQb
VDDQ
G
DQc
DQc
SBWc
NC
SBWb
DQb
DQb
H
DQc
DQc
V SS
NC
V SS
DQb
DQb
J
VDDQ
VDD
VREF
VDD
VREF
VDD
VDDQ
K
DQd
DQd
V SS
K
V SS
DQa
DQa
L
DQd
DQd
SBWd
K
SBWa
DQa
DQa
M
VDDQ
DQd
V SS
SW
V SS
DQa
VDDQ
N
DQd
DQd
V SS
SA
V SS
DQa
DQa
P
DQd
DQd
V SS
SA
V SS
DQa
DQa
R
NC
SA
M1 (1)
VDD
M2 (2)
SA
NC
T
NC
NC
(x18)
SA
SA
(x36)
SA
NC
(x18)
ZZ
U
VDDQ
TMS
TDI
TCK
TDO
RSVD (3)
VDDQ
Notes:
1. Pad Location 3R is defined as an M1 mode pin in LW SRAMs. However, it must be tied “low” in this device.
2. Pad Location 5R is defined as an M2 mode pin in LW SRAMs. However, it must be tied “high” in this device.
3. Pad Location 6U must be left unconnected. It is used by Sony for internal test purposes.
32Mb LW R-R, rev 0.6
2 / 22
March 16, 2004
SONY®
CXK77K36R320GB
Preliminary
Pin Description
Symbol
Type
Description
SA
Input
Synchronous Address Inputs - Registered on the rising edge of K.
DQa, DQb
DQc, DQd
I/O
Synchronous Data Inputs / Outputs - Registered on the rising edge of K during write operations.
Driven from the rising edge of K during read operations.
DQa - indicates Data Byte a
DQb - indicates Data Byte b
DQc - indicates Data Byte c
DQd - indicates Data Byte d
K, K
Input
Differential Input Clocks
SS
Input
Synchronous Select Input - Registered on the rising edge of K.
SS = 0
enables the device to accept read and write commands
SS = 1
disables the device
SW
Input
Synchronous Write Enable Input - Registered on the rising edge of K.
SW = 0
specifies a write operation when the device is enabled
SW = 1
specifies a read operation when the device is enabled
SBWa, SBWb
SBWc, SBWd
Input
Synchronous Byte Write Enable Inputs - Registered on the rising edge of K.
SBWa = 0 specifies write Data Byte a during a write operation
SBWb = 0 specifies write Data Byte b during a write operation
SBWc = 0 specifies write Data Byte c during a write operation
SBWd = 0 specifies write Data Byte d during a write operation
G
Input
Asynchronous Output Enable Input - Deasserted (high) disables the data output drivers.
ZZ
Input
Asynchronous Sleep Mode Input - Asserted (high) forces the device into low-power mode.
M1, M2
Input
Read Operation Protocol Select - These mode pins must be tied “low” and “high” respectively to
select Register - Register read operations.
ZQ
Input
Output Driver Impedance Control Resistor Input - This pin must be connected to VSS through an
external resistor RQ to program data output driver impedance. See the Programmable Output
Driver Impedance section for further information.
VDD
2.5V Core Power Supply - Core supply voltage.
VDDQ
Output Power Supply - Output buffer supply voltage.
VREF
Input Reference Voltage - Input buffer threshold voltage.
VSS
Ground
TCK
Input
JTAG Clock
TMS
Input
JTAG Mode Select - Weakly pulled “high” internally.
TDI
Input
JTAG Data In - Weakly pulled “high” internally.
TDO
Output
JTAG Data Out
RSVD
Reserved - This pin is reserved for Sony test purposes. It must be left unconnected.
NC
No Connect - These pins are true no-connects, i.e. there is no internal chip connection to these
pins. They can be left unconnected or tied directly to VDD, VDDQ, or VSS.
32Mb LW R-R, rev 0.6
3 / 22
March 16, 2004
SONY®
Preliminary
CXK77K36R320GB
•Clock Truth Table
K
ZZ
SS
(tn)
SW
(tn)
SBWx
(tn)
G
X
1
X
X
X
X
Sleep (Power Down) Mode
↑
0
1
X
X
X
Deselect
↑
0
0
1
X
1
↑
0
0
1
X
↑
0
0
0
↑
0
0
↑
0
0
DQ
(tn)
DQ
(tn+1)
Hi - Z
Hi - Z
***
Hi - Z
Read
Hi - Z
Hi - Z
0
Read
***
Q(tn)
0
X
Write All Bytes
***
D(tn)
0
X
X
Write Bytes With SBWx = 0
***
D(tn)
0
1
X
Abort Write
***
Hi - Z
Operation
Notes:
1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”.
2. “***” indicates that the input requirement or output state is determined by the previous operation.
3. DQs are tri-stated in response to Write and Deselect commands, one cycle after the command is sampled.
•Sleep (Power Down) Mode
Sleep (power down) mode is provided through the asynchronous input signal ZZ. When ZZ is asserted (high), the output
drivers are disabled and the SRAM begins to draw standby current. Contents of the memory array are preserved. An enable
time (tZZE) must be met before the SRAM is guaranteed to be in sleep mode, and a recovery time (tZZR) must be met before
the SRAM can resume normal operation.
•Programmable Impedance Output Drivers
These devices have programmable impedance output drivers. The output impedance is controlled by an external resistor RQ
connected between the SRAM’s ZQ pin and VSS, and is equal to one-fifth the value of this resistor, nominally. See the DC
Electrical Characteristics section for further information.
Output Driver Impedance Power-Up Requirements
Output driver impedance will reach the programmed value within 8192 cycles after power-up. Consequently, it is recommended that Read operations not be initiated until after the initial 8192 cycles have elapsed.
Output Driver Impedance Updates
Output driver impedance is updated during Write and Deselect operations when the output driver is disabled.
•Power-Up Sequence
For reliability purposes, Sony recommends that power supplies power up in the following sequence: V SS, VDD, VDDQ, VREF,
and Inputs. VDDQ should never exceed V DD. If this power supply sequence cannot be met, a large bypass diode may be required between VDD and VDDQ. Please contact Sony Memory Application Department for further information.
32Mb LW R-R, rev 0.6
4 / 22
March 16, 2004
SONY®
Preliminary
CXK77K36R320GB
•Absolute Maximum Ratings
Parameter
Symbol
Rating
Units
Supply Voltage
VDD
-0.5 to +3.2
V
Output Supply Voltage
VDDQ
-0.5 to +2.3
V
VIN
-0.5 to VDDQ + 0.5 (2.3V max)
V
Input Voltage (M1, M2)
VMIN
-0.5 to VDD + 0.5 (3.2V max)
V
Input Voltage (TCK, TMS, TDI)
VTIN
-0.5 to +3.8V
V
Operating Temperature
TA
0 to 85
°C
Junction Temperature
TJ
0 to 110
°C
Storage Temperature
TSTG
-55 to 150
°C
Input Voltage (Address, Control, Data, Clock)
Notes: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device at these or any other conditions other than those indicated
in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
•BGA Package Thermal Characteristics
Parameter
Junction to Case Temperature
Symbol
Rating
Units
ΘJC
3.6
°C/W
•I/O Capacitance
(TA = 25oC, f = 1 MHz)
Parameter
Input Capacitance
Output Capacitance
Symbol
Test conditions
Min
Max
Units
Address
CIN
VIN = 0V
---
4.0
pF
Control
CIN
VIN = 0V
---
4.0
pF
Clock
CKIN
VKIN = 0V
---
4.5
pF
Data
COUT
VOUT = 0V
---
5.0
pF
Note: These parameters are sampled and are not 100% tested.
32Mb LW R-R, rev 0.6
5 / 22
March 16, 2004
SONY®
Preliminary
CXK77K36R320GB
•DC Recommended Operating Conditions
Parameter
(VSS = 0V, TA = 0 to 85oC)
Symbol
Min
Typ
Max
Units
Notes
Supply Voltage
VDD
2.37
2.5
2.63
V
1
Output Supply Voltage
VDDQ
1.4
1.5
1.6
V
2
Input Reference Voltage
VREF
VDDQ/2 - 0.1
VDDQ/2
VDDQ/2 + 0.1
V
3
Input High Voltage (Address, Control, Data)
VIH
VREF + 0.1
---
VDDQ + 0.3
V
4
Input Low Voltage (Address, Control, Data)
VIL
-0.3
---
VREF - 0.1
V
5
Input High Voltage (M1, M2)
VMIH
VREF + 0.3
---
VDD + 0.3
V
Input Low Voltage (M1, M2)
VMIL
-0.3
---
VREF - 0.3
V
Clock Input Signal Voltage
VKIN
-0.3
---
VDDQ + 0.3
V
Clock Input Differential Voltage
VDIF
0.2
---
VDDQ + 0.6
V
Clock Input Common Mode Voltage
VCM
VDDQ/2 - 0.1
VDDQ/2
VDDQ/2 + 0.1
V
1. V DD = 1.8V ± 0.1V is also supported. Please contact Sony Memory Marketing Department for further information.
2. V DDQ = 1.8V ± 0.1V is also supported. Please contact Sony Memory Marketing Department for further information.
3. The peak-to-peak AC component superimposed on VREF may not exceed 5% of the DC component.
4. V IH (max) AC = VDDQ + 0.75V for pulse widths less than one-quarter of the cycle time (tCYC/4).
5. V IL (min) AC = -0.75V for pulse widths less than one-quarter of the cycle time (tCYC/4).
32Mb LW R-R, rev 0.6
6 / 22
March 16, 2004
SONY®
Preliminary
CXK77K36R320GB
•DC Electrical Characteristics
Parameter
Symbol
Input Leakage Current
(Address, Control, Clock)
ILI
Input Leakage Current
(M1, M2)
IMLI
Output Leakage Current
ILO
Average Power Supply
Operating Current
IDD-3
IDD-33
IDD-4
Power Supply
Standby Current
ISB
Output High Voltage
VOH
Output Low Voltage
VOL
(V DD = 2.5V ± 5%, V SS = 0V, TA = 0 to 85oC)
Test Conditions
Min
Typ
Max
Units
VIN = V SS to VDDQ
-5
---
5
uA
VMIN = VSS to V DD
-5
---
5
uA
-5
---
5
uA
-------
-------
650
600
540
mA
---
---
180
mA
VDDQ - 0.4
---
---
V
---
---
0.4
V
---
---
35
Ω
VOUT = VSS to VDDQ
G = VIH
IOUT = 0 mA
SS = V IL, ZZ = VIL
IOUT = 0 mA
ZZ = VIH
IOH = -6.0 mA
RQ = 250Ω
IOL = 6.0 mA
RQ = 250Ω
VOH, VOL = V DDQ/2
RQ < 150Ω
Output Driver Impedance
ROUT
VOH, VOL = VDDQ/2
(RQ/5)*
150Ω ≤ RQ ≤ 300Ω
0.85
VOH, VOL = VDDQ/2
51
RQ > 300Ω
(60*0.85)
RQ/5
(30*1.15)
(RQ/5)*
---
1.15
---
Notes
1
2
Ω
Ω
3
1. This parameter is guaranteed at TA = 0 to 55oC.
2. For maximum output drive (i.e. minimum impedance), the ZQ pin can be tied directly to VSS.
3. For minimum output drive (i.e. maximum impedance), the ZQ pin can be left unconnected or tied to VDDQ.
32Mb LW R-R, rev 0.6
7 / 22
March 16, 2004
SONY®
Preliminary
CXK77K36R320GB
•AC Electrical Characteristics
(VDD = 2.5V ± 5%, VSS = 0V, TA = 0 to 85oC)
-3
Parameter
-33
-4
Symbol
Units
Min
Max
Min
Max
Min
Max
Notes
Input Cycle Time
tKHKH
3.0
---
3.3
---
4.0
---
ns
Input Clock High Pulse Width
tKHKL
1.2
---
1.3
---
1.5
---
ns
Input Clock Low Pulse Width
tKLKH
1.2
---
1.3
---
1.5
---
ns
Address Input Setup Time
tAVKH
0.3
---
0.3
---
0.3
---
ns
Address Input Hold Time
tKHAX
0.5
---
0.6
---
0.7
---
ns
Write Enable Input Setup Time
tWVKH
0.3
---
0.3
---
0.3
---
ns
Write Enable Input Hold Time
tKHWX
0.5
---
0.6
---
0.7
---
ns
Sync Select Input Setup Time
tSVKH
0.3
---
0.3
---
0.3
---
ns
Sync Select Input Hold Time
tKHSX
0.5
---
0.6
---
0.7
---
ns
Data Input Setup Time
tDVKH
0.3
---
0.3
---
0.3
---
ns
Data Input Hold Time
tKHDX
0.5
---
0.6
---
0.7
---
ns
Input Clock High to Output Data Valid
tKHQV
---
1.6
---
1.6
---
2.0
ns
Input Clock High to Output Data Hold
tKHQX
0.65
---
0.65
---
0.65
---
ns
2
Input Clock High to Output Data Low-Z
tKHQX1
0.65
---
0.65
---
0.65
---
ns
2,3
Input Clock High to Output Data High-Z
tKHQZ
0.65
1.8
0.65
1.8
0.65
2.2
ns
2,3
Output Enable Low to Output Data Valid
tGLQV
---
2.5
---
2.5
---
2.5
ns
Output Enable Low to Output Data Low-Z
tGLQX
0.3
---
0.3
---
0.3
---
ns
2,3
Output Enable High to Output Data High-Z
tGHQZ
---
2.5
---
2.5
---
2.5
ns
2,3
Sleep Mode Enable Time
tZZE
---
15
---
15
---
15
ns
2
Sleep Mode Recovery Time
tZZR
20
---
20
---
20
---
ns
2
1
1
1
1
1. These parameters are measured from VREF ± 200mV to the clock mid-point.
2. These parameters are guaranteed by design through extensive corner-lot characterization.
3. These parameters are measured at ± 50mV from steady state voltage.
32Mb LW R-R, rev 0.6
8 / 22
March 16, 2004
SONY®
Preliminary
CXK77K36R320GB
•AC Test Conditions
(VDD = 2.5V ± 5%, VDDQ = 1.5V ± 0.1V, TA = 0 to 85°C)
Item
Symbol
Conditions
Units
VREF
0.75
V
Input High Level
VIH
1.25
V
Input Low Level
VIL
0.25
V
Input Rise & Fall Time
2.0
V/ns
Input Reference Level
0.75
V
Input Reference Voltage
Notes
Clock Input High Voltage
VKIH
1.25
V
VDIF = 1.0V
Clock Input Low Voltage
VKIL
0.25
V
VDIF = 1.0V
Clock Input Common Mode Voltage
VCM
0.75
V
Clock Input Rise & Fall Time
2.0
V/ns
Clock Input Reference Level
K/K cross
V
Output Reference Level
0.75
V
Output Load Conditions
RQ = 250Ω
See Figure 1
below
Figure 1: AC Test Output Load
16.7Ω
50Ω
50Ω
0.75V
16.7Ω
DQ
16.7Ω
50Ω
50Ω
32Mb LW R-R, rev 0.6
9 / 22
0.75V
March 16, 2004
SONY®
Preliminary
CXK77K36R320GB
Read-Write-Read Timing Diagram
Synchronously Controlled via SS and Deselect Operations (G = Low)
Figure 2
Read
Read
Read
Deselect
Deselect
Write
Write
Write
Read
Read
Read
A5
A6
A7
A8
A9
K
K
tKHKH
SA
A1
A2
tKHKL tKLKH
tAVKH tKHAX
A3
A4
tSVKH tKHSX
SS
tWVKH tKHWX
SW
tWVKH tKHWX
SBWx
G = VIL
tKHQV
DQ
tKHQX
Q1
tKHQZ
Q2
tDVKH tKHDX
D4
Q3
tKHQX1
D5
D6
Q7
Note: In the diagram above, two Deselect operations are inserted between Read and Write operations to control the data bus
transition from output to input. This depiction is for clarity purposes only. It is NOT a requirement. Depending on the application, one Deselect operation may be sufficient.
32Mb LW R-R, rev 0.6
10 / 22
March 16, 2004
SONY®
Preliminary
CXK77K36R320GB
Read-Write-Read Timing Diagram
Asynchronously Controlled via G and Dummy Read Operations (SS = Low)
Figure 3
Read
Read
Read
Dummy
Read
Dummy
Read
Write
Write
Write
Read
Read
Read
A5
A6
A7
A8
A9
K
K
tKHKH
SA
A1
A2
tKHKL tKLKH
tAVKH tKHAX
A3
A4
SS = VIL
tWVKH tKHWX
SW
tWVKH tKHWX
SBWx
G
tGLQV
tGHQZ
tKHQV
DQ
tKHQX
Q1
tKHQZ
Q2
Q3
tGLQX
tDVKH tKHDX
D4
tKHQX1
D5
D6
Q7
Note: In the diagram above, two Dummy Read operations are inserted between Read and Write operations to control the data
bus transition from output to input. This depiction is for clarity purposes only. It is NOT a requirement. Depending on the application, one Dummy Read operation may be sufficient.
32Mb LW R-R, rev 0.6
11 / 22
March 16, 2004
SONY®
Preliminary
CXK77K36R320GB
Sleep (Power-Down) Mode Timing Diagram
Figure 4
Read
(note 1)
Deselect
(note 2)
Deselect
(note 3)
Deselect
(note 4)
Read
(note 5)
Read
Read
A2
A3
A4
K
K
SA
A1
SS
SW
SBWx
G = VIL
tZZE
Begin
ISB
tZZR
ZZ
DQ
Q1
Q2
Notes:
1: This can be any operation. The depiction of a Read operation here is provided only as an example.
2: Before ZZ is asserted, at least two (2) Deselect operations must be initiated after the last Read or Write operation is initiated, in order to ensure the successful completion of the last Read or Write operation.
3: While ZZ is asserted, all of the SRAM’s address, control, data, and clock inputs are ignored.
4: After ZZ is deasserted, Deselect operations must be initiated until the specified recovery time (tZZR) has been met. Read
and Write operations may NOT be initiated during this time.
5: This can be any operation. The depiction of a Read operation here is provided only as an example.
32Mb LW R-R, rev 0.6
12 / 22
March 16, 2004
SONY®
Preliminary
CXK77K36R320GB
•Test Mode Description
These devices provide a JTAG Test Access Port (TAP) and Boundary Scan interface using a limited set of IEEE std. 1149.1
functions. This test mode is intended to provide a mechanism for testing the interconnect between master (processor, controller, etc.), SRAMs, other components, and the printed circuit board.
In conformance with a subset of IEEE std. 1149.1, these devices contain a TAP Controller and four TAP Registers. The TAP
Registers consist of one Instruction Register and three Data Registers (ID, Bypass, and Boundary Scan Registers).
The TAP consists of the following four signals:
TCK:
TMS:
TDI:
TDO:
Test Clock
Test Mode Select
Test Data In
Test Data Out
Induces (clocks) TAP Controller state transitions.
Inputs commands to the TAP Controller. Sampled on the rising edge of TCK.
Inputs data serially to the TAP Registers. Sampled on the rising edge of TCK.
Outputs data serially from the TAP Registers. Driven from the falling edge of TCK.
Disabling the TAP
When JTAG is not used, TCK should be tied “low” to prevent clocking the SRAM. TMS and TDI should either be tied
“high” through a pull-up resistor or left unconnected. TDO should be left unconnected.
Note: Operation of the TAP does not interfere with normal SRAM operation except when the SAMPLE-Z instruction is selected. Consequently, TCK, TMS, and TDI can be controlled any number of ways without adversely affecting the functionality of the device.
(VDD = 2.5V ± 5%, VSS = 0V, TA = 0 to 85°C)
JTAG DC Recommended Operating Conditions
Parameter
Symbol
Test Conditions
Min
Max
Units
JTAG Input High Voltage
VTIH
---
1.4
3.6
V
JTAG Input Low Voltage
VTIL
---
-0.3
0.8
V
JTAG Output High Voltage (CMOS)
VTOH
ITOH = -100uA
VDD - 0.1
---
V
JTAG Output Low Voltage (CMOS)
VTOL
ITOL = 100uA
---
0.1
V
JTAG Output High Voltage (TTL)
VTOH
ITOH = -8.0mA
VDD - 0.4
---
V
JTAG Output Low Voltage (TTL)
VTOL
ITOL = 8.0mA
---
0.4
V
VTIN = VSS to 3.3V
-10
10
uA
JTAG Input Leakage Current
ITLI
(VDD = 2.5V ± 5%, VSS = 0V, TA = 0 to 85°C)
JTAG AC Test Conditions
Parameter
Symbol
Conditions
Units
JTAG Input High Level
VTIH
2.5
V
JTAG Input Low Level
VTIL
0.0
V
JTAG Input Rise & Fall Time
1.0
V/ns
JTAG Input Reference Level
1.25
V
JTAG Output Reference Level
1.25
V
JTAG Output Load Condition
32Mb LW R-R, rev 0.6
Notes
See Fig.1 (page 9)
13 / 22
March 16, 2004
SONY®
Preliminary
CXK77K36R320GB
JTAG AC Electrical Characteristics
Parameter
Symbol
Min
TCK Cycle Time
tTHTH
50
ns
TCK High Pulse Width
tTHTL
20
ns
TCK Low Pulse Width
tTLTH
20
ns
TMS Setup Time
tMVTH
5
ns
TMS Hold Time
tTHMX
5
ns
TDI Setup Time
tDVTH
5
ns
TDI Hold Time
tTHDX
5
ns
Capture Setup Time (Address, Control, Data, Clock)
tCS
5
ns
Capture Hold Time (Address, Control, Data, Clock)
tCH
5
ns
TCK Low to TDO Valid
tTLQV
TCK Low to TDO Hold
tTLQX
Max
10
0
Unit
ns
ns
JTAG Timing Diagram
Figure 5
tTHTL
tTLTH
tTHTH
TCK
tMVTH
tTHMX
tDVTH
tTHDX
TMS
TDI
tTLQV
tTLQX
TDO
32Mb LW R-R, rev 0.6
14 / 22
March 16, 2004
SONY®
Preliminary
CXK77K36R320GB
TAP Controller
The TAP Controller is a 16-state state machine that controls access to the various TAP Registers and executes the operations
associated with each TAP Instruction. State transitions are controlled by TMS and occur on the rising edge of TCK.
The TAP Controller enters the “Test-Logic Reset” state in one of two ways:
1. At power up.
2. When a logic “1” is applied to TMS for at least 5 consecutive rising edges of TCK.
The TDI input receiver is sampled only when the TAP Controller is in either the “Shift-IR” state or the “Shift-DR” state.
The TDO output driver is active only when the TAP Controller is in either the “Shift-IR” state or the “Shift-DR” state.
TAP Controller State Diagram
Figure 6
1
Test-Logic Reset
0
0
Run-Test / Idle
1
Select-DR
1
Select-IR
0
1
0
1
Capture-DR
Capture-IR
0
0
0
Shift-DR
1
1
Exit1-DR
Exit1-IR
0
0
0
Pause-DR
1
0
Exit2-IR
Update-DR
32Mb LW R-R, rev 0.6
0
15 / 22
0
1
1
1
0
Pause-IR
1
Exit2-DR
0
Shift-IR
1
1
1
Update-IR
1
0
March 16, 2004
SONY®
CXK77K36R320GB
Preliminary
TAP Registers
TAP Registers are serial shift registers that capture serial input data (from TDI) on the rising edge of TCK, and drive serial
output data (to TDO) from the falling edge of TCK. They are divided into two groups: “Instruction Registers” (IR), which
are manipulated via the “IR” states in the TAP Controller, and “Data Registers” (DR), which are manipulated via the “DR”
states in the TAP Controller.
Instruction Register (IR - 3 Bits)
The Instruction Register stores the various TAP Instructions supported by these devices. It is loaded with the IDCODE instruction at power-up, and when the TAP Controller is in the “Test-Logic Reset” and “Capture-IR” states. It is inserted between TDI and TDO when the TAP Controller is in the “Shift-IR” state, at which time it can be loaded with a new instruction.
However, newly loaded instructions are not executed until the TAP Controller has reached the “Update-IR” state.
The Instruction Register is 3 bits wide, and is encoded as follows:
Code
(2:0)
Instruction
Description
000
BYPASS
See code “111”.
001
IDCODE
Loads a predefined device- and manufacturer-specific identification code into the ID Register
when the TAP Controller is in the “Capture-DR” state, and inserts the ID Register between
TDI and TDO when the TAP Controller is in the “Shift-DR” state.
See the ID Register description for more information.
010
SAMPLE-Z
Loads the individual logic states of all signals composing the SRAM’s I/O ring into the
Boundary Scan Register when the TAP Controller is in the “Capture-DR” state, and inserts
the Boundary Scan Register between TDI and TDO when the TAP Controller is in the “ShiftDR” state.
Also disables the SRAM’s data output drivers.
See the Boundary Scan Register description for more information.
011
PRIVATE
Do not use. Reserved for manufacturer use only.
100
SAMPLE
Loads the individual logic states of all signals composing the SRAM’s I/O ring into the
Boundary Scan Register when the TAP Controller is in the “Capture-DR” state, and inserts
the Boundary Scan Register between TDI and TDO when the TAP Controller is in the “ShiftDR” state.
See the Boundary Scan Register description for more information.
101
PRIVATE
Do not use. Reserved for manufacturer use only.
110
PRIVATE
Do not use. Reserved for manufacturer use only.
111
BYPASS
Loads a logic “0” into the Bypass Register when the TAP Controller is in the “Capture-DR”
state, and inserts the Bypass Register between TDI and TDO when the TAP Controller is in
the “Shift-DR” state.
See the Bypass Register description for more information.
Bit 0 is the LSB and Bit 2 is the MSB. When the Instruction Register is selected, TDI serially shifts data into the MSB, and
the LSB serially shifts data out through TDO.
32Mb LW R-R, rev 0.6
16 / 22
March 16, 2004
SONY®
Preliminary
CXK77K36R320GB
Bypass Register (DR - 1 Bit)
The Bypass Register is one bit wide, and provides the minimum length serial path between TDI and TDO. It is loaded with
a logic “0” when the BYPASS instruction has been loaded in the Instruction Register and the TAP Controller is in the “Capture-DR” state. It is inserted between TDI and TDO when the BYPASS instruction has been loaded into the Instruction Register and the TAP Controller is in the “Shift-DR” state.
ID Register (DR - 32 Bits)
The ID Register is loaded with a predetermined device- and manufacturer-specific identification code when the IDCODE
instruction has been loaded into the Instruction Register and the TAP Controller is in the “Capture-DR” state. It is inserted
between TDI and TDO when the IDCODE instruction has been loaded into the Instruction Register and the TAP Controller
is in the “Shift-DR” state.
The ID Register is 32 bits wide, and contains the following information:
Device
Revision Number
(31:28)
Part Number
(27:12)
Sony ID
(11:1)
Start Bit
(0)
1Mb x 36
xxxx
0000 0000 0111 0011
0000 1110 001
1
Bit 0 is the LSB and Bit 31 is the MSB. When the ID Register is selected, TDI serially shifts data into the MSB, and the LSB
serially shifts data out through TDO.
Boundary Scan Registers (DR - 70 Bits)
The Boundary Scan Register is equal in length to the number of active signal connections to the SRAM (excluding the TAP
pins) plus a number of place holder locations reserved for functional and/or density upgrades. It is loaded with the individual
logic states of all signals composing the SRAM’s I/O ring when the SAMPLE or SAMPLE-Z instruction has been loaded
into the Instruction Register and the TAP Controller is in the “Capture-DR” state. It is inserted between TDI and TDO when
the SAMPLE or SAMPLE-Z instruction has been loaded into the Instruction Register and the TAP Controller is in the “ShiftDR” state.
The Boundary Scan Register contains the following bits:
1Mb x 36
DQ
36
SA
20
K, K
2
SS, SW, SBWx
6
G, ZZ
2
ZQ, M1, M2
3
Place Holder
1
Note: K and K are connected to a differential input receiver that generates a single-ended input clock signal to the device.
Therefore, in order to capture deterministic values for these signals in the Boundary Scan Register, they must be at opposite
logic levels when sampled.
Note: When an external resistor RQ is connected between the ZQ pin and VSS, the value of the ZQ signal captured in the
Boundary Scan Register is non-deterministic.
Note: Place Holders are required for some NC pins to allow for future density and/or functional upgrades. They are connected to V SS internally, regardless of pin connection externally.
32Mb LW R-R, rev 0.6
17 / 22
March 16, 2004
SONY®
Preliminary
CXK77K36R320GB
Boundary Scan Register Bit Order Assignments
The table below depicts the order in which the bits are arranged in the Boundary Scan Register. Bit 1 is the LSB and bit 70
is the MSB. When the Boundary Scan Register is selected, TDI serially shifts data into the MSB, and the LSB serially shifts
data out through TDO.
1Mb x 36
Bit
Signal
Pad
Bit
Signal
Pad
1
M2
5R
36
SA
3B
2
SA
4P
37
SA
2B
3
SA
4T
38
SA
3A
4
SA
6R
39
SA
3C
5
SA
5T
40
SA
2C
6
ZZ
7T
41
SA
2A
7
DQa
6P
42
DQc
2D
8
DQa
7P
43
DQc
1D
9
DQa
6N
44
DQc
2E
10
DQa
7N
45
DQc
1E
11
DQa
6M
46
DQc
2F
12
DQa
6L
47
DQc
2G
13
DQa
7L
48
DQc
1G
14
DQa
6K
49
DQc
2H
15
DQa
7K
50
DQc
1H
16
SBWa
5L
51
SBWc
3G
17
K
4L
52
ZQ
4D
18
K
4K
53
SS
4E
19
G
4F
54
SA
4B
20
SBWb
5G
55
NC
(1)
4H
21
DQb
7H
56
SW
4M
22
DQb
6H
57
SBWd
3L
22
DQb
7G
58
DQd
1K
24
DQb
6G
59
DQd
2K
25
DQb
6F
60
DQd
1L
26
DQb
7E
61
DQd
2L
27
DQb
6E
62
DQd
2M
28
DQb
7D
63
DQd
1N
29
DQb
6D
64
DQd
2N
30
SA
6A
65
DQd
1P
31
SA
6C
66
DQd
2P
32
SA
5C
67
SA
3T
33
SA
5A
68
SA
2R
34
SA
6B
69
SA
4N
35
SA
5B
70
M1
3R
Note 1: NC pin at pad location 4H is connected to V SS internally, regardless of pin connection externally.
32Mb LW R-R, rev 0.6
18 / 22
March 16, 2004
SONY®
Preliminary
CXK77K36R320GB
•Ordering Information
Part Number
VDD
I/O Type
Size
Speed
(Cycle Time / Access Time)
CXK77K36R320GB-3
2.5V
HSTL
1Mb x 36
3.0ns / 1.6ns
CXK77K36R320GB-33
2.5V
HSTL
1Mb x 36
3.3ns / 1.6ns
CXK77K36R320GB-4
2.5V
HSTL
1Mb x 36
4.0ns / 2.0ns
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license
by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
32Mb LW R-R, rev 0.6
19 / 22
March 16, 2004
SONY®
Preliminary
CXK77K36R320GB
119 Pin BGA Package Dimensions
B
0.6 ± 0.1
A
X
S
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1.0
C
X4
21.0
22.0
7
1.
1.27
C
4-
C
3-
0.35 S
0.6 ± 0.1
1.
5
1.5
0.20
0.15
7.62
1.27
3.19
20.32
14.0
13.0
0.84
2.1 ± 0.3
12 345 67
φ0.75 ± 0.15
φ0.4
S A
φ0.2
S
B
S
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
BGA-119P-021
BORAD TREATMENT
COPPER-CLAD LAMINATE
EIAJ CODE
BGA119-P-1422
LEAD MATERIAL
SOLDER
PACKAGE MASS
1.1g
JEDEC CODE
This product utilizes lead (Pb) as one of the elements composing the package solder ball. The quantity of lead (Pb) per package is
approxmiately 70.81mg (1.7mg per ball * 119 balls * 35%). Lead (Pb) has been shown to be hazardous to the environment, and
therefore may be subject to regulations within each country.
32Mb LW R-R, rev 0.6
20 / 22
March 16, 2004
SONY®
CXK77K36R320GB
Preliminary
•Revision History
Rev. #
Rev. Date
Description of Modification
rev 0.0
11/30/01
Initial Version
rev 0.1
03/22/02
1. Modified BGA Package Thermal Characteristics section (p. 6).
1.0 °C/W to 3.6 °C/W
ΘJC
2. Modified DC Recommended Operating Conditions section (p. 7).
VDDQ (max)
VDD to 1.6V
VREF, V CM (max)
1.0V to 0.85V
Added note 1 regarding 2.5V VDD support.
Added note 2 regarding 1.8V VDDQ support.
3. Modified DC Electrical Characteristics section (p. 8).
ROUT
RQ/5 ± 10% (GBD) to RQ/5 ± 15% (TESTED)
4. Modified AC Electrical Characteristics section (p. 9).
Removed “-25” bin. Added “-33” bin.
-3
tKHQV
1.7ns to 1.5ns
tKHQZ, tGLQV, tGHQZ
1.9ns to 1.7ns
5. Removed 1.8V VDDQ AC Test Conditions.
6. Modified JTAG DC Recommended Operating Conditions section (p. 14).
VTIH (min)
1.2V to 1.4V
VTIL (max)
0.6V to 0.8V
7. Modified JTAG Instruction Register definition (p. 17).
Changed codes “011” and “110” from BYPASS to PRIVATE.
8. Modified 119 Pin BGA Package Dimensions section (p. 21).
Changed package from FC-BGA to WB-BGA.
rev 0.2
04/02/02
1. Modified DC Recommended Operating Conditions section (p. 7).
VDDQ (max)
1.6V to VDD
VREF, V CM (min)
0.65V to V DDQ/2 - 0.1V
VREF, V CM (max)
0.85V to VDDQ/2 + 0.1V
2. Added 1.8V V DDQ AC Test Conditions (p. 11).
rev 0.3
06/24/02
1. Modified AC Electrical Characteristics section (p. 9).
-3, -33
tAVKH, tWVKH, tSVKH, tDVKH
-3, -33
tKHAX, tKHWX, tKHSX, tKHDX
2. Modified JTAG DC Recommended Operating Conditions section (p. 15).
VTIH (min)
VTIL (max)
3. Modified JTAG AC Electrical Characteristics section (p.16).
TCK Cycle Time
TCK High / Low Pulse Widths
TMS/TDI Input Setup & Hold Times
TDO Output Valid Time
Added Capture Setup & Hold Times
rev 0.4
02/05/03
32Mb LW R-R, rev 0.6
0.5ns to 0.3ns
0.5ns to 0.3ns
1.4V to 1.2V
0.8V to 0.6V
100ns to 50ns
40ns to 20ns
10ns to 5ns
20ns to 10ns
5ns
1. Removed all x18 information (created separate x18 data sheet).
2. Changed VDD from 1.8V nominal to 2.5V nominal, throughout document.
3. Modified Absolute Maximum Ratings (p. 5).
VDD (max)
2.5V to 3.2V
4. Modified DC Recommended Operating Conditions section (p. 6).
VDD (min)
1.7V to 2.37V
VDD (max)
1.9V to 2.63V
VDDQ (max)
VDD to 1.6V
21 / 22
March 16, 2004
SONY®
Rev. #
CXK77K36R320GB
Rev. Date
Preliminary
Description of Modification
rev 0.4
02/05/03
5. Modified DC Electrical Characteristics section (p. 7).
IMLI, ILO (min/max)
± 10uA to ± 5uA
Added preliminary IDD and ISB specifications.
6. Modified AC Electrical Characteristics section (p. 8).
All Bins tKHQX, tKHQX1, tKHQZ (min)
0.5ns to 0.7ns
-3
tKHAX, tKHWX, tKHSX, tKHDX
0.3ns to 0.5ns
-33
tKHAX, tKHWX, tKHSX, tKHDX
0.3ns to 0.6ns
tKHQV
1.7ns to 1.6ns
tKHQZ, tGLQV, tGHQZ,
1.9ns to 1.8ns
-4
tKHAX, tKHWX, tKHSX, tKHDX
0.3ns to 0.7ns
7. Removed 1.8V VDDQ AC Test Conditions.
8. Modified JTAG DC Recommended Operating Conditions section (p. 13).
VTIH (min)
1.2V to 1.4V
VTIH (max)
VDD + 0.3V to 3.6V
VTIL (max)
0.6V to 0.8V
9. Removed 1.8V JTAG AC Test Conditions.
10. Added 2.5V JTAG AC Test Conditions (p.13).
rev 0.5
07/08/03
1. Modified AC Electrical Characteristics section (p. 8).
-3
tGLQV, tGHQZ
-33
tGLQV, tGHQZ
-4
tGLQV, tGHQZ
2. Modified JTAG ID Register definition (p. 17).
Changed Part Number code from T.B.D. to 0000 0000 0111 0011.
rev 0.6
03/16/04
32Mb LW R-R, rev 0.6
1.7ns to 2.5ns
1.8ns to 2.5ns
2.2ns to 2.5ns
1. Modified I/O Capacitance section (p. 5).
CIN
3.5pF to 4.0pF
CKIN
3.5pF to 4.5pF
COUT
4.5pF to 5.0pF
2. Modified AC Electrical Characteristics section (p. 8).
All Bins tKHQX, tKHQX1, tKHQZ (min)
0.7ns to 0.65ns
-3
tKHQV
1.5ns to 1.6ns
tKHQZ
1.7ns to 1.8ns
3. Added note to Package Dimensions section regarding lead content in solder balls (p. 20).
22 / 22
March 16, 2004