DATA SHEET MOS INTEGRATED CIRCUIT µPD70(F)3175 V850E/CA4TM HELIOS 32- bit RISC Microcontroller DESCRIPTION The V850E/CA4 Helios microcontroller is a member of NEC's V850 32-bit RISC family, which match the performance gains attainable with RISC-based controllers to the needs of embedded control applications. The V850 CPU offers easy pipeline handling and programming, resulting in compact code size comparable to 16-bit CISC CPUs. The V850E/CA4 Helios offers an excellent combination of general purpose peripheral functions, like serial communication interfaces (UART, clocked SI) and measurement inputs (A/D converter), with dedicated CAN network support. The device offers power-saving modes to manage the power consumption effectively under varying conditions.Thus equipped, the V850E/CA4 Helios is ideally suited for automotive applications, like Airbags. It is also an excellent choice for other applications where a combination of sophisticated peripheral functions and CAN network support is required. Functions in detail are described in the following user’s manuals. Be sure to read these manuals when you design your systems. <V850E/CA4 User Manual> <V850E Architecture Manual> : <U16241EE1V0UM00> : <U10243EJ6V0UM00> FEATURES • • • • • • 32-bit RISC CPU with Harvard Architecture Full-CAN Interface: 2 channels Serial Interfaces: 5 channels - 3-wire mode: 3 channels - UART mode: 2 channels Timers: 6 channels - 16-bit multi purpose timer/event counter: 2 channels - 16-bit multi purpose timer: 2 channels - Watch timer: 1 channel - Watchdog timer: 1 channel 10-bit resolution A/D Converter: 14 channels I/O lines: 76 • • • • • • Power supply voltage range: - +4.5 V ≤ VDD ≤ +5.5 V Frequency range: up to 32 MHz Built-in low power saving mode Built-in clock oscillator circuit with internal PLL Temperature range: - -40 °C to +85 °C (µPD70F3175(A), µPD703175(A)-32/24, µPD703176(A)-32/24) Package: - 100 LQFP, 0.5 mm pin-pitch (14 × 14 mm) ORDERING INFORMATION Device Part Number Package µPD70F3175(A)-32 V850E/CA4 LQFP100 µPD703175(A)-32/24 14 × 14 mm µPD703176(A)-32/24 ROM RAM FCAN option Oper. Frequency 256 K 12 K 2 Channels -40°C ~ +85°C 256 K 12 K 2 Channels -40°C ~ +85°C 192 K 10 K 2 Channels -40°C ~ +85°C The information contained in this document is released in advance of the production cycle for the device. The parameters for the device may change before final production, or NEC Corporation may, at its own discretion, withdraw the device prior to production. NEC Corporation 2003 Document No. U16242EE1V0DS00 Data Published: July 2003 µPD70(F)3175 INTERNAL BLOCK DIAGRAM NMI INTP00 to INTP02 INTP10, INTP15 INTP20, INTP25 INTP30, INTP32, INTP34 TIG00 to TIG05 TOG01 to TOG04 TIG10 to TIG15 TOG11 to TOG14 Interrupt Controller 16-bit Timer TMG0 16-bit Timer TMG1 16-bit Timer TMD0 CPU ROM 256 K (Flash & Mask) or 192 K (Mask) B VDD0 B VSS0 B VDD1 PC Multiplier 32 x 32 = 64 32-bit Barrel Shifter B VSS2 VPP (Flash only) System Registers RAM A L U General Registers 32-bit x 32 12 K (Flash & Mask) or 10 K (Mask) Voltage Regulator Voltage Regulator DMA 16-bit Timer TMD1 B VSS1 B VDD2 V DD0 V SS0 V SS1 REGC_M0 REGC_M1 CVDD CVSS REGC_0 Watch Timer Watchdog Timer PCL NPB Bus bridge Internal Peripheral Bus PLLDIV RXD60 UART60 TXD60 10-bit ADC 14 channels Ports RXD61 SI01 SO01 SCK01 CSI01 SI10 SO10 SCK10 CSI10 FCRXD0 FCTXD0 FCRXD1 AVREF AVSS AVDD CSI00 ANI0-ANI13 SI00 SO00 SCK00 PDH0-PDH8 PDL0-PDL15 UART61 P00-P02 P10-P15 P20-P25 P30-P35 P40-P45 P70-P713 PCD2-PCD3 PCM0-PCM3 PCT0,1,4,6 TXD61 Oscillator and Clock Generator System Control X1 X2 MODE1 MODE0 RESET BRG0 Note FCAN1 Note FCAN2 FCTXD1 Note: The CAN macro of this device fulfils the requirements according ISO 11898. Additionally the CAN macro was tested according to the test procedures required by ISO 16845. The CAN macro successfully passed all test patterns. Beyond these test patterns, other tests like robustness tests and processor interface tests as recommended by C&S/FH Wolfenbuettel have successfully been issued. 2 Data Sheet U16242EE1V0DS00 µPD70(F)3175 PIN IDENTIFICATION ANI0 to ANI13 Analog Inputs TOG01 to TOG04 Timer G0 Compare Output AVDD Analog Power Supply TOG11 to TOG14 Timer G1 Compare Output AVSS Analog Ground TIG00 to TIG05 Timer G0 Capture Input AVREF Analog reference Voltage supply TIG10 to TIG15 Timer G1 Capture Input PCL Processor Clock Output REGC_M0, REGC_M1 Main Regulator Output FCRXD0, FCRXD1 CAN Receive Data for channel 0 and 1 REGC_O Osc and PLL Regulator Output FCTXD0, FCTXD1 CAN Transmit Data for channel 0 and 1 MODE0, MODE1 Operation mode select INTP00, INTP01, INTP02, INTP10, INTP15, INPT20, INTP25, INTP30, INTP32, INTP34 External Interrupt Input X1, X2 Main System Clock NMI Non-Maskable Interrupt Input RESET Reset Input P00 to P02 Port 0 CVDD, CVSS Oscillator and PLL power supply P10 to P15 Port 1 VDD0 Digital power supply for Flash, CPU and I/O buffer P20 to P25 Port 2 VSS0, VSS1 Digital Ground for Flash, CPU and I/O buffer P30 to P35 Port 3 BVSS0 to BVSS2 I/O buffers Ground P40 to P45 Port 4 BVDD0 to BVDD2 I/O buffers supply P70 to P713 Port 7 VPP Programming Voltage PCM0 to PCM3 Port CM PCT0, PCT1, PCT4, PCT6 Port CT PCD2 to PCD3 Port CD PDL0 to PDL15 Port DL PDH0 to PDH8 Port DH RXD60, RXD61 UART Receive Data TXD60, TXD61 UART Transmission Data SCK00, SCK01, SCK10 Synchronous Interface Clock SI00, SI01, SI10 Synchronous Interface Input SO00, SO01, SO10 Synchronous Interface Output Data Sheet U16242EE1V0DS00 3 µPD70(F)3175 PIN CONFIGURATION • 100-Pin Plastic LQFP (0.5 mm pin pitch) (14 × 14 mm) • µPD70F3175(A)-32 • µPD703175(A)-32/24 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 P70/ANI0 P71/ANI1 P72/ANI2 P73/ANI3 P74/ANI4 P75/ANI5 P76/ANI6 P77/ANI7 P78/ANI8 P79/ANI9 P710/ANI10 P711/ANI11 P712/ANI12 P713/ANI13 PCM3 REGC_M0 VDD0 VSS0 BVSS2 BVDD2 PCM2 PCM1 PCM0 PCD3 PCD2 • µPD703176(A)-32/24 P23/TIG13/TOG13 P24/TIG14/TOG14 P25/TIG15/INTP25 P00/FCRXD1/INTP00 P01/FCTXD1/INTP01 75 74 73 72 71 70 18 19 20 21 22 23 24 25 58 57 56 55 54 53 52 51 NMI P32/RXD61/INTP32 P33/TXD61 P34/FCRXD0/INTP34 P35/FCTXD0 PDL0 PDL1 PDL2 PDL3 PDL4 PDL5 PDL6 PDL7 P31/TXD60 P40/SI00 P41/SO00 P42/SCK00 P43/SI01 P44/SO01 P45/SCK01 P02/PCL/INTP02 REGC_M1 VSS1 BVSS0 BVDD0 4 69 68 67 66 65 64 63 62 61 60 59 V850E/CA4 "HELIOS" 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 P30/RXD60/INTP30 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 48 49 50 AVREF AVDD AVSS P10/TIG00/INTP10 P11/TIG01/TOG01 P12/TIG02/TOG02 P13/TIG03/TOG03/SI10 P14/TIG04/TOG04/SO10 P15/TIG05/INTP15/SCK10 REGC_0 CVDD CVSS X1 X2 RESET MODE0 P20/TIG10/INTP20 P21/TIG11/TOG11 P22/TIG12/TOG12 Data Sheet U16242EE1V0DS00 PCT6 PCT4 PCT1 PCT0 PDH8 PDH7 PDH6 PDH5 PDH4 PDH3 PDH2 BVDD1 BVSS1 VPP MODE1 PDH1 PDH0 PDL15 PDL14 PDL13 PDL12 PDL11 PDL10 PDL9 PDL8 µPD70(F)3175 Table of Contents 1. Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1 1.2 1.3 1.4 2. Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 I/O Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Port Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Non-port Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Programming Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1 3.2 3.3 3.4 3.5 3.6 3.7 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1.1 Flash version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1.2 Mask version. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 General Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2.1 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2.2 PLL Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2.3 I/O Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.5.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.5.2 Oscillator Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.5.3 Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.5.4 RESET (power up/down sequence) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.5.5 Standby Mode Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.5.6 Interrupt Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Peripheral Function Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.6.1 Timer G. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.6.2 CSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.6.3 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.6.4 FCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.6.5 A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Flash EPROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4. Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Data Sheet U16242EE1V0DS00 5 µPD70(F)3175 List of Figures Figure 1-1: Figure 1-2: Figure 3-1: Figure 3-2: Figure 3-3: Figure 3-4: Figure 3-5: Figure 3-6: Figure 3-7: Figure 3-8: Figure 4-1: 6 Input / Output Circuits.................................................................................................. 12 Power Supply Connection ........................................................................................... 17 AC Test Input Waveform, AC Test Load Condition ..................................................... 24 Oscillator Recommendations....................................................................................... 24 Reset Timing ............................................................................................................... 25 Interrupt Timing ........................................................................................................... 26 Timer G Characteristics............................................................................................... 27 CSI Slave Mode Characteristics.................................................................................. 28 VDD0 Setup / Hold Time for VPP Terminal ................................................................... 31 Flash EPROM Serial Programming Operation Characteristics ................................... 31 Package Drawing ........................................................................................................ 32 Data Sheet U16242EE1V0DS00 µPD70(F)3175 List of Tables Table 1-1: Table 1-2: Table 1-3: Table 3-1: Table 3-2: Table 3-3: Table 3-4: Table 3-5: Table 3-6: Table 3-7: Table 3-8: Table 3-9: Table 3-10: Table 3-11: Table 3-12: Table 3-13: Table 3-14: Table 3-15: Table 3-16: Table 3-17: Table 3-18: Table 3-19: Table 3-20: Pin Functions.................................................................................................................... 8 Port Functions ................................................................................................................ 13 Non-Port Functions......................................................................................................... 16 Absolute Maximum Ratings............................................................................................ 19 Absolute Maximum Ratings............................................................................................ 20 Oscillator Characteristics................................................................................................ 21 PLL Characteristics ........................................................................................................ 21 I/O Capacitances ............................................................................................................ 21 Operating Conditions...................................................................................................... 22 DC Characteristics.......................................................................................................... 22 Power Supply Currents................................................................................................... 23 Clock AC Characteristics................................................................................................ 25 Reset Timing .................................................................................................................. 25 Standby Mode Timing..................................................................................................... 25 Interrupt Timing .............................................................................................................. 26 Timer G Characteristics.................................................................................................. 27 CSI Master Mode Characteristics................................................................................... 28 CSI Slave Mode Characteristics..................................................................................... 28 UART Characteristics ..................................................................................................... 29 FCAN Characteristics ..................................................................................................... 29 A/D Converter Characteristics ........................................................................................ 29 Flash EPROM Programming Characteristics Basic Specification .................................. 30 Flash EPROM Serial Programming Operation Characteristics ...................................... 30 Data Sheet U16242EE1V0DS00 7 µPD70(F)3175 1. Pin Functions 1.1 Pin Functions Table 1-1: Pin Functions (1/4) Pin No. Name Function Default Alternate I/O Driver Type 1 AVREF Reference-Voltage supply pin for A/D converter - - - 2 AVDD Power supply pin for A/D converter - - - 3 AVSS Ground potential for A/D converter - - - 4 P10/TIG00/ INTP10 Timer G0 Capture Trigger 0 External interrupt input INTP10 I/O 5 P11/TIG01/TOG01 Timer G0 Capture Trigger 0 Timer G0 Compare Output 0 I/O 6 P12/TIG02/TOG02 Timer G0 Capture Trigger 0 Timer G0 Compare Output 0 I/O 7 P13/TIG03/ TOG03/SI10 Timer G0 Capture Trigger 0 Timer G0 Compare Output 0 CSI1 channel 0 serial data input I/O 8 P14/TIG04/ TOG04/SO10 Timer G0 Capture Trigger 0 Timer G0 Compare Output 0 CSI1 channel 0 serial data output I/O 9 P15/TIG05/ INTP15/SCK10 Timer G0 Capture Trigger 0 External interrupt input INTP15 CSI1 channel 0 serial clock input I/O Port 1: 6-bit input/output port 5-K 10 REGC_O Pin for external 3.3 V Regulating Capacitor - - - 11 CVDD Power supply pin for oscillator and PLL - - - 12 CVSS Ground potential pin for oscillator and PLL - - - 13 X1 Resonator connection for clock - - - 14 X2 Resonator connection for clock - - - 15 RESET External System reset input - - 2 16 MODE0 MODE Definition Input pins - I 2 8 Data Sheet U16242EE1V0DS00 µPD70(F)3175 Table 1-1: Pin Functions (2/4) Pin No. Name Function Default P20/TIG10/ INTP20 Alternate I/O Timer G1 Capture Trigger 0 External interrupt input INTP20 I/O 18 P21/TIG11/TOG11 Timer G1 Capture Trigger 0 Timer G1 Compare Output 0 I/O 19 P22/TIG12/TOG12 Timer G1 Capture Trigger 0 Timer G1 Compare Output 0 I/O Timer G1 Capture Trigger 0 Timer G1 Compare Output 0 I/O Timer G1 Capture Trigger 0 Timer G1 Compare Output 0 I/O 17 20 P23/TIG13/TOG13 Port 2: 6-bit input/output port 21 P24/TIG14/TOG14 22 P25/TIG15/ INTP25 Timer G1 Capture Trigger 0 External interrupt input INTP25 I/O 23 P00/FCRXD1/ INTP00 FCAN channel 1 serial data input External interrupt input INTP00 I/O 24 P01/FCTXD1/ INTP01 FCAN channel 1 serial data output External interrupt input INTP01 I/O 25 P30/RXD60/ INTP30 UART60 asynchronous data input External interrupt input INTP30 I/O 26 P31/TXD60 Port 0: 3-bit input/output port Port 3: 6-bit input/output port 5-K UART60 asynchronous data output I/O 27 P40/SI00 CSI0 channel 0 serial data input I/O 28 P41/SO00 CSI0 channel 0 serial data output I/O CSI0 channel 0 serial clock input I/O CSI0 channel 1 serial data input I/O 31 P44/SO01 CSI0 channel 1 serial data output I/O 32 P45/SCK01 CSI0 channel 1 serial clock input I/O Processor clock output External interrupt input INTP02 I/O 29 P42/SCK00 30 P43/SI01 Port 4: 6-bit input/output port Driver Type 33 P02/PCL/INTP02 Port 0: 3-bit input/output port 34 REGC_M1 pin for external 3.3 V Regulating Capacitor - - - 35 VSS1 Ground potential pin for Flash, CPU and I/O buffers - - - 36 BVSS0 Ground potential pin for I/O buffers - - - 37 BVDD0 Power supply pin for I/O buffers - - - 38 NMI Non-maskable interrupt input pin - I 2 39 P32/RXD61/ INTP32 40 P33/TXD61 P34/FCRXD0/ 41 INTP34 42 P35/FCTXD0 UART61 asynchronous data input External interrupt input INTP32 Port 3: 6-bit input/output port I/O UART61 asynchronous data output I/O FCAN channel 0 serial data input External interrupt input INTP34 I/O FCAN channel 0 serial data output I/O Data Sheet U16242EE1V0DS00 5-K 9 µPD70(F)3175 Table 1-1: Pin Functions (3/4) Pin No. Name Function Default Alternate I/O 43 PDL0 - I/O 44 PDL1 - I/O 45 PDL2 - I/O 46 PDL3 - I/O 47 PDL4 - I/O 48 PDL5 - I/O 49 PDL6 - I/O - I/O - I/O 52 PDL9 - I/O 53 PDL10 - I/O 54 PDL11 - I/O 55 PDL12 - I/O 56 PDL13 - I/O 57 PDL14 - I/O 58 PDL15 - I/O 50 PDL7 51 PDL8 59 PDH0 Port DL: 16-bit input/output port Driver Type 5 - I/O 60 PDH1 Port DH: 9-bit output port - I/O 61 MODE1 MODE Definition Input pins - I/O 2 62 VPP Note High Voltage apply pin to program the device - - - 63 BVSS1 Ground potential pin for I/O buffers - - 64 BVDD1 Power supply pin for I/O buffers - - 65 PDH2 - I/O 66 PDH3 - I/O - I/O - I/O 69 PDH6 - I/O 70 PDH7 - I/O 71 PDH8 - I/O 72 PCT0 - I/O - I/O - I/O - I/O - I/O - I/O - I/O - I/O - I/O - - 67 PDH4 68 PDH5 73 PCT1 74 PCT4 Port DH: 9-bit output port Port CT: 4-bit input/output port 75 PCT6 76 PCD2 77 PCD3 Port CD: 2-bit output port 78 PCM0 79 PCM1 Port CM: 4-bit output port 80 PCM2 81 BVDD2 10 Power supply pin for I/O buffers Data Sheet U16242EE1V0DS00 5 - µPD70(F)3175 Table 1-1: Pin Functions (4/4) Pin No. Name Function Default Alternate I/O Driver Type 82 BVSS2 Ground potential pin for I/O buffers - - - 83 VSS0 Ground potential pin for Flash, CPU and I/O buffers - - - 84 VDD0 Power supply pin for Flash, CPU and I/O buffers - - - 85 REGC_M0 pin for external 3.3 V Regulating Capacitor - - - 86 PCM3 Port CM: 4-bit output port - I/O 5 87 P713/ANI13 ANI13 I/O 88 P712/ANI12 ANI12 I/O 89 P711/ANI11 ANI11 I/O 90 P710/ANI10 ANI10 I/O 91 P79/ANI9 ANI9 I/O 92 P78/ANI8 ANI8 I/O ANI7 I/O ANI6 I/O 95 P75/ANI5 ANI5 I/O 96 P74/ANI4 ANI4 I/O 97 P73/ANI3 ANI3 I/O 98 P72/ANI2 ANI2 I/O 99 P71/ANI1 ANI1 I/O 100 P70/ANI0 ANI0 I/O 93 P77/ANI7 94 P76/ANI6 Port 7: 14-bit input port 9 Note: Only for µPD70F3175 (Flash product) Data Sheet U16242EE1V0DS00 11 µPD70(F)3175 1.2 I/O Circuits Figure 1-1: Input / Output Circuits Type 9 Type 2 P-ch Comparator + - IN N-ch IN VREF (Threshold Voltage) Input enable Type 5 Type 5-K V DD V DD Data Data P-ch P-ch IN/OUT IN/OUT Output disable N-ch Output disable V SS V SS Input enable 12 N-ch Input enable Data Sheet U16242EE1V0DS00 µPD70(F)3175 1.3 Port Pins Table 1-2: Port name Pin name Port Functions (1/3) Pin function after Reset In Single Chip Mode P00/FCRXD1/INTP00 P0 P01/FCTXD1/INTP01 Port Mode (input mode) P02/PCL/INTP02 If not used Independently connect to BVSS or BVDD via resistor Output: leave open P10/TIG00/INTP10 P11/TIG01/TOG01 P1 P12/TIG02/TOG02 P13/TIG03/TOG03/SI10 Port Mode (input mode) Independently connect to BVSS or BVDD via resistor Output: leave open P14/TIG04/TOG04/SO10 P15/TIG05/INTP15/SCK10 P20/TIG10/INTP20 P21/TIG11/T0G11 P2 P22/TIG12/T0G12 P23/TIG13/T0G13 Port Mode (input mode) Independently connect to BVSS or BVDD via resistor Output: leave open P24/TIG14/T0G14 P25/TIG15/INTP25 P30/RXD60/INTP30 P31/TXD60 P3 P32/RXD61/INTP32 P33/TXD61 Port Mode (input mode) Independently connect to BVSS or BVDD via resistor Output: leave open P34/FCRXD0/INTP34 P35/FCTXD0 P40/SI00 P41/SO00 P4 P42/SCK00 P43/SI01 Port Mode (input mode) Independently connect to BVSS or BVDD via resistor Output: leave open P44/SO01 P45/SCK01 Data Sheet U16242EE1V0DS00 13 µPD70(F)3175 Table 1-2: Port name Pin name Port Functions (2/3) Pin function after Reset In Single Chip Mode If not used P70/ANI0 P71/ANI1 P72/ANI2 P73/ANI3 P74/ANI4 P75/ANI5 P7 P76/ANI6 P77/ANI7 Port Mode (input mode) Independently connect to AVSS or AVDD via resistor P78/ANI8 P79/ANI9 P710/ANI10 P711/ANI11 P712/ANI12 P713/ANI13 PCT0 PCT PCT1 PCT4 Port Mode (input mode) Independently connect to BVSS or BVDD via resistor Output: leave open PCT6 PDH0 PDH1 PDH2 PDH3 PDH PDH4 Port Mode (input mode) PDH5 Independently connect to BVSS or BVDD via resistor Output: leave open PDH6 PDH7 PDH8 PCM0 PCM PCM1 PCM2 Port Mode (input mode) Output: leave open PCM3 PCD2 PCD PCD3 Independently connect to BVSS or BVDD via resistor Port Mode (input mode) Independently connect to BVSS or BVDD via resistor Output: leave open 14 Data Sheet U16242EE1V0DS00 µPD70(F)3175 Table 1-2: Port name Pin name Port Functions (3/3) Pin function after Reset In Single Chip Mode If not used PDL0 PDL1 PDL2 PDL3 PDL4 PDL5 PDL6 PDL PDL7 PDL8 Port Mode (input mode) Independently connect to BVSS or BVDD via resistor Output: leave open PDL9 PDL10 PDL11 PDL12 PDL13 PDL14 PDL15 Data Sheet U16242EE1V0DS00 15 µPD70(F)3175 1.4 Non-port Pins Table 1-3: Pin Number Pin name Non-Port Functions Connection for normal operation If not used 1 AVREF Analog voltage reference for A/D converter - 2 AVDD Analog Power Supply - 3 AVSS Analog Ground 10 REGC_O Connect to CVSS via a capacitor Note 1 - 11 CVDD Power supply pin for oscillator and PLL - 12 CVSS Ground potential pin for oscillator and PLL - 13 X1 - 14 X2 Refer to Figure 3-2, “Oscillator Recommendations,” on page 24 for recommended circuit 15 RESET External system reset input - 16 MODE0 Connect to VSSn via a resistor - 34 REGC_M1 Connect to VSS1 via a capacitor Note 2 - 35 VSS1 Ground potential pin for Flash, CPU and I/O buffers - 36 BVSS0 Ground potential pin for I/O buffers - 37 BVDD0 Power supply pin for I/O buffers - NMI NMI 61 MODE1 Connect to VSSn via a resistor 62 VPP Note 3 On Flash devices connect VPP to ground via a resistor. 63 BVSS1 Ground potential pin for I/O buffers 64 BVDD1 Power supply pin for I/O buffers 81 BVDD2 Power supply pin for I/O buffers - 82 BVSS2 Ground potential pin for I/O buffers - 83 VSS0 Ground potential pin for Flash, CPU and I/O buffers - 84 VDD0 Power supply pin for Flash, CPU and I/O buffers - 85 REGC_M0 Connect to REGC_M1 pin with the shortest way (lowest impedance) - NMI Connect to BVSS - Independently connect to VSS or VDD via resistor On ROM devices connect directly to ground Notes: 1. NEC specifies to connect a minimum 330 nF Capacitor. 2. NEC specifies to connect a minimum 1 µF Capacitor. 3. Only for µPD70F3175 (Flash product) Cautions: 1. On REGC-pin and each pin of VDDn, a capacitor has to be attached as tight as possible to the pin. 2. The capacitors used should have only very low serial impedance. 3. All ground pin have to be connected together. 4. For EMI optimization, NEC recommends to separate power supply for VDDn, CVDDn and BVDD (refer to Figure 1-2, “Power Supply Connection,” on page 17). 16 Data Sheet U16242EE1V0DS00 µPD70(F)3175 Figure 1-2: Power Supply Connection 330 nF min REGC_0 CVSS / VSSn BVSSn / AVSS BVDDn I/O Buffer 5 V Power Supply V850E/CA4 HELIOS PLL CVDD VREG 5 V Power Supply OSC REGC_M1 10 nF CPU, Flash and Peripherals VDD0 VREG AVDD AD 5 V Power Supply 5 V Power Supply REGC_M0 AV REF 1 µF min 10 nF Data Sheet U16242EE1V0DS00 17 µPD70(F)3175 2. Programming Flash Memory The device µPD70F3175 supports the programming of the internal flash in two ways: Either by using the flashMASTER programming tool or by performing self-programming using software functions and I/O communications. For programming details about both methods, see the User’s Manual. For timing characteristics about the initial programming using flashMASTER and some more electrical data about the Flash Memory, please see 3.7 “Flash EPROM Characteristics” on page 30. 18 Data Sheet U16242EE1V0DS00 µPD70(F)3175 3. Electrical Specifications 3.1 Absolute Maximum Ratings 3.1.1 Flash version (TA = +25°C,VSSx = CVSS = BVSSx = 0 V) Table 3-1: Parameter Absolute Maximum Ratings Symbol Supply voltage Ratings Unit VDD0 -0.5 to +6.0 V CVDD -0.5 to +6.0 V CVSS -0.5 to +0.5 V BVDDn -0.5 to +6.0 V BVSSn -0.5 to +0.5 V -0.5 to +5.5 V -0.5 to +0.5 V AVDD Test Conditions AVDD ≤ VDD0 + 0.5 V AVSS Input voltage Input voltage Output current low Output current high Operating temperature Storage temperature alphabetical Ports 1 pin All pins 1 pin All pins VI (all except X1, X2, AVREF) VI < BVDDx + 0.5 V -0.5 to +6.0 V AVREF AVREF ≤ AVDD -0.5 to +0.5 V VPP Flash programming mode -0.5 to +8.5 V VAN VAN < AVDD +0.5 V -0.5 to +6.0 V 4.0 mA 50 mA -4.0 mA -50 mA IOL IOH TOPR µPD70F3175(A) -40 ~ +85 °C TSTGB Before programming -55 ~ +150 °C TSTGA After programming -55 ~ +125 °C Data Sheet U16242EE1V0DS00 19 µPD70(F)3175 3.1.2 Mask version (TA = +25°C, VSSx = CVSS = BVSSx = 0 V) Table 3-2: Parameter Absolute Maximum Ratings Symbol Supply voltage Ratings Unit VDD0 -0.5 to +6.0 V CVDD -0.5 to +6.0 V CVSS -0.5 to +0.5 V BVDDn -0.5 to +6.0 V BVSSn -0.5 to +0.5 V -0.5 to +5.5 V -0.5 to +0.5 V AVDD Test Conditions AVDD < VDD0 + 0.5 V AVSS Input voltage Input voltage Output current low Output current high alphabetical Ports 1 pin All pins 1 pin All pins VI (all except X1, X2, AVREF) VI < BVDDx + 0.5 V -0.5 to +6.0 V AVREF AVREF < AVDD -0.5 to +0.5 V VAN VAN < AVDD +0.5 V -0.5 to +6.0 V 4.0 mA 50 mA -4.0 mA -50 mA -40 ~ +85 °C -65 ~ +150 °C IOL IOH Operating temperature TOPR Storage temperature TSTG 20 µPD703175(A), µPD703176A) Data Sheet U16242EE1V0DS00 µPD70(F)3175 3.2 General Characteristics 3.2.1 Oscillator Characteristics (TA= -40 ~ +85°C, VDD0 = CVDD = BVDDx = 4.5 V to 5.5 V, VSSx = CVSS = BVSSx = 0 V) Table 3-3: Resonator Crystal oscillator Ceramic oscillator Parameter Oscillator Characteristics Symbol Oscillator Frequency (fXX) fOSC Oscillation Stabilization time TOST Oscillator Frequency (fXX) fOSC Oscillation Stabilization time TOST Test Conditions MIN. TYP. 6 After VDD0 reaches, oscillator voltage range MIN. 4.5 V MAX. Unit 8 MHz TBD ms Note 6 8 After VDD0 reaches, oscillator voltage range MIN. 4.5 V MHz TBD ms Note Note: Max. stabilization time depends to particular crystal or Ceramic characteristics. 3.2.2 PLL Characteristics (TA= -40 ~ +85°C) Table 3-4: PLL Characteristics Parameter Symbol Test Conditions PLL lock time TPLL OSC MODE PLL on and PLL off MIN. TYP. MAX. Unit 1 ms MAX. Unit 15 pF 15 pF 15 pF 3.2.3 I/O Capacitances (TA = 25°C, VDD5x = VSS5x = 0 V) Table 3-5: Parameter Input capacitance Symbol CI Input/output capacitance CIO Output capacitance CO I/O Capacitances Test Conditions MIN. fC = 1 MHz Unmeasured pins returned to 0 V Data Sheet U16242EE1V0DS00 TYP. 21 µPD70(F)3175 3.3 Operating Conditions Table 3-6: Clock Mode Operation Mode Operating Conditions Operating Temperature (TA) OSC Mode, PLL on Supply Voltage (VDDx) Inside Operation Clock Frequency 12 MHz ≤ fCPU ≤ 32 MHz ALL Modes -40 ~ +85°C 4.5 V ≤ VDDx ≤ 5.5 V OSC Mode, PLL off 6 MHz ≤ fCPU ≤ 8 MHz 3.4 DC Characteristics (TA = -40 ~ +85°C, VDD0 = CVDD = BVDDx = 4.5 V to 5.5 V, VSSx = CVSS = BVSSx = 0 V) Table 3-7: Parameter High level Input voltage Low level Input voltage High level Input voltage Low level Input voltage High level Input voltage Low level Input voltage DC Characteristics Symbol P00-P02, P10-P15, P20-P25, P30-P35, P40-P45, RESET PDL0-PDL15, PDH0-PDH8, PCM0-PCM3, PCD2-PCD3, PCT0, PCT1, PCT4, PCT6, NMI P70-P713 (Port shared with ANIxNote Test Conditions MIN. TYP. MAX. Unit VIH1 0.8 BVDDx BVDDx V VIL1 BVSSx 0.2 BVDDx V VIH2 0.7 BVDDx BVDDx V VIL2 BVSSx 0.3 BVDDx V VIHT 0.7 BVDDx BVDDx V VILT 0 0.3 BVDDx V High level Output voltage VOH1 IOH = -3.0 mA BVDDx-1.0 BVDDx V Low level Output voltage VOL1 IOL = 3.0 mA 0 0.4 V ILIH VI = VDD5 5 µA ILIL VI = 0 V -5 µA High level Input leakage current Low level Input leakage current VI = BVDDx VI = REGC_O Note: P7 can only be use as digital input port when AVDD = VDD. 22 Data Sheet U16242EE1V0DS00 µPD70(F)3175 Table 3-8: Parameter Symbol IDD1 Supply Current Note 1 Flash version Supply Current Note 1 mask 32 MHz version mask 24 MHz version Notes: Test Conditions Operating mode IDD2 HALT mode IDD3 IDLE mode Note 2 Note 3 Note 4 MIN. TYP. MAX. Unit 100 150 mA 50 75 mA 9 13.5 mA 1 1.5 mA IDD4 WATCH mode IDD5 STOP mode 50 300 µA IDD1 Operating mode Note 2 100 150 mA IDD2 HALT mode Note 3 50 75 mA IDD3 IDLE mode 9 13.5 mA 1 1.5 mA 50 300 µA 75 113 mA 38 56 mA 7 10.5 mA 1 1.5 mA 50 300 µA IDD4 WATCH mode IDD5 STOP mode IDD1 Supply Current Note 1 Power Supply Currents Note 4 Operating mode IDD2 HALT mode IDD3 IDLE mode Note 2 Note 3 IDD4 WATCH mode IDD5 STOP mode Note 4 1. AVREF current, port current are not included. 2. fCPU = 4fXX: fXX = 8 MHz for 32 MHz version, fXX = 6 MHz for 24 MHz, peripheral functions operating 3. fXX = 8 MHz, CPU stopped, peripheral functions operating with highest speed with PLL multiplied clock. 4. fXX = 8 MHz, CPU stopped, all peripheral functions stopped (Watch timer and Watchdog timer operating). Data Sheet U16242EE1V0DS00 23 µPD70(F)3175 3.5 AC Characteristics 3.5.1 General (TA = -40 ~ +85°C, VDD0 = CVDD = BVDDx = 4.5 V to 5.5 V, VSSx = CVSS = BVSSx = 0 V) Figure 3-1: AC Test Input Waveform, AC Test Load Condition Test Points VDD5 0.8 VDD5 0.2 VDD5 0V DUT Load on test CL = 50 pF 3.5.2 Oscillator Recommendations Figure 3-2: Oscillator Recommendations X1 X2 * *: This resistor is optional and depends of resonator supplier Note: Values of capacitors depends on used resonator and must be specified in cooperation with manufacturer. 24 Data Sheet U16242EE1V0DS00 µPD70(F)3175 3.5.3 Clock Table 3-9: Parameter Clock AC Characteristics Symbol Test Conditions MIN. MAX. Unit fOSC OSC MODE 6 8 MHz MIN. MAX. X1, X2 oscillator frequency 3.5.4 RESET (power up/down sequence) Table 3-10: Parameter RESET high-level width RESET low-level width Symbol Reset Timing Test Conditions tWRSH Unit 500 ns tWRSLW During WATCH mode 1 ms tWRSL0 After power on, during STOP mode TBD Note ms tWRSL1 Other than above 500 ns Note: The maximum time depends on the oscillation stabilization time of the external oscillator. Figure 3-3: Reset Timing tWRSH tWRSL RESET 3.5.5 Standby Mode Characteristics Table 3-11: Parameter WATCH mode release time STOP mode release time Symbol tWATCH tSTOP Standby Mode Timing Test Conditions MIN. After WATCH mode release 1Note ms TBD Note ms After STOP mode release MAX. Unit Note: This is the minimum time required for internal stabilization. If STOP mode is released by reset, OSC stabilization must be ensured by active reset (please see Table 3-10, “Reset Timing,” on page 25). Data Sheet U16242EE1V0DS00 25 µPD70(F)3175 3.5.6 Interrupt Timing Table 3-12: Parameter Symbol Interrupt Timing Test Conditions MIN. MAX. Unit NMI, INTPn, TIEm high-level width tWITHA 500 ns NMI, INTPn, TIEm low-level width tWITLA 500 ns Remark: n = 0 - 10 m=1-4 Figure 3-4: tWITHA Interrupt Timing tWITLA NMI, INTPn, TIEm 26 Data Sheet U16242EE1V0DS00 µPD70(F)3175 3.6 Peripheral Function Characteristics 3.6.1 Timer G Table 3-13: Timer G Characteristics Test Conditions Parameter Symbol MIN. MAX. Unit TIGmn input high-level width Note tWTIGH TMGn count clock × 2 + 20 ns TIGmn input low-level width Note tWTIGL TMGn count clock × 2 + 20 ns Note: n = 0, 1 and m = 0,..., 5 Figure 3-5: tWTIGH Timer G Characteristics tWTIGL TIGmn Data Sheet U16242EE1V0DS00 27 µPD70(F)3175 3.6.2 CSI Table 3-14: Parameter CSI Master Mode Characteristics Symbol Test Conditions MIN. SCK cycle time tCYSK Output 125 ns SCK high level width tWSKH Output 0.5 tCYSK - 10 ns SCK low level width tWSKL Output 0.5 tCYSK - 10 ns SI set up time (to SCK ↑) tSSISK 40 ns SI hold time (from SCK ↑) tHSKSI 30 ns SO output delay time (from SCK ↓) tDSKSO SO output hold time (from SCK ↑) tHSKSO Table 3-15: Parameter MAX. 30 5 Unit ns ns CSI Slave Mode Characteristics Symbol Test Conditions MIN. SCK cycle time tCYSK Input 125 ns SCK high level width tWSKH Input 0.5 tCYSK - 10 ns SCK low level width tWSKL Input 0.5 tCYSK - 10 ns SI set up time (to SCK ↑) tSSISK 40 ns SI hold time (from SCK ↑) tHSKSI 30 ns SO output delay time (from SCK ↓) tDSKSO SO output hold time (from SCK ↑) tHSKSO Figure 3-6: 50 tWSKH CSI Slave Mode Characteristics tCYSK tWSKL tWSKH SCK tSSISK SI tHSKSI Hi-Z Input Data tDSKSO tHSKSO SO 28 MAX. Output Data Data Sheet U16242EE1V0DS00 Unit ns ns µPD70(F)3175 3.6.3 UART Table 3-16: Parameter Transfer rate UART Characteristics Symbol Test Conditions TUART fPeriferal ≥ 5 MHz MIN. MAX. Unit 312500 bps MAX. Unit 1 Mbps 3.6.4 FCAN Table 3-17: Parameter Transfer rate FCAN Characteristics Symbol Test Conditions TFCAN fCPU ≥ 16 MHz MIN. 3.6.5 A/D Converter Table 3-18: A/D Converter Characteristics (TA = -40 ~ +85°C, VVDD5x = VAVDD = 4.5 ~ 5.5 V, VSS5x = VAVSS = 0 V) Parameter Resolution Symbol Test Conditions MIN. TYP. MAX. Unit - 10 Bit - ±3 LSB 12 µs VIAN AVREF V Reference Voltage AVREF AVDD V Reference Voltage input current Note 4 IAVREF 2 mA Overall Error Note 1 Conversion Time Note 2 Analog Input Voltage tCONV 5 AVREF = AVDD 1 Notes: 1. Quantization error is not included 2. tCONV depends on register ADSCM1 3. tSAM depends on register ADSCM1 4. If ADC is set to standby mode, AVREF can be disconnected externally (left open) to reduce current consumption. Data Sheet U16242EE1V0DS00 29 µPD70(F)3175 3.7 Flash EPROM Characteristics Table 3-19: Flash EPROM Programming Characteristics Basic Specification Parameter Symbol Test conditions VDD Supply voltage MIN. MAX. Unit 4.5 5.5 V +0.3 V 7.8 8.1 V 60 90 mA 100 times VPPL Low input -0.3 VPPH Programming mode 7.5 IPP1 Supply current TYP. Maximum times of reprogramming CWRT Write time tIWRTW Word (32-bit) 20 200 µs tERASCB Block (128 K) 0.2 20 s tERASCC Chip (256 K) 0.4 40 s +70 °C Erase time tPRG Programming temperature Table 3-20: 0 Flash EPROM Serial Programming Operation Characteristics Parameter Symbol Test conditions MIN. TYP. MAX. Unit VDD0 ↑ setup time to VPP ↑ tVDD5SU 1.0 ms VDD5X ↑ hold time to VPP ↑ tVDD5HD 1.0 ms VDD5X ↑ setup time to RESET ↑ tDRRR 10 µs VPP↑ setup time to RESET ↑ tPSRRF 1 µs RESET ↑ count start setup time (to VPPH level) tRFOF 5T + 500 µs Times of VPP counting VPP = VPPH, T = 1/fXX tCOUNT 10 ms VPP count High level width tCH 1 µs VPP count low level width tCL 1 µs Note: T= 1 / fCPU 30 Data Sheet U16242EE1V0DS00 µPD70(F)3175 Figure 3-7: VDD0 Setup / Hold Time for VPP Terminal t VDD5SU t VDD5HD 4.5 V VDD0 VDD0 VPP Figure 3-8: VDD0 Flash EPROM Serial Programming Operation Characteristics VDD0 0V t COUNT t RFOF VPP VPP t CH VDD0 t PSRRF 0V VDD0 RESET t CL t DRRR 0V Data Sheet U16242EE1V0DS00 31 µPD70(F)3175 4. Package Drawing • 100-PIN PLASTIC LQFP (FINE PITCH) (14 × 14) Figure 4-1: 32 Package Drawing Data Sheet U16242EE1V0DS00 µPD70(F)3175 5. Revision History Version Date Author Data Sheet U16242EE1V0DS00 Remarks 33 µPD70(F)3175 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 34 Data Sheet U16242EE1V0DS00 µPD70(F)3175 • The information in this document is current as of 23.07. 2003. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC Electronics. 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