Automatic Calibration Schemes for the RFFC207x

AN RFMD® APPLICATION NOTE
Integrated Configurable Components from
RFMD Multi-Market Products Group
Automatic Calibration Schemes for the
RFFC207x, RFFC507x, and RFMD208x Series
Introduction
The RFFC207x, RFFC507x, and RFMD208x integrated synthesizer products have three automatic calibration schemes. These
allow high performance and very wide band devices to be manufactured with superior performance characteristics.
These calibration schemes allow:
• Selection of the correct voltage controlled oscillator (VCO)
• Selection of the correct VCO tuning capacitance (CT calibration)
• Correction for variation in the VCO tuning sensitivity (KV calibration)
VCO1
VCO tuning
gain (KV)
calibration
Loop filter
Phase
detector
2700-3450 MHz
VCO2
3450-4450 MHz
VCO autoselect and
coarse tune
(CT)
calibration
N-div
VCO3
4450-5400 MHz
Figure 1. Calibration Mechanisms
The VCO and tuning capacitance selection (CT_CAL) is on by default, but may be switched off, if required (to minimize lock
time, for example). The VCO tuning sensitivity correction (KV_CAL) is off by default and can be switched on, if required.
Auto VCO selection
The device achieves its wide tuning range with the use of three VCOs. An algorithm is used to automatically select the correct
VCO for the desired frequency. This is performed as part of the coarse tune calibration; initially the VCO set in p1/p2vcosel
[1:0] of the P1/P2_FREQ1 register is selected. This is normally set to VCO1; it can be set to another VCO dependant on the programmed frequency in order to reduce calibration time. If the coarse tune calibration reaches an end stop, the VCO is changed
and the CT_CAL is performed again with the next VCO. The end stop values are set using the ctmin and ctmax values in the
VCO_AUTO register. These values should be set to h00 and h3F respectively to ensure there is sufficient overlap between adjacent VCO's.
Auto-VCO selection can be disabled by clearing the auto bit [15] in the VCO_AUTO register. However, this is not recommended
because it will then be necessary to program the correct VCO number into the P1_FREQ1 and/or P2_FREQ1 registers.
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Automatic Calibration Schemes for the the RFFC207x/507x Series
Coarse tuning calibration (CT_CAL)
Each of the three VCOs within the chip consists of an integrated inductor, a switched bank of capacitors, and a voltage controlled variable capacitor, as shown in Figure 2. The switched bank of capacitors is used to center the VCO close to the correct
operating frequency. The voltage variable capacitor is then used to lock the frequency of the VCO using the control voltage
(VCTRL) output from the loop filter.
The coarse tune calibration value is determined when the device is enabled.
2 4 8 16 32 64
C C C C C C C
L
Vctrl
Figure 2. Voltage Controlled Oscillator
It is important that the correct fixed capacitance is selected to ensure that the voltage control can cover the required range. For
example, Figure 3 shows the tuning curves for a number of fixed capacitance values around a VCO frequency of 3400MHz.
N+4
N+3
N+2
N+1
VCO frequency (MHz)
3420
N
3410
N-1
3400
N-2
3390
N-3
3380
Vnom
0.5 VCTRL range
1.0
VCO tuning voltage (V)
1.5
Figure 3. VCO Tuning Curves and CT_CAL Strategy
A number of tuning curves can be used to lock the phase-locked loop (PLL). The internal algorithm selects the curve that locks
with a VCTRL closest to VNOM, in this case curve N. It is possible to change the nominal lock voltage by programming the coarse
tune values in the CT_CAL1 and CT_CAL2 registers. The recommended coarse tune value is p1/p2ctv = h0C.
Coarse tune calibration can be disabled by clearing the cten bits in the CT_CAL1 and CT_CAL2 registers. If this is done, the
user must program a suitable coarse tune value into the ctdef bits in the CT_CAL1 and CT_CAL2 registers otherwise the VCO
will not be able to lock.
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Automatic Calibration Schemes for the the RFFC207x/507x Series
VCO tuning sensitivity calibration (KV_CAL)
When calculating loop filter components, a number of assumptions are made regarding the phase detector gain (, A/deg),
divider ratio (N), and VCO gain (KV, MHz/V) in order to determine the required capacitor and resistor values. It is usually acceptable to take the default values for  and KV and a nominal value for N to do the calculation, since loop bandwidth accuracy is
not critical in many applications. However, where it is critical, a calibration method has been included in the chips to correct for
variation in KV. Figure 4 shows the tuning curves in the vicinity of 3400MHz.
N+4
N+3
N+2
N+1
VCO frequency (MHz)
3420
N
3410
N-1
3400
ΔV
Δf
N-2
3390
N-3
3380
0.5 VCTRL range
1.0
VCO tuning voltage (V)
1.5
Figure 4. VCO Tuning Curves and KV_CAL Strategy
The KV calibration is performed by changing the frequency of the VCO and measuring the difference in VCO tuning voltage, as
shown in Figure 4. The measured voltage is then used to modify the charge pump current to correct the loop bandwidth. The
following shows how this can be achieved.
The PLL loop gain (and therefore loop bandwidth) is G ICP * KV/N where ICP is the charge pump current, KV is the VCO gain
and N is the divider ratio, as shown in Figure 5. The ICP can be used to compensate for changes in KV to keep G (and therefore
the loop bandwidth) constant.
Figure 5. Simplified Phase Locked Loop (PLL) Block Diagram
The internal calibration routine uses a frequency step programmed into the dn and sgn bits of the PLL_CAL registers. The dn
value will be added to, or subtracted from (based on the value of sgn), the fractional part of the frequency programming word.
To calculate the required frequency shift, first determine the approximate range of VCO gains that are likely to occur. The total
spread in VCO gain is approximately 12-45MHz/V (nominal: 23MHz/V). However if the VCO frequency range is restricted, a narrower estimate can be made. Figure 6 shows the minimum and maximum VCO gain versus frequency of the three VCOs.
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Automatic Calibration Schemes for the the RFFC207x/507x Series
K V Frequency (1/mV)
KV Min. and Max. versus Frequency
VCO Frequency (MHz)
Figure 6. VCO Gain versus Frequency
To determine the optimum register settings, first determine the minimum VCO gain (KV) value, KVmin.
To achieve the best phase noise the maximum charge pump current should be used (189A).
To calculate the desired frequency shift take the minimum VCO gain and multiply it by 0.363V (the maximum voltage that is
used to determine the VCO gain), for example: f < 0.363*KVmin.
If a wide operating temperature range is desired the value of KVmin should be reduced approximately 10% to allow for variation
of KVmin with temperature.
The loop filter components should be calculated based upon the average (geometric mean of minimum and maximum values)
charge pump current and divider ratio to center the design correctly.
If the VCO frequency range is large the frequency shift can be modified to correct for the variation of N. In this case, the minimum value of KV/N should be used to determine f. Figure 7 illustrates the typical variation of KV/N with frequency.
K V Frequency (1/mV)
Normalized KV Range versus Frequency
VCO Frequency (MHz)
Figure 7. Normalized VCO Gain versus Frequency
As shown in Figure 7, the minimum value of KV/N occurs near fNOM = 4450MHz. The value of KVmin is determined at this frequency (see Figure 6), and fNOM is determined from the equation above. The value of f used for dn is then set at:
f = fNOM*fVCO/fNOM.
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7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
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