RENESAS PD46365084BF1-E33-EQ1-A

Datasheet
μPD46365084B
μPD46365094B
μPD46365184B
μPD46365364B
36M-BIT QDRTM II SRAM
4-WORD BURST OPERATION
R10DS0090EJ0400
Rev.4.00
Nov 09 2012
Description
The μPD46365084B is a 4,194,304-word by 8-bit, the μPD46365094B is a 4,194,304-word by 9-bit, the
μPD46365184B is a 2,097,152-word by 18-bit and the μPD46365364B is a 1,048,576-word by 36-bit
synchronous quad data rate static RAM fabricated with advanced CMOS technology using full CMOS sixtransistor memory cell.
The μPD46365084B, μPD46365094B, μPD46365184B and μPD46365364B integrate unique synchronous
peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (K and K#) are
latched on the positive edge of K and K#. These products are suitable for application which require
synchronous operation, high speed, low voltage, high density and wide bit configuration.
These products are packaged in 165-pin PLASTIC BGA.
Features
• 1.8 ± 0.1 V power supply
• 165-pin PLASTIC BGA (13 x 15)
• HSTL interface
• PLL circuitry for wide output data valid window and future frequency scaling
• Separate independent read and write data ports with concurrent transactions
• 100% bus utilization DDR READ and WRITE operation
• Four-tick burst for reduced address frequency
• Two input clocks (K and K#) for precise DDR timing at clock rising edges only
• Two output clocks (C and C#) for precise flight time
and clock skew matching-clock and data delivered together to receiving device
• Internally self-timed write control
• Clock-stop capability. Normal operation is restored in 20 μs after clock is resumed.
• User programmable impedance output (35 to 70 Ω)
• Fast clock cycle time : 3.3 ns (300 MHz) , 4.0 ns (250 MHz)
• Simple control logic for easy depth expansion
• JTAG 1149.1 compatible test access port
R10DS0090EJ0400 Rev.4.00
Nov 09, 2012
Page 1 of 38
μPD46365084B, μPD46365094B, μPD46365184B, μPD46365364B
Ordering Information
Part No.
μPD46365084BF1-E33-EQ1-A
μPD46365084BF1-E40-EQ1-A
μPD46365094BF1-E33-EQ1-A
μPD46365094BF1-E40-EQ1-A
μPD46365184BF1-E33-EQ1-A
μPD46365184BF1-E40-EQ1-A
μPD46365364BF1-E33-EQ1-A
μPD46365364BF1-E40-EQ1-A
μPD46365084BF1-E33Y-EQ1-A
μPD46365084BF1-E40Y-EQ1-A
μPD46365094BF1-E33Y-EQ1-A
μPD46365094BF1-E40Y-EQ1-A
μPD46365184BF1-E33Y-EQ1-A
μPD46365184BF1-E40Y-EQ1-A
μPD46365364BF1-E33Y-EQ1-A
μPD46365364BF1-E40Y-EQ1-A
μPD46365084BF1-E33-EQ1
μPD46365084BF1-E40-EQ1
μPD46365094BF1-E33-EQ1
μPD46365094BF1-E40-EQ1
μPD46365184BF1-E33-EQ1
μPD46365184BF1-E40-EQ1
μPD46365364BF1-E33-EQ1
μPD46365364BF1-E40-EQ1
μPD46365084BF1-E33Y-EQ1
μPD46365084BF1-E40Y-EQ1
μPD46365094BF1-E33Y-EQ1
μPD46365094BF1-E40Y-EQ1
μPD46365184BF1-E33Y-EQ1
μPD46365184BF1-E40Y-EQ1
μPD46365364BF1-E33Y-EQ1
μPD46365364BF1-E40Y-EQ1
R10DS0090EJ0400 Rev.4.00
Nov 09, 2012
Operating
Ambient
Temperature
TA = 0 to 70°C
Organization
(word x bit)
Cycle
time
Clock
frequency
Core
Supply
Voltage
4M x 8
3.3ns
300MHz
1.8 ± 0.1 V
4.0ns
250MHz
4M x 9
3.3ns
300MHz
BGA
4.0ns
250MHz
(13 x 15)
3.3ns
300MHz
Lead-free
4.0ns
250MHz
2M x 18
1M x 36
4M x 8
4M x 9
2M x 18
1M x 36
3.3ns
300MHz
4.0ns
250MHz
3.3ns
300MHz
4.0ns
250MHz
3.3ns
300MHz
4.0ns
250MHz
3.3ns
300MHz
4.0ns
250MHz
3.3ns
300MHz
Package
165-pin
PLASTIC
1.8 ± 0.1 V
TA = −40 to 85°C
1.8 ± 0.1 V
TA = 0 to 70°C
4.0ns
250MHz
4M x 8
3.3ns
300MHz
4.0ns
250MHz
4M x 9
3.3ns
300MHz
BGA
4.0ns
250MHz
(13 x 15)
Lead
2M x 18
1M x 36
4M x 8
4M x 9
2M x 18
1M x 36
3.3ns
300MHz
4.0ns
250MHz
3.3ns
300MHz
4.0ns
250MHz
3.3ns
300MHz
4.0ns
250MHz
3.3ns
300MHz
4.0ns
250MHz
3.3ns
300MHz
4.0ns
250MHz
3.3ns
300MHz
4.0ns
250MHz
165-pin
PLASTIC
1.8 ± 0.1 V
TA = −40 to 85°C
Page 2 of 38
μPD46365084B, μPD46365094B, μPD46365184B, μPD46365364B
Pin Arrangement
165-pin PLASTIC BGA (13 x 15)
(Top View)
[μPD46365084B]
4M x 8
1
2
3
4
5
6
7
8
9
10
11
A
CQ#
VSS/72M
A
W#
NW1#
K#
NC/144M
R#
A
A
CQ
B
NC
NC
NC
A
NC/288M
K
NW0#
A
NC
NC
Q3
C
NC
NC
NC
VSS
A
NC
A
VSS
NC
NC
D3
D
NC
D4
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
E
NC
NC
Q4
VDDQ
VSS
VSS
VSS
VDDQ
NC
D2
Q2
F
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
G
NC
D5
Q5
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
H
DLL#
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
Q1
D1
K
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
L
NC
Q6
D6
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
Q0
M
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
D0
N
NC
D7
NC
VSS
A
A
A
VSS
NC
NC
NC
P
NC
NC
Q7
A
A
C
A
A
NC
NC
NC
R
TDO
TCK
A
A
A
C#
A
A
A
TMS
TDI
A
D0 to D7
Q0 to Q7
R#
W#
NW0#, NW1#
K, K#
C, C#
CQ, CQ#
ZQ
DLL#
: Address inputs
: Data inputs
: Data outputs
: Read input
: Write input
: Nibble Write data select
: Input clock
: Output clock
: Echo clock
: Output impedance matching
: PLL disable
TMS
TDI
TCK
TDO
VREF
VDD
VDDQ
VSS
NC
NC/xxM
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
: No connection
: Expansion address for xxMb
Remarks 1. ×××# indicates active LOW.
2. Refer to Package Dimensions for the index mark.
3. 2A, 7A and 5B are expansion addresses : 2A for 72Mb
: 2A and 7A for 144Mb
: 2A, 7A and 5B for 288Mb.
2A of this product can also be used as NC.
R10DS0090EJ0400 Rev.4.00
Nov 09, 2012
Page 3 of 38
μPD46365084B, μPD46365094B, μPD46365184B, μPD46365364B
Pin Arrangement
165-pin PLASTIC BGA (13 x 15)
(Top View)
[μPD46365094B]
4M x 9
1
2
3
4
5
6
7
8
9
10
11
A
CQ#
VSS/72M
A
W#
NC
K#
NC/144M
R#
A
A
CQ
B
NC
NC
NC
A
NC/288M
K
BW0#
A
NC
NC
Q4
C
NC
NC
NC
VSS
A
NC
A
VSS
NC
NC
D4
D
NC
D5
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
E
NC
NC
Q5
VDDQ
VSS
VSS
VSS
VDDQ
NC
D3
Q3
F
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
G
NC
D6
Q6
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
H
DLL#
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
Q2
D2
K
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
L
NC
Q7
D7
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
Q1
M
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
D1
N
NC
D8
NC
VSS
A
A
A
VSS
NC
NC
NC
P
NC
NC
Q8
A
A
C
A
A
NC
D0
Q0
R
TDO
TCK
A
A
A
C#
A
A
A
TMS
TDI
A
D0 to D8
Q0 to Q8
R#
W#
BW0#
K, K#
C, C#
CQ, CQ#
ZQ
DLL#
: Address inputs
: Data inputs
: Data outputs
: Read input
: Write input
: Byte Write data select
: Input clock
: Output clock
: Echo clock
: Output impedance matching
: PLL disable
TMS
TDI
TCK
TDO
VREF
VDD
VDDQ
VSS
NC
NC/xxM
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
: No connection
: Expansion address for xxMb
Remarks 1. ×××# indicates active LOW.
2. Refer to Package Dimensions for the index mark.
3. 2A, 7A and 5B are expansion addresses : 2A for 72Mb
: 2A and 7A for 144Mb
: 2A, 7A and 5B for 288Mb
2A of this product can also be used as NC.
R10DS0090EJ0400 Rev.4.00
Nov 09, 2012
Page 4 of 38
μPD46365084B, μPD46365094B, μPD46365184B, μPD46365364B
Pin Arrangement
165-pin PLASTIC BGA (13 x 15)
(Top View)
[μPD46365184B]
2M x 18
1
2
3
4
5
6
7
8
9
10
11
A
CQ#
VSS/144M
A
W#
BW1#
K#
NC/288M
R#
A
VSS/72M
CQ
B
NC
Q9
D9
A
NC
K
BW0#
A
NC
NC
Q8
C
NC
NC
D10
VSS
A
NC
A
VSS
NC
Q7
D8
D
NC
D11
Q10
VSS
VSS
VSS
VSS
VSS
NC
NC
D7
E
NC
NC
Q11
VDDQ
VSS
VSS
VSS
VDDQ
NC
D6
Q6
F
NC
Q12
D12
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
Q5
G
NC
D13
Q13
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
D5
H
DLL#
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
D14
VDDQ
VDD
VSS
VDD
VDDQ
NC
Q4
D4
K
NC
NC
Q14
VDDQ
VDD
VSS
VDD
VDDQ
NC
D3
Q3
L
NC
Q15
D15
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
Q2
M
NC
NC
D16
VSS
VSS
VSS
VSS
VSS
NC
Q1
D2
N
NC
D17
Q16
VSS
A
A
A
VSS
NC
NC
D1
P
NC
NC
Q17
A
A
C
A
A
NC
D0
Q0
R
TDO
TCK
A
A
A
C#
A
A
A
TMS
TDI
A
D0 to D17
Q0 to Q17
R#
W#
BW0#, BW1#
K, K#
C, C#
CQ, CQ#
ZQ
DLL#
: Address inputs
: Data inputs
: Data outputs
: Read input
: Write input
: Byte Write data select
: Input clock
: Output clock
: Echo clock
: Output impedance matching
: PLL disable
TMS
TDI
TCK
TDO
VREF
VDD
VDDQ
VSS
NC
NC/xxM
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
: No connection
: Expansion address for xxMb
Remarks 1. ×××# indicates active LOW.
2. Refer to Package Dimensions for the index mark.
3. 2A, 7A and 10A are expansion addresses
: 10A for 72Mb
: 10A and 2A for 144Mb
: 10A, 2A and 7A for 288Mb
2A and 10A of this product can also be used as NC.
R10DS0090EJ0400 Rev.4.00
Nov 09, 2012
Page 5 of 38
μPD46365084B, μPD46365094B, μPD46365184B, μPD46365364B
Pin Arrangement
165-pin PLASTIC BGA (13 x 15)
(Top View)
[μPD46365364B]
1M x 36
1
2
3
4
5
6
7
8
9
10
11
W#
BW2#
K#
BW1#
R#
A
VSS/144M
CQ
A
CQ#
B
Q27
Q18
D18
A
BW3#
K
BW0#
A
D17
Q17
Q8
C
D27
Q28
D19
VSS
A
NC
A
VSS
D16
Q7
D8
D
D28
D20
Q19
VSS
VSS
VSS
VSS
VSS
Q16
D15
D7
E
Q29
D29
Q20
VDDQ
VSS
VSS
VSS
VDDQ
Q15
D6
Q6
F
Q30
Q21
D21
VDDQ
VDD
VSS
VDD
VDDQ
D14
Q14
Q5
G
D30
D22
Q22
VDDQ
VDD
VSS
VDD
VDDQ
Q13
D13
D5
H
DLL#
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
D31
Q31
D23
VDDQ
VDD
VSS
VDD
VDDQ
D12
Q4
D4
K
Q32
D32
Q23
VDDQ
VDD
VSS
VDD
VDDQ
Q12
D3
Q3
L
Q33
Q24
D24
VDDQ
VSS
VSS
VSS
VDDQ
D11
Q11
Q2
M
D33
Q34
D25
VSS
VSS
VSS
VSS
VSS
D10
Q1
D2
N
D34
D26
Q25
VSS
A
A
A
VSS
Q10
D9
D1
P
Q35
D35
Q26
A
A
C
A
A
Q9
D0
Q0
R
TDO
TCK
A
A
A
C#
A
A
A
TMS
TDI
VSS/288M NC/72M
A
D0 to D35
Q0 to Q35
R#
W#
BW0# to BW3#
K, K#
C, C#
CQ, CQ#
ZQ
DLL#
: Address inputs
: Data inputs
: Data outputs
: Read input
: Write input
: Byte Write data select
: Input clock
: Output clock
: Echo clock
: Output impedance matching
: PLL disable
TMS
TDI
TCK
TDO
VREF
VDD
VDDQ
VSS
NC
NC/xxM
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
: No connection
: Expansion address for xxMb
Remarks 1. ×××# indicates active LOW.
2. Refer to Package Dimensions for the index mark.
3. 2A, 3A and 10A are expansion addresses : 3A for 72Mb
: 3A and 10A for 144Mb
: 3A, 10A and 2A for 288Mb
2A and 10A of this product can also be used as NC.
R10DS0090EJ0400 Rev.4.00
Nov 09, 2012
Page 6 of 38
μPD46365084B, μPD46365094B, μPD46365184B, μPD46365364B
Pin Description
(1/2)
Symbol
Type
A
Input
D0 to Dxx
Input
Q0 to Qxx
Output
R#
Input
W#
Input
BWx#
NWx#
Input
K, K#
Input
C, C#
Input
Description
Synchronous Address Inputs: These inputs are registered and must meet the setup and
hold times around the rising edge of K. All transactions operate on a burst of four words
(two clock periods of bus activity). These inputs are ignored when device is deselected,
i.e., NOP (R# = W# = HIGH).
Synchronous Data Inputs: Input data must meet setup and hold times around the rising
edges of K and K# during WRITE operations. See Pin Arrangement for ball site location
of individual signals.
x8 device uses D0 to D7.
x9 device uses D0 to D8.
x18 device uses D0 to D17.
x36 device uses D0 to D35.
Synchronous Data Outputs: Output data is synchronized to the respective C and C# or to
K and K# rising edges if C and C# are tied HIGH. Data is output in synchronization with C
and C# (or K and K#), depending on the R# command. See Pin Arrangement for ball site
location of individual signals.
x8 device uses Q0 to Q7.
x9 device uses Q0 to Q8.
x18 device uses Q0 to Q17.
x36 device uses Q0 to Q35.
Synchronous Read: When LOW this input causes the address inputs to be registered and
a READ cycle to be initiated. This input must meet setup and hold times around the rising
edge of K. If a READ command (R# = LOW) is input, an input of R# on the subsequent
rising edge of K is ignored.
Synchronous Write: When LOW this input causes the address inputs to be registered and
a WRITE cycle to be initiated. This input must meet setup and hold times around the rising
edge of K. If a WRITE command (W# = LOW) is input, an input of W# on the subsequent
rising edge of K is ignored.
Synchronous Byte Writes (Nibble Writes on x8): When LOW these inputs cause their
respective byte or nibble to be registered and written during WRITE cycles. These signals
must meet setup and hold times around the rising edges of K and K# for each of the two
rising edges comprising the WRITE cycle. See Pin Arrangement for signal to data
relationships.
x8 device uses NW0#, NW1#.
x9 device uses BW0#.
x18 device uses BW0#, BW1#.
x36 device uses BW0# to BW3#.
See Byte Write Operation for relation between BWx#, NWx# and Dxx.
Input Clock: This input clock pair registers address and control inputs on the rising edge of
K, and registers data on the rising edge of K and the rising edge of K#. K# is ideally 180
degrees out of phase with K. All synchronous inputs must meet setup and hold times
around the clock rising edges.
Output Clock: This clock pair provides a user controlled means of tuning device output
data. The rising edge of C# is used as the output timing reference for first and third output
data. The rising edge of C is used as the output reference for second and fourth output
data. Ideally, C# is 180 degrees out of phase with C. When use of K and K# as the
reference instead of C and C#, then fixed C and C# to HIGH. Operation cannot be
guaranteed unless C and C# are fixed to HIGH (i.e. toggle of C and C#).
R10DS0090EJ0400 Rev.4.00
Nov 09, 2012
Page 7 of 38
μPD46365084B, μPD46365094B, μPD46365184B, μPD46365364B
(2/2)
Symbol
Type
Description
CQ, CQ#
Output
ZQ
Input
DLL#
Input
TMS
TDI
TCK
Input
TDO
Output
VREF
−
VDD
Supply
VDDQ
Supply
VSS
Supply
Power Supply: Ground
NC
−
No Connect: These signals are not connected internally.
Input
Synchronous Echo Clock Outputs. The rising edges of these outputs are tightly matched
to the synchronous data outputs and can be used as a data valid indication. These signals
run freely and do not stop when Q tristates. If C and C# are stopped (if K and K# are
stopped in the single clock mode), CQ and CQ# will also stop.
Output Impedance Matching Input: This input is used to tune the device outputs to the
system data bus impedance. Q, CQ and CQ# output impedance are set to 0.2 x RQ,
where RQ is a resistor from this bump to ground. The output impedance can be minimized
by directly connect ZQ to VDDQ. This pin cannot be connected directly to GND or left
unconnected. The output impedance is adjusted every 20 μs upon power-up to account
for drifts in supply voltage and temperature. After replacement for a resistor, the new
output impedance is reset by implementing power-on sequence.
PLL Disable: When debugging the system or board, the operation can be performed at a
clock frequency slower than TKHKH (MAX.) without the PLL circuit being used, if DLL# =
LOW. The AC/DC characteristics cannot be guaranteed. For normal operation, DLL#
must be HIGH and it can be connected to VDDQ through a 10 kΩ or less resistor.
IEEE 1149.1 Test Inputs: 1.8 V I/O level. These balls may be left Not Connected if the
JTAG function is not used in the circuit.
IEEE 1149.1 Clock Input: 1.8 V I/O level. This pin must be tied to VSS if the JTAG function
is not used in the circuit.
IEEE 1149.1 Test Output: 1.8 V I/O level.
When providing any external voltage to TDO signal, it is recommended to pull up to VDD.
HSTL Input Reference Voltage: Nominally VDDQ /2. Provides a reference voltage for the
input buffers.
Power Supply: 1.8 V nominal. See Recommended DC Operating Conditions and DC
Characteristics for range.
Power Supply: Isolated Output Buffer Supply. Nominally 1.5 V. 1.8 V is also permissible. See
Recommended DC Operating Conditions and DC Characteristics for range.
R10DS0090EJ0400 Rev.4.00
Nov 09, 2012
Page 8 of 38
μPD46365084B, μPD46365094B, μPD46365184B, μPD46365364B
Block Diagram
[μPD46365084B]
20
ADDRESS
R#
ADDRESS
W#
20
REGISTRY
& LOGIC
K
W#
MUX
NW0#
MEMORY
ARRAY
16
OUTPUT
BUFFER
16
32
OUTPUT
SELECT
& LOGIC
OUTPUT
REGISTER
REGISTRY
R#
2 x 32
SENSE
AMPS
D0 to D7
20
WRITE
DRIVER
DATA
8
WRITE
REGISTER
NW1#
8
16
16
Q0 to Q7
2
CQ,
CQ#
MUX
K
K
K#
K
C, C#
OR
K, K#
[μPD46365094B]
20
ADDRESS
R#
ADDRESS
W#
20
REGISTRY
& LOGIC
K
W#
MUX
BW0#
MEMORY
ARRAY
18
OUTPUT
BUFFER
18
36
OUTPUT
SELECT
& LOGIC
OUTPUT
REGISTER
REGISTRY
2 x 36
SENSE
AMPS
R#
20
WRITE
DRIVER
D0 to D8
WRITE
REGISTER
9
DATA
9
18
18
Q0 to Q8
2
CQ,
CQ#
MUX
K
K#
R10DS0090EJ0400 Rev.4.00
Nov 09, 2012
K
K
C, C#
OR
K, K#
Page 9 of 38
μPD46365084B, μPD46365094B, μPD46365184B, μPD46365364B
[μPD46365184B]
19
ADDRESS
R#
ADDRESS
W#
19
REGISTRY
& LOGIC
K
W#
MUX
BW0#
36
36
ARRAY
36
OUTPUT
BUFFER
36
72
OUTPUT
SELECT
& LOGIC
R#
MEMORY
18
OUTPUT
REGISTER
REGISTRY
2 x 72
SENSE
AMPS
D0 to D17
19
WRITE
DRIVER
18
DATA
WRITE
REGISTER
BW1#
Q0 to Q17
2
CQ,
CQ#
MUX
K
K
K#
K
C, C#
OR
K, K#
[μPD46365364B]
18
ADDRESS
R#
ADDRESS
W#
18
REGISTRY
& LOGIC
K
W#
MUX
ARRAY
72
OUTPUT
BUFFER
R#
MEMORY
36
144
OUTPUT
SELECT
72
2 x 144
SENSE
AMPS
& LOGIC
18
WRITE
DRIVER
REGISTRY
WRITE
REGISTER
DATA
36
D0 to D35
72
72
OUTPUT
REGISTER
BW0#
BW1#
BW2#
BW3#
Q0 to Q35
2
CQ,
CQ#
MUX
K
K#
R10DS0090EJ0400 Rev.4.00
Nov 09, 2012
K
K
C, C#
OR
K, K#
Page 10 of 38
μPD46365084B, μPD46365094B, μPD46365184B, μPD46365364B
Power-On Sequence in QDR II SRAM
QDR II SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
The following timing charts show the recommended power-on sequence.
The following power-up supply voltage application is recommended: VSS, VDD, VDDQ, VREF, then VIN. VDD and VDDQ
can be applied simultaneously, as long as VDDQ does not exceed VDD by more than 0.5 V during power-up. The
following power-down supply voltage removal sequence is recommended: VIN, VREF, VDDQ, VDD, VSS. VDD and VDDQ
can be removed simultaneously, as long as VDDQ does not exceed VDD by more than 0.5 V during power-down.
Power-On Sequence
Apply power and tie DLL# to HIGH.
Apply VDDQ before VREF or at the same time as VREF.
Provide stable clock for more than 20 μs to lock the PLL.
Continuous min.4 NOP(R# = high) cycles are required after PLL lock up is done.
PLL Constraints
The PLL uses K clock as its synchronizing input and the input should have low phase jitter which is specified as
TKC var. The PLL can cover 120 MHz as the lowest frequency. If the input clock is unstable and the PLL is
enabled, then the PLL may lock onto an undesired clock frequency.
Power-On Waveforms
VDD/VDDQ
VDD/VDDQ Stable (< ±0.1 V DC per 50 ns)
DLL#
Fix HIGH (or tied to VDDQ)
Clock
Unstable Clock
20 μs or more
Stable Clock
4 Times NOP
Normal Operation
Start
R#
R10DS0090EJ0400 Rev.4.00
Nov 09, 2012
Page 11 of 38
μPD46365084B, μPD46365094B, μPD46365184B, μPD46365364B
Truth Table
Operation
WRITE cycle
CLK
R#
W#
L→H
H
L
D or Q
Data in
Load address, input write data on
Input data
DA(A+0) DA(A+1) DA(A+2) DA(A+3)
consecutive K and K# rising edge
Input clock
K(t+1) ↑ K#(t+1) ↑ K(t+2) ↑ K#(t+2) ↑
READ cycle
L→H
L
×
Data out
Load address, read data on
Output data QA(A+0) QA(A+1) QA(A+2) QA(A+3)
consecutive C and C# rising edge
Output clock C#(t+1) ↑ C(t+2) ↑ C#(t+2) ↑ C(t+3) ↑
NOP (No operation)
Clock stop
L→H
H
H
D = ×, Q = High-Z
Stopped
×
×
Previous state
Remarks 1. H : HIGH, L : LOW, × : don’t care, ↑ : rising edge.
2. Data inputs are registered at K and K# rising edges. Data outputs are delivered at C and C# rising edges
except if C and C# are HIGH then data outputs are delivered at K and K# rising edges.
3. All control inputs in the truth table must meet setup/hold times around the rising edge (LOW to HIGH) of
K. All control inputs are registered during the rising edge of K.
4. This device contains circuitry that ensure the outputs to be in high impedance during power-up.
5. Refer to state diagram and timing diagrams for clarification.
6. It is recommended that K = K# = C = C# when clock is stopped. This is not essential but permits most
rapid restart by overcoming transmission line charging symmetrically.
7. If R# was LOW to initiate the previous cycle, this signal becomes a don't care for this WRITE operation
however it is strongly recommended that this signal is brought HIGH as shown in the truth table.
8. W# during write cycle and R# during read cycle were HIGH on previous K clock rising edge. Initiating
consecutive READ or WRITE operations on consecutive K clock rising edges is not permitted. The
device will ignore the second request.
R10DS0090EJ0400 Rev.4.00
Nov 09, 2012
Page 12 of 38
μPD46365084B, μPD46365094B, μPD46365184B, μPD46365364B
Byte Write Operation
[μPD46365084B]
Operation
K#
NW0#
NW1#
L→H
−
0
0
−
L→H
0
0
L→H
−
0
1
−
L→H
0
1
Write D4 to D7
L→H
−
1
0
−
L→H
1
0
Write nothing
L→H
−
1
1
−
L→H
1
1
Write D0 to D7
Write D0 to D3
K
Remarks 1. H : HIGH, L : LOW, → : rising edge.
2. Assumes a WRITE cycle was initiated. NW0# and NW1# can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
[μPD46365094B]
Operation
Write D0 to D8
Write nothing
K
K#
BW0#
L→H
−
0
−
L→H
0
L→H
−
1
−
L→H
1
Remarks 1. H : HIGH, L : LOW, → : rising edge.
2. Assumes a WRITE cycle was initiated. BW0# can be altered for any portion of the BURST WRITE
operation provided that the setup and hold requirements are satisfied.
[μPD46365184B]
Operation
K#
BW0#
BW1#
L→H
−
0
0
−
L→H
0
0
L→H
−
0
1
−
L→H
0
1
Write D9 to D17
L→H
−
1
0
−
L→H
1
0
Write nothing
L→H
−
1
1
−
L→H
1
1
Write D0 to D17
Write D0 to D8
K
Remarks 1. H : HIGH, L : LOW, → : rising edge.
2. Assumes a WRITE cycle was initiated. BW0# and BW1# can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
R10DS0090EJ0400 Rev.4.00
Nov 09, 2012
Page 13 of 38
μPD46365084B, μPD46365094B, μPD46365184B, μPD46365364B
[μPD46365364B]
Operation
K#
BW0#
BW1#
BW2#
BW3#
L→H
−
0
0
0
0
−
L→H
0
0
0
0
Write D0 to D8
L→H
−
0
1
1
1
−
L→H
0
1
1
1
Write D9 to D17
L→H
−
1
0
1
1
−
L→H
1
0
1
1
Write D18 to D26
L→H
−
1
1
0
1
−
L→H
1
1
0
1
Write D27 to D35
L→H
−
1
1
1
0
−
L→H
1
1
1
0
Write nothing
L→H
−
1
1
1
1
−
L→H
1
1
1
1
Write D0 to D35
K
Remarks 1. H : HIGH, L : LOW, → : rising edge.
2. Assumes a WRITE cycle was initiated. BW0# to BW3# can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
R10DS0090EJ0400 Rev.4.00
Nov 09, 2012
Page 14 of 38
μPD46365084B, μPD46365094B, μPD46365184B, μPD46365364B
Bus Cycle State Diagram
LOAD NEW
READ ADDRESS;
R_Count = 0;
R_Init = 1
LOAD NEW
WRITE ADDRESS;
W_Count = 0
Always
W# = LOW & W_Count = 4
R# = LOW & R_Count = 4
WRITE DOUBLE;
W_Count = W_Count+2
W# = LOW
R_Init = 0
Always
READ DOUBLE;
R_Count = R_Count+2
R# = HIGH
& R_Count = 4
W_Count = 2
Always
R_Count = 2
Always
R# = LOW
INCREMENT WRITE
ADDRESS BY TWO
W# = HIGH
& W_Count = 4
INCREMENT READ
ADDRESS BY TWO
R_Init = 0
R# = HIGH
W# = HIGH
WRITE PORT NOP
Power UP
Supply voltage
provided
Supply voltage
provided
READ PORT NOP
R_Init = 0
Remarks 1. The address is concatenated with two additional internal LSBs to facilitate burst operation.
The address order is always fixed as: xxx...xxx+0, xxx...xxx+1, xxx...xxx+2, xxx...xxx+3.
Bus cycle is terminated at the end of this sequence (burst count = 4).
2. Read and write state machines can be active simultaneously.
Read and write cannot be simultaneously initiated. Read takes precedence.
3. State machine control timing is controlled by K.
R10DS0090EJ0400 Rev.4.00
Nov 09, 2012
Page 15 of 38
μPD46365084B, μPD46365094B, μPD46365184B, μPD46365364B
Electrical Characteristics
Absolute Maximum Ratings
Parameter
Rating
Unit
VDD
−0.5 to +2.5
V
VDDQ
−0.5 to VDD
V
Input voltage
VIN
−0.5 to VDD+0.5 (2.5 V MAX.)
V
Input / Output voltage
VI/O
−0.5 to VDDQ+0.5 (2.5 V MAX.)
V
Operating ambient temperature
TA
(E** series)
0 to 70
°C
(E**Y series)
-40 to 85
°C
−55 to +125
°C
Supply voltage
Output supply voltage
Storage temperature
Symbol
Conditions
Tstg
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (TA = 0 to 70°C, TA = −40 to 85°C)
Parameter
MIN.
TYP.
MAX.
Unit
VDD
1.7
1.8
1.9
V
Output supply voltage
VDDQ
1.4
VDD
V
1
Input HIGH voltage
VIH (DC)
VREF +0.1
VDDQ+0.3
V
1, 2
Input LOW voltage
VIL (DC)
−0.3
VREF −0.1
V
1, 2
Clock input voltage
VIN
−0.3
VDDQ+0.3
V
1, 2
Reference voltage
VREF
0.68
0.95
V
Supply voltage
Symbol
Conditions
Note
Notes 1. During normal operation, VDDQ must not exceed VDD.
2. Power-up: VIH ≤ VDDQ+0.3 V and VDD ≤ 1.7 V and VDDQ ≤ 1.4 V for t ≤ 200 ms
Recommended AC Operating Conditions (TA = 0 to 70°C, TA = −40 to 85°C)
Parameter
Symbol
Input HIGH voltage
VIH (AC)
Input LOW voltage
VIL (AC)
Conditions
MIN.
MAX.
VREF +0.2
VREF −0.2
Unit
Note
V
1
V
1
Note 1. Overshoot: VIH (AC) ≤ VDD + 0.7 V (2.5 V MAX.) for t ≤ TKHKH/2
Undershoot: VIL (AC) ≥ −0.5 V for t ≤ TKHKH/2
Control input signals may not have pulse widths less than TKHKL (MIN.) or operate at cycle rates less than
TKHKH (MIN.).
R10DS0090EJ0400 Rev.4.00
Nov 09, 2012
Page 16 of 38
μPD46365084B, μPD46365094B, μPD46365184B, μPD46365364B
DC Characteristics 1 (TA = 0 to 70°C, VDD = 1.8 ± 0.1 V)
Parameter
Symbol
Test condition
MIN.
MAX.
x8
x9
Unit
x18 x36
Input leakage current
ILI
−2
+2
μA
I/O leakage current
ILO
−2
+2
μA
Operating supply current
IDD
520 520 580 740
mA
(Read cycle / Write cycle)
VIN ≤ VIL or VIN ≥ VIH, -E33
II/O = 0 mA,.
Cycle = MAX.
Standby supply current
Note
ISB1
(NOP)
-E40
460 460 520 650
VIN ≤ VIL or VIN ≥ VIH, -E33
390 390 400 430
mA
II/O = 0 mA,.
Cycle = MAX.
-E40
370 370 380 400
Inputs static
Output HIGH voltage
VOH(Low)
VOH
Output LOW voltage
VOL(Low)
VOL
Notes 1.
2.
3.
4.
|IOH| ≤ 0.1 mA
Note1
IOL ≤ 0.1 mA
Note2
VDDQ − 0.2
VDDQ
V
3, 4
VDDQ/2−0.12
VDDQ/2+0.12
V
3, 4
VSS
0.2
V
3, 4
VDDQ/2−0.12
VDDQ/2+0.12
V
3, 4
Outputs are impedance-controlled. | IOH | = (VDDQ/2)/(RQ/5) ±15% for values of 175 Ω ≤ RQ ≤ 350 Ω.
Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) ±15% for values of 175 Ω ≤ RQ ≤ 350 Ω.
AC load current is higher than the shown DC values.
HSTL outputs meet JEDEC HSTL Class I standards.
R10DS0090EJ0400 Rev.4.00
Nov 09, 2012
Page 17 of 38
μPD46365084B, μPD46365094B, μPD46365184B, μPD46365364B
DC Characteristics 2 (TA = -40 to 85°C, VDD = 1.8 ± 0.1 V)
Parameter
Symbol
Test condition
MIN.
MAX.
x8
x9
Unit Note
x18 x36
Input leakage current
ILI
−2
+2
μA
I/O leakage current
ILO
−2
+2
μA
Operating supply current
IDD
(Read cycle / Write cycle)
Standby supply current
VIN ≤ VIL or VIN ≥ VIH,
-E33Y
640 640 710 870 mA
Cycle = MAX.
-E40Y
580 580 650 780
VIN ≤ VIL or VIN ≥ VIH,
-E33Y
510 510 520 550 mA
-E40Y
490 490 500 520
II/O = 0 mA,.
ISB1
(NOP)
II/O = 0 mA,.
Cycle = MAX.
Inputs static
Output HIGH voltage
VOH(Low)
VOH
Output LOW voltage
VOL(Low)
VOL
Notes 1.
2.
3.
4.
|IOH| ≤ 0.1 mA
Note1
IOL ≤ 0.1 mA
Note2
VDDQ − 0.2
VDDQ
V
3, 4
VDDQ/2−0.12
VDDQ/2+0.12
V
3, 4
VSS
0.2
V
3, 4
VDDQ/2−0.12
VDDQ/2+0.12
V
3, 4
Outputs are impedance-controlled. | IOH | = (VDDQ/2)/(RQ/5) ±15% for values of 175 Ω ≤ RQ ≤ 350 Ω.
Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) ±15% for values of 175 Ω ≤ RQ ≤ 350 Ω.
AC load current is higher than the shown DC values.
HSTL outputs meet JEDEC HSTL Class I standards.
R10DS0090EJ0400 Rev.4.00
Nov 09, 2012
Page 18 of 38
μPD46365084B, μPD46365094B, μPD46365184B, μPD46365364B
Capacitance (TA = 25°C, f = 1 MHz)
Parameter
Symbol
Test conditions
MIN.
MAX.
Unit
Input capacitance (Address, Control)
CIN
VIN = 0 V
5
pF
Input / Output capacitance
CI/O
VI/O = 0 V
7
pF
Cclk
Vclk = 0 V
6
pF
(D, Q, CQ, CQ#)
Clock Input capacitance
Remark These parameters are periodically sampled and not 100% tested.
Thermal Characteristics
Parameter
Thermal resistance
Symbol
θ ja
Substrate
4-layer
from junction to ambient air
8-layer
Thermal characterization parameter
Ψ jt
4-layer
from junction to the top center
of the package surface
Thermal resistance
8-layer
θ jc
Airflow
TYP.
Unit
0 m/s
16.5
°C/W
1 m/s
13.2
°C/W
0 m/s
15.5
°C/W
1 m/s
12.6
°C/W
0 m/s
0.07
°C/W
1 m/s
0.13
°C/W
0 m/s
0.06
°C/W
1 m/s
0.12
°C/W
3.86
°C/W
from junction to case
R10DS0090EJ0400 Rev.4.00
Nov 09, 2012
Page 19 of 38
μPD46365084B, μPD46365094B, μPD46365184B, μPD46365364B
AC Characteristics (TA = 0 to 70°C, TA = −40 to 85°C,VDD = 1.8 ± 0.1 V)
AC Test Conditions (VDD = 1.8 ± 0.1 V, VDDQ = 1.4 V to VDD)
Input waveform (Rise / Fall time ≤ 0.3 ns)
1.25 V
0.75 V
Test Points
0.75 V
0.25 V
Output waveform
Test Points
VDDQ / 2
VDDQ / 2
Output load condition
Figure 1. External load at test
VDDQ / 2
0.75 V
50 Ω
VREF
ZO = 50 Ω
SRAM
250 Ω
ZQ
R10DS0090EJ0400 Rev.4.00
Nov 09, 2012
Page 20 of 38
μPD46365084B, μPD46365094B, μPD46365184B, μPD46365364B
Read and Write Cycle
Parameter
Clock
Average Clock cycle time
(K, K#, C, C#)
Clock phase jitter (K, K#, C, C#)
Clock HIGH time (K, K#, C, C#)
Clock LOW time (K, K#, C, C#)
Clock HIGH to Clock# HIGH
(K → K#, C → C#)
Clock# HIGH to Clock HIGH
(K# → K, C# → C)
Clock to data clock
(K → C, K# → C#)
PLL lock time (K, C)
K static to PLL reset
Symbol
TKHKH
-E33,-E33Y
(300 MHz)
MIN.
MAX.
3.3
8.4
-E40,-E40Y
(250 MHz)
MIN.
MAX.
4.0
0.2
Unit
Note
8.4
ns
1
0.2
2
TKC var
TKHKL
TKLKH
TKHK#H
1.32
1.32
1.49
1.6
1.6
1.8
ns
ns
ns
ns
TK#HKH
1.49
1.8
ns
TKHCH
0
TKC lock
TKC reset
20
30
20
30
μs
ns
3
4
TCQHCQ#H
1.24
1.55
ns
5
TCQ#HCQH
1.24
1.55
ns
5
1.45
0
1.8
ns
Output Times
CQ HIGH to CQ# HIGH
(CQ → CQ#)
CQ# HIGH to CQ HIGH
(CQ# → CQ)
C, C# HIGH to output valid
C, C# HIGH to output hold
C, C# HIGH to echo clock valid
C, C# HIGH to echo clock hold
CQ, CQ# HIGH to output valid
CQ, CQ# HIGH to output hold
C HIGH to output High-Z
C HIGH to output Low-Z
Setup Times
Address valid to K rising edge
Control inputs (R#, W#) valid to
K rising edge
Data inputs and write data
select
inputs (BWx#, NWx#) valid to
K, K# rising edge
Hold Times
K rising edge to address hold
K rising edge to control inputs
(R#, W#) hold
K, K# rising edge to data inputs
and write data select inputs
(BWx#, NWx#) hold
R10DS0090EJ0400 Rev.4.00
Nov 09, 2012
TCHQV
TCHQX
TCHCQV
TCHCQX
TCQHQV
TCQHQX
TCHQZ
TCHQX1
0.45
–0.45
–0.45
ns
ns
ns
ns
ns
ns
ns
ns
TAVKH
TIVKH
0.4
0.4
0.5
0.5
ns
ns
7
7
TDVKH
0.3
0.35
ns
7
TKHAX
TKHIX
0.4
0.4
0.5
0.5
ns
ns
7
7
TKHDX
0.3
0.35
ns
7
–0.45
0.45
–0.45
0.45
–0.45
0.45
–0.45
0.27
–0.27
0.3
–0.3
0.45
0.45
6
6
Page 21 of 38
μPD46365084B, μPD46365094B, μPD46365184B, μPD46365364B
Notes 1. When debugging the system or board, these products can operate at a clock frequency slower than TKHKH
(MAX.) without the PLL circuit being used, if DLL# = LOW. Read latency (RL) is changed to 1.0 clock
cycle in this operation. The AC/DC characteristics cannot be guaranteed, however.
2. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. TKC var
(MAX.) indicates a peak-to-peak value.
3. VDD slew rate must be less than 0.1 V DC per 50 ns for PLL lock retention.
PLL lock time begins once VDD and input clock are stable.
It is recommended that the device is kept NOP (R# = W# = HIGH) during these cycles.
4. K input is monitored for this operation. See below for the timing.
K
TKC reset
or
K
TKC reset
5. Guaranteed by design.
6. Echo clock is very tightly controlled to data valid / data hold. By design, there is a ± 0.1 ns variation from
echo clock to data. The data sheet parameters reflect tester guardbands and test setup variations.
7. This is a synchronous device. All addresses, data and control lines must meet the specified setup
and hold times for all latching clock edges.
Remarks 1. This parameter is sampled.
2. Test conditions as specified with the output loading as shown in AC Test Conditions unless otherwise
noted.
3. Control input signals may not be operated with pulse widths less than TKHKL (MIN.).
4. If C, C# are tied HIGH, K, K# become the references for C, C# timing parameters.
5. VDDQ is 1.5 V DC.
R10DS0090EJ0400 Rev.4.00
Nov 09, 2012
Page 22 of 38
μPD46365084B, μPD46365094B, μPD46365184B, μPD46365364B
Read and Write Timing
1
2
WRITE
READ
WRITE
READ
NOP
3
4
5
NOP
6
7
K
TKHKL
TKLKH
TKHKH
TKHK#H TK#HKH
K#
R#
TKHIX
TIVKH
TKHIX
TIVKH
W#
A0
Address
A2
A1
TDVKH
TAVKH TKHAX
Data in
Data out
Qx2
Qx3
TCHQX1
A3
TKHDX
TDVKH TKHDX
D10
D11
D12
D13
D30
D31
Q00
Q01
Q02
Q03
Q20
Q21
TCHQX
D32
D33
Q22
Q23
TCQHQX
TCHQX
TCHQZ
TCHQV
TCQHQV
TCHQV
CQ
TCHCQX
TCHCQV
TCQHCQ#H TCQ#HCQH
CQ#
TKHCH
TCHCQX
TCHCQV
C
TKHKL
TKLKH
TKHKH
TKHK#H TK#HKH
TKHCH
C#
Remarks 1. Q00 refers to output from address A0+0.
Q01 refers to output from the next internal burst address following A0,i.e.,A0+1.
2. Outputs are disabled (high impedance) 3.5 clock cycles after the last READ (R# = LOW) is input in the
sequences of [READ]-[NOP]-[NOP], [READ]-[WRITE]-[NOP] and [READ]-[NOP]-[WRITE].
3. In this example, if address A2 = A1, data Q20 = D10, Q21 = D11, Q22 = D12 and Q23 = D13.
Write data is forwarded immediately as read results.
R10DS0090EJ0400 Rev.4.00
Nov 09, 2012
Page 23 of 38
μPD46365084B, μPD46365094B, μPD46365184B, μPD46365364B
Application Example
SRAM#1
D
Vt
SRAM
Controller
A
R#
ZQ
CQ#
CQ
Q
R=
250 Ω
D
ZQ
CQ#
CQ
Q
A
R# W# BWx# C/C# K/K#
...
SRAM#4
W# BWx# C/C# K/K#
R=
250 Ω
R
Data In
Data Out
R
Address
Vt
R
R#
Vt
W#
BW#
...
SRAM#1 CQ/CQ#
SRAM#4 CQ/CQ#
Vt
R
Vt
R
Source CLK/CLK#
Return CLK/CLK#
Vt
R
R = 50 Ω Vt = Vref
Remark AC Characteristics are defined at the condition of SRAM outputs, CQ, CQ# and Q with termination.
R10DS0090EJ0400 Rev.4.00
Nov 09, 2012
Page 24 of 38
μPD46365084B, μPD46365094B, μPD46365184B, μPD46365364B
JTAG Specification
These products support a limited set of JTAG functions as in IEEE standard 1149.1.
Test Access Port (TAP) Pins
Pin name
Pin assignments
Description
TCK
2R
TMS
10R
TDI
11R
Test Data Input. This is the input side of the serial registers placed between
TDI and TDO. The register placed between TDI and TDO is determined by the
state of the TAP controller state machine and the instruction that is currently
loaded in the TAP instruction.
TDO
1R
Test Data Output. This is the output side of the serial registers placed between
TDI and TDO. Output changes in response to the falling edge of TCK.
Test Clock Input. All input are captured on the rising edge of TCK and all
outputs propagate from the falling edge of TCK.
Test Mode Select. This is the command input for the TAP controller state
machine.
Remark The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held HIGH
for five rising edges of TCK. The TAP controller state is also reset on the SRAM POWER-UP.
JTAG DC Characteristics (TA = 0 to 70°C, VDD = 1.8 ± 0.1 V, unless otherwise noted)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
JTAG Input leakage current
ILI
0 V ≤ VIN ≤ VDD
−5.0
+5.0
μA
JTAG I/O leakage current
ILO
0 V ≤ VIN ≤ VDDQ,
−5.0
+5.0
μA
Outputs disabled
JTAG input HIGH voltage
VIH
1.3
VDD+0.3
V
JTAG input LOW voltage
VIL
−0.3
+0.5
V
JTAG output HIGH voltage
JTAG output LOW voltage
R10DS0090EJ0400 Rev.4.00
Nov 09, 2012
VOH1
| IOHC | = 100 μA
1.6
V
VOH2
| IOHT | = 2 mA
1.4
V
VOL1
IOLC = 100 μA
0.2
V
VOL2
IOLT = 2 mA
0.4
V
Page 25 of 38
μPD46365084B, μPD46365094B, μPD46365184B, μPD46365364B
JTAG AC Test Conditions
Input waveform (Rise / Fall time ≤ 1 ns)
1.8 V
0.9 V
Test Points
0.9 V
0.9 V
Test Points
0.9 V
0V
Output waveform
Output load
Figure 2. External load at test
VTT = 0.9 V
50 Ω
ZO = 50 Ω
TDO
20 pF
R10DS0090EJ0400 Rev.4.00
Nov 09, 2012
Page 26 of 38
μPD46365084B, μPD46365094B, μPD46365184B, μPD46365364B
JTAG AC Characteristics (TA = 0 to 70°C)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Clock
Clock cycle time
tTHTH
50
ns
Clock frequency
fTF
Clock HIGH time
tTHTL
20
20
MHz
ns
Clock LOW time
tTLTH
20
ns
TCK LOW to TDO unknown
tTLOX
0
TCK LOW to TDO valid
tTLOV
Output time
ns
10
ns
Setup time
TMS setup time
tMVTH
5
ns
TDI valid to TCK HIGH
tDVTH
5
ns
tCS
5
ns
TMS hold time
tTHMX
5
ns
TCK HIGH to TDI invalid
tTHDX
5
ns
tCH
5
ns
Capture setup time
Hold time
Capture hold time
JTAG Timing Diagram
tTHTH
TCK
tMVTH
tTHTL
tTLTH
TMS
tTHMX
tDVTH
TDI
tTHDX
tTLOX
tTLOV
TDO
R10DS0090EJ0400 Rev.4.00
Nov 09, 2012
Page 27 of 38
μPD46365084B, μPD46365094B, μPD46365184B, μPD46365364B
Scan Register Definition (1)
Register name
Description
Instruction register
The instruction register holds the instructions that are executed by the TAP controller
when it is moved into the run-test/idle or the various data register state. The register can
be loaded when it is placed between the TDI and TDO pins. The instruction register is
automatically preloaded with the IDCODE instruction at power-up whenever the controller
is placed in test-logic-reset state.
Bypass register
The bypass register is a single bit register that can be placed between TDI and TDO. It
allows serial test data to be passed through the RAMs TAP to another device in the scan
chain with as little delay as possible.
ID register
The ID Register is a 32 bit register that is loaded with a device and vendor specific 32 bit
code when the controller is put in capture-DR state with the IDCODE command loaded in
the instruction register. The register is then placed between the TDI and TDO pins when
the controller is moved into shift-DR state.
Boundary register
The boundary register, under the control of the TAP controller, is loaded with the contents
of the RAMs I/O ring when the controller is in capture-DR state and then is placed
between the TDI and TDO pins when the controller is moved to shift-DR state. Several
TAP instructions can be used to activate the boundary register.
The Scan Exit Order tables describe which device bump connects to each boundary
register location. The first column defines the bit’s position in the boundary register. The
second column is the name of the input or I/O at the bump and the third column is the
bump number.
Scan Register Definition (2)
Register name
Bit size
Unit
Instruction register
3
bit
Bypass register
1
bit
ID register
32
bit
Boundary register
109
bit
ID Register Definition
Part number
Organization
ID [31:28] vendor
revision no.
ID [27:12] part no.
ID [11:1] vendor
ID no.
ID [0] fix bit
μPD46365084B
4M x 8
XXXX
0000 0000 0100 1101
00000010000
1
μPD46365094B
4M x 9
XXXX
0000 0000 0100 1110
00000010000
1
μPD46365184B
2M x 18
XXXX
0000 0000 0100 1111
00000010000
1
μPD46365364B
1M x 36
XXXX
0000 0000 0101 0000
00000010000
1
R10DS0090EJ0400 Rev.4.00
Nov 09, 2012
Page 28 of 38
μPD46365084B, μPD46365094B, μPD46365184B, μPD46365364B
SCAN Exit Order
Bit
no.
Signal name
x8
x9
x18
x36
Bump
Bit
Signal name
ID
no.
x8
x9
x18
Bump
Bit
Signal name
Bump
x36
ID
no.
x8
x9
x18
x36
ID
1
C#
6R
37
NC
NC
NC
D15
10D
73
NC
NC
NC
Q28
2C
2
C
6P
38
NC
NC
NC
Q15
9E
74
Q4
Q5
Q11
Q20
3E
3
A
6N
39
NC
NC
Q7
Q7
10C
75
D4
D5
D11
D20
2D
4
A
7P
40
NC
NC
D7
D7
11D
76
NC
NC
NC
D29
2E
5
A
7N
41
NC
NC
NC
D16
9C
77
NC
NC
NC
Q29
1E
6
A
7R
42
NC
NC
NC
Q16
9D
78
NC
NC
Q12
Q21
2F
7
A
8R
43
Q3
Q4
Q8
Q8
11B
79
NC
NC
D12
D21
3F
8
A
8P
44
D3
D4
D8
D8
11C
80
NC
NC
NC
D30
1G
9
A
9R
45
NC
NC
NC
D17
9B
81
NC
NC
NC
Q30
1F
NC
NC
NC
Q17
10B
82
Q5
Q6
Q13
Q22
3G
11A
83
D5
D6
D13
D22
2G
10A
84
10
NC
Q0
Q0
Q0
11P
46
11
NC
D0
D0
D0
10P
47
12
NC
NC
NC
D9
10N
48
13
NC
NC
NC
Q9
9P
49
A
9A
85
NC
NC
NC
D31
1J
14
NC
NC
Q1
Q1
10M
50
A
8B
86
NC
NC
NC
Q31
2J
15
NC
NC
D1
D1
11N
51
A
7C
87
NC
NC
Q14
Q23
3K
16
NC
NC
NC
D10
9M
52
NC
6C
88
NC
NC
D14
D23
3J
17
NC
NC
NC
Q10
9N
53
R#
8A
89
NC
NC
NC
D32
2K
18
Q0
Q1
Q2
Q2
11L
54
BW1#
7A
90
NC
NC
NC
Q32
1K
19
D0
D1
D2
D2
11M
55
NW0# BW0# BW0# BW0#
7B
91
Q6
Q7
Q15
Q24
2L
20
NC
NC
NC
D11
9L
56
K
6B
92
D6
D7
D15
D24
3L
21
NC
NC
NC
Q11
10L
57
K#
6A
93
NC
NC
NC
D33
1M
22
NC
NC
Q3
Q3
11K
58
NC
NC
BW3#
5B
94
NC
NC
NC
Q33
1L
23
NC
NC
D3
D3
10K
59
NW1#
NC
BW1# BW2#
5A
95
NC
NC
Q16
Q25
3N
24
NC
NC
NC
D12
9J
60
W#
4A
96
NC
NC
D16
D25
3M
25
NC
NC
NC
Q12
9K
61
A
5C
97
NC
NC
NC
D34
1N
26
Q1
Q2
Q4
Q4
10J
62
A
4B
98
NC
NC
NC
Q34
2M
27
D1
D2
D4
D4
11J
63
3A
99
Q7
Q8
Q17
Q26
3P
11H
64
VSS
2A
100
D7
D8
D17
D26
2N
CQ#
1A
101
NC
NC
NC
D35
2P
NC
NC
NC
Q35
1P
28
ZQ
CQ
A
NC
A
A
VSS
NC
NC
NC
A
A
VSS
NC
DLL#
1H
29
NC
NC
NC
D13
10G
65
30
NC
NC
NC
Q13
9G
66
NC
NC
Q9
Q18
2B
102
31
NC
NC
Q5
Q5
11F
67
NC
NC
D9
D18
3B
103
A
3R
32
NC
NC
D5
D5
11G
68
NC
NC
NC
D27
1C
104
A
4R
33
NC
NC
NC
D14
9F
69
NC
NC
NC
Q27
1B
105
A
4P
34
NC
NC
NC
Q14
10F
70
NC
NC
Q10
Q19
3D
106
A
5P
35
Q2
Q3
Q6
Q6
11E
71
NC
NC
D10
D19
3C
107
A
5N
36
D2
D3
D6
D6
10E
72
NC
NC
NC
D28
1D
108
A
5R
109
–
Internal
Remarks
Bump ID 10A of bit no. 48 can also be used as NC if the product is x18 or x36.
Bump ID 2A of bit no. 64 can also be used as NC.
The register always indicates LOW, however.
R10DS0090EJ0400 Rev.4.00
Nov 09, 2012
Page 29 of 38
μPD46365084B, μPD46365094B, μPD46365184B, μPD46365364B
JTAG Instructions
Instructions
Description
EXTEST
The EXTEST instruction allows circuitry external to the component package to be tested.
Boundary-scan register cells at output pins are used to apply test vectors, while those at
input pins capture test results. Typically, the first test vector to be applied using the
EXTEST instruction will be shifted into the boundary scan register using the PRELOAD
instruction. Thus, during the update-IR state of EXTEST, the output drive is turned on and
the PRELOAD data is driven onto the output pins.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the
controller is in capture-DR mode and places the ID register between the TDI and TDO pins
in shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up
and any time the controller is placed in the test-logic-reset state.
BYPASS
When the BYPASS instruction is loaded in the instruction register, the bypass register is
placed between TDI and TDO. This occurs when the TAP controller is moved to the shiftDR state. This allows the board level scan path to be shortened to facilitate testing of other
devices in the scan path.
SAMPLE / PRELOAD SAMPLE / PRELOAD is a Standard 1149.1 mandatory public instruction. When the
SAMPLE / PRELOAD instruction is loaded in the instruction register, moving the TAP
controller into the capture-DR state loads the data in the RAMs input and Q pins into the
boundary scan register. Because the RAM clock(s) are independent from the TAP clock
(TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input
buffers are in transition (i.e., in a metastable state). Although allowing the TAP to sample
metastable input will not harm the device, repeatable results cannot be expected. RAM
input signals must be stabilized for long enough to meet the TAPs input data capture setup
plus hold time (tCS plus tCH). The RAMs clock inputs need not be paused for any other
TAP operation except capturing the I/O ring contents into the boundary scan register.
Moving the controller to shift-DR state then places the boundary scan register between the
TDI and TDO pins.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM Q pins are forced
to an inactive drive state (high impedance) and the boundary register is connected between
TDI and TDO when the TAP controller is moved to the shift-DR state.
JTAG Instruction Coding
IR2
IR1
IR0
Instruction
0
0
0
EXTEST
Note
0
0
1
IDCODE
0
1
0
SAMPLE-Z
1
0
1
1
RESERVED
2
1
0
0
SAMPLE / PRELOAD
1
0
1
RESERVED
2
1
1
0
RESERVED
2
1
1
1
BYPASS
Notes 1. TRISTATE all Q pins and CAPTURE the pad values into a SERIAL SCAN LATCH.
2. Do not use this instruction code because the vendor uses it to evaluate this product.
R10DS0090EJ0400 Rev.4.00
Nov 09, 2012
Page 30 of 38
μPD46365084B, μPD46365094B, μPD46365184B, μPD46365364B
Output Pin States of CQ, CQ# and Q
Instructions
Control-Register Status
Output Pin Status
CQ,CQ#
Q
0
Update
High-Z
1
Update
Update
0
SRAM
SRAM
1
SRAM
SRAM
SAMPLE-Z
0
High-Z
High-Z
1
High-Z
High-Z
SAMPLE
0
SRAM
SRAM
1
SRAM
SRAM
0
SRAM
SRAM
1
SRAM
SRAM
EXTEST
IDCODE
BYPASS
Remark The output pin statuses during each instruction vary according
to the Control-Register status (value of Boundary Scan
Register, bit no. 109).
Boundary Scan
Register
CAPTURE
Register
There are three statuses:
Update : Contents of the “Update Register” are output to
SRAM : Contents of the SRAM internal output “SRAM
SRAM
Output
Update
Register
the output pin (QDR Pad).
Update
Output” are output to the output pin (QDR Pad).
High-Z : The output pin (QDR Pad) becomes high
impedance by controlling of the “High-Z JTAG
QDR
Pad
SRAM
ctrl”.
High-Z
The Control-Register status is set during Update-DR at the
EXTEST or SAMPLE instruction.
R10DS0090EJ0400 Rev.4.00
Nov 09, 2012
SRAM
Output
Driver
High-Z
JTAG ctrl
Page 31 of 38
μPD46365084B, μPD46365094B, μPD46365184B, μPD46365364B
Boundary Scan Register Status of Output Pins CQ, CQ# and Q
Instructions
SRAM Status
Boundary Scan Register Status
CQ,CQ#
Q
READ (Low-Z)
Pad
Pad
NOP (High-Z)
Pad
Pad
READ (Low-Z)
–
–
NOP (High-Z)
–
–
SAMPLE-Z
READ (Low-Z)
Pad
Pad
NOP (High-Z)
Pad
Pad
SAMPLE
READ (Low-Z)
Internal
Internal
NOP (High-Z)
Internal
Pad
READ (Low-Z)
–
–
NOP (High-Z)
–
–
EXTEST
IDCODE
BYPASS
Remark The Boundary Scan Register statuses during execution each
instruction vary according to the instruction code and SRAM
operation mode.
Note
No definition
No definition
Boundary Scan
Register
CAPTURE
Register
There are two statuses:
Internal
Pad
: Contents of the output pin (QDR Pad) are captured
in the “CAPTURE Register” in the Boundary Scan
Update
Register
Pad
SRAM
Output
Register.
Internal : Contents of the SRAM internal output “SRAM
Output” are captured in the “CAPTURE Register”
in the Boundary Scan Register.
QDR
Pad
SRAM
Output
Driver
High-Z
JTAG ctrl
R10DS0090EJ0400 Rev.4.00
Nov 09, 2012
Page 32 of 38
μPD46365084B, μPD46365094B, μPD46365184B, μPD46365364B
TAP Controller State Diagram
1
Test-Logic-Reset
0
1
0
1
1
Select-IR-Scan
Select-DR-Scan
Run-Test / Idle
0
0
1
1
Capture-IR
Capture-DR
0
0
0
Shift-DR
0
Shift-IR
1
1
1
1
Exit1-DR
Exit1-IR
0
0
0
Pause-DR
0
Pause-IR
1
1
0
0
Exit2-DR
Exit2-IR
1
1
Update-DR
1
Update-IR
0
1
0
Disabling the Test Access Port
It is possible to use this device without utilizing the TAP. To disable the TAP Controller without interfering with
normal operation of the device, TCK must be tied to VSS to preclude mid level inputs. TDI and TMS may be left open
but fix them to VDD via a resistor of about 1 kΩ when the TAP controller is not used. TDO should be left unconnected
also when the TAP controller is not used.
R10DS0090EJ0400 Rev.4.00
Nov 09, 2012
Page 33 of 38
New Instruction
μPD46365084B, μPD46365094B, μPD46365184B, μPD46365364B
Run-Test/Idle
Update-IR
Exit1-IR
Shift-IR
Exit2-IR
IDCODE
Pause-IR
Exit1-IR
Shift-IR
R10DS0090EJ0400 Rev.4.00
Nov 09, 2012
Select-IR-Scan
Run-Test/Idle
Instruction
Register state
TDI
Controller
state
TMS
Test-Logic-Reset
TDO
Output Inactive
Select-DR-Scan
TCK
Test Logic Operation (Instruction Scan)
Capture-IR
Page 34 of 38
IDCODE
μPD46365084B, μPD46365094B, μPD46365184B, μPD46365364B
Test-Logic-Reset
Select-IR-Scan
Select-DR-Scan
Run-Test/Idle
Update-DR
Exit1-DR
Shift-DR
Exit2-DR
Instruction
Pause-DR
Exit1-DR
Shift-DR
Capture-DR
R10DS0090EJ0400 Rev.4.00
Nov 09, 2012
Instruction
Register state
TDI
Controller
state
TMS
TCK
Test Logic (Data Scan)
Run-Test/Idle
TDO
Output Inactive
Select-DR-Scan
Page 35 of 38
μPD46365084B, μPD46365094B, μPD46365184B, μPD46365364B
Package Dimensions
165-PIN PLASTIC BGA(13x15)
ZD
w S B
E
ZE
B
11
10
9
8
7
6
5
4
3
2
1
A
D
R P N M L K J H G F E D C B A
w S A
INDEX MARK
A
y1
(UNIT:mm)
A2
S
S
y
e
S
b
x
A1
M
S AB
ITEM
D
DIMENSIONS
13.00±0.10
E
15.00±0.10
w
0.30
A
1.35±0.11
A1
0.37±0.05
A2
0.98
e
1.00
b
+0.10
0.50 −0.05
x
0.10
y
0.15
y1
0.25
ZD
1.50
ZE
0.50
T165F1-100-EQ1
R10DS0090EJ0400 Rev.4.00
Nov 09, 2012
Page 36 of 38
μPD46365084B, μPD46365094B, μPD46365184B, μPD46365364B
Recommended Soldering Condition
Please consult with our sales offices for soldering conditions of these products.
Types of Surface Mount Devices
μPD46365084BF1-EQ1
:
165-pin PLASTIC BGA (13 x 15)
μPD46365094BF1-EQ1
:
165-pin PLASTIC BGA (13 x 15)
μPD46365184BF1-EQ1
:
165-pin PLASTIC BGA (13 x 15)
μPD46365364BF1-EQ1
:
165-pin PLASTIC BGA (13 x 15)
Quality Grade
• A quality grade of the products is “Standard”.
• Anti-radioactive design is not implemented in the products.
• Semiconductor devices have the possibility of unexpected defects by affection of cosmic ray that reach to
the ground and so forth.
R10DS0090EJ0400 Rev.4.00
Nov 09, 2012
Page 37 of 38
Revision History
Rev.
Rev.1.00
Rev.2.00
Rev.3.00
Rev.4.00
Date
’11.05.19
’11.11.07
’12.07.13
’12.11.09
μPD46365084B, μPD46365094B, μPD46365184B, μPD46365364B
Page
P11
ALL
ALL
Description
Summary
New Data Sheet
Modified comments for Power on Sequence
Addition : E**Y series
Addition : -E33,-E33Y series, Lead series
Deletion : -E50,-E50Y series
All trademarks and registered trademarks are the property of their respective owners.
C - 38
Notice
1.
All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas
Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to
be disclosed by Renesas Electronics such as that disclosed through our website.
2.
Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or
technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or
others.
3.
You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.
4.
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the
use of these circuits, software, or information.
5.
When exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and
regulations. You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to
the development of weapons of mass destruction. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is
prohibited under any applicable domestic or foreign laws or regulations.
6.
Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics
7.
Renesas Electronics products are classified according to the following three quality grades: "Standard", "High Quality", and "Specific". The recommended applications for each Renesas Electronics product
assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.
depends on the product's quality grade, as indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas
Electronics product for any application categorized as "Specific" without the prior written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for
which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the
use of any Renesas Electronics product for an application categorized as "Specific" or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics.
The quality grade of each Renesas Electronics product is "Standard" unless otherwise expressly specified in a Renesas Electronics data sheets or data books, etc.
"Standard":
Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools;
personal electronic equipment; and industrial robots.
"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; safety equipment; and medical equipment not specifically
designed for life support.
"Specific":
Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical
implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life.
8.
You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage
range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the
use of Renesas Electronics products beyond such specified ranges.
9.
Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and
malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the
possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to
redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult,
please evaluate the safety of the final products or system manufactured by you.
10. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics
products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes
no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.
11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.
(Note 1)
"Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.
(Note 2)
"Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.
http://www.renesas.com
SALES OFFICES
Refer to "http://www.renesas.com/" for the latest and detailed information.
Renesas Electronics America Inc.
2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A.
Tel: +1-408-588-6000, Fax: +1-408-588-6130
Renesas Electronics Canada Limited
1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada
Tel: +1-905-898-5441, Fax: +1-905-898-3220
Renesas Electronics Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K
Tel: +44-1628-585-100, Fax: +44-1628-585-900
Renesas Electronics Europe GmbH
Arcadiastrasse 10, 40472 Düsseldorf, Germany
Tel: +49-211-65030, Fax: +49-211-6503-1327
Renesas Electronics (China) Co., Ltd.
7th Floor, Quantum Plaza, No.27 ZhiChunLu Haidian District, Beijing 100083, P.R.China
Tel: +86-10-8235-1155, Fax: +86-10-8235-7679
Renesas Electronics (Shanghai) Co., Ltd.
Unit 204, 205, AZIA Center, No.1233 Lujiazui Ring Rd., Pudong District, Shanghai 200120, China
Tel: +86-21-5877-1818, Fax: +86-21-6887-7858 / -7898
Renesas Electronics Hong Kong Limited
Unit 1601-1613, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong
Tel: +852-2886-9318, Fax: +852 2886-9022/9044
Renesas Electronics Taiwan Co., Ltd.
13F, No. 363, Fu Shing North Road, Taipei, Taiwan
Tel: +886-2-8175-9600, Fax: +886 2-8175-9670
Renesas Electronics Singapore Pte. Ltd.
1 harbourFront Avenue, #06-10, keppel Bay Tower, Singapore 098632
Tel: +65-6213-0200, Fax: +65-6278-8001
Renesas Electronics Malaysia Sdn.Bhd.
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: +60-3-7955-9390, Fax: +60-3-7955-9510
Renesas Electronics Korea Co., Ltd.
11F., Samik Lavied' or Bldg., 720-2 Yeoksam-Dong, Kangnam-Ku, Seoul 135-080, Korea
Tel: +82-2-558-3737, Fax: +82-2-558-5141
© 2012 Renesas Electronics Corporation. All rights reserved.
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