(Preliminary) PL565-37/38 VCXO Family PRODUCT DESCRIPTION FEATURES PhaseLink’s Analog Frequency Multiplier (AFM) is the industry’s first ‘Balanced Oscillator’ utilizing analog multiplication of the fundamental frequency (at double or quadruple frequency), combined with an attenuation of the fundamental of the reference crystal, without the use of a phase-locked loop (PLL), in CMOS technology. PhaseLink’s PL565-37/38products can achieve up to 250 MHz output frequency with little jitter or phase noise deterioration. In addition, the low frequency input crystal requirement makes the AFMs the most affordable high-performance timing-source in the market. Product Selector Part Number PL565-38 PL565-37 Output Type PECL Output CMOS Output Non-PLL frequency multiplication Input frequency from 30-62.5 MHz Output frequency from 120-250 MHz Low phase noise and jitter (equivalent to fundamental crystal at the output frequency) Ultra-low jitter o RMS phase jitter < 0.25 ps (12kHz-20MHz) o RMS period jitter < 25 ps Low phase noise o -147 dBc/Hz @100kHz offset from 155.52 MHz o -157 dBc/Hz @10MHz offset from 155.52 MHz High linearity pull range (typ. 5%) +/- 120 PPM pullability VCXO Low input frequency eliminates the need for expensive crystals Differential output levels PECL or single-ended CMOS Single 3.3V, ±10% power supply Optional industrial temperature range (-40C to +85C) Figure 1: 4X AFM Phase Noise at 155.52MHz 2880 Zanker Rd., San Jose, California 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 11/18/11 Page 1 (Preliminary) PL565-37/38 VCXO Family L2X VCON OE X IN O s c illa to r A m p lifie r XOUT QBAR F re q u e n c y X2 F re q u e n c y X4 Q O n ly r e q u ir e d in x 4 d e s ig n s L4X Figure 2: Block Diagram of VCXO AFM Figure 3 shows the period jitter histogram of the 4X Analog Frequency Multiplier at 311.04 MHz, while Figure 4 shows the very low rejection levels of sub-harmonics that correspond to the exceptionally low jitter performance. Figure 3: Period Jitter Histogram at 155.52 MHz Analog Frequency Multiplier (4x) with 38.88MHz crystal Figure 4: Spectrum Analysis at 155.52 MHz Analog Frequency Multiplier (4x) with sub-harmonics below –39 dBc OE LOGIC SELECTION OUTPUT OESEL 0 (Default) LVPECL 1 0 (Default) LVCMOS 1 OE Output State 0 (Default) Enabled 1 Tri-state 0 Tri-state 1 (Default) Enabled 0 Tri-state 1 (Default) Enabled 0 (Default) Enabled 1 Tri-state OESEL and OE: Connect to VDD or leave floating to set to “1”, connect to GND to set to “0”. Internally set to default through pull-down / -up. 2880 Zanker Rd., San Jose, California 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 11/18/11 Page 2 (Preliminary) PL565-37/38 VCXO Family PRODUCT SELECTION GUIDE FREQUENCY VERSUS PHASE NOISE PERFORMANCE Phase Noise at Frequency Offset From Carrier (dBc/Hz) Part Number Input Frequency Range (MHz) Analog Frequency Multiplication Factor Output Frequency Range (MHz) Output Type PL565-37 30 - 60 4 120 - 250 PL565-38 30 - 60 4 120 - 250 Carrier Freq. (MHz) 10Hz 100Hz 1kHz 10kHz 100kHz 1MHz 10MHz LVCMOS 155.52 -51 -88 -119 -138 -147 -151 -157 LVPECL 155.52 -51 -88 -119 -138 -147 -151 -157 JITTER, AND SUB-HARMONIC PERFORMANCE Part Number RMS Period Jitter (ps) Peak to Peak RMS RMS Phase Jitter Period Jitter Accumulated 12kHz to 20MHz Spectral Specifications / Sub-harmonic Content (dBc), Output Frequency (MHz) (ps) (L.T.) Jitter (ps) (ps) Freq. Carrier @ @ @ @ @ @ (MHz) Min Typ Max Min Typ Max Min Typ Max Min Typ Max Freq. -75% -50% -25% +25% +50% +75% (Fc) (Fc) (Fc) (Fc) (Fc) (Fc) (Fc) PL565-37 155 18 25 50 100 25 0.25 155.52 -75 -39 -40 -75 PL565-38 155 18 25 50 100 25 0.25 155.52 -75 -39 -40 -75 www.phaselink.com Rev 11/18/11 Page 3 Note: Agilent 5052B was used for phase jitter measurements. Spectral specifications were obtained using Agilent E7401A. 2880 Zanker Rd., San Jose, California 95134 Tel (408) 571-1668 Fax (408) 571-1688 (Preliminary) PL565-37/38 VCXO Family DIE SPECIFICATIONS 16 17 15 14 Chip size, active area 1.414mm x 1.385mm 13 12 19 11 20 Y 0,0 2 3 PAD size 80µm x 80µm 9 Scribe Line Dimension X = 80µm Y = 80µm 8 Chip Base GND level X 7 1 200 ± 20µm 10 Die ID 21 22 Chip thickness 4 5 6 SCRIBE LINE 18 Die ID: C561A CCCCCCC C561A DDDDDDD PL565-37DC PL565-38DC SCRIBE LINE PAD ASSIGNMENT AND DESCRIPTION (The X/Y coordinates indicate pad centers) Name Pad Assignment* Type Description Pad # X (µm) Y (µm) L4X VDDOSC GNDANA GNDANA GNDBUF GNDBUF GNDBUF 1 2 3 4 5 6 7 -352 -183 +15 +144 +292 +469 +502 -557 -557 -557 -557 -557 -557 -365 I P P P P P P OUTB 8 +502 -215 O OUT VDDBUF VDDBUF VDDANA N.C. OESEL VDDOSC L2X OSCOFFSEL GNDOSC VCON XIN XOUT OE 9 10 11 12 13 14 15 16 17 18 19 20 21 22 +502 +502 +571 +571 +377 +183 -57 -214 -410 -572 -572 -572 -572 -572 -54 +79 +236 +413 +554 +554 +554 +554 +554 +554 +394 +199 -309 -521 O P P P External inductor connection VDD connection GND connection GND connection GND connection GND connection GND connection -37: LVCMOS 2 nd in-phase output -38: LVPECL complementary output -37: LVCMOS output, -38: LVPECL output VDD connection VDD connection VDD connection I P I I P I I O I OE style selection pin VDD connection External inductor connection Oscillator Off selection pin GND connection Control voltage input Crystal Input pad Crystal Output pad Output Enable input * Note: Pad coordinates referenced to the center of the die. 2880 Zanker Rd., San Jose, California 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 11/18/11 Page 4 (Preliminary) PL565-37/38 VCXO Family AFM DIE APPLICATION CIRCUIT FOR PL565-37 (LVCMOS) C1, C2: Power Supply Decoupling. The advised value is 0.01µF. R1: Oscillator Amplitude Control. The advised value is 10K. L2X, L4X: Multiplier Tuning. Contact factory for optimum values. 1 st and 2 nd CMOS outputs are 8mA drive each. They are in-phase and connected together they make a 16mA drive output. 16mA drive is advised for driving 50 PCB traces. A 7x5mm ceramic substrate was designed to assemble and operate the AFM die at optimum performance: VDD N.C. VCON OE CMOS GND Substrate part number: Kyocera KD-VA9501 2880 Zanker Rd., San Jose, California 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 11/18/11 Page 5 (Preliminary) PL565-37/38 VCXO Family AFM DIE APPLICATION CIRCUIT FOR PL565-38 (LVPECL) C1, C2: Power Supply Decoupling. The advised value is 0.01µF. R1: Oscillator Amplitude Control. The advised value is 10K. L2X, L4X: Multiplier Tuning. Contact factory for optimum values. A 7x5mm ceramic substrate was designed to assemble and operate the AFM die at optimum performance: VDD VCON PECLB PECL OE GND Substrate part number: Kyocera KD-VA9501 2880 Zanker Rd., San Jose, California 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 11/18/11 Page 6 (Preliminary) PL565-37/38 VCXO Family AFM QFN PACKAGE APPLICATION CIRCUIT RECOMMENDED PCB LAYOUT Avoid ground planes underneath the crystal and inductor traces to limit parasitic capacitance. Add bypass capacitor close to VDDBUF pin. Avoid bypass capacitors near VDDOSC pins to lower cross-talk of unwanted frequencies. L1X(a,b) can be used to increase the VCXO pulling range. Using a ferrite core inductor limits the oscillation amplitude which can have a positive effect on phase noise. L2X and L4X tune the frequency multiplier tank circuits. They need to be wire wound inductors with high Q-factor, preferably >20. The large center pad is the “thermal relief” pad and can be connected to ground. 2880 Zanker Rd., San Jose, California 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 11/18/11 Page 7 (Preliminary) PL565-37/38 VCXO Family INDUCTOR VALUE OPTIMIZATION The required inductor values for the best performance depend on the operating frequency, and the board layout or module specifications. The listed values in this datasheet are based on the calculated parasitic values from PhaseLink’s evaluation board design. These inductor values provide the user with a starting point to determine the optimum inductor values. Additional fine-tuning may be required to determine the optimal solution. The inductor is recommended to be a high Q small size 0402 or 0603 SMD component, and must be placed between L2X / L4X and adjacent VDDOSC pin. Place inductor as close to the IC as possible to minimize parasitic effects and to maintain inductor Q. To assist with the inductor value optimization, PhaseLink has developed AFM “Tuning Assistant” documents. You can download these documents from PhaseLink’s web site (www.phaselink.com). The documents consist of tables with recommended inductor values for certain output frequency ranges. Figure 10: Diagram Representation of the Related System Inductance and Capacitance DIE SIDE - Cinternal at L2X = 34.125 pF, at L4X = 16.50 pF - Cpad = 1.0 pF, Bond pad and its ESD circuitry - C11 = 0.4 pF, the following amplifier stage PCB side - LWB1 = 2 nH, (2 places), Stray inductance - Cstray = 0.5 pF, Stray capacitance - L2X (L4X) = 2x or 4x inductor - C2X (C4X) = range (0.1 to 2.7 pF), Fine tune the tank, if used. Work out the resonance of this network and you have a good first guess for the required inductor values for optimum performance. Non-linear behavior at large signal amplitudes can shift the tank resonance significantly, especially at the L2X side, to a lower frequency than the calculation suggests. 2880 Zanker Rd., San Jose, California 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 11/18/11 Page 8 (Preliminary) PL565-37/38 VCXO Family CRYSTAL SPECIFICATIONS & TUNING PERFORMANCE CRYSTAL SPECIFICATIONS PART NUMBER TUNING PERFORMANCE CRYSTAL CL (xtal) RESONATOR MODE FREQUENCY CONDITYP (FXIN) TIONS At FundaVCON = PL565-37/38 30 to 62.5MHz mental 1.65V 5pF ESR (RE) MAX 30Ω CRYSTAL TUNING (Typical) CRYSTAL FREQ (MHz) C0 C1 C0/C1 VC: 1.65V 0V VC: 1.65V 3.3V 30.72 2.8pF 12.4fF 228 -167ppm +176 ppm 30.72 4.5pF 19.1fF 236 -163 ppm +167 ppm 38.88 5.1pF 20.9fF 242 -131 ppm +98 ppm 38.88 5.3pF 25.6fF 207 -157 ppm +141 ppm 77.76 2.0pF 6.7fF 305 -92 ppm +110 ppm Note: Non specified parameters can be chosen as standard values from crystal suppliers. CL ratings larger than 5pF require a crystal frequency adjustment. Request detailed crystal specifications from PhaseLink. VOLTAGE CONTROL SPECIFICATION PARAMETERS VCXO Stabilization Time SYMBOL T VCXOSTB CONDITIONS MIN. From power valid VCXO Tuning Range XTAL C 0 /C 1 <300 200 CLK Output Pullability VCON= 1.65V, 1.65V XTAL C 0 /C 1 <300 100 Linearity 0V < VCON < 3.3V, -3dB 2880 Zanker Rd., San Jose, California 95134 Tel (408) 571-1668 Fax (408) 571-1688 MAX. UNITS 10 ms ppm 120 5 VCON Input Impedance VCON Modulation BW TYP. ppm 10 % 10 MΩ 16 kHz www.phaselink.com Rev 11/18/11 Page 9 (Preliminary) PL565-37/38 VCXO Family ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PARAMETERS SYMBOL Supply Voltage MIN. MAX. UNITS 4.6 V V DD Input Voltage, DC VI GND-0.5 V DD +0.5 V Output Voltage, DC VO GND-0.5 V DD +0.5 V Storage Temperature TS -65 150 C Ambient Operating Temperature, Industrial T A_I -40 +85 C Ambient Operating Temperature, Commercial T A_C 0 +70 C 125 C 260 C 2 kV Junction Temperature TJ Lead Temperature (soldering, 10s) Input Static Discharge Voltage Protection Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied . LVPECL ELECTRICAL CHARACTERISTICS FOR PL565-38 PARAMETERS SYMBOL CONDITIONS Supply Current, loaded outputs I DD Fout = 155.52MHz Operating Voltage* V DD Output Clock Duty Cycle MIN. TYP. MAX. UNITS 75 80 mA 3.63 V 55 % 2.97 @ V DD – 1.3V 45 50 50 Short Circuit Current Output High Voltage V OH Output Low Voltage V OL R L = 50Ω to (V DD – 2V) Clock Rise Time tr @ 20/80% Clock Fall Time tf @ 80/20% LVPECL Levels Test Circuit mA V DD -1.025 V V DD -1.620 V 0.25 0.45 ns 0.25 0.45 ns LVPECL Transistion Time Waveform DUTY CYCLE OUT VDD 50? 2.0V 45 - 55% 55 - 45% OUT 80% 50% 50? 20% OUT OUT tR 2880 Zanker Rd., San Jose, California 95134 Tel (408) 571-1668 Fax (408) 571-1688 tF www.phaselink.com Rev 11/18/11 Page 10 (Preliminary) PL565-37/38 VCXO Family LVCMOS ELECTRICAL CHARACTERISTICS FOR PL565-37 PARAMETERS SYMBOL CONDITIONS Supply Current, loaded outputs I DD At 150MHz, 15pF load Operating Voltage V DD V OH3.3 I OH = -8mA, 3.3V Output Low Voltage (LVTTL) V OL3.3 I OL = 8mA, 3.3V Output High Voltage (LVCMOS) V OHC3.3 I OH = -4mA, 3.3V Output Drive Current I OSD3.3 V OL = 0.4V, V OH = 2.4V (per output), 3.3V T r ,T f Output Clock Duty Cycle TYP. MAX. UNITS 20 30 mA 3.63 V 2.97 Output High Voltage (LVTTL) Output Clock Rise/Fall Time MIN. 2.4 V 0.4 V V DD – 0.4 V 8 mA 10% / 90% V DD , 10 pF load, 1 output 1.2 1.6 ns 10% / 90% V DD , 15 pF load, 2 outputs 1.0 1.5 ns 50 55 % Measured @ 50% V DD 45 PACKAGE INFORMATION Symbol Dimension (mm) Min Nom Max A 0.70 0.75 0.80 A1 0.00 - 0.05 0.20 A3 b 0.20 0.25 0.30 D 2.95 3.00 3.05 E 2.95 3.00 3.05 D1 1.65 1.70 1.75 E1 1.65 1.70 1.75 L 0.250 0.300 0.350 e 0.50BSC 2880 Zanker Rd., San Jose, California 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 11/18/11 Page 11 (Preliminary) PL565-37/38 VCXO Family ORDERING INFORMATION For part ordering, please contact our Sales Department: 2880 Zanker Rd., San Jose, CA 95134, USA Tel: (408) 571-1668 Fax: (408) 571-1688 PART NUMBER The order number for this device is a combination of the following: Part number, Package type and Operating temperature range PL565-3X X X X PART NUMBER NONE= TUBE R= TAPE AND REEL PACKAGE TYPE Q= QFN-16L D= Die TEMPERATURE C=COMMERCIAL I=INDUSTRIAL Order Number PL565-37DC PL565-38DC PL565-37QC PL565-37QC-R PL565-38QC PL565-38QC-R Marking P565 37(I) LLL P565 38(I) LLL Package Option Die Only QFN – Tube QFN – Tape and Reel QFN – Tube QFN – Tape and Reel Marking Notes: “LLL”, “LLLLL” represents the production lot number PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 2880 Zanker Rd., San Jose, California 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 11/18/11 Page 12