PL500-17 - Phaselink.com

PL500-17
Low Phase Noise VCXO (17MHz to 36MHz)
FEATURES


DESCRIPTION
XIN
1
VDD*
2
VCON
3
GND
4
8
XOUT
7
OE^
6
VDD*
5
CLK
SOP-8L
XOUT
1
GND
2
CLK
3
PL500-17
VCXO output for the 17MHz to 36MHz range
Low phase noise (-130dBc @ 10kHz offset at
35.328MHz)
LVCMOS output with OE tri-state control
17 to 36MHz fundamental crystal input
Integrated high linearity variable capacitors
8mA drive capability at TTL output
±150 ppm pull range, max 5% (typ.) linearity
Low jitter (RMS): 2.5ps period jitter
2.5 to 3.3V operation
Available in 8-Pin SOP, 6-pin SOT23 GREEN/
RoHS compliant packages, or Die
PL500-17








PIN CONFIGURATION
6
XIN
5
VDD
4
VCON
SOT23-6L
The PL500-17 is a low cost, high performance and
low phase noise VCXO for the 17 to 36MHz range,
providing less than -130dBc at 10kHz offset at
35.328MHz. The very low jitter (2.5 ps RMS period
jitter) makes this chip ideal for applications requiring
voltage controlled frequency sources. Input crystal
can range from 17 to 36MHz (fundamental resonant
mode).
^: Denotes internal Pull-up
*: Only one VDD pin needs to be connected
BLOCK DIAGRAM
XIN
Xtal
Osc
CLK
XOUT
VCON
Varicap
OE
2880 Zanker RD., San Jose, California 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 6/15/10 Page 1
PL500-17
Low Phase Noise VCXO (17MHz to 36MHz)
DIE PAD LAYOUT
DIE SPECIFICATIONS
32 mil
(812,986)
8
1
XOUT
XIN
OE^ 7
39 mil
2
VDD
VDD 6
3 VCON
Name
Value
Size
39 x 32 mil
Reverse side
GND
Pad dimensions
80 micron x 80 micron
Thickness
8 mil
CLK 5
4 GND
DIE ID: C500xxxxxx
Y
(0,0)
X
Note: ^ denotes internal pull up
PACKAGE PIN AND DIE PAD ASSIGNMENT
Name
Pin#
Die Pad Position
Type
Description
SOP-8
SOT23-6
X (m)
Y (m)
XIN
1
6
94.183
768.599
I
Crystal input pin.
VDD
2
5
94.157
605.029
P
VDD power supply pin. Only one VDD pin is
necessary.
VCON
3
4
94.183
331.756
I
Frequency control voltage input pin.
GND
4
2
94.193
140.379
P
Ground pin.
CLK
5
3
715.472
203.866
O
Output clock pin.
VDD
6
-
715.307
455.726
P
VDD power supply pin. Only one VDD pin is
necessary.
OE*
7
-
715.472
626.716
I
Output Enable input pin. Disables the output
when low. Internal pull-up enables output by
default if pin is not connected to low.
XOUT
8
1
476.906
888.881
I
Crystal output pin. Ref Clock input.
* OE (Output Enable) pin is not available in SOT23-6L package, the output will always be enabled by the build in pull-up resister.
2880 Zanker RD., San Jose, California 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 6/15/10 Page 2
PL500-17
Low Phase Noise VCXO (17MHz to 36MHz)
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
SYMBOL
Supply Voltage
MIN.
V DD
MAX.
UNITS
4.6
V
Input Voltage, dc
VI
-0.5
V DD +0.5
V
Output Voltage, dc
VO
-0.5
V DD +0.5
V
Storage Temperature
TS
-65
150
C
Ambient Operating Temperature*
TA
-40
85
C
Junction Temperature
TJ
125
C
260
C
Lead Temperature (soldering, 10s)
ESD Protection, Machine Model
200
V
2
kV
ESD Protection, Human Body Model
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functiona l operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.* Note: Operating Temperature is guaranteed by design for all parts
(COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL g rade only.
2. Voltage Control Crystal Oscillator
PARAMETERS
VCXO Stabilization Time *
SYMBOL
T VCXOSTB
CONDITIONS
MIN.
From power valid
VCXO Tuning Range
XTAL C 0 /C 1 < 250
0V  VCON  3.3V
CLK Output Pullability
VCON=1.65V, 1.65V
UNITS
10
ms
ppm
ppm
150
100
Pull Range Linearity
PWSRR
Frequency change, V DD ±10%
VCON Pin Input Impedance
VCON Modulation BW
MAX.
300
VCXO Tuning Characteristic
Power Supply Rejection
TYP.
0V  VCON  3.3V, -3dB
-1
ppm/V
5
%
+1
ppm
5000
k
18
kHz
Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits.
2880 Zanker RD., San Jose, California 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 6/15/10 Page 3
PL500-17
Low Phase Noise VCXO (17MHz to 36MHz)
3. AC Electrical Specifications
PARAMETERS
Input Crystal Frequency
Output Clock Rise/Fall Time
SYMBOL
CONDITIONS
MIN.
TYP.
F in
Fundamental Mode
tr / tf
0.8V to 2.0V, 10 pF load
1.15
tr / tf
0.3V to 3.0V, 15 pF load
3.7
Output Clock Duty Cycle
17
45
50
MAX.
UNITS
36
MHz
ns
55
%
Output Enable/Disable Time
t OE
5
ns
Start-Up Time
t SU
1
ms
4. Jitter and Phase Noise Specifications
PARAMETERS
RMS Period Jitter
(1 sigma – 1000 samples)
Phase Noise,
Relative to Carrier
CONDITIONS
MIN.
TYP.
MAX.
UNITS
With capacitive decoupling between
V DD and GND.
2.5
ps
27MHz @100Hz offset
-100
dBc/Hz
27MHz @1kHz offset
-125
dBc/Hz
27MHz @10kHz offset
-142
dBc/Hz
27MHz @100kHz offset
-150
dBc/Hz
27MHz @1MHz offset
-150
dBc/Hz
5. DC Specifications
PARAMETERS
SYMBOL
Supply Current,
Dynamic
I DD
Supply Current,
Output Disabled
I DD_OE
CONDITIONS
TYP.
MAX.
27MHz, 15pF Load, 3.3V
3.7
5
27MHz, 15pF Load, 2.5V
2.4
3.5
27MHz, 3.3V, OE=Low
1.4
27MHz, 2.5V, OE=Low
1
Operating Voltage
V DD
Output Low Voltage,CMOS
V OLC
I OL = +4mA
Output High Voltage, CMOS
V OHC
I OH = -4mA
Output Drive Current
VCXO Control Voltage
2.25
For V OL <0.4V or V OH >2.4V
VCON
MIN.
0
mA
mA
3.63
V
0.4
V
V DD – 0.4
8
UNITS
V
9.5
mA
V DD
V
2880 Zanker RD., San Jose, California 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 6/15/10 Page 4
PL500-17
Low Phase Noise VCXO (17MHz to 36MHz)
6. Crystal Specifications
PARAMETERS
SYMBOL
MIN.
TYP.
C L (xtal)
(see note
below)
Crystal Loading Rating (VCON = 1.65V, 3.3V Operation)
Crystal Loading Rating (VCON = 1.25V, 2.5V Operation)
MAX.
7.8
pF
8.9
Maximum Sustainable Drive Level
200
Operating Drive Level
UNITS
50
W
W
Max C0
5
pF
C0/C1
250
-
30
Ω
ESR
RS
Note: The crystal must be such that it oscillates (parallel resonant) at nominal frequency when presented a C Load as specified above.
If the crystal requires more load to be at nominal frequency, the additional load must be added externally. This however may reduce the pull range.
Note that the Cload values above are for the IC only, and do not include PCB parasitics. Crystal specifications for Cload include PCB parasitics.
PACKAGE INFORMATION (GREEN PACKAGE COMPLIANT)
SOP-8L
Symbol
A
A1
A2
B
C
D
E
H
L
e
Dimension in MM
Min.
Max.
1.35
1.75
0.10
0.25
1.25
1.50
0.33
0.53
0.19
0.27
4.80
5.00
3.80
4.00
5.80
6.20
0.40
0.89
1.27 BSC
E
H
D
A2 A
A1
C
L
b
e
SOT23-6 L
Symbol
A
A1
A2
b
c
D
E
H
L
e
Dimension in MM
Min.
Max.
1.05
1.35
0.05
0.15
1.00
1.20
0.30
0.50
0.08
0.20
2.80
3.00
1.50
1.70
2.60
3.0
0.35
0.55
0.95 BSC
Pin1 Dot
E
H
D
A2 A
A1
C
e
b
L
2880 Zanker RD., San Jose, California 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 6/15/10 Page 5
PL500-17
Low Phase Noise VCXO (17MHz to 36MHz)
ORDERING INFORMATION (GREEN PACKAGE)
For part ordering, please contact our Sales Department:
2880 Zanker RD., San Jose, California 95134
Tel (408) 571-1668 Fax (408) 571-1688
PART NUMBER
The order number for this device is a combination of the following:
Part number, Package type and Operating temperature range
Part / Order Number
Marking*
Package Option
PL500-17DC
N/A
Die (Waffle Pack)
PL500-17WC
N/A
P500-17
SC
LLLLL
B17
LLL
WAFER
PL500-17SC
PL500-17SC-R
PL500-17TC-R
8-Pin SOP (Tube)
8-Pin SOP (Tape and Reel)
6-Pin SOT23 (Tape and Reel)
*Note: LLL and LLLLL represent the production lot number
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information fu rnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this pr oduct.
LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the e xpress written approval of the President of PhaseLink Corporation.
2880 Zanker RD., San Jose, California 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 6/15/10 Page 6