RENESAS PD70F3564

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Cover
Data Sheet
32
V850E2/FL4-H
32-bit Single-Chip Microcontroller
µPD70F3564
Renesas Electronics
www.renesas.com
R01DS0144ED0100
2013-05-24
Notice
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2
The quality grade of each Renesas Electronics product is “Standard”
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“Standard”:
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3
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2. “Renesas Electronics product(s)” means any product developed or
manufactured by or for Renesas Electronics.
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Regional Information
Some information contained in this document may vary from country to
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please contact the Renesas Electronics office in your country to obtain a list of
authorized representatives and distributors. They will verify:
•
•
•
•
•
Device availability
Ordering information
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voltages, and so forth)
• Network requirements
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Visit
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to get in contact with your regional representatives and distributors.
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5
Notes for CMOS Devices
(1)
Precaution against ESD for semiconductors
Strong electric field, when exposed to a MOS device, can cause destruction of
the gate oxide and ultimately degrade the device operation. Steps must be
taken to stop generation of static electricity as much as possible, and quickly
dissipate it once, when it has occurred. Environmental control must be
adequate. When it is dry, humidifier should be used. It is recommended to
avoid using insulators that easily build static electricity. Semiconductor devices
must be stored and transported in an anti-static container, static shielding bag
or conductive material. All text and measurement tools including work bench
and floor should be grounded. The operator should be grounded using wrist
strap. Semiconductor devices must not be touched with bare hands. Similar
precautions need to be taken for PW boards with semiconductor devices on it.
(2)
Handling of unused input pins for CMOS
No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level
may be generated due to noise, etc., hence causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry. Each unused pin should be connected to VDD or GND with a resistor,
if it is considered to have a possibility of being an output pin. All handling
related to the unused pins must be judged device by device and related
specifications governing the devices.
(3)
Status before initialization of MOS devices
Power-on does not necessarily define initial status of MOS device. Production
process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized until
the reset signal is received. Reset operation must be executed immediately
after power-on for devices having reset function.
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6
Table of contents
Chapter 1
1.1
1.2
1.3
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
Naming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.1
Alternative function pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.2
Power supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.1
AC characteristic measurement condition. . . . . . . . . . . . . . . . . . . . . . . . . . .
10
10
10
11
11
11
Chapter 2
2.1
2.2
2.3
2.4
2.5
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
Supply voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
13
14
14
15
Chapter 3
3.1
3.2
3.3
3.4
3.5
Power supply specification . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
Requirements for external power supply connections . . . . . . . . . . . . . . . . . . . . .
Power area definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power supply groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.1
AWO Regulator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.2
Amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.3
POC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.4
Voltage Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-up/-down sequence of external supply voltages . . . . . . . . . . . . . . . . . . . .
3.5.1
External FLMDn Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.2
Condition 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.3
Condition 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.4
Condition 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.5
Condition 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.6
Condition 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.7
Condition 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
16
17
18
19
19
21
21
22
22
22
23
24
25
26
27
Chapter 4
4.1
4.2
4.3
4.4
Clock generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28
CPU clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peripheral clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.1
Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.2
Sub-oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.3
Internal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28
28
28
28
29
30
31
Chapter 5
5.1
5.2
5.3
Supply current specification. . . . . . . . . . . . . . . . . . . . . . . . . .
32
Total supply current for µPDF70F3564 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
CVDD supply current for µPDF70F3564 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Voltage Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
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7
Chapter 6
6.1
I/O specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
34
Port Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1.1
Condition settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1.2
PgE0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1.3
PgE1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1.4
PgB0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1.5
PgA0 and PgA1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
34
34
35
36
37
38
Chapter 7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
7.14
7.15
7.16
7.17
7.18
7.19
Peripherals specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
39
Reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NMI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
INTP timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FLMD0 timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
_DCUTRST timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiplexed bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.7.1
MEMC0CLK asynchronous timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.7.2
MEMC0CLK synchronous timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSI timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.8.1
Master modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.8.2
Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FCN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FlexRay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ethernet timing (MII interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.12.1 Transmission interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.12.2 Reception interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IIC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Frequency Output Function (FOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VLVI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage comparator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LVI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A/D Converter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.18.1 12bit A/D (for ADC channels without S/H functionality) . . . . . . . . . . . . . . . .
7.18.2 12bit A/D (For channel ADCA0I0-5 when the S/H function is not used) . . . .
7.18.3 12bit A/D (When channel S/H function is used) . . . . . . . . . . . . . . . . . . . . . .
7.18.4 10bit A/D (for ADC channels without S/H functionality) . . . . . . . . . . . . . . . .
7.18.5 10bit A/D (For channel ADCA0I0-5 when the S/H function is not used) . . . .
7.18.6 10bit A/D (When channel S/H function is used) . . . . . . . . . . . . . . . . . . . . . .
7.18.7 Equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.18.8 ADTRG timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Key Return . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
39
39
40
40
40
41
42
43
46
49
49
55
58
59
60
62
62
63
64
66
66
67
68
69
69
70
71
72
73
74
75
75
76
Chapter 8
8.1
8.2
8.3
Memory specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
77
Code flash specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Data flash specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Serial write operation specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Chapter 9
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Pinning and package specification . . . . . . . . . . . . . . . . . .
78
8
9.1
9.2
Pinning specification PBGA 272 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Package specification PBGA 272. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
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9
Chapter 1
Overview
Chapter 1 Overview
1.1 Naming
1.1.1 Alternative function pins
Peripheral
Prefix
Function
name
Suffix
Short-cut of
macro name
Consecutive number for
same peripheral modulea
Peripheral
Macro pin
naming
Consecutive number
for same pin namesa
a)
This is an option that can be omitted if meaning is obvious
Example:
– TAUB0I0, TAUB1I5
– URTE0TX, URTE0RX, URTE1TX, URTE1RX
– CSIG0SO, CSIG0SI, CSIG0SC, CSIG0RY
1.1.2 Power supply pins
a)
Function
Prefix
Kind of
supply
Suffix
Symbol
Consecutive number for
different functionsa
VDD or VSS
Consecutive number
for different pins with
same meaninga
This is an option that can be omitted if meaning is obvious
Example:
– E0VDDn, REG0VSS
Table 1-1
Selection for Functions
Function
C
Explanation
Core supply
REG
Internal regulator supply
OSC
Oscillator supply
F
Flash module supply
E
Standard buffer supply (mainly 5V or up to 40Mhz)
B
Standard buffer supply (mainly 3.3V or beyond 40Mhz)
A
Analog module supply (e.g. ADC)
If not mentioned otherwise this document neglects suffixes for power supply
pins with same functions that can be treated as equal.
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Chapter 1
Overview
1.2 Pin Groups
Symbol
Pin group supplied by
Related pins / ports
PgE0
E0VDD / E0VSS
JP0, P0, _RESET, FLMD0, WAKE, PWDG,
VCPC0IN, VCPC1IN
PgE1
E1VDD / E1VSS
P1, P2, P3, P4
PgB0
B0VDD / B0VSS
P21, P24, P25, P27
OSCVDD / OSCVSS
X1, X2, XT1, XT2
PgA0
A0VDD / A0VSS
P10, P11, ADCA0Im
PgA1
A1VDD / A1VSS
P12, P13
PgOSC
1.3 General measurement conditions
1.3.1 AC characteristic measurement condition
AC test input waveform
xVDD
xVSS
7*)NJO
7*-NBY
.FBTVSFNFOU
7*)NJO
7*-NBY
AC test output waveform
xVDD
xVSS
70)NJO
70-NBY
.FBTVSFNFOU
70)NJO
70-NBY
Standard AC test condition is 70%/30% of the applied IO supply voltage
(XmVDD) if not otherwise stated in the according AC timing specification of an
interface.
AC Test Condition: Ext. Capacitive Load
DUT
R01DS0144ED0100
Electrical Target Specification
Load on test:
CL = 50pF
11
Chapter 2
Absolute maximum ratings
Chapter 2 Absolute maximum ratings
2.1 Supply voltages
Table 2-1
VDD Data
Parameter
Symbol
System
Ratings
Unit
CVDD
-0.5 ~ 1.6
V
FVDD
-0.5 ~ 6.0
V
OSCVDD
-0.5 ~ 6.0
V
REG0VDD
-0.5 ~ 6.0
V
REG1VDD
-0.5 ~ 6.0
V
REG2VDD
-
V
REG3VDD
-
V
E0VDD
-0.5 ~ 6.0
V
E1VDD
-0.5 ~ 6.0
V
Port
B0VDD
-0.5 ~ 6.0
V
ADCA0
A0VREFP
-0.3 ~ A0VDD+0.3
-0.3~6.0
V
ADCA0
A0VDD
-0.5 ~ 6.0
V
A1VDD
-0.5 ~ 6.0
V
A1VREFP
-0.3 ~ A1VDD+0.3
-0.3~6.0
V
Ratings
Unit
System
Ports
ADCA1
Table 2-2
Condition
VSS Data
Parameter
Symbol
System
CVSS
-0.5 ~0.5
V
FVSS
-0.5 ~0.5
V
OSCVSS
-0.5 ~0.5
V
REG0VSS
-0.5 ~0.5
V
REG1VSS
-0.5 ~0.5
V
REG2VSS
-
V
REG3VSS
-
V
E0VSS
-0.5 ~0.5
V
E1VSS
-0.5 ~0.5
V
B0VSS
-0.5 ~0.5
V
A0VSS
-0.5 ~0.5
V
A0VREFM
-0.3 ~ A0VDD+0.3
-0.3~6.0
V
A1VSS
-0.5 ~0.5
V
A1VREFM
-0.3 ~ A1VDD+0.3
-0.3~6.0
V
System
Ports
ADC0
ADC1
R01DS0144ED0100
Electrical Target Specification
Condition
12
Chapter 2
Absolute maximum ratings
2.2 Port voltages
Table 2-3
Parameter
Input
a)
b)
Port Input voltage
Pin Group
Symbola
PgE0
VI0
PgE1
voltageb
Condition
Ratings
Unit
E0VDD≤5.5
-0.5 ~ E0VDD+0.5
V
VI1
E1VDD≤5.5
-0.5 ~ E1VDD+0.5
V
PgB0
VI2
B0VDD≤5.5
-0.5 ~ B0VDD+0.5
V
PgOSC
VI5
OSCVDD≤5.5
-0.5 ~ OSCVDD+0.5
V
PgA0
VI3
A0VDD+0.3
V
PgA1
VI4
A1VDD+0.3
V
The symbols reflect all supplies within the device series. Therefore not every symbol is available for each
product.
The characteristics of the alternative-function pins are the same as those of the port pins unless otherwise
specified.
R01DS0144ED0100
Electrical Target Specification
13
Chapter 2
Absolute maximum ratings
2.3 Port current
Table 2-4
High level port output current
Pin Groupa
Parameter
Symbol
PgE0
PgE1
High level output
current
IOH
PgA0
a)
High level output
current
PgA1
IOH
High level output
current
PgB0
IOH
Max. spec
1 pin of PgE0
-10
Power supply of PgE0
-50
1 pin of PgE1
-10
Power supply of PgE1
-150
1 pin of PgA0
-10
Power supply of PgA0
-25
1 pin of PgA1
-10
Power supply of PgA1
-25
1 pin of PgB0
-10
Power supply of PgB0
-200
Unit
mA
mA
mA
The column reflects all supplies within the device series. Therefore not each pin group is available for each
product.
Table 2-5
Low level port output current
Pin Groupa
Parameter
Symbol
PgE0
PgE1
Low level output
current
IOL
PgA0
a)
Condition
Low level output
current
PgA1
IOL
Low level output
current
PgB0
IOL
Condition
Max. spec
1 pin of PgE0
10
Power supply of PgE0
50
1 pin of PgE1
10
Power supply of PgE1
150
1 pin of PgA0
10
Power supply of PgA0
25
1 pin of PgA1
10
Power supply of PgA1
25
1 pin of PgB0
10
Power supply of PgB0
150
Unit
mA
mA
mA
The column reflects all supplies within the device series. Therefore not each pin group is available for each
product.
2.4 Capacitance
Parameter
Symbol
Input capacitance
CI
Input/Output capacitance
CIO
Output capacitance
CO
R01DS0144ED0100
Electrical Target Specification
Condition
f = 1 MHz
0V for non measurement pins
Max. spec
Unit
15
pF
15
pF
15
pF
14
Chapter 2
Absolute maximum ratings
2.5 Thermal characteristics
Table 2-6
Thermal characteristics
Parameter
Symbol
Storage temperature
TSTG
Operating ambient
temperature
Junction temperature
Ta
Tj
Condition
Ratings
Unit
-65 ~150
(A) grade products
-40 ~85
(A1) grade products
-40 ~110
°C
-40 ~150
This section specifies the absolute maximum limitation of operating and
storage temperature.
The device’s functions are not guaranteed outside of the specified maximum
temperature ratings.
R01DS0144ED0100
Electrical Target Specification
15
Chapter 3
Power supply specification
Chapter 3 Power supply specification
3.1 Requirements for external power supply
connections
The user has to ensure a low resistive connection of all VSS pins on the PCB.
This specification denotes ground supply pins as:
• VSS = OSCVSS = REGnVSS = EnVSS = BnVSS = AnVSS = AnVREM =
CVSS = 0V
in the further text.
With
• EnVSS = E0VSS = E1VSS
• BnVSS = B0VSS
• REGnVSS = REG0VSS = REG1VSS
• AnVSS = A0VSS = A1VSSAnVREFM = A0VREFM = A1VREFM
The user has to ensure a low resistive connection of all VDD pins to the related
power supply. This specification denotes power supply pins as:
• EnVDD, BnVDD, FVDD, REGnVDD, OSCVDDCVDD, AnVDD and
AnVREFP.
in the further text.
With
• EnVDD = E0VDD = E1VDD
• BnVDD = B0VDD
• REGnVDD = REG0VDD = REG1VDD.
• AnVDD = A0VDD = A1VDD
• AnVREFP = A0VREFP = A1VREFP
• I/OVDD = AnVDD, EnVDD, B0VDD, FVDD, OSCVDD
3.2 Power area definitions
The device consists of the following power areas:
• AWO (Always On area)
• ISO0 (Isolated area 0)
• ISO1 (Isolated area 1)
The table below lists the related core and port voltage supply of each power
area:
R01DS0144ED0100
Electrical Target Specification
16
Chapter 3
Power supply specification
Table 3-1
Power
Area
AWO
ISO0
ISO1
Power areas supply voltages
Supply voltage
Related pins
Core supply
REG0VDD, REG0VSS, REG0C
Port Supply
E0VDD, E0VSS
Other
OSCVDD, OSCVSS
FVDD0
Core supply
REG1VDD, REG1VSS
CVDD, CVSS
Port Supply
E1VDD, E1VSS
Other
A0VREFP, A0VREFM
A0VDD, A0VSS
Core supply
REG1VDD, REG1VSS
CVDD, CVSS
Port Supply
B0VDD, B0VSS
Other
A1VDD, A1VSS
A1VREFP, A1VREFM
3.3 Power supply groups
For each of the following power supply groups the same voltage must by
supplied:
Table 3-2
Power supply groups
Power supply
group
R01DS0144ED0100
Electrical Target Specification
Related pins
#1
REG0VDD, REG1VDD, FVDD, OSCVDD, E0VDD, E1VDD
#2
B0VDD
#3
-
#4
CVDD
#5
A0VDD, A0VREFP
#6
A1VDD, A1VREFP
#7
All VSS
17
Chapter 3
Power supply specification
3.4 Supply voltages
Table 3-3
VDD Data
Parameter
Symbol
System supply voltage
Condition
Ratings
Unit
Min
Typ
Max
FVDD
VPOC
-
5.5
V
System supply voltage
OSCVDD
VPOC
-
5.5
V
System supply voltage
REG0VDD
VPOC
-
5.5
V
System supply voltage
REG1VDD
VPOC
-
5.5
V
System supply voltage
REG2VDD
-
-
-
V
System supply voltage
REG3VDD
-
-
-
V
System supply voltage
CVDD
1.1
-
1.3
V
System supply voltage
slopes
AIVS
-
-
5.6
V/ms
Port supply voltages
E0VDD
VPOC
-
5.5
V
Port supply voltages
E1VDD
VPOC
-
5.5
V
VPOC
-
5.5
V
Port supply voltages
REG0VDD = REG1VDD
REG1VDD = 3.0V to 5.5V
B0VDD
B0VDD ≤ power supply group #1 voltages
ADC supply voltages
A0VDD
12bit resolution
4.5
-
5.5
V
ADC supply voltages
A0VDD
10bit resolution
VPOC
-
5.5
V
ADC supply voltages
A0VREFP
A0VDD
-
A0VDD
V
12bit resolution
4.5
-
5.5
V
10bit resolution
VPOC
-
5.5
V
A1VREFP-A1VREFM > A1VDD/2
A1VDD
-
A1VDD
V
ADC supply voltages
ADC supply voltages
ADC supply voltages
A1VDD
A1VREFP
R01DS0144ED0100
Electrical Target Specification
18
Chapter 3
Power supply specification
3.4.1 AWO Regulator characteristics
Table 3-4
AWO Regulator characteristics
Parameter
Symbol
Regulator Output
voltage
VRO
System supply voltage
slope
RAVS
Capacitance on
REG0C
REG0C
Output voltage
stabilization time
TRAA
Ratings
Condition
Unit
Min
Typ
Max
1.1
1.2
1.3
V
-
-
1800
V/ms
3.29
4.7
6.11
µF
After REG0VDD reaches 3.0V
-
-
1
ms
After DeepStop mode
-
-
0.5
ms
0V to 3.0V
During power-up sequence
REG0VDD
VPOC
RAVS
VRO
VROMIN
TRAA
After DeepStop mode
REG0VDD
VPOC to 5.5V
VRO
VROMIN
TRAA
DeepStop
Release timing
3.4.2 Amplifier characteristics
Parameter
Symbol
System supply voltage
REG1VDD
Capacitance on CVDD
CVDDC
Voltage slope
AIVS
R01DS0144ED0100
Electrical Target Specification
Condition
Ratings
Min
Typ
VPOC
For each
CVDDa
3.0V to 5.5V
Max
Unit
5.5
V
3.29
4.7
6.11
µF
-
-
5.6
V/ms
19
Chapter 3
Power supply specification
Parameter
Symbol
PTCTL1 stabilization
time
TRAI
PTCTL1 output current
IPTCTL
a)
Condition
Ratings
Unit
Min
Typ
Max
After REG1VDD reaches 3.0V
-
-
1
ms
After DeepStop mode
-
-
0.5
ms
-
-
1.55
mA
Required when using an external power transistor such as 2SD1584 (base connected to PTCTL1)
During power-up sequence
REG1VDD
3.0V
AIVS
PTCTL1
TRAI
After DeepStop mode
REG1VDD
VPOC to 5.5V
PTCTL1
TRAI
DeepStop
Release timing
R01DS0144ED0100
Electrical Target Specification
20
Chapter 3
Power supply specification
3.4.3 POC characteristics
Table 3-5
POC characteristics
Parameter
Symbol
Detection voltage
Ratings
Condition
Unit
Min
Typ
Max
VPOC
2.8
2.9
3.0
V
Voltage slope 1
PVS1
0.18
-
1800
V/ms
Voltage slope 2
PVS2
0.0018
-
1800
V/ms
Response time 1
tPTHD
From detect voltage to release of reset
signal.
Voltage slope = PVS1, PVS2
-
-
2
ms
Response time 2
tPD
From detect voltage to occurence of
reset signal
Voltage slope = PVS2
-
-
2
ms
VDD minimum width
tPW
0.2
-
-
ms
VDD
Pvs2
D etect voltage(MAX.)
D etect voltage(TYP.)
D etect voltage(MIN.)
Pvs1
tPW
tPTHD
tPTHD
tPD
3.4.4 Voltage Comparator characteristics
Table 3-6
VCMP characteristics
Parameter
Symbol
Input voltage range of VCPCnIN
Note
R01DS0144ED0100
Electrical Target Specification
VICMP
Condition
Ratings
Min
Typ
Max
REG0VSS
-
REG0VDD
Unit
V
VDD: REG0VDD
21
Chapter 3
Power supply specification
3.5 Power-up/-down sequence of external supply
voltages
3.5.1 External FLMDn Resistors
Valid for all conditions described in the following
Parameter
Symbol
Condition
Ratings
Min
Typ
Max
Unit
FLMD0 external pull-down resistor
R1
82
-
-
kΩ
FLMD1 external pull-down resistor
R2
-
10
-
kΩ
3.5.2 Condition 1
RESET, WAKE and PTCTL1 are not used
Normal operating mode
Parameter
Symbol
Condition
Ratings
Min
Typ
Max
Unit
REG0VDD, REG1VDD, IOVDD (rise) to
CVDD (rise)
tR0CON
1
-
10
ms
REG0VDD, IOVDD (rise) to
FLMD0,1(≤VIL) hold time
tR0MDH
2
-
-
ms
FLMD0,1 (≤VIL) to REG0VDD, IOVDD
(fall)
tMDR0OF
0
-
-
ms
CVDD (0V) to REG0VDD, IOVDD (fall)
tCR0OF
0
-
-
ms
REGnVDD
IOVDD
3.0V
3.0V
1.1V
CVDD
tROCON
FLMD0
P0_1/FLMD1
tROCOF
VIL
VIL
tROMDH
Note
R01DS0144ED0100
Electrical Target Specification
tMDR0OF
IOVDD: AnVDD, B0VDD, EnVDD, FVDD, OSCVDD
22
Chapter 3
Power supply specification
3.5.3 Condition 2
RESET is used; WAKE and PTCTL1 are not used
Normal operating mode / Serial programming mode
Parameter
Symbol
Ratings
Condition
Min
Typ
Max
Unit
REGnVDD, IOVDD (rise) to CVDD (0V)
hold time
tR0CH
1
-
-
ms
REG0VDD, REG1VDD, IOVDD (rise) to
FLMD0,1(≤VIL) hold time
tR0MDH
1
-
-
ms
tCRR
0
-
-
ms
tMDRR
1
-
-
ms
_RESET (rise) to FLMD0,1(≥VIH or ≤VIL)
hold time
tRMDH
1
-
-
ms
FLMD0,1,MODE0,1(≤VIL) to _RESET
(≥VIH) (fall) setup time
tMDRF
0
-
-
ms
tRCF
0
-
-
ms
CVDD (0V) to REGnVDD, IOVDD (fall)
tCR0OF
0
-
-
ms
_RESET (≤VIL) (fall) to REGnVDD,
IOVDD (fall) hold time
tRR0OF
0
-
-
ms
CVDD (rise) to _RESET (rise)
FLMD0,1 (≥VIH or VIL1)
_RESET(≤VIL) (rise)
a
to
_RESET (fall) to CVDD (fall)
a)
In case of BSCAN mode set also the MODE0,1 pins.
REGnVDD
IOVDD
3.0V
3.0V
CVDD
1.1V
tR0CH
FLMD0
P0_1/FLMD1
1.1V
tCRR
tRCF
VIH
VIL
tROMDH
tCROOF
VIL
tMDRR tRMDH
VIH
_RESET
VIL
tMDRF
Note
R01DS0144ED0100
Electrical Target Specification
tRR0OF
There is no specification for _RESET rise and fall times.
23
Chapter 3
Power supply specification
3.5.4 Condition 3
RESET is not used; WAKE/PWGD is used
Normal operating mode
Parameter
Symbol
Ratings
Condition
Min
Typ
Max
Unit
REG0VDD, REG1VDD, IOVDD (rise) to
WAKE (rise) output delay time
tR0WRD
-
-
2
ms
WAKE (rise) to CVDD (rise)
tWCON
0
-
8
ms
CVDD (rise) to PWGD (rise)
tCPWDH
0
-
-
ms
REG0VDD, REG1VDD, IOVDD (rise) to
FLMD0,1(≤VIL) hold time
tR0MDH
2
-
-
ms
FLMD0,1 (≤VIL) to REG0VDD, IOVDD
(fall)
tMDR0OF
0
-
-
ms
tWCOF
0
-
8
ms
WAKE (fall) to CVDD (0V)
REG0VDD
REG1VDD
IOVDD
3.0V
3.0V
CVDD
1.1V
tWCOF
tWCON
PWGD
VIL
tCPWDH
FLMD0
P0_1/FLMD1
VIL
tROMDH
VIL
tMDR0OF
VIH
WAKE
VIL
tR0WRD
The WAKE signal falls at the same time as the fall of the IOVDD voltage due to
the lack of output voltage.
Even if REG0VDD keeps some voltage, the WAKE signal falls at least 2ms
after the POC detection.
R01DS0144ED0100
Electrical Target Specification
24
Chapter 3
Power supply specification
3.5.5 Condition 4
RESET and WAKE/PWGD are used.
Normal operating mode / Serial programming mode / BSCAN mode
Parameter
Symbol
Condition
Ratings
Min
Typ
Max
Unit
REG0VDD, REG1VDD, IOVDD (rise) to
FLMD0,1 (≤VIL) hold time
tR0MDH
1
-
-
ms
FLMD0,1 (VIH or VIL) a to _RESET (rise)
tMDRR
1
-
-
ms
_RESET (rise) to CVDD (rise)
tRCON
0
-
10
ms
WAKE (rise) to CVDD (rise)
tWCON
0
-
-
ms
tCPWDH
0
-
-
ms
tRMDH
1
-
-
ms
tMDRF
0
-
-
ms
_RESET (fall) to CVDD (fall)
tRCF
0
-
10
ms
WAKE (fall) to CVDD (fall)
tWCF
0
-
-
ms
PWGD (VIH) to CVDD (fall)
tPCS
0
-
-
ms
tCR0OF
0
-
-
ms
CVDD (rise) to PWGD (rise)
_RESET (rise) to FLMD0,1(VIH or VIL)
hold time
a
FLMD0,1 (≤VIL) to _RESET (fall)
CVDD (0V) to REG0VDD, IOVDD (fall)
a)
In case of BSCAN mode set also the MODE0,1 pins.
REG0VDD
REG1VDD
IOVDD
3.0V
3.0V
CVDD
1.1V
1.1V
tRCON
tRCF
tWCON
tCR0OF
tWCF
VIH
PWGD
VIL
tWPF
tCPWDH
tPR0OF
VIH
FLMD0
P0_1/FLMD1
VIL
tR0MDH
VIL
tMDRR tRMDH
VIH
VIL
_RESET
tMDRF
WAKE
VIH
R01DS0144ED0100
Electrical Target Specification
VIL
25
Chapter 3
Power supply specification
3.5.6 Condition 5
PTCTL1 is used
Normal operating mode
Parameter
Symbol
Condition
Ratings
Min
Typ
Max
Unit
REG0VDD, REG1VDD, IOVDD (rise) to
PTCTL1 (rise) setup time
tR1PTON
-
-
1
ms
REG0VDD, REG1VDD, IOVDD (rise) to
CVDD (rise) byPTCTL1 (rise)
tR0CON
1
-
10
ms
REG0VDD, REG1VDD, IOVDD (rise) to
FLMD0,1(≤VIL) hold time
tR0MDH
2
-
-
ms
FLMD0,1 (≤VIL) to REG0VDD,
REG1VDD, IOVDD (fall)
tMDR0OF
0
-
-
ms
REG0VDD, REG1VDD, IOVDD (fall) to
PTCTL1 (fall)
tR1PTOF
-
-
1
ms
PTCTL1 (fall) to CVDD (fall)
tPTCOF
0
-
8
ms
REG0VDD
REG1VDD
IOVDD
3.0V
3.0V
1.1V
CVDD
tR0CON
FLMD0
P0_1/FLMD1
VIL
tR0MDH
tPTCOF
VIL
tMDR0OF
PTCTL1
tR1PTON
R01DS0144ED0100
Electrical Target Specification
tR1PTOF
26
Chapter 3
Power supply specification
3.5.7 Condition 6
RESET is used; PTCTL1 is used
Normal operating mode / Serial programming mode / BSCAN mode
Parameter
Symbol
Condition
Ratings
Min
Typ
Max
Unit
REG0VDD, REG1VDD, IOVDD (rise) to
CVDD (0V) hold time
tR0CH
-
-
1
ms
REG1VDD (rise) to PTCTL1 (rise) setup
time
tR1PTON
-
-
1
ms
REG0VDD, IOVDD (rise) to FLMD0,1
(≤VIL) hold time
tR0MDH
1
-
-
ms
tCRR
0
-
-
ms
FLMD0,1 (VIH or VIL) to _RESET (rise)
tMDRR
1
-
-
ms
_RESET (rise) to FLMD0,1 (VIH or VIL)
hold time
tRMDH
1
-
-
ms
FLMD0,1,MODE0,1 (≤VIL) a to _RESET
(fall)
tMDRF
0
-
-
ms
_RESET (fall) to REG0VDD, IOVDD (fall)
tRR0OF
0
-
-
ms
REG1VDD (fall) to PTCTL1 (fall)
tR1PTOF
-
-
1
ms
PTCTL1 (fall) to CVDD (fall)
tPTCOF
0
-
8
ms
CVDD (rise) to _RESET (rise)
a
a)
In case of BSCAN mode set also the MODE0,1 pins.
REG0VDD
REG1VDD
IOVDD
3.0V
3.0V
CVDD
1.1V
tCRR
tR0CH
tPTCOF
VIH
FLMD0
P0_1/FLMD1
VIL
VIL
tR0MDH
tMDRR
tRMDH
VIH
_RESET
tMDRF tRR0OF
PTCTL1
tR1PTON
Note
R01DS0144ED0100
Electrical Target Specification
tR1PTOF
There is no specification for _RESET rise and fall times.
27
Chapter 4
Clock generators
Chapter 4 Clock generators
4.1 CPU clock
Table 4-1
CPU clock frequency
Parameter
Symbol
CPU clock frequency
fCPU
Ratings
Condition
Unit
Min
Typ
Max
PLL based
-
-
160
MHz
SSCG based
-
-
176.64
MHz
4.2 Peripheral clock
Table 4-2
Peripheral clock frequency
Parameter
Symbol
Peripheral clock
frequency
Ratings
Condition
fPERI
Min
Typ
Max
-
-
80
Unit
MHz
4.3 Oscillator characteristics
4.3.1 Main oscillator
A ceramic or crystal resonator can be connected to the main clock input pins
as shown in figure 4-1 “Recommended Main Oscillator Circuit”
.
X1
X2
internal
external
Rd
C1
Figure 4-1
Caution
C2
Recommended Main Oscillator Circuit
Values of C1, C2 and Rd and the best setting for MOSCC.AMPSEL[1:0]
register depend on the used ceramic or crystal resonator and must be
specified in cooperation with ceramic or crystal resonator manufacturer.
The main oscillator amplifier gain for the external resonator can be selected by
MOSCC.MOSCCAMPSEL[1:0]. Thereby it can be adjusted to support a wide
R01DS0144ED0100
Electrical Target Specification
28
Chapter 4
Clock generators
range of frequencies to cope with different external resonators and their
external circuitry.
As an example a typical setting for quartz crystals is shown in Table 4-3
“Typical setting of MOSCC.AMPSEL[1:0] for different quartz crystals
frequencies”.
Note
Table 4-3
For details to the setting of MOSCC.MOSCCAMPSEL[1:0] please refer to the
user manual.
Typical setting of MOSCC.AMPSEL[1:0] for different quartz crystals
frequencies
MOSCC.AMPSEL[
1:0]
Amplification
gain
Typical condition for quartz
crystals
00
high
16 < fMOSC ≤ 20 MHz
01
medium
8 < fMOSC ≤ 16 MHz
10
low
4 < fMOSC≤ 8 MHz
11
very low
4 MHz
(1)
Main oscillator charactrisitics
Table 4-4
Main oscillator characteristics
Parameter
Symbol
MainOSC frequency
Cautions
Condition
fMOSC
Ratings
Min
Typ
Max
4
-
20
Unit
MHz
1. External clock input is prohibited.
2. General guidance for PCB layout:
• Keep the wiring length as short as possible.
• Do not cross the wiring with other signal lines.
• Do not route this circuit close to a signal line with high fluctuating current
flow.
• Always make the ground point of the oscillator capacitor the same
potential as REG0VSS and OSCVSS.
• Do not ground the capacitor to a ground pattern with high current flow.
• Do not tap signals from the oscillator.
4.3.2 Sub-oscillator
A crystal resonator can be connected to the sub clock input pins as shown in
figure 4-2 “Recommended Sub Oscillator Circuit”
R01DS0144ED0100
Electrical Target Specification
29
Chapter 4
Clock generators
.
XT1
XT2
internal
external
Rds
C1s
Figure 4-2
Caution
C2s
Recommended Sub Oscillator Circuit
Values of C1s, C2s and Rds depend on the used crystal and must be specified
in cooperation with crystal manufacturer.
(1)
Sub-oscillator characteristics
Table 4-5
Sub-oscillator characteristics
Parameter
Symbol
MainOSC frequency
Condition
fSOSC
Ratings
Min
Typ
Max
-
32.768
-
Unit
kHz
4.3.3 Internal oscillator
Table 4-6
Internal oscillator characteristics
Parameter
Symbol
fRL
Lowspeed OSC frequency
fRLLP
fRH
Highspeed OSC frequency
fRHLP
Highspeed OSC
stabilization time
R01DS0144ED0100
Electrical Target Specification
TRHSTB
Condition
Ratings
Unit
Min
Typ
Max
220.8
240
259.2
kHz
• DeepStop mode with
PSC0.REGSTP = 1
216
240
264
kHz
• Other than DeepStop mode
• DeepStop mode with
PSC0.REGSTP = 0
7.2
8.0
8.8
MHz
• DeepStop mode with
PSC0.REGSTP = 1
6.64
8.0
8.8
MHz
-
-
19
µs
• Other than DeepStop mode
• DeepStop mode with
PSC0.REGSTP = 0
30
Chapter 4
Clock generators
4.4 PLL Characteristics
Table 4-7
Parameter
PLL characteristics
Symbol
Input frequency
fxn
Output frequency
fxxn
Lock time
Condition
Unit
Min
Typ
Max
PLL mode and SSCG mode
4
-
20
MHz
PLL mode
25
-
160
MHz
22.40
-
176.6
MHz
SSCG mode
TLCKPn
PLL mode
-
-
650
µs
TLCKSn
SSCG mode
-
-
1300
µs
-150
-
150
ps
-1.275
-
1.275
ns
Period jittera
tPJn
Peak to peak,
fixed frequency mode,
Pr=2
Long term jittera
tLTJn
PLL mode, Peak to peak,
term=1µs
fVCOOUT=160MHz (Pr=2)
a)
Ratings
Not tested in production. Specified by design.
R01DS0144ED0100
Electrical Target Specification
31
Chapter 5
Supply current specification
Chapter 5 Supply current specification
5.1 Total supply current for µPDF70F3564
Table 5-1
Total supply current
Powera
Conditionb
Item
RUN
mode
HALT
mode
a)
b)
Specification
Unit
ISO0
ISO1
8MHz
intOSC
Main
OSC
Sub
OSC
PLL
CPU
Freq
Peripherals
ON
ON
ON
ON
ON
ON
160
Min.
Typ.
(A)
(A1)
WORKING
247
394
416
mA
ON
ON
ON
ON
ON
ON
160
STOPPED
153
-
-
mA
ON
ON
ON
OFF
ON
OFF
8
WORKING
30
60
62
mA
ON
ON
ON
OFF
ON
OFF
8
STOPPED
22
-
-
mA
ON
OFF
ON
ON
ON
ON
160
WORKING
176
285
300
mA
ON
OFF
ON
ON
ON
ON
160
STOPPED
140
-
-
mA
ON
OFF
ON
OFF
ON
OFF
8
WORKING
24
50
52
mA
ON
OFF
ON
OFF
ON
OFF
8
STOPPED
21
-
-
mA
ON
ON
ON
ON
ON
ON
160
WORKING
236
305
311
mA
ON
ON
ON
ON
ON
ON
160
STOPPED
150
-
-
mA
ON
ON
ON
OFF
ON
OFF
8
WORKING
29
50
51
mA
ON
ON
ON
OFF
ON
OFF
8
STOPPED
21
-
-
mA
STOP
mode
ON
ON
OFF
OFF
OFF
OFF
-
STOPPED
2.5
57
67
mA
ON
OFF
OFF
OFF
OFF
OFF
-
STOPPED
2.2
49
57
mA
DEEPSTOP
mode
OFF
OFF
OFF
OFF
OFF
OFF
-
STOPPED
0.06
3.4
3.6
mA
OFF
OFF
ON
OFF
OFF
OFF
-
STOPPED
0.60
8.0
9.2
mA
OFF
OFF
ON
OFF
ON
OFF
-
STOPPED
0.60
8.1
9.2
mA
The AWO is always ON.
The 240kHz IntOSC is always ON.
Notes
1. The above currents do not include port buffer currents or ADC currents.
2. The currents in run mode include currents for self-programming and
EEPROM emulation.
3. The current of FlexRay is not included in case of CPU frequency = 8MHz.
4. The ‘typical’ specification is for reference only and not a guaranteed value.
The ‘typical’ specification is applicable under the following conditions:
• Ta = 25°C
• REGnVDD=FVDD=OSCVDD=EmVDD=B0VDD=AmVDD=AmVREFP=5.0V
(n=0-3, m=0-1).
• CVDD = 1.2V
• REGnVSS=OSCVSS=EmVSS=B0VSS=AmVSS=AmVREFM=0V
(n=0-3, m=0-1)
R01DS0144ED0100
Electrical Target Specification
32
Chapter 5
Supply current specification
5.2 CVDD supply current for µPDF70F3564
Table 5-2
CVDD supply current
Powera
Conditionb
Item
RUN
mode
HALT
mode
a)
b)
Specification
Unit
ISO0
ISO1
8MHz
intOSC
Main
OSC
Sub
OSC
PLL
CPU
Freq
Peripherals
ON
ON
ON
ON
ON
ON
160
Min.
Typ.
(A)
(A1)
WORKING
216
347
365
mA
ON
ON
ON
ON
ON
ON
160
STOPPED
129
-
-
mA
ON
ON
ON
OFF
ON
OFF
8
WORKING
18
41
43
mA
ON
ON
ON
OFF
ON
OFF
8
STOPPED
11
-
-
mA
ON
OFF
ON
ON
ON
ON
160
WORKING
145
237
250
mA
ON
OFF
ON
ON
ON
ON
160
STOPPED
116
-
-
mA
ON
OFF
ON
OFF
ON
OFF
8
WORKING
12
32
33
mA
ON
OFF
ON
OFF
ON
OFF
8
STOPPED
9
-
-
mA
ON
ON
ON
ON
ON
ON
160
WORKING
205
267
272
mA
ON
ON
ON
ON
ON
ON
160
STOPPED
126
-
-
mA
ON
ON
ON
OFF
ON
OFF
8
WORKING
17
35
36
mA
ON
ON
ON
OFF
ON
OFF
8
STOPPED
10
-
-
mA
STOP
mode
ON
ON
OFF
OFF
OFF
OFF
-
STOPPED
1.7
37
43
mA
ON
OFF
OFF
OFF
OFF
OFF
-
STOPPED
1.3
28
33
mA
DEEPSTOP
mode
OFF
OFF
OFF
OFF
OFF
OFF
-
STOPPED
0.0
0.0
0.0
mA
OFF
OFF
ON
OFF
OFF
OFF
-
STOPPED
0.0
0.0
0.0
mA
OFF
OFF
ON
OFF
ON
OFF
-
STOPPED
0.0
0.0
0.0
mA
The AWO is always ON.
The 240kHz IntOSC is always ON.
Notes
1. The above currents do not include port buffer currents or ADC currents.
2. The currents in run mode include currents for self-programming and
EEPROM emulation.
3. The current of FlexRay is not included in case of CPU frequency = 8MHz.
4. The ‘typical’ specification is for reference only and not a guaranteed value.
The ‘typical’ specification is applicable under the following conditions:
• Ta = 25°C
• REGnVDD=FVDD=OSCVDD=EmVDD=B0VDD=AmVDD=AmVREFP=5.0V
(n=0-3, m=0-1).
• CVDD = 1.2V
REGnVSS=OSCVSS=EmVSS=B0VSS=AmVSS=AmVREFM=0V
(n=0-3, m=0-1)
5.3 Voltage Comparator characteristics
Table 5-3
VCMP characteristics
Parameter
Symbol
VCMP current
IVCMP
R01DS0144ED0100
Electrical Target Specification
Condition
Ratings
Min
Typ
Max
200
300
Unit
µA
33
Chapter 6
I/O specification
Chapter 6 I/O specification
6.1 Port Characteristics
6.1.1 Condition settings
Some of the conditions mentioned in this chapter can be selected by software.
The related register settings are described below:
(1)
Input characteristic
The input characteristics can be selected by the registers PIS and PISE with
the following coding:
Table 6-1
a)
R01DS0144ED0100
Electrical Target Specification
Input characteristic selection
PISE
PIS
Reference in
UserManual
Electrical
characteristic
0
0
Type 1
CMOSa
0
1
Type 2
Schmitt2
1
0
Type 3
Schmitt1
1
1
Type 4
Schmitt4
Default setting after reset
34
Chapter 6
I/O specification
6.1.2 PgE0
Table 6-2
Parameter
High level input voltage
Low level input voltage
PgE0 characteristics
Symbol
VIH
VIL
High level output voltage
VOH
Low level output voltage
VOL
Input hysteresis of Schmit
VH
Condition
Ratings
Min
Typ
Max
CMOS
0.7·E0VDD
-
E0VDD+0.3
Schmitt1
0.7·E0VDD
-
E0VDD+0.3
Schmitt2
0.8·E0VDD
-
E0VDD+0.3
Schmitt4 (E0VDD=VPOC~3.0)
0.84·E0VDD
-
E0VDD+0.3
Schmitt4 (E0VDD=3.0~5.5)
0.8·E0VDD
-
E0VDD+0.3
CMOS
-0.5
-
0.3·E0VDD
Schmitt1
-0.5
-
0.3·E0VDD
Schmitt2
-0.5
-
0.2·E0VDD
Schmitt4 (E0VDD=VPOC~3.0)
-0.5
-
0.4·E0VDD
Schmitt4 (E0VDD=3.0~5.5)
-0.5
-
0.5·E0VDD
IOH = -5mA
E0VDD-1.0
-
IOH = -100µA
E0VDD-0.5
-
IOL = 5mA
-
-
0.4
IOL = 100µA
-
-
0.4
Schmitt1
0.3
-
Schmitt2
0.3
-
Schmitt4
0.1
-
Unit
V
V
V
V
V
Internal pull-up resistor
RU
20
40
100
kΩ
Internal pull-down resistor
RD
20
40
100
kΩ
High level port output
current
IOH
Power supply of PgE0
-
-
-20
mA
Low level port output
current
IOL
Power supply of PgE0
-
-
20
mA
High level input leakage
current
ILIH
VI = E0VDD
-
-
0.5
µA
Low level input leakage
current
ILIL
VI = 0V
-
-
-0.5
µA
High level output leakage
current
ILOH
VO = E0VDD
-
-
0.5
µA
Low level output leakage
current
ILOL
VO = 0V
-
-
-0.5
µA
Slow mode
-
-
25
Fast mode
-
-
40
Slow mode
-
-
15
ns
Fast mode
-
-
8
ns
Slow mode
-
-
15
ns
Fast mode
-
-
8
ns
Output frequency
fO
Rise time (output)
tKRP
Fall time (output)
tKFP
R01DS0144ED0100
Electrical Target Specification
MHz
35
Chapter 6
I/O specification
6.1.3 PgE1
Table 6-3
Parameter
High level input voltage
Low level input voltage
PgE1 characteristics
Symbol
VIH
VIL
High level output voltage
VOH
Low level output voltage
VOL
Input hysteresis of Schmit
VH
Condition
Ratings
Min
Typ
Max
CMOS
0.7·E1VDD
-
E1VDD+0.3
Schmitt1
0.7·E1VDD
-
E1VDD+0.3
Schmitt2
0.8·E1VDD
-
E1VDD+0.3
Schmitt4 (E1VDD=VPOC~3.0)
0.84·E1VDD
-
E1VDD+0.3
Schmitt4 (E1VDD=3.0~5.5)
0.8·E1VDD
-
E1VDD+0.3
CMOS
-0.5
-
0.3·E1VDD
Schmitt1
-0.5
-
0.3·E1VDD
Schmitt2
-0.5
-
0.2·E1VDD
Schmitt4 (E1VDD=VPOC~3.0)
-0.5
-
0.4·E1VDD
Schmitt4 (E1VDD=3.0~5.5)
-0.5
-
0.5·E1VDD
E1VDD-1.0
-
E1VDD-0.5
-
IOL = 5mAa
-
-
0.4
IOL = 100µA
-
-
0.4
Schmitt1
0.3
-
Schmitt2
0.3
-
Schmitt4
0.1
-
IOH =
-5mAa
IOH = -100µA
Unit
V
V
V
V
V
Internal pull-up resistor
RU
20
40
100
kΩ
Internal pull-down resistor
RD
20
40
100
kΩ
High level port output
current
IOH
Power supply of PgE1
-
-
-150
mA
Low level port output
current
IOL
Power supply of PgE1
-
-
150
mA
High level input leakage
current
ILIH
VI = E1VDD
-
-
0.5
µA
Low level input leakage
current
ILIL
VI = 0V
-
-
-0.5
µA
High level output leakage
current
ILOH
VO = E1VDD
-
-
0.5
µA
Low level output leakage
current
ILOL
VO = 0V
-
-
-0.5
µA
Slow mode
-
-
25
Fast mode
-
-
40
Slow mode
-
-
15
ns
Fast mode
-
-
8
ns
Slow mode
-
-
15
ns
Fast mode
-
-
8
ns
Output frequency
fO
Rise time (output)
tKRP
Fall time (output)
tKFP
a)
MHz
The maximum number of PgE1 pins with ‘ON’ signal at the same time is 5 in ‘Slow mode’.
The maximum number of PgE1 pins with ‘ON’ signal at the same time is 8 in ‘Fast mode’.
See the UM for the related description of the Port drive strength control.
R01DS0144ED0100
Electrical Target Specification
36
Chapter 6
I/O specification
6.1.4 PgB0
Table 6-4
Parameter
High level input voltage
Low level input voltage
PgB0 characteristics
Symbol
VIH
VIL
High level output voltage
VOH
Low level output voltage
VOL
Input hysteresis of Schmit
VH
Condition
Ratings
Min
Typ
Max
CMOS
0.7·B0VDD
-
B0VDD+0.3
Schmitt1
0.7·B0VDD
-
B0VDD+0.3
Schmitt2
0.8·B0VDD
-
B0VDD+0.3
Schmitt4 (B0VDD=VPOC~3.0)
0.84·B0VDD
-
B0VDD+0.3
Schmitt4 (B0VDD=3.0~5.5)
0.8·B0VDD
-
B0VDD+0.3
CMOS
-0.5
-
0.3·B0VDD
Schmitt1
-0.5
-
0.3·B0VDD
Schmitt2
-0.5
-
0.2·B0VDD
Schmitt4 (B0VDD=VPOC~3.0)
-0.5
-
0.4·B0VDD
Schmitt4 (B0VDD=3.0~5.5)
-0.5
-
0.5·B0VDD
B0VDD-1.0
-
-
B0VDD-0.5
-
-
IOL = 5mAa
-
-
0.4
IOL = 100µA
-
-
0.4
Schmitt1
0.3
-
-
Schmitt2
0.3
-
-
Schmitt4
0.1
-
-
IOH =
-5mAa
IOH = -100µA
Unit
V
V
V
V
V
Internal pull-up resistor
RU
20
40
100
kΩ
Internal pull-down resistor
RD
20
40
100
kΩ
High level port output
current
IOH
Power supply of PgB0
-
-
-150
mA
Low level port output
current
IOL
Power supply of PgB0
-
-
High level input leakage
current
ILIH
VI =B0VDD
-
-
0.5
µA
Low level input leakage
current
ILIL
VI = 0V
-
-
-0.5
µA
150
mA
High level output leakage
current
ILOH
VO = B0VDD
-
-
0.5
µA
Low level output leakage
current
ILOL
VO = 0V
-
-
-0.5
µA
Slow mode
-
-
25
Fast mode
-
-
40
Slow mode
-
-
15
ns
Fast mode
-
-
8
ns
Slow mode
-
-
15
ns
Fast mode
-
-
8
ns
Output frequency
fO
Rise time (output)
tKRP
Fall time (output)
tKFP
a)
MHz
The maximum number of PgB0 pins with ‘ON’ signal at the same time is 5 in ‘Slow mode’ (Except the pins
related to the external memory interface (MEMC)).
The maximum number of PgB0 pins with ‘ON’ signal at the same time is 8 in ‘Fast mode’.
See the UM for the related description of the Port drive strength control.
R01DS0144ED0100
Electrical Target Specification
37
Chapter 6
I/O specification
6.1.5 PgA0 and PgA1
Table 6-5
Parameter
PgA0 and PGA1 characteristics
Symbol
Condition
Ratings
Min
Typ
Max
Unit
High level input voltage
VIH
CMOS
0.7·AnVDD
-
AnVDD+0.3
V
Low level input voltage
VIL
CMOS
-0.5
-
0.3·AnVDD
V
IOH = -1mA
AnVDD-1.0
-
-
IOH = -100µA
AnVDD-0.5
-
-
IOL = 1mA
-
-
0.4
IOL = 100µA
-
-
0.4
High level output voltage
VOH
V
Low level output voltage
VOL
High level port output
current
IOH
Power supply of PgA0 and
PgA1
-
-
-20
mA
Low level port output
current
IOL
Power supply of PgA0 and
PgA1
-
-
20
mA
High level input leakage
current
ILIH
VI = AnVDD
-
-
0.2
µA
Low level input leakage
current
ILIL
VI = 0V
-
-
-0.2
µA
V
High level output leakage
current
ILOH
VO = AnVDD
-
-
0.2
µA
Low level output leakage
current
ILOL
VO = 0V
-
-
-0.2
µA
Output frequency
fO
-
-
25
MHz
Rise time (output)
tKRP
-
-
15
ns
Fall time (output)
tKFP
-
-
15
ns
R01DS0144ED0100
Electrical Target Specification
38
Chapter 7
Peripherals specification
Chapter 7 Peripherals specification
7.1 Reset timing
Parameter
Symbol
RESET input High level width
tWRSH
RESET input Low level width
tWRSL
Ratings
Condition
Unit
Min
Typ
Max
Highspeed OSC is operating
450
-
-
ns
Highspeed OSC is stopped
4.7
-
-
µs
Highspeed OSC is operating
450
-
-
ns
Highspeed OSC is stopped
4.7
-
-
µs
tWRSL
tWRSH
_RESET
7.2 NMI timing
Parameter
Symbol
Ratings
Condition
Min
Typ
Max
Unit
NMI input High level width
tWNIH
300
-
-
ns
NMI input Low level width
tWNIL
300
-
-
ns
tWKRH
tWKRL
KRn
R01DS0144ED0100
Electrical Target Specification
39
Chapter 7
Peripherals specification
7.3 INTP timing
Parameter
Symbol
Condition
Ratings
Min
Typ
Max
Unit
INTPn input High level width
tWITH
300
-
-
ns
INTPn input Low level width
tWITL
300
-
-
ns
tWITH
tWITL
INTPn
7.4 FLMD0 timing
Parameter
Symbol
Condition
Ratings
Min
Typ
Max
Unit
FLMD0 input High level width
tWMDH
300
-
-
ns
FLMD0 input Low level width
tWMDL
300
-
-
ns
FLMD0 external pull down resistor
RFLMD0
82
-
-
kΩ
tWMDL
tWMDH
FLMD0
7.5 _DCUTRST timing
Parameter
Symbol
Condition
Ratings
Min
Typ
Max
Unit
_DCUTRST input High level width
tWRH
450
-
-
ns
_DCUTRST input Low level width
tWTRL
450
-
-
ns
tWTRH
tWTRL
_TRST
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Electrical Target Specification
40
Chapter 7
Peripherals specification
7.6 Timer timing
Table 7-1
Timer timing
Parameter
Symbol
Condition
Ratings
Min
Typ
Max
Unit
TAUAnI input High level
width
tTAIH
n=0
a,b
-
-
ns
TAUAnI input Low level
width
tTAIL
n=0
a,b
-
-
ns
TAUBnI input High level
width
tTBIH
n=1
ab
,
-
-
ns
TAUBnI input Low level
width
tTBIL
n=-1
a,b
-
-
ns
TAUJnI input High level
width
tTJIH
n=0,1
300
-
-
ns
TAUJnI input High level
width
tTJIH
4.7
-
-
µs
TAUJnI input High level
width
tTJIH
b
-
-
ns
TAUJnI input Low level
width
tTJIL
300
-
-
ns
TAUJnI input Low level
width
tTJIL
4.7
-
-
µs
TAUJnI input Low level
width
tTJIL
b
-
-
ns
n=0,1
TAUAnO output cycle
tTACYK
n=0
-
-
20
MHz
TAUBnO output cycle
tTBCYK
n=1
-
-
20
MHz
TAUCnO output cycle
tTCCYK
n=2-7
-
-
20
MHz
TAUJnO output cycle
tTJCYK
n=0,1
-
-
20
MHz
TAPAnESO input High level
width
tWESH
n=0
300
-
-
ns
TAPAnESO input Low level
width
tWESL
n=0
300
-
-
ns
ENCAnTmIN high level
width
tWENmH
n=0, m=A,B,Z
a,b
-
-
ns
ENCAnTmIN low level width
tWENmL
n=0, m=A,B,Z
a,b
-
-
ns
ENCAnTINm high level
width
tWENmH
n=0, m=0-1
a,b
-
-
ns
ENCAnTINm low level width
tWENmL
n=0, m=0-1
a,b
-
-
ns
a)
b)
With digital noise filter enabled: 2, 3, 4 or 5 x Tsamp + 20 (Tsamp shows sampling period specified in Noise
filter macro. More than 1 PCLK width of Timer macro must be kept regarding DNF pass through pulse width.
With digital noise filter disabled: 1xtSYNC+20 ( tSYNC: 1 PCLK of Timer macro)
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Chapter 7
Peripherals specification
tTAIH
tTBIH
tTJIH
tTAIL
tTBIL
tTJIL
TAUAnI
TAUBnI
TAUJnI
tTACYK
tTBCYK
tTCC YK
tTJCYK
TAUAnO
TAUBnO
TAUCnO
TAUJnO
tWESH
tWESL
tWENmH
tWENmL
TAPAnESO
ENCAnTmIN
ENCAnTINm
7.7 Multiplexed bus timing
Table 7-2
MEMC0CLK timing
Parameter
Symbol
Ratings
Condition
Unit
Min
Typ
Max
tMEMC
25
-
-
ns
MEMC0CLK high level width
tWKHMEM
tMEMC / 2 - 10
-
-
ns
MEMC0CLK low level width
tWKLMEM
tMEMC / 2 - 10
-
-
ns
MEMC0CLK rise time
tKRMEM
-
-
10
ns
MEMC0CLK fall time
tKFMEM
-
-
10
ns
MEMC0CLK output cycle
tMBMC
tWKHMBM
tWKLMBM
MEMC0CLK
tKRMBM
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Electrical Target Specification
t KF MBM
42
Chapter 7
Peripherals specification
7.7.1 MEMC0CLK asynchronous timing
Parameter
Symbol
Condition
Unit
Min
Typ
Max
25
-
-
ns
Bus operational period
T
Address setup time to
MEMC0ASTBZ (f)
tSAST
<1>
(1+ASW)·T-15
-
-
ns
Address hold time from
MEMC0ASTBZ (f)
tHSTA
<2>
(1+AHW)·T-15
-
-
ns
Address float delay time from
MEMC0RDZ (f)
tFRDA
<3>
-
-
6
ns
Address hold time from
MEMC0RDZ (r)
tHRDA
<4>
0
-
-
ns
Data input delay time from
MEMC0RDZ (f)
tDRDID
<5>
6
-
(1+w)·T-35
ns
Data input hold time from
MEMC0RDZ (r)
tHRDID
<6>
0
-
-
ns
Delay time from ASTB(f) to
MEMC0RDZ (f)
tDSTRD
<7>
(1+AHW)·T-15
-
-
ns
Delay time from ASTB(f) to
MEMC0WRZ (f)
tDSTWR
<8>
(1+AHW)·T-15
-
-
ns
MEMC0RDZ, MEMC0WRZ
low level width
tWRDST
<9>
(1+w)·T-10
-
-
ns
Data output delay time from
MEMC0WRZ (f)
tDWROD
<10>
-
-
10
ns
tHWRA
<11>
T-15
-
-
ns
Data output setup time to
MEMC0WRZ (r)
tSODWR
<12>
(1+w)·T-15
-
-
ns
Data output hold time from
MEMC0WRZ (r)
tHWROD
<13>
T-15
-
-
ns
MEMC0WAITZ setting delay
from MEMC0ASTBZ (f)
tSSTWT1
<14>
-
-
(1+AHW)·T (2·HEAPCLK+35)
ns
MEMC0WAITZ hold time from
MEMC0ASTBZ (f)
tSSTWT2
<15> w≥1
-
-
(1+w+AHW)·T (2·HEAPCLK+35)
ns
MEMC0WAITZ setting delay
from Address
tHSTWT1
<16> w≥1
(w+AHW)·T(2*HEAPCLK+20)
-
-
ns
MEMC0WAITZ hold time from
Address
tHSTWT2
<17> w≥1
(1+w+AHW)·T2*HEAPCLK+20)
-
-
ns
Address hold time from
MEMC0WRZ (r)
Notes
-
Ratings
1. ASW: Number of Address Setup Wait for multiplex bus
2. AHW: Number of Address Hold Wait for multiplex bus
3. w: Number of data wait
4. In case the bus operational period (T) is shorter then 41ns, tDRDID
requires at least 1 data wait (w=1).
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Electrical Target Specification
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Chapter 7
Peripherals specification
(1)
Multiplex write cycle (Asynchronous; 1 data wait)
T1
TA
TDEW
T2
TDHW
MEMC0CLK
(output)
MEMC0CSZ4-2
(output)
MEMC0A18-16
(output)
Address
MEMC0AD15-0
(I/O)
Address
<1>
Data
<2>
MEMC0ASTBZ
(output)
<12>
<8>
<11>
<13>
<10>
MEMC0WRZ
(output)
<9>
<14>
<16>
<15>
<17>
MEMC0WAITZ
(input)
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Electrical Target Specification
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Chapter 7
Peripherals specification
(2)
Multiplex read cycle (Asynchronous; 1 data wait)
T1
TA
TDEW
T2
MEMC0CLK
(output)
MEMC0CSZ4-2
(output)
MEMC0A18-16
output)
Address
MEMC0AD15-0
(I/O)
Data
Address
<1>
<2>
MEMC0ASTBZ
(output)
<3>
<7>
<4>
<5>
<6>
MEMC0RDZ
(output)
<9>
<14>
<16>
<15>
<17>
MEMC0WAITZ
(input)
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Electrical Target Specification
45
Chapter 7
Peripherals specification
7.7.2 MEMC0CLK synchronous timing
Parameter
Bus operational period
Symbol
Condition
T
Ratings
Unit
Min
Typ
Max
25
-
-
ns
Delay time from MEMC0CLK (r) to
address
tDKA
<18>
0
-
12
ns
Delay time from MEMC0CLK (r) to
address float
tFKA
<19>
0
-
12
ns
Delay time from MEMC0CLK (r) to
ASTB (f)
tDKST
<20>
0
-
11
ns
Delay time from MEMC0CLK (r) to
MEMC0RDZ and MEMC0WRZ
tDKRDWR
<21>
-2.5
-
6
ns
Data input setup time
(from MEMC0CLK (r))
tSIDK
<22>
10
-
-
ns
Data input hold time
(from MEMC0CLK (r))
tHKID
<23>
2.5
-
-
ns
Data output delay time
(from MEMC0CLK (r))
tDKOD
<24>
-
-
11
ns
MEMC0WAITZ setup time
(to MEMC0CLK (r))
tSWTK
<25> B0VDD≥3.5V
23
-
-
ns
<25> B0VDD<3.5V
27
-
-
ns
MEMC0WAITZ hold time
(from MEMC0CLK (r))
tHKWT
<26>
2.5
-
-
ns
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Electrical Target Specification
46
Chapter 7
Peripherals specification
(1)
Multiplex write cycle (Synchronous; 1 data wait)
T1
TA
TDEW
TDEW
T2
TDHW
MEMC0CLK
(output)
<18>
MEMC0CSZ4-2
(output)
<24>
MEMC0A18-16
(output)
MEMC0AD15-0
(I/O)
Address
Address
Data
<20>
MEMC0ASTBZ
(output)
<21>
<21>
MEMC0WRZ
(output)
<25>
<26>
<25>
<26>
MEMC0WAITZ
(input)
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Electrical Target Specification
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Chapter 7
Peripherals specification
(2)
Multiplex read cycle (Synchronous; 1 data wait)
T1
TA
TDEW
TDEW
T2
MEMC0CLK
(output)
<18>
<19>
MEMC0CSZ4-2
(output)
MEMC0A18-16
output)
Address
<22>
MEMC0AD15-0
(I/O)
<23>
Data
Address
<20>
MEMC0ASTBZ
(output)
<21>
<21>
MEMC0RDZ
(output)
<25>
<26>
<25>
<26>
MEMC0WAITZ
(input)
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Electrical Target Specification
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Chapter 7
Peripherals specification
7.8 CSI timing
7.8.1 Master modes
(1)
Table 7-3
CSIG timing
CSIG timing (Master mode)
Parameter
Symbol
Macro Operation clock cycle
time
Condition
Ratings
Unit
Min
Typ
Max
tKCYGn
12.5
-
-
ns
CSIGnSC cycle time
tKCYMGn
100
-
-
ns
CSIGnSC high level width
tKWHMGn
0.5 · tKCYMGn-10
-
-
ns
CSIGnSC low level width
tKWLMGn
0.5 · tKCYMGn-10
-
-
ns
CSIGnSI setup time
(vs. CSIGnSC )
tSSIMGn
[email protected]=1
30
-
-
ns
CSIGnSI setup time
(vs. CSIGnSC )
tSSIMGn
[email protected]=0
38
-
-
ns
CSIGnSI hold time
(vs. CSIGnSC)
tHSIMGn
0
-
-
ns
CSIGnSO output delay
(vs. CSIGnSC)
tDSOMGn
-
-
7
ns
CSIGnRYI setup time
(vs. CSIGnSC)
tSRYIGn
CSIGnCTL1.CSIGnSIT=x
CSIGnCTL1.CSIGnHSE=1
2 · tKCYGn+25
-
-
ns
CSIGnRYI High level width
tWRYIGn
CSIGnCTL1.CSIGnHSE=1
tKCYGn- 5.0
-
-
ns
Note
R01DS0144ED0100
Electrical Target Specification
n: Number of macro instances. Refer to the User Manual for the detailed
specification.
49
Chapter 7
Peripherals specification
(2)
Table 7-4
CSIH timing master mode
CSIH timing (Master mode)
Parameter
Symbol
Macro Operation clock cycle
time
Condition
Ratings
Unit
Min
Typ
Max
tKCYHn
12.5
-
-
ns
CSIHnSC cycle time
tKCYMHn
100
-
-
ns
CSIHnSC high level width
tKWHMHn
0.5 · tKCYMHn-10
-
-
ns
CSIHnSC low level width
tKWLMHn
0.5 · tKCYMHn-10
-
-
ns
CSIHnSI setup time
(vs. CSIHnSC )
tSSIMHn
[email protected]=1
30
-
-
ns
[email protected]=0
38
-
-
ns
CSIHnSI hold time
(vs. CSIHnSC)
tHSIMHn
0
-
-
ns
CSIHnSO output delay
(vs. CSIHnSC)
tDSOMHn
-
-
7
ns
CSIHnRYI setup time
(vs. CSIHnSC)
tSRYIHn
CSIHnCTL1.CSIHnSIT=x
CSIHnCTL1.CSIHnHSE=1
2 · tKCYHn+25
-
-
ns
CSIHnRYI High level width
tWRYIHn
CSIHnCTL1.CSIHnHSE=1
tKCYHn- 5.0
-
-
ns
tWSCSBHn
CSIDLE ×
tKCYMHn - 5.0
-
-
ns
tSSCSBHn0 CSIHnCTL1.CSIHnDAP=0
CSSETUP ×
tKCYMHn-5.0
-
-
ns
tSSCSBHn1 CSIHnCTL1.CSIHnDAP=1
(CSSETUP + 0.5 ) ×
tKCYMHn-5.0
-
-
ns
tHSCSBHn0 CSIHnCTL1.CSIHnSIT=0
CSHOLD ×
tKCYMHn-10.0
-
-
ns
tHSCSBHn1 CSIHnCTL1.CSIHnSIT=1
(CSSHOLD + 0.5) ×
tKCYMHn-5.0
-
-
ns
CSIHnCSS0-7 inactive
width
CSIHnCSS0-7 setup time
( vs. CSIHnSC )
CSIHnCSS0-7 hold time
( vs. CSIHnSC )
Notes
1. n: Number of macro instances. Refer to the User Manual for the detailed
specification.
2. CSSETUP: Value of CSIHnCFG0-7.CSIHnSP0-7[3:0]
3. CSHOLD: Value of CSIHnCFG0-7.CSIHnHD0-7[3:0]
4. CSIDLE: Value of CSIHnCFG0-7.CSIHnID0-7[2:0]
R01DS0144ED0100
Electrical Target Specification
50
Chapter 7
Peripherals specification
(3)
Timing diagrams
SCKO / SI / SO
CSIG ( CSIGnCTL1 : CSIGnCKR/ CSIGnCFG0 :CHIGnDAP0 = 0 / 0 or 1 / 1 )
CSIH (CSIHnCFGm:CSIHnCKPm/ CSIHnCFGm: CHIHnDAPm= 0 /0 or 1/1 )
tKCYGn
tKCYHn
Clock
tKCYMGn
tKCYMHn
tKWLMGn
tKWLMHn
tKW HMGn
tKW HMHn
CSIGnSC
CSIHnSC
tD SOMGn
tD SOMHn
CSIGnSO
CSIHnSO
tSSIMGn
tSSIMHn
tHSIMGn
tHSIMHn
CSIGnSI
CSIHnSI
CSIG( CSIGnCTL1 : CSIGnCKR/ CSIGnCFG0 :CHIGnDAP0 = 1 / 0 or 0 / 1)
CSIH (CSIHnCFGm:CSIHnCKPm/ CSIHnCFGm: CHIHnDAPm= 1/ 0 or 0/ 1 )
tKCYGn
tKCYHn
Clock
tKCYMGn
tKCYMHn
tKWHMGn
tKWHMHn
tKW LMGn
tKW LMHn
CSIGnSC
CSIHnSC
tDSOMGn
tDSOMHn
CSIGnSO
CSIHnSO
tSSIMGn
tSSIMHn
tHSIMGn
tHSIMHn
CSIGnSI
CSIHnSI
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Chapter 7
Peripherals specification
RYI
CSIGnCTL1 : CSIGnHSE=1, CSIGnCTL1 : CSIGnSIT = 0 )
CSIHnCTL1 : CSIHnHSE=1, CSIHnCTL1 : CSIHnSIT = 0 )
CSIG (CSIGnCTL1 :CSIGnCKR= 0)
CSIH (CSIHnCFGm:CSIHnCKPm= 0)
tKCYGn
tKCYHn
Clock
t SRYIGn
tSRYIHn
CSIGnSC
CSIHnSC
tWRYIGn
tWRYIHn
CSIGnRYI
CSIHnRYI
CSIG (CSIGnCTL1 :CSIGnCKR= 1)
CSIH (CSIHnCFGm:CSIHnCKPm= 1)
tKCYGn
tKCYHn
Clock
tSRYIGn
tSRYIHn
CSIGnSC
CSIHnSC
tWRYIGn
tWRYIHn
CSIGnRYI
CSIHnRYI
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Electrical Target Specification
52
Chapter 7
Peripherals specification
CSSn
CSIHnCFGm:CSIHnCKPm= 0,CSIHnCFGm:CHIHnDAPm= 0
tKCYHn
Clock
CSIHnSC
tSSCSBHn0
CSIHnCSS0-7
CSIHnSO
CSIHnCFGm:CSIHnCKPm= 0,CSIHnCFGm:CHIHnDAPm= 1
tKCYHn
Clock
CSIHnSC
tSSCSBHn1
CSSETUP x tKCYMHn
0.5x tKCYMHn
CSIHnCSS0-7
CSIHnSO
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Electrical Target Specification
53
Chapter 7
Peripherals specification
CSIHnCTL1 : CSIHnSIT=0, CSIHnCFGm: CSIHnCKPm= 0,CSIHnCFGm:
CHIHnDAPm= 0
tKCYHn
Clock
CSIHnSC
tHSCSBHn0
CSHnCSS0-7
CSIHnCTL1 : CSIHnSIT=1, CSIHnCFGm: CSIHnCKPm= 0,CSIHnCFGm:
CHIHnDAPm= 0
tKCYHn
Clock
CSIHnSC
tHSCSBHn1
0.5 x tKCYMHn
CSHOLD
x tKCYMHn
CSHnCSS0-7
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Electrical Target Specification
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Chapter 7
Peripherals specification
7.8.2 Slave mode
(1)
Table 7-5
CSIG timing slave mode
CSIG timing (Slave mode)
Parameter
Symbol
Macro Operation clock cycle
time
Condition
Ratings
Unit
Min
Typ
Max
tKCYGn
12.5
-
-
ns
CSIGnSC cycle time
tKCYSGn
200
-
-
ns
CSIGnSC high level width
tKWHSGn
0.5 · tKCYSGn-10
-
-
ns
CSIGnSC low level width
tKWLSGn
0.5 · tKCYSGn-10
-
-
ns
CSIGnSI setup time
(vs. CSIGnSC )
tSSISGn
20
-
-
ns
CSIGnSI hold time
(vs. CSIGnSC)
tHSISGn
tKCYGn+5.0
-
-
ns
SO output delay (vs SCKI)
tDSOSGn
-
-
35
ns
CSIGnRYO output delay
tSRYOGn
-
-
35
ns
_CSIGnSSI setup time (vs
CSIGnSC)
tSSSISGn
0.5 · tKCYSn-5.0
-
-
ns
_CSIGnSSI hold time (vs
CSIGnSC)
tHSSISGn
tKCY+5.0
-
-
ns
Note
(2)
Table 7-6
n: Number of macro instances. Refer to the User Manual for the detailed
specification.
CSIH timing slave mode
CSIH timing (Slave mode)
Parameter
Symbol
Macro Operation clock cycle
time
Condition
Ratings
Unit
Min
Typ
Max
tKCYHn
12.5
-
-
ns
CSIHnSC cycle time
tKCYSHn
200
-
-
ns
CSIHnSC high level width
tKWHSHn
0.5 · tKCYSHn-10
-
-
ns
CSIHnSC low level width
tKWLSHn
0.5 · tKCYSHn-10
-
-
ns
CSIHnSI setup time
(vs. CSIHnSC )
tSSISHn
20
-
-
ns
CSIHnSI hold time
(vs. CSIHnSC)
tHSISHn
tKCYHn+5.0
-
-
ns
SO output delay (vs SCKI)
tDSOSHn
-
-
35
ns
CSIHnRYO output delay
tSRYOHn
-
-
35
ns
CSIHnSSI setup time
(vs. CSIHnSC)
tSSSISHn
0.5 · tKCYSn-5:0
-
-
ns
CSIHnSSI hold time
(vs. CSIHnSC)
tHSSISHn
tKCYn* 5.0
-
-
ns
Note
R01DS0144ED0100
Electrical Target Specification
n: Number of macro instances. Refer to the User Manual for the detailed
specification.
55
Chapter 7
Peripherals specification
(3)
Timing diagrams
SCKO / SI / SO
CSIG (CSIGnCTL1 : CSIGnCKR/ CSIGnCFG0 :CHIGnDAP0 = 0/0 or 1/1)
CSIH (CSIHnCFGm:CSIHnCKPm/ CSIHnCFGm: CHIHnDAPm= 0/0 or 1/1)
tKCYGn
tKCYHn
Clock
tKCYSGn
tKCYSHn
tKWLSGn
tKWLSHn
tKWHSGn
tKWHSHn
CSIGnSC
CSIHnSC
tD SOSGn
tD SOSHn
CSIGnSO
CSIHnSO
tSSISGn
tSSISHn
tHSISGn
tHSISHn
CSIGnSI
CSIHnSI
CSIG (CSIGnCTL1 : CSIGnCKR/ CSIGnCFG0 :CHIGnDAP0 = 1/0 or 0/1)
CSIH (CSIHnCFGm:CSIHnCKPm/ CSIHnCFGm: CHIHnDAPm= 1/0 or 0/1)
tKCYGn
tKCYHn
Clock
tKCYSGn
tKCYSHn
tKWHSGn
tKWHSHn
tKWLSGn
tKWLSHn
CSIGnSC
CSIHnSC
tD SOSGn
tD SOSHn
CSIGnSO
CSIHnSO
tSSISGn
tSSISHn
tHSISGn
tHSISHn
CSIGnSI
CSIHnSI
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Electrical Target Specification
56
Chapter 7
Peripherals specification
RYO
CSIG (CSIGnCTL1 : CSIGnCKR/ CSIGnCFG0 :CHIGnDAP0 = 0/0)
CSIH (CSIHnCFGm:CSIHnCKPm/ CSIHnCFGm: CHIHnDAPm= 0/0)
CSIGnSC
CSIHnSC
tSRYOGn
tSRYOHn
CSIGnRYO
CSIHnRYO
CSIG (CSIGnCTL1 : CSIGnCKR/ CSIGnCFG0 :CHIGnDAP0 = 0/1)
CSIH (CSIHnCFGm:CSIHnCKPm/ CSIHnCFGm: CHIHnDAPm= 0/1)
CSIGnSC
CSIHnSC
tSRYOGn
tSRYOHn
CSIGnRYO
CSIHnRYO
CSIG (CSIGnCTL1 : CSIGnCKR/ CSIGnCFG0 :CHIGnDAP0 = 1/0)
CSIH (CSIHnCFGm:CSIHnCKPm/ CSIHnCFGm: CHIHnDAPm= 1/0)
CSIGnSC
CSIHnSC
tSRYOGn
tSRYOHn
CSIGnRYO
CSIHnRYO
CSIHnTIC
CSIG (CSIGnCTL1 : CSIGnCKR/ CSIGnCFG0 :CHIGnDAP0 = 1/1)
CSIH (CSIHnCFGm:CSIHnCKPm/ CSIHnCFGm: CHIHnDAPm= 1/1)
CSIGnSC
CSIHnSC
tSRYOGn
tSRYOHn
CSIGnRYO
CSIHnRYO
R01DS0144ED0100
Electrical Target Specification
57
Chapter 7
Peripherals specification
SSI:
CSIG (CSIGnCTL1 :CSIGnSSE=1, CSIGnCTL1 : CSIGnCKR,/ CSIGnCFG0 :
CHIGnDAP0 = 0/0 or 1/1)
CSIH (CSIHnCTL1 : CSIHnSSE=1, CSIHnCFGm : CSIHnCKPm /
CSIHnCFGm : CHIHnDAPm = 0/0 or 1/1)
CSIGnSC
CSIHnSC
tSSSISGn
tSSSISHn
tHSSISGn
tHSSISHn
_CSIGnSSI
_CSIHnSSI
Hi-Z
CSIGnSO
CSIHnSO
CSIG (CSIGnCTL1 :CSIGnSSE=1, CSIGnCTL1 : CSIGnCKR,/ CSIGnCFG0 :
CHIGnDAP0 = 1/0 or 0/1 ) n=0, 4
CSIH (CSIHnCTL1 : CSIHnSSE=1, CSIHnCFGm : CSIHnCKPm /
CSIHnCFGm : CHIHnDAPm = 1/0 or 0/1)
CSIGnSC
CSIHnSC
tSSSISGn
tSSSISHn
tHSSI SGn
tHSSI SHn
_CSIGnSSI
_CSIHnSSI
Hi-Z
CSIGnSO
CSIHnSO
7.9 UART timing
Parameter
Transfer rate
R01DS0144ED0100
Electrical Target Specification
Symbol
Condition
Ratings
Min
Typ
Max
-
-
1.5
Unit
Mbps
58
Chapter 7
Peripherals specification
7.10 FCN timing
Parameter
Symbol
Ratings
Condition
Transfer rate
Internal delay time
tINTDEL
CAN Node delay time
tNODE
tCYCLE = 62.5ns
Unit
Min
Typ
Max
-
-
1
Mbps
-
-
37.5
ns
-
-
100
ns
CAN macro clock
toutput
FCnTX pin
( Transfer data )
tGATE
tCYCLE
FCnRX pin
( Receive data )
tINPUT = tGATE + tCYCLE
CAN node delay time (tNODE) = INPUT delay time (tinput) + Output delay time (toutput)
Internal delay time (tINTDEL) = Internal gate delay time (tGATE) + Output delay time (toutput)
V850E2/Fx4
CAN
macro
Output delay time
(tOUTPUT)
FCnTX pin
Input delay time
(tINPUT)
Input gate delay time
(tGATE)
FCnRX pin
Image of Internal delay time
R01DS0144ED0100
Electrical Target Specification
59
Chapter 7
Peripherals specification
7.11 FlexRay timing
Parameter
Symbol
Ratings
Condition
Typ
Max
-
-
10
Mbps
FLX0TXDA, FLX0TXDB,
-
-
FLX0TXENA, FLX0TXENB
-
-
25
ns
FLX0RXDA, FLX0RXDB
-
-
10
ns
Transfer rate
Node Output Delay
Node Input Delay
tOUTPUT
tINPUT
Unit
Min
uCOM device with
FlexRay macro
Node Output Delay
FlexRay macro
(internal system clock)
eray_sclk
FRTXDx
DQ
QD
FRRXDx
I/O Port
I/O Buf
Pxx/TXDx
I/O Port
I/O Buf
Pxx/RXDx
Node Input Delay
FRSCLK
(internal clock)
touput
FRTXDx
(macro output)
TXDx*
(chip output)
RXDx*
(chip input)
tinput
FRRXDx
(macro input)
R01DS0144ED0100
Electrical Target Specification
60
Chapter 7
Port
FLX0TXENA
FLX0TXENB
Peripherals specification
Name
Unit
Typ
Max
-
-
9
ns
dCCTxEN01
-
-
25
ns
dCCTxEN10
-
-
25
ns
measured at 50% E1VDD
-
-
2.45
ns
Cload=25pF, measured at 20-80% E1VDD
-
-
9
ns
Cload=10pF, measured at 20-80% E1VDD
at the end of a 50ohm, 1ns microstripline
-
-
9
ns
dCCTxD01
-
-
-
25
ns
dCCTxD10
-
-
-
25
ns
measured at 50% of E1VDD
Input signal: Cload=25pF, 6.5ns (20-80%
E1VDD)
-
-
5.5
ns
C_CCRxD
-
-
-
10
pf
uLogic_1
-
35
-
70
%
uLogic_0
-
30
-
65
%
dCCRxD01
-
-
-
10
ns
dCCRxD10
-
-
-
10
ns
dTxENRISE-FALL
dCCTxDRISE25 +
dCCTxDFALL25
dCCRxAsmAccept
FLX0RXDA
FLX0RXDB
Ratings
Min
dCCTxAsym
FLX0TXDA
FLX0TXDB
Condition
R01DS0144ED0100
Electrical Target Specification
Cload=25pF, measured at 20-80% E1VDD
61
Chapter 7
Peripherals specification
7.12 Ethernet timing (MII interface)
7.12.1 Transmission interface
(CL = 30pF)
Item
Symbol
Condition
Ratings
Min
Typ
Max
Unit
ETH0TXD[3:0] delay vs ETH0TXCLK(r)
tDTKTD
0
-
25
ns
ETH0TXEN, ETH0TXER delay vs
ETH0TXCLK(r)
tDTKTE
0
-
25
ns
ETH0TXCLK clock period
tCYTK
40
-
-
ns
ETH0TXCLK high level width
tTKH
0.4·tCYTK
-
0.6·tCYTK
ns
ETH0TXCLK low level width
tTKL
0.4·tCYTK
-
0.6·tCYTK
ns
tCYTK
t TKH
t TKL
ETH0TXCLK
tDTKTD
ETH0TXD[3:0]
ETH0TXEN
ETH0TXER
tDTK TE
R01DS0144ED0100
Electrical Target Specification
tDTK TE
62
Chapter 7
Peripherals specification
7.12.2 Reception interface
(CL=30pF)
Item
Symbol
Condition
Ratings
Min
Typ
Max
Unit
ETH0RXD[3:0] hold time vs
ETH0RXCLK(r)
tHRKRD
5
-
-
ns
ETH0RXD[3:0] setup time vs
ETH0RXCLK(r)
tSRDRK
5
-
-
ns
ETH0RXER, ETH0RXDV hold time vs
ETH0RXCLK(r)
tHRKRV
5
-
-
ns
ETH0RXER, ETH0RXDV setup time vs
ETH0RXCLK(r)
tSRVRK
5
-
-
ns
tCYRK
40
-
-
ns
ETH0RXCLK high level width
tRKH
0.4·tCYRK
-
0.6·tCYRK
ns
ETH0RXCLK low level width
tRKL
0.4·tCYRK
-
0.6·tCYRK
ns
ETH0RXCLK clock period
tRKL
tRKH
ETH0RXCLK
tSRDRK
tHRKRD
tCYRK
ETH0RXD[3:0]
ETH0RXDV
ETH0RXER
tHRK RV
tSRVRK
Management Interface
(CL = 30pF)
Item
Symbol
ETH0MDC clock period
Condition
Ratings
Unit
Min
Typ
Max
tCYMDC
400
-
-
ns
ETH0MDO delay vs ETH0MDC(r)
tDMCMD
0
-
300
ns
ETH0MDI setup time vs ETH0MDC(r)
tSMDMC
50
-
-
ns
ETH0MDI hold time vs ETH0MDC(r)
tHMCMD
50
-
-
ns
R01DS0144ED0100
Electrical Target Specification
63
Chapter 7
Peripherals specification
7.13 IIC timing
Table 7-7
Normal mode
Parameter
Symbol
Condition
Ratings
Min
SCL clock period
fCLK
0
Bus free time (between stop condition
and start condition)
tBUF
4.7
tHD:STA
SCL clock low state hold time
SCL clock high state hold time
Typ
Max
Unit
100
kHz
-
-
µs
4
-
-
µs
tLOW
4.7
-
-
µs
tHIGH
4
-
-
µs
Setup time for start/restart condition
tSU:STA
4.7
-
-
µs
Data hold time
tHD:DAT
CBUS compatible
5
-
-
µs
IIC bus
0
-
-
µs
Data setup time
tSU:DAT
250
-
-
ns
Rising transition time of SDA or SCL
tR
-
-
1000
ns
Falling transition time of SDA or SCL
tF
-
-
300
ns
tSU:STO
4
-
-
µs
Cb
-
-
400
pF
Start/Restart Hold time (New clock
pulse
is generated after this hold time as a
master.)
Setup time of stop condition
Bus capacitance
R01DS0144ED0100
Electrical Target Specification
64
Chapter 7
Peripherals specification
Table 7-8
Fast mode
Parameter
Symbol
Ratings
Condition
Min
Typ
Max
Unit
SCL clock period
fCLK
0
-
400
kHz
Bus free time (between stop condition
and start condition)
tBUF
1.3
-
-
µs
tHD:STA
0.6
-
-
µs
SCL clock low state hold time
tLOW
1.3
-
-
µs
SCL clock high state hold time
tHIGH
0.6
-
-
µs
Setup time for start/restart condition
tSU:STA
0.6
-
-
µs
Data hold time
tHD:DAT
0
-
0.9
µs
Data setup time
tSU:DAT
100
-
-
ns
Rising transition time of SDA or SCL
tR
20+0.1Cb
-
300
ns
Falling transition time of SDA or SCL
tF
20+0.1Cb
-
300
ns
tSU:STO
0.6
-
-
µs
Noise elimination width
tSP
0
-
50
ns
Bus capacitance
Cb
-
-
400
pF
Start/Restart Hold time (New clock
pulse
is generated after this hold time as a
master.)
Setup time of stop condition
tLOW
IIC bus
tR
tHI GH
tF
SCL0
tHD: STA
tHD: DAT
tSU: DAT
SDA0
tBUF
P
S
tSU: STA
tHD: STA
Sr
Notes
1. P: Stop condition
Notes
1. S: Start condition
Notes
1. Sr: Restart condition
R01DS0144ED0100
Electrical Target Specification
tSP
tSU: STO
P
65
Chapter 7
Peripherals specification
7.14 Frequency Output Function (FOUT)
Table 7-9
Frequency Output Function (FOUT)
Parameter
Symbol
Ratings
Condition
Unit
Min
Typ
Max
tFO
50
-
-
ns
CSCXFOUTP high level width
tWKHFO
tFOUT / 2 - 10
-
-
ns
CSCXFOUTP low level width
tWKLFO
tFOUT / 2 - 10
-
-
ns
CSCXFOUTP rise time
tKRFO
-
-
10
ns
CSCXFOUTP fall time
tKFFO
-
-
10
ns
CSCXFOUTP output cycle
tFO
tWKHFO
tWKLFO
CSCXFOUT
tKRFO
tKFFO
7.15 VLVI characteristics
Table 7-10
Parameter
VLVI characteristics
Symbol
Ratings
Condition
Unit
Min
Typ
Max
VRAMHF
1.8
1.9
2.0
V
Voltage slope1
Rvs1
0.18
-
1800
V/ms
Voltage slope2
Rvs2
0.0018
-
1800
V/ms
tRAMHD
-
-
2
ms
Detection voltage
Response
a)
timea
From detection voltage to setting of VLVF bit (VLVF.bit0)
VDD
Rvs2
Rvs1
Detectvoltage(MAX.)
Detectvoltage(TYP.)
Detectvoltage(MIN.)
tRAMHD
Note
R01DS0144ED0100
Electrical Target Specification
tRAMHD
tRAMHD
VDD: REG0VDD
66
Chapter 7
Peripherals specification
7.16 Voltage comparator characteristics
Parameter
Symbol
Condition
Ratings
Min
Typ
Max
Unit
VCMP current
IVCMP
-
200
300
µA
Threshould voltage (rise)
VCMPR
1.745
1.780
1.815
V
Threshould voltage (fall)
VCMPF
1.645
1.680
1.715
V
Voltage slope
VCVS
-
-
50
mV/µs
Detection time
tVCMPD
-
-
2
µs
Stabilization time
tVCMPST
-
-
2
ms
VCMP operation readyness after
VCPC0OEn is set to 1
VCPCnIN
VCMPR (MAX.)
VCMPR(TYP.)
VCMPR(MIN.)
VCMPF(MAX.)
VCMPF(TYP.)
VCMPF(MIN.)
t VCMPD
tVCMPD
VCPCnOUT
n=0,1
R01DS0144ED0100
Electrical Target Specification
67
Chapter 7
Peripherals specification
7.17 LVI characteristics
Table 7-11
Parameter
Detection voltage
LVI characteristics
Symbol
Ratings
Condition
Min
Typ
Max
Unit
VLVI0
LVICNT.LVICNT[2:0]=001B
3.9
4.0
4.1
V
VLVI1
LVICNT.LVICNT[2:0]=010B
3.6
3.7
3.8
V
VLVI2
LVICNT.LVICNT[2:0]=011B
3.4
3.5
3.6
V
Voltage slope1
LVS1
0.18
-
1800
V/ms
Voltage slope2
LVS2
0.0018
-
1800
V/ms
Response time
tLD
-
-
2.0
ms
VDD minimum width
tLW
2
-
-
ms
-
-
350
µs
Stabilization time
tLVIST
LVICNT0,1 is set to 1, then LVI is
ready to operate
VDD
LVS2
D etect voltage(MAX.)
D etect voltage(TYP.)
D etect voltage(MIN.)
LVS1
tLW
tLD
R01DS0144ED0100
Electrical Target Specification
tLD
68
Chapter 7
Peripherals specification
7.18 A/D Converter characteristics
7.18.1 12bit A/D (for ADC channels without S/H functionality)
Table 7-12
12bit A/D
Parameter
Symbol
Condition
Ratings
Unit
Min
Typ
Max
RESn
12
12
12
bit
Total conversion time
TCONn
1.5
-
10
µs
errora
TOEn
-
-
±6.0
LSB
ILEn
-
-
±2.5
LSB
DLEn
-
-
±1.5
LSB
ZSEn
-
-
±5.0
LSB
FSEn
-
-
±5.0
LSB
VAIN
AnVREFM
AnVREFP
V
Resolution
Overall
Non-liniarity
errora
Differencial liniarity
Zero scale
Full scale
errora
errora
errora
Analog input
voltagea
Power on stabilization
timeb
-
-
1
µs
ADAnBPC=0, withDiagnosis
function
-
4.0
6.3
mA
ADAnBPC=0, w/o Diagnosis
function
-
5.2
8.1
mA
ADAnBPC=1, with Diagnosis
function
-
4.6
7.4
mA
ADAnBPC=1, w/o Diagnosis
function
-
6.2
9.2
mA
-
1
-
µA
-
650
-
µA
4015
-
4095
LSB
TESHLn3 2/3 AnVDD was converted
2691
2731
2771
LSB
TESHLn2 1/2 AnVDD was converted
2018
2048
2078
LSB
TESHLn1 1/3 AnVDD was converted
1325
1365
1405
LSB
0
-
80
LSB
AIDDn
AnVDD current
AIDDnPD Power down
AnVREFP current
AIREFn
TESHn
Conversion result by
Diagnosis functionc
TESLn
a)
b)
c)
AnVDD was converted
AGND was converted
The specification does not include the quantization error.
‘Power on’ refers to
- setting ADCAnGPS = 1
The values given do not include influence of injected current
Notes
1. n: Number of macro instances. Refer to the User Manual for the detailed
specification.
2. m: Number of channels. Refer to the User Manual for the detailed
specification.
R01DS0144ED0100
Electrical Target Specification
69
Chapter 7
Peripherals specification
7.18.2 12bit A/D (For channel ADCA0I0-5 when the S/H function is
not used)
Table 7-13
12bit A/D (When channel Sample & Hold function is not used)
Parameter
Symbol
Condition
Ratings
Unit
Min
Typ
Max
RES0SN
12
12
12
bit
Total conversion time
TCON0SN
1.5
-
10
µs
errora
TOE0SN
-
-
±6.0
LSB
ILE0SN
-
-
±2.5
LSB
DLE0SN
-
-
±1.5
LSB
ZSE0SN
-
-
±5.0
LSB
FSE0SN
-
-
±5.0
LSB
VAIN0SN
A0VREFM
-
A0VREFP
V
-
-
1
µs
ADA0BPC=0, withDiagnosis
function
-
4.0
6.3
mA
ADA0BPC=0, w/o Diagnosis
function
-
5.2
8.1
mA
ADA0BPC=1, with Diagnosis
function
-
4.6
7.4
mA
ADA0BPC=1, w/o Diagnosis
function
-
6.2
9.2
mA
-
1
-
µA
-
650
-
µA
4015
-
4095
LSB
TESHL0SN3 2/3 A0VDD was converted
2691
2731
2771
LSB
TESHL0SN2 1/2 A0VDD was converted
2018
2048
2078
LSB
TESHL0SN1 1/3 A0VDD was converted
1325
1365
1405
LSB
0
-
80
LSB
Resolution
Overall
a
Non-liniarity error
Differencial liniarity
Zero scale
Full scale
errora
errora
errora
Analog input
voltagea
Power on stabilization
timeb
AIDD0SN
A0VDD current
AIDD0SNPD Power down
A0VREFP current
AIREF0SN
TESH0SN
Conversion result by
Diagnosis functionc
TESL0SN
a)
b)
c)
A0VDD was converted
AGND was converted
The specification does not include the quantization error.
‘Power on’ refers to
- setting ADCAnGPS = 1
The values given do not include influence of injected current
Notes
1. n: Number of macro instances. Refer to the User Manual for the detailed
specification.
2. m: Number of channels. Refer to the User Manual for the detailed
specification.
R01DS0144ED0100
Electrical Target Specification
70
Chapter 7
Peripherals specification
7.18.3 12bit A/D (When channel S/H function is used)
Table 7-14
12bit A/D (When channel Sample & Hold function is used [ADCA0I0 to
ADCA0I5])
Parameter
Symbol
Resolution
Total conversion time
Condition
Overall
a
Non-liniarity error
Differencial liniarity error
Zero scale
Full scale
a
errora
errora
Analog input voltage
Typ
Max
RES0S
12
12
12
bit
TCON0SN
1.8
-
12
µs
50
-
-
µs
TOE0S
-
-
±8.0
LSB
ILE0S
-
-
±4.0
LSB
DLE0S
-
-
±2.5
LSB
ZSE0S
-
-
±6.0
LSB
FSE0S
-
-
±6.0
LSB
VAIN0S
0.2
-
A0VREFP-0.2
V
-
-
1
µs
withDiagnosis function
-
Note3
22.1
mA
w/o Diagnosis function
-
Note3
24.0
mA
-
1
-
µA
-
650
-
µA
TESHLS3 2/3 A0VDD was converted
2689
2731
2773
LSB
TESHLS2 1/2 A0VDD was converted
2016
2048
2080
LSB
TESHLS1 1/3 A0VDD was converted
1323
1365
1407
LSB
Power on stabilization
timeb
AIDD0S
A0VDD current
AIDD0SPD Power down
A0VREFP current
Conversion result by
Diagnosis functionc
a)
b)
c)
Unit
Min
Sample & Hold time
errora
Ratings
AIREF0S
The specification does not include the quantization error.
‘Power on’ refers to
- setting ADCAnGPS = 1
The values given do not include influence of injected current
Notes
1. n: Number of macro instances. Refer to the User Manual for the detailed
specification.
2. m: Number of channels. Refer to the User Manual for the detailed
specification.
3. AIDDn + 1.72mA x (number of channels used with S/H)
R01DS0144ED0100
Electrical Target Specification
71
Chapter 7
Peripherals specification
7.18.4 10bit A/D (for ADC channels without S/H functionality)
Table 7-15
10 bit A/D
Parameter
Symbol
Condition
Ratings
Unit
Min
Typ
Max
RESn
10
10
10
bit
Total conversion time
TCONn
1.5
10
µs
errora
TOEn
Resolution
Overall
-
-
±2.0
LSB
ILEn
-
-
±1.5
LSB
DLEn
-
-
±1.0
LSB
Zero scale error
ZSEn
-
-
±1.5
LSB
errora
FSEn
-
-
±1.5
LSB
VAIN
AnVREFM
AnVREFP
V
-
1
µs
a
Non-liniarity error
Differencial liniarity error
a
a
Full scale
Analog input
voltagea
Power on stabilization
Excluding quantization error
timeb
AIDDn
AnVDD current
ADAnBPC=0, withDiagnosis
function
-
4.0
6.3
mA
ADAnBPC=0, w/o Diagnosis
function
-
5.2
8.1
mA
ADAnBPC=1, with Diagnosis
function
-
4.6
7.4
mA
ADAnBPC=1, w/o Diagnosis
function
-
6.2
9.2
mA
-
1
-
µA
-
500
-
µA
1023
LSB
AIDDnPD Power down
AnVREFP current
AIREFn
TESHn
Conversion result by
Diagnosis functionc
b)
c)
1003
TESHLn3 2/3 AnVDD was converted
673
683
693
LSB
TESHLn2 1/2 AnVDD was converted
504
512
520
LSB
TESHLn1 1/3 AnVDD was converted
331
341
351
LSB
20
LSB
TESLn
a)
AnVDD was converted
AGND was converted
0
The specification does not include the quantization error.
‘Power on’ refers to
- setting ADCAnGPS = 1
The values given do not include influence of injected current
Notes
1. n: Number of macro instances. Refer to the User Manual for the detailed
specification.
2. m: Number of channels. Refer to the User Manual for the detailed
specification.
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Chapter 7
Peripherals specification
7.18.5 10bit A/D (For channel ADCA0I0-5 when the S/H function is
not used)
Table 7-16
10 bit A/D
Parameter
Symbol
Condition
Ratings
Unit
Min
Typ
Max
RES0SN
10
10
10
bit
Total conversion time
TCON0SN
1.5
10
µs
errora
TOE0SN
-
-
±2.0
LSB
ILE0SN
-
-
±1.5
LSB
DLE0SN
-
-
±1.0
LSB
ZSE0SN
-
-
±1.5
LSB
FSE0SN
-
-
±1.5
LSB
VAIN0SN
AnVREFM
AnVREFP
V
Resolution
Overall
a
Non-liniarity error
Differencial liniarity
Zero scale
Full scale
errora
errora
errora
Analog input
voltagea
Power on stabilization
timeb
-
-
1
µs
ADAnBPC=0, withDiagnosis
function
-
4.0
6.3
mA
ADAnBPC=0, w/o Diagnosis
function
-
5.2
8.1
mA
ADAnBPC=1, with Diagnosis
function
-
4.6
7.4
mA
ADAnBPC=1, w/o Diagnosis
function
-
6.2
9.2
mA
-
1
-
µA
-
500
-
µA
1003
-
1023
LSB
TESHL0SN3 2/3 AnVDD was converted
673
683
693
LSB
TESHL0SN2 1/2 AnVDD was converted
504
512
520
LSB
TESHL0SN1 1/3 AnVDD was converted
331
341
351
LSB
0
-
20
LSB
AIDD0SN
AnVDD current
AIDD0SNPD Power down
AnVREFP current
AIREF0SN
TESH0SN
Conversion result by
Diagnosis functionc
TESL0SN
a)
b)
c)
AnVDD was converted
AGND was converted
The specification does not include the quantization error.
‘Power on’ refers to
- setting ADCAnGPS = 1
The values given do not include influence of injected current
Notes
1. n: Number of macro instances. Refer to the User Manual for the detailed
specification.
2. m: Number of channels. Refer to the User Manual for the detailed
specification.
3. AIDDn + 1.72mA x (number of channels used with S/H)
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Chapter 7
Peripherals specification
7.18.6 10bit A/D (When channel S/H function is used)
Table 7-17
10 bit A/D
Parameter
Symbol
Resolution
Total conversion time
Condition
Overall
Non-liniarity
errora
Differencial liniarity error
Zero scale
Full scale
a
errora
errora
Analog input voltagea
Typ
Max
RES0S
10
10
10
bit
TCON0S
1.84
-
12.2
µs
50
-
-
µs
TOE0S
-
-
±2.5
LSB
ILE0S
-
-
±2.0
LSB
DLE0S
-
-
±1.5
LSB
ZSE0S
-
-
±2.0
LSB
FSE0S
-
-
±2.0
LSB
VAIN0S
0.2
-
A0VREFP0.2
V
-
-
1
µs
ADAnBPC=1, with Diagnosis
function
-
c
22.1
mA
ADAnBPC=1, w/o Diagnosis
function
-
c
24.0
mA
-
1
-
µA
-
500
-
µA
TESHL0S3 2/3 AnVDD was converted
672
683
694
LSB
TESHL0S2 1/2 AnVDD was converted
503
512
521
LSB
TESHL0S1 1/3 AnVDD was converted
330
341
352
LSB
Power on stabilization timeb
AIDD0S
AnVDD current
AIDD0SPD Power down
AnVREFP current
Conversion result by
Diagnosis functiond
a)
b)
c)
d)
Unit
Min
Sample & Hold time
errora
Ratings
AIREF0S
The specification does not include the quantization error.
‘Power on’ refers to
- setting ADCAnGPS = 1
AIDDn x 1.72 x the number of used channels with Sample & Hold
The values given do not include influence of injected current
Notes
1. n: Number of macro instances. Refer to the User Manual for the detailed
specification.
2. m: Number of channels. Refer to the User Manual for the detailed
specification.
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Electrical Target Specification
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Chapter 7
Peripherals specification
7.18.7 Equivalent circuit
ADCAnIm
(n=0, m=0-23)
(n=1, m=0-23)
RIN
CIN
Terminals
Condition
RIN[kΩ]
CIN[pF]
0.7
3.6
ADA0BPC=0
1.6
12.6
ADA0BPC=1
1.5
7.1
ADA0BPC=0
1.2
11.9
ADA0BPC=1
1.1
7.1
ADA0BPC=0
1.2
11.9
ADA0BPC=1
1.1
7.1
When S&H is used
ADCA0I0-ADCA0I5
When S&H is not
used
ADCA0I6-ADCA0I23
ADCA1I0-ADCA1I23
Caution
These specifications are not tested in outgoing inspection. Therefore RIN and
CIN values are not guaranteed and are reference values only.
Additionally these values are specified as maximum values.
7.18.8 ADTRG timing
Parameter
Symbol
ADCAnTRGm input High level width
ADCAnTRGm input Low level width
a)
b)
tWADH
tWADL
Condition
Ratings
Unit
Min
Typ
Max
with digital noise filter
a
-
-
ns
without digital noise filter
b
-
-
ns
with digital noise filter
a
-
-
ns
without digital noise filter
b
-
-
ns
2, 3, 4 or 5 x Tsamp + 20 (Tsamp shows sampling period specified in noise filter).
More than 1 PCLK width of ADC macro must be kept regarding DNF pass through pulse width.
1 × tSYNC+20 ( tSYNC: 1 PCLK of ADC macro)
Notes
1. n: Number of macro instances. Refer to the User Manual for the detailed
specification.
2. m: Number of channels. Refer to the User Manual for the detailed
specification.
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Electrical Target Specification
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Chapter 7
Peripherals specification
tWADH
tWADL
ADCAn
7.19 Key Return
Table 7-18
Parameter
Symbol
Condition
Ratings
Min
Typ
Max
Unit
KRn input High level width
tWKRH
300
-
-
ns
KRn input Low level width
tWKRL
300
-
-
ns
Note
n: Number of instances. Refer to the User Manual for the detailed specification.
tWNIH
tWNIL
NMI
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Electrical Target Specification
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Chapter 8
Memory specification
Chapter 8 Memory specification
8.1 Code flash specification
Table 8-1
a)
Code flash
Parameter
Symbol
Number of Re-Writesa
CWRT
Condition
Data retention 20 years
Ratings
Unit
Min
Typ
Max
-
-
100
times
-
85
°C
-
110
°C
(A) grade products
-40
Programming
tPRG
(A1) grade products
-40
Temperature
Please contact RENESAS sales office regarding specification other than the above.
8.2 Data flash specification
Table 8-2
Data flash
Parameter
Number of
a)
Symbol
Re-Writesa
Condition
Ratings
Min
Typ
Max
Unit
DWRT1
Data retention 20 years
-
-
1000
times
DWRT2
Data retention 15 years
-
-
5000
times
DWRT3
Data retention 5 years
-
-
15000
times
-
85
°C
-
110
°C
(A) grade products
-40
Programming
tPRG
(A1) grade products
-40
Temperature
Please contact RENESAS sales office regarding specification other than the above.
8.3 Serial write operation specification
Serial write operation
Parameter
Symbol
Condition
Ratings
Min
Typ
Max
Unit
FLMD0 setup time
tDR
1
-
-
ms
RESET release
tPR
2
-
-
ms
FLMD0 pulse input start
tRP
-
100
-
ms
FLMD0 low/high level width
tPW
10
-
100
µs
FLMD0 raise time
tR
-
-
20
ns
FLMD0 fall time
tF
-
-
20
ns
Programming time
per 128 bit
-
-
50
µs
Erase time
per 4KB
-
-
54
ms
R01DS0144ED0100
Electrical Target Specification
77
Chapter 9
Pinning and package specification
Chapter 9 Pinning and package specification
9.1 Pinning specification PBGA 272
1
2
3
4
5
6
7
8
9
10
11
12
A
E1VSS
FLMD0
P0_15
P0_10
P0_7
P0_4
P0_1
XT1
XT2
X1
JP0_5
JP0_2
B
P4_10
P4_11
P0_14
P0_11
P0_8
P0_5
P0_2
P0_0
OSCVSS
X2
JP0_4
JP0_1
C
P4_8
P4_9
FVDD
P0_13
P0_12
P0_9
P0_6
P0_3
OSCVDD
E0VSS
JP0_3
D
P4_5
P4_6
P4_7
E0VSS
E0VSS
E0VSS
E0VDD
E0VSS
E0VSS
E0VSS
E0VSS
E
P4_2
P4_3
P4_4
F
P3_12
P4_0
G
P3_9
H
16
17
18
19
20
VCPC0IN REG0VSS _RESET
P24_3
P24_0
P21_3
P27_5
B0VSS
A
VCPC1IN REG0C
PWGD
P24_2
P21_2
P21_4
B0VSS
P27_2
B
JP0_0
WAKE REG0VDD P24_4
P24_1
CVDD
B0VSS
P27_1
P27_0
C
E0VDD
E0VSS
P24_5
B0VSS
P25_15
P25_14
P25_13
D
E1VSS
B0VSS
P25_12
P25_11
P25_10
E
P4_1
E1VSS
B0VDD
P25_9
P25_8
P25_7
F
P3_10
P3_11
E1VDD
B0VSS
P25_6
P25_5
P25_4
G
P3_6
P3_7
P3_8
E1VSS
B0VSS
P25_3
P25_2
P25_1
H
J
P3_3
P3_4
P3_5
E1VSS
E1VSS
B0VSS
B0VSS
B0VSS
B0VDD
P25_0
P24_7
P24_6
J
K
P2_3
P3_1
P3_2
E1VDD
E1VSS
E1VSS
B0VSS
B0VSS
B0VSS
P21_1
P21_0
P21_11
K
L
P2_2
P1_15
P3_0
E1VSS
E1VSS
E1VSS
B0VSS
B0VSS
B0VSS
P21_10
P21_9
P21_8
L
M
P1_13
P1_12
P1_14
E1VDD
E1VSS
E1VSS
E1VSS
B0VSS
B0VDD
P13_2
P13_3
P21_7
M
N
P1_10
P1_9
P1_11
E1VSS
B0VSS
P12_15
P13_0
P13_1
N
P
P1_7
P1_6
P1_8
E1VSS
B0VSS
P12_12
P12_13
P12_14
P
R
P1_4
P1_3
P1_5
E1VSS
B0VSS
P12_9
P12_10
P12_11
R
T
P1_1
P11_7
P1_2
E1VSS
B0VSS
P12_6
P12_7
P12_8
T
U
P11_5
P11_4
P11_6
E1VSS
E1VSS
E1VSS
E1VSS
E1VSS
E1VSS
E1VSS
E1VDD
P12_4
P12_5
U
V
P11_2
P11_1
P11_3
A0VSS
P10_8
P10_11
P10_14
ADCA0I1
(P10_1)
CVSS
CVDD
CVDD
W
P11_0
E1VSS
AVREFP0
P10_6
P10_9
P10_12
P10_15
ADCA0I2 ADCA0I4
(P10_2) (P10_4)
N.C.
REG1VSS
Y
E1VSS
A0VDD AVREFM0
P10_7
P10_10
P10_13
ADCA0I0 ADCA0I3 ADCA0I5
(P10_0) (P10_3) (P10_5)
P2_0
4
5
6
10
1
2
3
13
14
15
CVSS
E0VSS
V850E2/FL4-H
R01DS0144ED0100
Electrical Target Specification
7
8
9
B0VSS
B0VDD
B0VSS
B0VSS
B0VSS
B0VSS
A1VSS
REG1VDD P24_10
P21_6
P24_14
P13_5
P12_0
B0VSS
P27_4
P24_9
P21_5
P24_13
P13_4
P13_7
P12_2
B0VSS
A1VDD
W
P2_1
PTCTL1
P24_8
P24_11
P24_12
P24_15
P13_6
P12_1
P12_3
B0VSS
Y
11
12
13
14
15
16
17
18
19
20
AVREFP1 AVREFM1
V
78
Chapter 9
Pinning and package specification
9.2 Package specification PBGA 272
R01DS0144ED0100
Electrical Target Specification
79
Revision History
Version
1.0
Date
2013-05-24
R01DS0144ED0100
Electrical Target Specification
Document number
R01DS0144ED0100
Description
Initial release
Document was EASE-DS-0032-1.2
Changes:
- Added FLMD0 / FLMD1 resistor values
- Corrected timing diagram for wake-signal (chapter 3.5.5
Condition 4)
- Updated Power Supply Currents (chapter 5.1)
80