XE1202A TrueRF™

IAmp
VDD
VDDA
QAMP
IAMP
VDDP
VDDF
VDDD
Data Sheet
XE1202A TrueRF™
QAmp
SCAN
I
BPF
AMP
Limiter
AMP
DCLK
RFA
FSK
Demod.
LNA
Bit
Sync.
RFB
DATAOUT
Q
AMP
BPF
Limiter
AMP
Pattern
Recognition
LO
Buff.
Phase
Shifter
PATTERN
FEI
RSSI
MODE 0
MODE 1
Prog.
divider
MODE 2
Control
Logic
SI
SO
RFOUT
PA
VCO
modulator
/n Synthesizer
PFD
SCK
EN
POR
Oscillator
I Ref
/n
Clock Out
VSS
VSSA
VSSA
TSUPP
TVCO
CLKOUT
XTB
XTA
LFB
TKA
TKB
VSSP
VSSP
VSSF
VSSD
VSSF
DATAIN
XE1202A TrueRF™
433 MHz / 868 MHz / 915 MHz
Low-Power, Integrated UHF Transceiver
GENERAL DESCRIPTION
KEY PRODUCT FEATURES
The XE1202A TrueRF™ is a single chip transceiver
operating in the 433, 868 and 915 MHz license free
ISM (Industry Scientific and Medical) frequency bands.
Its highly integrated architecture allows for minimum
external components while maintaining design
flexibility. All major RF communication parameters are
programmable and most of them can be dynamically
set. The XE1202A TrueRF™ offers a wide range of
channel bandwidths, without the need to modify the
number or parameters of the external components.
The XE1202A TrueRF™ is optimized for low power
consumption whilst offering high RF output power and
channelized operation suitable for both the European
(ETSI-300-220) and the North American (FCC part 15)
regulatory standards.
•
Programmable RF output power: up to +15 dBm
•
High reception sensitivity: down to –116 dBm
•
Low power consumption: RX = 14 mA;
TX = 62 mA @15 dBm output power
•
Supply voltage down to 2.4V
•
Data rates from 4.8 kbit/s to 76.8 kbit/s, NRZ
coding
•
Channel filter bandwidths from 20 kHz to 400 kHz
•
On-chip frequency synthesizer with minimum
frequency resolution of 500 Hz
•
Continuous phase 2-level FSK modulation
•
Incoming data pattern recognition
•
Built-in Bit-Synchronizer for incoming data and
APPLICATIONS
clock synchronization and recovery
•
Security systems
•
Voice and data over an RF link
•
Process and building control
•
Access control
•
Home automation
•
Home appliances interconnection
•
RSSI (Received Signal Strength Indicator) and FEI
(Frequency Error Indicator)
ORDERING INFORMATION
Part number
Temperature range
Package
XE1202AI027TRLF
-40 °C to +85 °C
LQFP44
XEMICS SA • e-mail: [email protected] • web: www.xemics.com
Data Sheet
XE1202A TrueRF™
TABLE OF CONTENTS
1
2
3
3.1
3.2
3.2.1
3.2.2
4
4.1
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
4.1.6
4.1.7
5
5.1
5.1.1
5.1.2
5.1.3
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
5.3
5.4
5.5
5.6
5.7
5.8
6
6.1
6.2
6.3
6.4
6.5
7
2
Functional Block Diagram ..........................................................................................................................3
Pin description.............................................................................................................................................4
Electrical Characteristics ...........................................................................................................................5
Absolute Maximum Operating Ranges .........................................................................................................5
Specifications ................................................................................................................................................5
Operating Range ...........................................................................................................................................5
Electrical Specifications.................................................................................................................................5
Description...................................................................................................................................................8
Detailed description.......................................................................................................................................8
Receiver ........................................................................................................................................................8
Receiver LNA modes ..................................................................................................................................10
RSSI ............................................................................................................................................................10
Frequency Error Indicator - FEI...................................................................................................................11
Transmitter ..................................................................................................................................................13
Pattern recognition ......................................................................................................................................14
Frequency synthesizer ................................................................................................................................15
Serial Interface Definition, Principles of Operation ...............................................................................16
Serial Control Interface................................................................................................................................16
General description .....................................................................................................................................16
Write sequence............................................................................................................................................16
Read sequence ...........................................................................................................................................16
Configuration and Status registers ..............................................................................................................17
RTParam configuration register ..................................................................................................................17
FSParam configuration register...................................................................................................................19
DataOut register ..........................................................................................................................................20
ADParam configuration register ..................................................................................................................20
Pattern register ............................................................................................................................................21
Supplementary configuration.......................................................................................................................23
Operating Modes.........................................................................................................................................23
Transmitted Data Interface..........................................................................................................................25
Received Data Interface..............................................................................................................................25
Pattern Recognition Interface......................................................................................................................26
Clock Output Interface.................................................................................................................................26
Default settings at power-up........................................................................................................................26
Application Information ............................................................................................................................27
Receiver matching network .........................................................................................................................27
Transmitter matching network .....................................................................................................................27
VCO tank .....................................................................................................................................................30
Loop filter of the frequency synthesizer ......................................................................................................31
Reference crystal for the frequency synthesizer .........................................................................................32
Packaging information..............................................................................................................................33
D0504-281
Data Sheet
XE1202A TrueRF™
The XE1202A TrueRF™ UHF Transceiver IC provides a single chip solution intended for use as a low cost FSK
transceiver to establish a frequency-agile, half-duplex, bi-directional RF link, with non-return to zero data coding.
The device is available in an LQFP44 package and is designed to provide a fully functional multi-channel FSK
transceiver. It is intended for applications in the 433 and 868 MHz European bands and the North American 902928 MHz ISM band. The single chip transceiver operates down to 2.4V and provides low power consumption
solutions for battery-operated and power sensitive applications. Thanks to the low external components count, the
XE1202A TrueRF™ is ideal for small size, low-cost UHF links. Its reference board design has no tunable
components, which facilitates high volume cost sensitive production.
The XE1202A TrueRF™ can easily be interfaced to a controller such as the XEMICS’ XE8000 Series of ultra lowpower microcontrollers. The XE1202A TrueRF™ serial control registers are programmed by the MCU and the MCU
manages the communication protocol.
IAmp
VDDA
VDD
QAMP
IAMP
VDDP
VDDF
VDDD
1 Functional Block Diagram
QAmp
SCAN
I
BPF
AMP
Limiter
AMP
DCLK
RFA
FSK
Demod.
LNA
Bit
Sync.
RFB
DATAOUT
Q
AMP
BPF
Limiter
AMP
Pattern
Recognition
LO
Buff.
Phase
Shifter
PATTERN
FEI
RSSI
MODE 0
MODE 1
Prog.
divider
MODE 2
Control
Logic
SI
SO
PA
RFOUT
VCO
modulator
/n Synthesizer
PFD
SCK
EN
POR
Oscillator
I Ref
/n
Clock Out
VSS
VSSA
VSSA
TSUPP
TVCO
CLKOUT
XTB
XTA
LFB
TKB
TKA
VSSP
VSSP
VSSF
VSSF
VSSD
DATAIN
Figure 1: XE1202A TrueRF™ block diagram
3
D0504-281
Data Sheet
XE1202A TrueRF™
2 Pin description
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
NAME
MODE(1)
MODE(0)
/EN
VSSF
RFA
RFB
VSSP
VSSP
RFOUT
VDDP
VSSP
VDD
TKA
TKB
VSSF
LFB
VDDD
VSSD
TSUPP
SCAN
OPT
TMOD[0]
TMOD[1]
VSSA
XTA
VSSA
XTB
VDDA
QAMP
IAMP
TMOD[2]
TMOD[3]
TIBIAS
VDD
SO
SI
SCK
CLKOUT
VSS
DCLK
DATAOUT
DATAIN
PATTERN
MODE(2)
In
In
In
In
In
In
In
Out
I/O
I/O
I/O
In
DESCRIPTION
Transmit/Receive/Standby/Sleep Mode Select
Transmit/Receive/Standby/Sleep Mode Select
Chip Enable
RF Analog Ground
RF Input
RF Input
Power Amplifier Ground
Power Amplifier Ground
RF Output
Power Amplifier Supply Voltage
Power Amplifier Ground
RF Analog Supply Voltage
VCO Tank
VCO Tank
RF Analog Ground
PLL Loop Filter
RF Digital Supply Voltage
RF Digital Ground
Test Circuit Supply Voltage (connected to VSS in normal operation)
Scan Test Input (connected to VSS in normal operation)
(connected to VSS in normal operation)
(connected to VSS in normal operation)
(connected to VSS in normal operation)
Analog Ground
I/O
Ref Xtal / Input of external clock
I/O
Analog Ground
Reference Xtal
Analog Supply Voltage
Out
Out
Buffered Q Output
Buffered I Output
Out
In
In
Out
Out
Out
In
Out
In
(connected to VSS in normal operation)
(connected to VSS in normal operation)
(connected to VSS in normal operation)
Digital Supply Voltage
Configuration Register Serial Output
Configuration Register Serial Input
Configuration Register Serial Clock
Output clock at reference frequency divided by 4, 8, 16 or 32
Digital Ground
Recovered Received Data Clock
Received Data
Transmit Data
Output of the pattern recognition block
Transmit/Receive/Standby/Sleep Mode Select
Table 1: Pin Description
4
D0504-281
Data Sheet
XE1202A TrueRF™
3 Electrical Characteristics
3.1
Absolute Maximum Operating Ranges
Stresses above those values listed below may cause permanent device failure. Exposure to absolute maximum
ratings for extended periods may affect device reliability.
Symbol
Description
Min.
Max.
Unit
VDDmax
Supply voltage
-0.4
3.9
V
ML
Receiver input level
-5
dBm
Tmax
Storage temperature
125
°C
Min.
Max.
Unit
2.4 (*)
3.6
V
-40
85
°C
-
25
pF
-55
Table 2: Absolute Maximum Operating Ranges
The device is ESD sensitive and should be handled with precaution.
3.2
Specifications
3.2.1
Operating Range
Symbol
Description
VDD
Supply voltage
T
Temperature
CLop
Load capacitance on digital ports
Table 3: Operating Range
(*) For narrow-band configurations (base-band filter bandwidths of 10, 20 and 40 kHz), the minimum operating
supply voltage is 2.4V. For 200 kHz base-band filter bandwidth setting the minimum operating supply voltage is
2.7V.
3.2.2
Electrical Specifications
The table below gives the electrical specifications of the transceiver under the following conditions:
Supply Voltage = 3.3V, temperature = 25 °C, 2-level FSK without pre-filtering, fC = 434, 869 and 915 MHz,
∆f = 5 kHz, Bit rate = 4.8 kbit/s, BWSSB = 10 kHz, BER = 1% (measured at the output of the bit synchronizer), LNA
input and PA output matched to 50Ω, environment as defined in section 6, unless otherwise specified.
5
Symbol
Description
IDDSL
Supply current in sleep mode
IDDST
Supply current in standby
mode
IDDR
Supply current in receive
mode
IDDT
Supply current in transmitter
mode
RFS
Conditions
Min
Typ
Max
Unit
-
0.2
1
uA
-
0.85
1.10
mA
-
14
16.5
mA
RFOP = 5 dBm
RFOP = 15 dBm
-
33
62
40
75
mA
mA
RF sensitivity 869 / 915 MHz
A-mode
B-mode
-
-116
-103
-113
-100
dBm
dBm
RF sensitivity 434 MHz
A-mode
B-mode
-
-114
-100
-111
-98
dBm
dBm
Crystal oscillator (39 MHz)
enabled
D0504-281
Data Sheet
XE1202A TrueRF™
Symbol
Description
Conditions
FDA
Frequency deviation
Programmable
CCR
Co-channel rejection
IIP3
Input intercept point (from
LNA input to base-band filter
output)
f1 = fLO + 1 MHz,
f2 = fLO + 1.995 MHz
A-mode
B-mode
Min
Typ
Max
Unit
-
5
10
20
40
100
-
kHz
kHz
kHz
kHz
kHz
-13
-10
-
dBc
-36
-21
-33
-18
-
dBm
dBm
-
10
20
40
200
-
kHz
kHz
kHz
kHz
BW
Base band filter bandwidth
Programmable
ACR
Adjacent channel rejection
869 / 915 MHz
funw = fLO + 65 kHz
Pw=-107 dBm, A-mode
45
48
-
dBc
Adjacent channel rejection
434 MHz
funw = fLO + 65 kHz
Pw=-102 dBm, A-mode
42
45
-
dBc
BR
Bit rate
Programmable
-
4.8
9.6
19.2
38.4
76.8
-
kbit/s
kbit/s
kbit/s
kbit/s
kbit/s
RFOP
RF output power
Programmable
-3
+2
+7
+12
-
dBm
dBm
dBm
dBm
433
868
902
0
+5
+10
+15
-
435
870
928
MHz
MHz
MHz
RFOP1
RFOP2
RFOP3
RFOP4
FR
Synthesizer frequency range
Programmable
Each range with its own
external components
TS_BBR
Receiver baseband wake-up
time (first step)
Crystal oscillator enabled
-
200
250
us
TS_TR
Transmitter wake-up time
Frequency synthesizer
enabled
-
100
150
us
TS_FS
Frequency synthesizer wakeup time
Crystal oscillator enabled
-
200
250
us
TS_BB2
Receiver RF Front-End
wake-up time
Frequency synthesizer
enabled
-
500
600
us
100
150
us
RTParam_WBB=0
TS_FSW
6
Frequency synthesizer
switching time
Between 2 channels at 1
MHz channel spacing
D0504-281
Data Sheet
XE1202A TrueRF™
Symbol
Description
Conditions
Min
Typ
Max
Unit
TS_RS
RSSI wake-up time (receiver
operation in mode 100)
RSSI enabled during
mode 010 0.5 ms before
switching to mode 100
(see figure 8)
-
-
1.0
ms
RSSI enabled during
mode 100
-
-
1.5
ms
TS_RSM
RSSI measurement time
-
0.5
-
ms
TS_OS
Crystal oscillator wake-up
time
-
0.3
0.5
ms
TS_FE
FEI wake-up time
(RTParam_Fsel = 1)
FEI counting duration
(RTParam_Fsel = 0)
-
-
20/BR
4/BR
ms
ms
-
39
MHz
500
-
-
-105
-100
-95
-90
-85
-80
-
dBm
Receiver enabled
RTParam_Fsel = 1
RTParam_Fsel = 0
FXTAL
Crystal oscillator frequency
FSTEP
Frequency synthesizer step
VTHR
Equivalent RSSI input
thresholds
Exact step is XTAL /
77824
A-mode,low range:VTHR1
VTHR2
VTHR3
A-mode,high range:VTHR1
VTHR2
VTHR3
Hz
dBm
dBm
dBm
dBm
dBm
FERR
FEI error threshold
Pw=-100 dBm, A-mode
RTParam_Fsel = 1
-
0.5
-
-
SPR
Spurious emission in receiver
mode
(1)
-
-65
-
dBm
VIH
Digital input level high
% VDD
75
-
-
%
VIL
Digital input level low
% VDD
-
-
25
%
VOH
Digital output level high
% VDD
75
-
-
%
VOL
Digital output level low
% VDD
-
-
25
%
Table 4: Electrical Specifications
(1) SPR strongly depends on the design of the application board and the choice of the external components.
Values down to -70 dBm can be achieved with careful design.
7
D0504-281
Data Sheet
XE1202A TrueRF™
4 Description
The XE1202A TrueRF™ is a direct conversion (Zero-IF) half-duplex data transceiver. It includes a receiver, a
transmitter, a frequency synthesizer and some service blocks. The circuit operates in the 3 ISM frequency bands
(433 MHz, 868 MHz, 915 MHz) and uses 2-level FSK modulation/demodulation to provide a complete transmission
link.
In a typical application, the XE1202A TrueRF™ is programmed by a microcontroller via the 3-wire serial bus, SI,
SO, SCK to write to and read from the configuration registers.
The circuit consists of 5 main functional blocks:
The Receiver converts the incoming 2-level FSK modulated signal into a synchronized bit stream. The receiver is
composed of a low-noise amplifier, down-conversion mixers, baseband filters, baseband amplifiers, limiters,
demodulator and the bit synchronizer. The bit synchronizer transforms the data output of the demodulator into a
glitch-free bit stream DATAOUT and generates a synchronized clock, DCLK, which can be used to sample
DATAOUT without requiring external signal processing. In addition, the receiver includes a Received Signal
Strength Indicator (RSSI) function, a Frequency Error Indicator (FEI) function that provides an indication of local
oscillator frequency error, and pattern recognition function to detect programmable reference words in the received
bit stream. The bandwidth of the base-band filters, the frequency deviation of the expected incoming FSK signal as
well as the bit rate of the received data are all programmable.
The Transmitter performs the modulation of the carrier by an input bit stream and the transmission of the
modulated signal. Carrier modulation is achieved directly through the frequency synthesizer via a Sigma-Delta
modulator. The frequency deviation and bit rate of the modulated carrier are programmable. An on-chip power
amplifier then amplifies the signal. The output power can be programmed to one of 4 possible settings.
The Frequency Synthesizer generates the local oscillator (LO) signal for the receiver section as well as the
continuous phase FSK (CPFSK) modulated signal for the transmitter section. The core of the synthesizer is
implemented with a PLL structure. The frequency is programmable with a step size of 500 Hz in the 3 ISM
frequency bands at 433, 868 and 915 MHz. This frequency synthesizer includes a crystal oscillator which provides
the reference for the PLL. This reference frequency can be divided by 4, 8, 16 or 32 and available as CLKOUT to
provide a clock signal for an external processor.
The Digital Interface provides internal control signals for the whole circuit according to the configuration register
settings.
The Service Block provides the internal voltage and current sources and provides all the necessary functions for
the circuit to work properly.
4.1
Detailed description
4.1.1
Receiver
The outputs of the receiver are the two signals DATAOUT and DCLK. When “RTParam_Bits” is set to “1” (see the
Configuration register section below), the bit synchronizer is enabled, and the two output signals are the output
NRZ demodulated data and the sampling clock, respectively. The function of the bit synchronizer is to remove the
glitches from DATAOUT and to provide the output clock DCLK to sample the data. The value of DATAOUT is valid
at the rising edge of DCLK.
To ensure correct operation of the bit synchronizer, the following three conditions must be satisfied:
- the received data must start with a preamble of 24 bits for synchronization; this preamble must be a
sequence of alternating “0” and “1”,
- the received data must have at least one transition from “0” to “1” or from “1” to “0” every 8 bits,
-
8
the accuracy of the bit rate must be within ± 5% of that programmed (assuming the reference Xtal
oscillator is 39 MHz).
D0504-281
Data Sheet
XE1202A TrueRF™
When “RTParam_Bits” is set to “0”, the bit synchronizer is turned off, and DATAOUT is the output of the
demodulator. In this case DCLK is not used and its value is set “low”.
For guaranteed operation of the demodulator, the modulation index, β, of the modulated carrier should meet the
2 ⋅ ∆f
following condition:
β=
≥ 2,
BR
where ∆f is the frequency deviation, and BR the bit rate.
Table 5 details typical sensitivity figures for different bit rates, frequency deviations and baseband filter bandwidths.
Bit rate
[kbit/s]
∆f
[kHz]
BW
[kHz]
4.8
5
mode A
mode B
10
-116
-103
20
40
-117
-104
10
20
-115
-101
20
40
-115.5
-102.5
20
40
-112.5
-99.5
40
200
-109
-97.5
40
200
-107
-95
100
200
-109
-97.5
100
200
-106.5
-95
9.6
19.2
38.4
76.8
Sensitivity for 1% BER [dBm]
Table 5: Sensitivity for 1 % BER
Figure 2 illustrates the typical BER curve under narrowband conditions:
RX in mode A
-2
10
-3
10
BER
-4
10
-5
10
-6
10
-116
-115
-114
-113
-112
Pin [dBm]
-111
-110
-109
Figure 2: BER versus Rx input power with BR=4.8 kbit/s, Df=5 kHz, BW=10 kHz
9
D0504-281
Data Sheet
XE1202A TrueRF™
4.1.2
Receiver LNA modes
The receiver can be operated in two different modes that provide the highest sensitivity (for reception of weak
signals) or the highest linearity (in areas of strong signals). The receiver mode is determined by the programming of
the “RTParam_Rmode” register (see the Configuration register section below).
-
A-mode: high sensitivity mode (see RFS parameter)
-
B-mode: high linearity mode (see IIP3 parameter)
4.1.3
RSSI
When enabled, this function provides an RSSI (Received Signal Strength Indication) based on the signal at the
output of the base-band filter. To enable the RSSI function, the bit “RTParam_RSSI” should be set to “1” (see the
Configuration register section below). When enabled, the status of the RSSI is a 2-bit word stored in register
“DataOut_RSSI”, which can be read via the serial control interface. The contents of the register are defined in
Table 6 below, where VRFFIL is the differential amplitude of the equivalent input RF signal when the receiver is
operated in A-mode. The thresholds VTHRi are the thresholds at the output of the base-band filter divided by the
gain between the input of the receiver and this output.
DataOut_RSSI
Description
00
VRFFIL ≤ VTHR1
01
VTHR1 < VRFFIL ≤ VTHR2
10
VTHR2 < VRFFIL ≤ VTHR3
11
VTHR3 < VRFFIL
Table 6: RSSI status description
Two ranges, each of three VTHRi thresholds are defined and selected via the setting of the register
“RTParam_RSSR”, to provide an overall RSSI range of typically 25 dB.
The timing diagram of an RSSI measurement is illustrated by Figure 3 below. When the RSSI function has been
activated the signal strength is periodically measured and the result is stored in the register “DataOut_RSSI” at
each rising edge of DATAIN. TS_RS is the wake-up time required after the function has been enabled to ensure
that a valid reading of RSSI is obtained. For a proper operation, the pulse length on DATAIN has to be higher than
8 µs.
RTParam_RSSI
/en
TS_RS
RSSI_out
(internal signal)
xxx
TS_RSM
val1
val2
val3
val4
0
datain
DataOut_RSSI
xxx
val1
val4
Figure 3: RSSI measurement timing diagram
10
D0504-281
Data Sheet
XE1202A TrueRF™
For applications where a valid RSSI reading is required within as short a time frame as possible, enabling the RSSI
during receiver mode 010 instead of 100 (see the definition of TS_RS on page 6) allows a valid RSSI within 1 ms of
valid data being received.
4.1.4
Frequency Error Indicator - FEI
When enabled, this function provides an indication of the frequency error of the local oscillator compared with the
received carrier frequency. For guaranteed operation of the FEI function, the following two conditions should be
satisfied.
The modulation index, b, of the modulated carrier should meet the following condition:
2 ⋅ ∆f
β=
≥ 2,
BR
where ∆f is the frequency deviation and BR is the bit rate.
The bandwidth of the baseband filter (BBW) must be greater than the sum of the frequency offset and the received
signal bandwith, as defined below:
BBW > fOFFSET + BWSIGNAL
where BBW is the baseband filter bandwidth defined by the RTParam_BW parameter (see the Configuration
Registers section below), fOFFSET is the difference between the carrier frequency and the LO frequency, and
⎞
⎛ BR
BWSIGNALis equal to ⎜
+ ∆f ⎟ .
2
⎠
⎝
The FEI function has two modes of operation, defined by the value set in the register “RTParam_Fsel” (see the
Configuration register section below).
4.1.4.1
“RTParam_Fsel” = 1
With the “RTParam_FEI” bit set to “1” and the “RTParam_Fsel” bit set to “1”, the FEI uses frequency correlation to
provide a 2-bit status word, which is stored in the register “DataOut_FEI”. The contents of this register are defined
below in Table 7. The status of this register is provided in the following table, where fLO is the internal local oscillator
frequency, and fRF is the carrier frequency of the received signal.
DataOut_FEI
Meaning
00
⏐fLO-fRF⏐ ≤ fERR
01
-
10
(fLO-fRF) > fERR
11
(fLO-fRF) < -fERR
Table 7: FEI status description
The value fERR = FERR * BR, where BR is the bit rate and FERR is a ratio given in the electrical specifications. As
an example, for a bit rate of 4.8 kbit/s and with FERR = 0.5, fERR is 2.4 kHz.
The FEI-Correlator function works properly only if the input signal is the preamble sequence defined under the
Receiver section above, and if the frequency error to be detected is lower than 20 kHz.
The time diagram of an FEI measurement is similar to that of an RSSI measurement, and is illustrated in Figure 4
below. When the FEI is enabled, the frequency error is periodically measured and the result is stored in the register
“DataOut_FEI” at each rising edge of DATAIN. TS_FE is the wake-up time required after the function has been
enabled to obtain a valid result. For a proper operation, the pulse length on DATAIN has to be higher than 8 µs.
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XE1202A TrueRF™
RTParam_FEI
en
fei_out
XX
VAL1
VAL2
VAL3
VAL4
XX
datain
DataOut_FEI
XX
VAL2
VAL4
TS_FE
Figure 4: FEI measurement timing diagram when “RTParam_Fsel” = 1
4.1.4.2 “RTParam_Fsel” = 0
With the “RTParam_FEI” bit set to “1” and the RTParam_Fsel” bit set to “0”, the FEI function uses over sampling of
the signal at the output of the demodulator. When activated by the rising edge of DATAIN, this function provides an
8-bit word equivalent to the duty cycle of the demodulated preamble, stored in register “DataOut_FEI”.
Each sample is used to control an up/down counter, when the sample is "1" the content of the counter is
incremented, when the sample is "0" the content of the counter is decremented. As a consequence, the final 8-bit
value of the counter stored in “DataOut_FEI” gives an indication of the duty cycle of the demodulated signal. The
range of stored values is from -128 and +127. The further from 0 the value of DataOut_FEI, the higher the error on
the LO frequency. If the stored value in “DataOut_FEI” is typically zero, then the duty cycle of the preamble is about
50%, and the LO frequency is nominally correct.
Since this FEI uses the signal before the bit synchronizer, its value can vary from one measurement to another,
due to the presence of jitter and glitches in the signal. If possible, it is advised to make 4-5 measurements and take
the average value.
The timing diagram for this FEI measurement is illustrated in Figure 5 below. The FEI function is activated at the
rising edge of the /EN signal when the RTParam_FEI bit is set to “1”. Then, the internal FEI counter is activated at
the rising edge of DATAIN. After a period TS_FE equal to the duration of 4 bits (see Electrical Specifications), the
counter is stopped and the contents are stored in the register DataOut_FEI. For a proper operation, the pulse
length on DATAIN has to be higher than 8 µs.
The maximum delay between the rising edge of DATAIN and the first clock on the internal FEI counter is 1/(16*BR),
where BR is the bit rate.
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XE1202A TrueRF™
RTParam_FEI
en
Demodulated
ffdemod_out
data
BIT B0
BIT B0+1
BIT B0+2
BIT B0+3
BIT B0+4
datain
counter_out
0
N
DataOut_FEI
N
X
TS_FE
Figure 5: Timing diagram of an FEI measurement when “RTParam_Fsel” = 0
(the number of transitions on “counter_out” is for illustration only)
4.1.5
Transmitter
The output power of the power amplifier is programmable on four values with the register “RTParam_Tpow” (see
the Configuration register section below), as shown in the table below, where RFOP values are given in Electrical
Specifications section.
RTParam_Tpow
Output power
00
RFOP1
01
RFOP2
10
RFOP3
11
RFOP4
Table 8: output power settings
The degree of filtering of the baseband data prior to the modulation of the LO carrier frequency is programmable
via the RTParam_Filter register:
- the input bit stream is directly applied to the frequency synthesizer without any pre-filtering
(RTParam_Filter=0)
- the input bit stream is pre-filtered before being applied to the frequency synthesizer; with this filtering, each
edge of the bit stream is linearly smoothed with a staircase transition (RTParam_Filter=1).
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XE1202A TrueRF™
This is illustrated in Figure 6, where DATAIN is the input bit stream to be transmitted:
tbit
datain
no filtering
IN freq_synth
trise
staircase filtering
IN freq_synth
Figure 6: Modulation without and with pre-filtering
The characteristic of the smoothing filter is the ratio trise/tbit. The value of this ratio is programmable with the register
“RTParam_Stair”, as illustrated in Table 9:
FSParam_Stair
trise/tbit
0
10%
1
20%
Table 9: Smoothing filter
4.1.6
Pattern recognition
XE1202A TrueRF™ includes a pattern recognition function. When “ADParam_Pattern” (see the Configuration
register section below) is set to “1” pattern recognition is enabled, providing that the bit synchronizer is also
enabled. With the pattern recognition function enabled, the demodulated data is compared with a pattern stored in
the “Pattern” register. The length of this pattern can be 8, 16, 24, or 32 bits, as defined by “ADParam_Psize”. When
comparing the streams 0, 1, 2, or 3 errors, as defined by “ADParam_Psize” can be allowed to detect a match. The
PATTERN output is driven by the output of this comparator. It is “high” when a match is detected, otherwise “low”.
When the feature is disabled, the PATTERN output is set to “low”.
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4.1.7
Frequency synthesizer
The exact frequency step of the frequency synthesizer can be obtained from the following equation:
FSTEP = FXTAL / 77 824.
As an example, if FXTAL is exactly 39 MHz, FSTEP = 501.13 Hz.
When the “RTParam_Clkout” bit is set high, FXTAL is frequency divided by 4, 8, 16, or 32, depending on the value
of register “ADParam_Clkfreq” (see the Configuration register section below), and made available as CLKOUT, for
use as clock signal for an MCU or external circuitry. If the reference frequency is 39 MHz, the available output
frequency of CLKOUT is 1.22, 2.44, 4.87, or 9.75 MHz, respectively. When the XE1202A TrueRF™ is in Sleep
Mode (MODE[2:0] = 000), CLKOUT is disabled.
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XE1202A TrueRF™
5 Serial Interface Definition, Principles of Operation
5.1
Serial Control Interface
5.1.1
General description
A 3-wire bi-directional bus (SCK, SI, SO) is used to program the XE1202A TrueRF™ and read data from it. SCK
and SI are input signals, for example generated by a microcontroller. SO is an output signal controlled by the
XE1202A TrueRF™. In write mode, at the falling edge of the SCK signal, the logic data on the SI line is written into
an internal shift register. In read mode, at the rising edge of the SCK signal, the data on the SO line becomes valid
and should be sampled at the next falling edge of SCK.
The signal /EN must be low during the complete write and read sequences. In write mode the actual content of the
configuration register is updated at the rising edge of the /EN signal. Before this, the new data is stored in
temporary registers whose content does not affect the transceiver settings.
5.1.2
Write sequence
The time diagram of a write sequence is illustrated in Figure 7 below. This sequence is initiated when a Start
condition is detected, defined by the SI signal being set to “0” during a period of SCK. The next bit is a read/write
(R/W) bit which should be “0” to indicate a write operation. The next 5 bits are the address of the control register
A[4:0] to be accessed, MSB first. Then the next 8 bits contain the data to be written in the register. The sequence
ends with 2 stop bits set to “1”. The data on SI should change at the rising edges of SCK, and is sampled at the
falling edge of SCK. After the 2 stop bits, the data transfer is terminated, even if the SI line stays at “1”. After this
the SI line should be at “1” for at least one clock cycle on SCK before a new write or read sequence can start. This
mode of operation allows data to be written to multiple registers without the need to alter the status of EN.
The maximum frequency of SCK is 1 MHz. The minimum clock pulse width is 0.5 us. Set-up and hold time for SI on
the falling edge of SCK is 200 ns, over the operating supply and temperature range.
SCK
SI
ST AR T
R/W
A(4)
A(1)
A(0)
D(7)
D(6)
D(3)
D(2)
D(1)
D(0)
STOP
STOP
SO
/EN
Figure 7: Write sequence into configuration register
5.1.3
Read sequence
The time diagram of a read sequence is illustrated in Figure 8. The sequence is initiated when a Start condition is
detected, defined by the SI signal being set to “0” during a period of SCK. The next bit is a read/write (R/W) bit
which should be “1” to indicate a read operation. The next 5 bits are the address of the control register A[4:0] to be
accessed, MSB first. The data from the register is then output on the SO pin.
The data becomes valid at the rising edges of SCK and should be sampled at the falling edge of SCK. After this the
data transfer is terminated. The SI line must stay high for at least one clock cycle on SCK to start a new write or
read sequence. The maximum current drive on SO is 2 mA for a supply voltage of 2.7V, and the maximum load is
CLop, as defined in the Electrical Specifications.
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XE1202A TrueRF™
SC K
SI
START
R/W
A(4)
A(0)
SO
D(7)
D(6)
D(5)
D(4)
D(3)
D(2)
D(1)
D(0)
/EN
Figure 8: Read sequence into configuration register
When the serial interface is not used for read or write operations, both SCK and SI should be set to “1”.
Note that except in read mode, SO is set to “0” and cannot be configured in a high-impedance mode.
5.2
Configuration and Status registers
XE1202A TrueRF™ has a series of configuration registers programmable through the serial control interface
described above. Their details are listed in Table 10 below. The size of these registers is 1, 2, 3, or 4 bytes. Their
byte address is a 5 bit address, A[4:0]. In addition, there is one register, DataOut, from which users can read
various transceiver status information.
Name
Size
Byte Address
Description
RTParam
2 x 8 bit
00000
00001
Receiver and transmitter
parameters registers
FSParam
3 x 8 bit
00010
00011
00100
Frequency parameters
DataOut
1 x 8 bit
00101
Transceiver data register
ADParam
2 x 8 bit
00110
00111
Additional parameters
Pattern
4 x 8 bit
01000
01001
01010
01011
Reference pattern for the “pattern
recognition” function
Table 10: Configuration registers
All the bits that are referred to as “reserved” in this section should be set to “0” during write operations.
5.2.1
17
RTParam configuration register
Name
Bits
Byte Address
Description
RTParam_Rmode
7
00000
Receiver modes:
0 -> A-mode (high sensitivity)
1 -> B-mode (high linearity)
RTParam_Bits
6
00000
Bit synchronizer on/off:
0 -> off; 1 -> on
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XE1202A TrueRF™
Name
Bits
Byte Address
Description
RTParam_RSSI
5
00000
RSSI on/off:
0 -> off; 1 -> on
RTParam_FEI
4
00000
FEI on/off:
0 -> off; 1 -> on
RTParam_BW
3-2
00000
Bandwidth of the BB filter:
0 0 -> 10 kHz
0 1 -> 20 kHz
1 0 -> 40 kHz
1 1 -> 200 kHz
RTParam_Tpow
1-0
00000
Transmitter output power:
0 0 -> 0 dBm
0 1 -> 5 dBm
1 0 -> 10 dBm
1 1 -> 15 dBm
RTParam_Osc
7
00001
Source for the reference frequency:
0 -> on-chip crystal oscillator
1 -> external signal
RTParam_WBB
6
00001
Receiver wake-up type selection
0 -> “Boost” power up sequence
1 -> Standard power-up sequence
RTParam_Filter
5
00001
Pre-filtering of bit stream in
transmitter mode:
0 -> no filtering; 1 -> filtering
RTParam_Fsel
4
00001
RTParam_Stair
3
00001
FEI mode:
0 -> FEI_Demodulator
1 -> FEI_Correlator
Rise and fall time when
RTParam_Filter = 1:
0 -> 10 % of bit duration
1 -> 20 % of bit duration
RTParam_Modul
2
00001
Modulation switch:
0 -> modulation enabled;
1 -> modulation disabled
RTParam_RSSR
1
00001
RSSI range:
0 -> low range; 1 -> high range
RTParam_Clkout
0
00001
CLKOUT enable:
0 -> CLKOUT disabled
1 -> CLKOUT enabled (equal to
FXTAL divided by 4, 8, 16 or 32)
Table 11: RTParam configuration register
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5.2.2
FSParam configuration register
Name
Bits
Byte
Address
Description
FSParam_Band
7-6
00010
Frequency band:
0 0 -> not valid
0 1 -> 433 – 435 MHz
1 0 -> 868 – 870 MHz
1 1 -> 902 – 928 MHz
FSParam_Dev
5-3
00010
Frequency deviation:
0 0 0 -> 5 kHz
0 0 1 -> 10 kHz
0 1 0 -> 20 kHz
0 1 1 -> 40 kHz
1 0 0 -> 100 kHz
FSParam_BR
2-0
00010
Bit rate:
0 0 0 -> 4.8 kbit/s
0 0 1 -> 9.6 kbit/s
0 1 0 -> 19.2 kbit/s
0 1 1 -> 38.4 kbit/s
1 0 0 -> 76.8 kbit/s
others -> not valid
FSParam_Freq
7-0
7-0
00011
00100
LO frequency in 2’s-complement representation:
00…0 -> fLO = middle of the range
0X…X -> fLO = higher than the middle of the range
1X…X -> fLO = lower than the middle of the range
MSB = bit 7 of byte at pos. 00011
LSB = bit 0 of byte at pos. 00100
See example below
Table 12: FSParam configuration register
Table 13 below provides an example of LO frequency setting in FSParam_Freq.
Byte Address
00011
Bit 7
Bit 0
Byte Address
00100
Bit 7
Bit 0
LO frequency
Note: FXTAL = 39.0 MHz
00000000
00000000
F0, where F0 depends on the selected
frequency band (see FSParam_Band )
F0 = 434.0 MHz for the 433-435 MHz band
F0 = 869.0 MHz for the 868-870 MHz band
F0 = 915.0 MHz for the 902-928 MHz band
00000000
00000001
F0 + 500 Hz
00000000
00000010
F0 + 2 * 500 Hz
11111111
11111111
F0 – 500 Hz
11111111
11111110
F0 – 2 * 500 Hz
Table 13: LO Frequency setting
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XE1202A TrueRF™
5.2.3
DataOut register
Name
Bits
Byte Address
Description
DataOut_RSSI
7-6
00101
RSSI output:
0 0 -> lowest level
0 1 -> 2nd level
1 0 -> 3rd level
1 1 -> highest level
DataOut_FEI
When
RTParam_Fsel = 0
7-0
00101
FEI output:
Output of the up/down counter in
2’s-complement representation
MSB = bit 7
DataOut_FEI
When
RTParam_Fsel = 1
5-4
00101
FEI output:
0 0 -> frequency OK
1 0 -> frequency too low
1 1 -> frequency too high
Table 14: DataOut register
5.2.4
20
ADParam configuration register
Name
Bits
Byte Address
Description
ADParam_Pattern
7
00110
Pattern recognition enable:
0 -> Disabled
1 -> Enabled
ADParam_Psize
6-5
00110
Size of reference pattern recognition
word:
0 0 -> 8 bits
0 1 -> 16 bits
1 0 -> 24 bits
1 1 -> 32 bits
ADParam_Ptol
4-3
00110
Number of tolerated errors for the
pattern recognition:
0 0 -> 0 error
0 1 -> 1 error
1 0 -> 2 errors
1 1 -> 3 errors
ADParam_Clkfreq
2-1
00110
Frequency of CLKOUT:
0 0 -> 1.22 MHz (div. ratio: 32)
0 1 -> 2.44 MHz (div. ratio: 16)
1 0 -> 4.87 MHz (div. ratio: 8)
1 1 -> 9.75 MHz (div. ratio: 4)
ADParam_IQA
0
00110
IQ amplifiers enable:
0 -> Disabled
1 -> Enabled
ADParam_Res1
7
00111
Reserved. Should be set to “0”
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Data Sheet
XE1202A TrueRF™
Name
Bits
Byte Address
Description
ADParam_Invert
6
00111
Inversion of the Rx output data:
0 -> non-inverted data
1 -> inverted data
ADParam_RegBW
5
00111
Baseband filter bandwidth
regulation:
0 -> Enabled
1 -> Disabled
ADParam_Regfreq
4
00111
Periodicity of baseband filter
bandwidth regulation:
0 -> only at start-up of the receiver
1 -> every 60 seconds whilst
receiver enabled
ADParam_Regcond
3
00111
Regulation process of the baseband
filter bandwidth according to the
selected bandwidth:
0 -> regulation restarted each time
the bandwidth is changed
1 -> no regulation when
bandwidth is changed
ADParam_WBBcond
2
00111
Boosting process of the baseband
filter according to the selected
bandwidth:
0 -> boosting restarted each time
the bandwidth is changed
1 -> no boosting when
bandwidth is changed
ADParam_Xsel
1
00111
Selection of the XOSC load
capacitance mode:
0 -> CLop + C0 = 15 pF
1 -> CLop + C0 = 11 pF (low-current
mode)
RESERVED
0
00111
RESERVED
Table 15: ADParam configuration register
5.2.5
Pattern register
The pattern register may be used to automatically detect the reception of a user-defined pattern and asserts the
PATTERN signal for one bit duration. In this register, a reference pattern length of 8, 16, 24, or 32 bits (see
ADParam_Psize parameter) may be defined. The first byte of the pattern is always stored at byte address A[4:0] (=
01000). If defined, the second and subsequent byte(s) are stored at address A[4:0] = 01001, and so on.
The MSB of the reference pattern is always bit 7 of the address 01000 and the LSB is bit 0 of address 01000,
01001, 01010, or 01011 if the pattern length is 8, 16, 24, or 32 bits, respectively.
Comparing the demodulated data, the first bit received of the last word (or second, third or fourth from last word,
depending upon the value stored in the ADParam_Psize register) is compared with bit 7 (the MSB) of byte address
01000. The last bit received is compared with bit 0 (the LSB) in the Pattern register.
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XE1202A TrueRF™
Name
Bits
Byte Address
Pattern
7-0
01000
01001
01010
01011
Description
1st byte of the reference pattern
2nd byte
3rd byte
4th byte
Table 16: Pattern register addresses
Table 17 below shows an example of pattern recognition with a 32-bit pattern:
Byte Address
01000
Bit 7
Bit 0
Byte Address
01001
Bit 7
Bit 0
Byte Address
01010
Bit 7
Bit 0
Byte Address
01011
Bit 7
Bit 0
10010011
10101010
10010011
10101010
101 10010011
10101010
10010011
10101010
previous bits from
demodulator
last bit received
Table 17: Pattern recognition example (32-bit)
Table 18 below shows an example of pattern recognition with an 8-bit pattern.
Byte Address
01000
Bit 7
Bit 0
Byte Address
01001
Bit 7
Bit 0
Byte Address
01010
Bit 7
Bit 0
Byte Address
01011
Bit 7
Bit 0
10010011
xxxxxxxx
xxxxxxxx
xxxxxxxx
101 10010011
previous bits from
demodulator
last bit received
Table 18: Pattern recognition example (8-bit)
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XE1202A TrueRF™
5.2.6
Supplementary configuration
Configuration settings to optimize device performance under certain operation conditions are described in Table 19
below:
Name
Bits
Byte Address
TParam_BW
2
10011
Description
Bandwidth decoding map:
Baseband filter bandwidth
(RTParam_BW):
0 -> default values:
RTParam_BW(1:0) = 00 => 10 kHz
RTParam_BW(1:0) = 01 => 20 kHz
RTParam_BW(1:0) = 10 => 40 kHz
RTParam_BW(1:0) = 11 => 200 kHz
1 -> new values:
RTParam_BW(1:0) = 00 => 14.3 kHz
RTParam_BW(1:0) = 01 => 28.5 kHz
RTParam_BW(1:0) = 10 => 66.7 kHz
RTParam_BW(1:0) = 11 => 100 kHz
TParam_HPF
5-3
10110
Cut-off frequency of the HPF stages
allowing to cancel the DC and lowfrequency offsets in the baseband
circuit:
0 0 0 -> 660 Hz (default value)
0 0 1 -> 1.48 kHz
0 1 0 -> 1.75 kHz
0 1 1 -> 1.96 kHz
1 0 0 -> 2.55 kHz
1 0 1 -> 3.34 kHz
1 1 0 -> 5.11 kHz
1 1 1 -> 10.2 kHz
Table 19: Supplementary configuration
Using TParam_BW allows intermediate bandwidths to be accessed; these additional bandwidths can be selected to
optimize the sensitivity and the selectivity of the applications for which the signal bandwidth is different from the 4
default filter bandwidths.
The wake-up time of the receiver may be reduced by increasing the cut-off frequency of the HPF stages. This is
accomplished by changing the value of TParam_HPF.
Note that the selected cut-off frequency should be less than (∆f – (BR/2)) to avoid sensitivity degradation.
5.3
Operating Modes
The XE1202A TrueRF™ has 4 main operating modes as set by the MODE[2:0] inputs as illustrated in Table 20
below. Switching between modes is only possible when the /EN signal is low. The actual change will be applied to
the transceiver upon the rising edge of the /EN signal.
Over the operating supply and temperature range, set-up and hold time for MODE[2:0] on the rising edge of /EN is
200 ns, while the negative pulse duration on /EN is 2 us minimum. Please refer to Figure 9.
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XE1202A TrueRF™
MODE[2:0]
XXX
YXY
Transceiver in Mode XXX
Transceiver in Mode YXY
EN
Figure 9: Switching mode sequence
Name
MODE(2:0)
Description
Sleep mode
000
-
Standby mode
001
Xtal oscillator enabled
Receiver mode
100
Xtal oscillator, Frequency synthesizer, Receiver enabled
Transmitter mode
111
Xtal oscillator, Frequency synthesizer, Transmitter enabled
Table 20: XE1202A TrueRF™ Main operating modes
Three additional operating modes are defined and should be used when the transceiver is switched from the
standby mode to the receiver or transmitter mode. These additional operating modes are illustrated in Table 21
below.
Name
MODE(2:0)
Receiver mode
010
Xtal oscillator, Baseband enabled (first step)
011
Xtal oscillator, Frequency synthesizer, Baseband enabled
(first step)
110
Xtal oscillator, Frequency synthesizer enabled
Transmitter mode
Description
Table 21: XE1202A TrueRF™ Additional operating modes
The power up sequence from sleep to receiver mode is selected by setting the RTParam_WBB parameter to “0”. The
sequence is described in Table 22 below:
Received data valid
Mode = 000
Mode = 001
Mode = 010
Mode = 011
Mode = 100
Mode=001
- Sleep
- Xtal
oscillator
enenabled
- Baseband
- Xtal
oscillator
enabled
- Frequency
synthesizer
- Baseband
- Xtal oscillator
enabled
- RF Front End
- Frequency synthesizer
- Baseband
- Xtal oscillator
enabled
- Xtal
oscillator
enabled
≥TS_OS
≥TS_BBR
≥TS_FS
≥TS_BB2
Table 22: Power up sequence from Standby to Receive Mode
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XE1202A TrueRF™
The typical current consumption values during the power-up sequence from Standby to Receive Mode are shown
in Table 23 as follows:
14.0 mA
11.5 mA
3.0 mA
0.85 mA
<1 uA
Mode= 000
Mode= 001
Mode=010
Mode =011
Mode = 100
≥TS_OS
≥TS_BBR
≥TS_FS
≥TS_BB2
Table 23: Typical current consumption profile during the power up sequence from Standby to Receive Mode
The power up sequence from sleep to transmit mode is described in Table 24:
Transmission
Mode = 000
Mode = 001
Mode = 110
Mode =111
Mode=001
- Sleep
- Xtal
oscillator
enabled
- Frequency
synthesizer
- Xtal
oscillator
enabled
- Power Amplifier
- Frequency synthesizer
- Xtal oscillator
enabled
- Xtal
oscillator
enabled
≥TS_OS
≥TS_FS
≥TS_TR
Table 24: Standard power up sequence from Standby to Transmit Mode
5.4
Transmitted Data Interface
When in transmit mode (MODE[2:0] = 111), the DATAIN signal is used as input for the on-chip modulator. DATAIN
is not sampled, so the bit duration should match the bit rate setting of the receiver. Whenever XE1202A TrueRF™
are used on both sides of the communication link, the bit rate should be one of those defined in Table 4 (BR). In
this case the bit rate error should be less than 5% compared to the specified value.
DATAIN
(NRZ)
BIT N+1
BIT N
1/BR
Figure 10: DATAIN timing
5.5
Received Data Interface
The outputs of the receiver are the two signals DATAOUT and DCLK. When the bit “RTParam_Bits” is “1”, the bit
synchronizer is turned on, and the two output signals are respectively the output NRZ bit stream and the sampling
clock. The value of DATAOUT is valid at the rising edge of DCLK (see Figure 11 on next page):
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Data Sheet
XE1202A TrueRF™
DATAOUT
(NRZ)
BIT N+1
BIT N
DCLK
Figure 11: DATAOUT timing
When “RTParam_Bits” is “0”, the bit synchronizer is turned off, and the signal DATAOUT is the output of the
demodulator. In this case DCLK is not used and its value is set to “low”. The maximum current drive on DATAOUT
and DCLK is 2 mA @ 2.7V, the maximum load is CLop.
5.6
Pattern Recognition Interface
When this feature is enabled, the incoming NRZ bit stream is compared with a pattern stored in the “Pattern”
register. The PATTERN output (active-low) is driven by the output of this comparator and is synchronized by DCK.
It is asserted when a match is detected, otherwise negated (please see Figure 12, below). Changes occur at the
rising edge of DCK.
DATAOUT
(NRZ)
BIT N-x=PATTERN[x]
BIT N-1=PATTERN[1] BIT N=PATTERN[0]
DCLK
PATTERN
Figure 12: Pattern Recognition timing
When the feature is disabled, the PATTERN output is always negated. The maximum current drive on PATTERN is
2 mA @ 2.7V, the maximum load is CLop.
5.7
Clock Output Interface
CLKOUT is a clock signal at 1.22, 2.44, 4.87, or 9.75 MHz, depending on user-programming. When the XE1202A
TrueRF™ is in Sleep Mode (MODE[2:0] = 000) or when “RTParam_Clkout” is low, this clock is disabled.
5.8
Default settings at power-up
Upon power-up all RTParam, FSParam, ADParam and Pattern registers are set to 00H.
At power-up, the XE1202A TrueRF™ is in Standby mode, which means that the Xtal oscillator is enabled;
additionally a clock signal at 1.22 MHz (reference frequency divided by 32) is present at CLKOUT. However,
internally, RTParam_Clkout is low, which means that if the configuration register remains unaltered, the clock
signal at CLKOUT will be disabled on the first rising edge of /EN; in addition, at the first rising edge of /EN, the
circuit will be put in the mode corresponding to the status of the signals at MODE(2:0) inputs. Thus, to keep the
circuit in Standby mode and the clock signal present on CLKOUT, RTParam_Clkout has to be set high during the
first communication through the 3-wire bus, and the MODE(0) has to be set high before the first rising edge of /EN.
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Data Sheet
XE1202A TrueRF™
6 Application Information
This section provides details of the recommended component values for the frequency dependant blocks of the
XE1202A TrueRF™. Note that these values are dependent upon circuit layout and PCB structure, and that
decoupling components have been omitted for clarity.
6.1
Receiver matching network
The schematic of the matching network at the input of the receiver is given Figure 13 below (for a source
impedance of 50Ω).
CR1
RFA
SOURCE
LR1
CR3
XE1202A
EAGLE ASIC
TrueRF™
RFB
CR2
VSS
Figure 13: Receiver matching network
The typical recommended values for the external components are given in Table 25.
Name
434 MHz
869 MHz
915 MHz
CR1
1.5 pF ± 5%
1.2 pF ± 5%
0.82 pF ± 5%
CR2
1.5 pF ± 5%
1.5 pF ± 5%
0.82 pF ± 5%
CR3
NC
NC
NC
LR1
100 nH ± 5%
27 nH ± 5%
27 nH ± 5%
Table 25: External Matching Components
6.2
Transmitter matching network
The optimum load impedances for 15 dBm output power at the three main frequencies are given in Table 26.
PA optimum load
434 MHz
869 MHz
915 MHz
66 – 5j
66 + 14j
64 + 13j
Table 26: Optimum load impedance versus frequency
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Data Sheet
XE1202A TrueRF™
The Smith charts in Figure 14 and Figure 15 below show curves of output power versus load impedance when the
highest output level is selected (15 dBm mode).
15 dBm 869MHz
0.5
0.2
0.1
15 dBm
0.1
0.2
0.5
14 dBm
0.1
12 dBm
0.2
0.5
Figure 14: Output power versus load impedance at 869 MHz
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Data Sheet
XE1202A TrueRF™
15 dBm 915MHz
1
1.2
1.4
1.6
1.8
0.5
2
2.4
3
4
0.2
5
0.1
15 dBm
10
20
0.1
0.2
0.5
50
2.4
50
20
14 dBm
10
0.1
5
0.2
12 dBm
4
3
0.5
2
1.8
1.6
1.4
1
1.2
Figure 15: Output power versus load impedance at 915 MHz
The schematic of the recommended matching network at the output of the transmitter is given in Figure 16 below.
The two Π-sections are used to provide harmonic filtering for passing FCC and ETSI regulations:
LT1
LT2
XE1202A
TrueRF™
CT3
CT4
LT3
CT5
CT2
CT1
VDD
...
Figure 16: Transmitter output network
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Data Sheet
XE1202A TrueRF™
The typical component values of this matching circuit are given Table 27 below.
Name
Typical Value
for 434 MHz
Typical Value
for 869 MHz
Typical Value
for 915 MHz
Tolerance
CT1
6.8 pF
1.5 pF
1.8 pF
± 5%
CT2
1.0 pF
0.56 pF
NC
± 5%
CT3
22 pF
15 pF
33 pF
± 5%
CT4
6.8 pF
3.3 pF
3.3 pF
± 5%
CT5
4.7 pF
2.2 pF
2.2 pF
± 5%
LT1
33 nH
39 nH
47 nH
± 5%
LT2
22 nH
10 nH
10 nH
± 5%
LT3
22 nH
8.2 nH
8.2 nH
± 5%
Table 27: Matching circuit component values
6.3
VCO tank
The tank of the VCO is implemented with an inductor in parallel with an (optional) capacitor. The recommended
values for these components are given in Table 28 below.
Name
434 MHz
869 MHz
915 MHz
LR1
39 nH ± 2%
6.8 nH ± 2%
5.6 nH ± 2%
CR1
NC
NC
NC
Table 28: VCO tank component values
In order to optimize the tuning range of the VCO, the value of the inductance should be as high as possible and
external capacitance must be avoided if possible. It is recommended that the PCB layout includes two ‘footprints’ in
order to place two inductances in parallel; this enables the tank of the VCO to be centered more precisely.
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Data Sheet
XE1202A TrueRF™
6.4
Loop filter of the frequency synthesizer
The loop filter of the frequency synthesizer is shown in Figure 17 below:
LFB
RL1
CL2
XE1202A
TrueRF™
CL1
VSS
Figure 17: Loop filter of the frequency synthesizer
The recommended values for the external components are given in the following table.
Name
434 MHz
869 MHz
915 MHz
CL1
22 nF ± 10%
22 nF ± 10%
22 nF ± 10%
CL2
1 nF ± 5%
1 nF ± 5%
1 nF ± 5%
RL1
0.56 kΩ ± 5%
0.47 kΩ ± 5%
0.47 kΩ ± 5%
Table 29: loop filter component values
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Data Sheet
XE1202A TrueRF™
6.5
Reference crystal for the frequency synthesizer
For narrow band applications, (lowest frequency deviation and the narrowest baseband filter), the crystal for
reference oscillator of the frequency synthesizer should have characteristics as shown in Table 30:
Name
Fs
Description
Nominal frequency
CL
Rm
Cm
C0
∆fs(0)
∆fs(∆T)
Load capacitance for fs (on-chip)
Motional resistance
Motional capacitance
Shunt capacitance
Calibration tolerance at 25 °C
Stability over temperature range
(-40 °C to 85 °C)
Aging tolerance in first 5 years
∆fs(∆t)
Min. value
-
Max. value
-
-
Typ. Value
39.0 MHz
(fundamental)
8 pF (*)
-
-
-
5 ppm
40Ω
30 fF
7 pF (*)
10 ppm
10 ppm
Table 30: Recommended crystal characteristics
(*) The on-chip oscillator is implemented in two selectable versions: the first for CL = 8 pF and C0 = 7 pF, and the
second for CL = 8 pF and C0 = 3 pF; the latter will allow larger amplitude for the internal signal with slightly lower
power consumption.
The electrical specifications given in Section 3.2.2 are valid provided the crystal satisfies the specifications given in
Table 30.
For less demanding applications (wider signal bandwidth and/or reduced temperature range), it is possible to use a
crystal with larger values for ∆fs(0), ∆fs(∆T), and/or ∆fs(∆t). In this case fOFFSET + BWssb should be lower than
BBW, where fOFFSET is the offset (error) from the carrier frequency (the sum of ∆fs(0), ∆fs(∆T), and/or ∆fs(∆t)),
BWssb is the single side-band bandwidth of the signal, and BBW is the single side-band bandwidth of the baseband filter.
The XE1202A TrueRF™ can be used with a 3rd overtone reference crystal operating on its 3rd harmonic at 39.00
MHz. Note however that:
a) the oscillator start-up time is higher than in fundamental mode,
b) an extra 1.5 k – 16 kΩ resistor has to be placed in parallel with the crystal. In this case, the crystal should
have CL = 8 to 10 pF, Rm < 60 Ω, C0 < 7 pF.
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Data Sheet
XE1202A TrueRF™
7 Packaging information
VDD
SO
SI
SCK
CLKOUT
VSS
DCLK
DATAOUT
DATAIN
PATTERN
MODE(2)
XE1202A TrueRF™ is assembled in a 44-lead LQFP package as shown in Figure 18.
VSS
MODE(1)
VSS
MODE(0)
VSS
EN
IAMP
VSSF
RFA
QAMP
XE1202A
XE1202A
TrueRF™
RFB
VSSP
VDDA
XTB
VSSA
VSSP
XTA
RFOUT
VSSA
VDDP
VSS
VSS
VSS
SCAN
TSUPP
VSSD
VDDD
LFB
VSSF
TKB
TKA
.
VDDF
VSSP
Figure 18: Package pinning and dimensions
©XEMICS 2005
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