SC4806 Datasheet

SC4806
Multiple Function
Double Ended PWM Controller
POWER MANAGEMENT
Description
Features
The SC4806 is a double ended, high speed, highly
integrated PWM controller optimized for applications
requiring minimum space. The device is easily configurable
for current mode or voltage mode operation and contains
all the control circuitry required for isolated applications,
where a secondary side error amplifier is used.
Designed for simplicity, the SC4806 is fully featured and
requires only a few external components. It features a
programmable frequency up to 1MHZ, external
programmable soft start, pulse-by-pulse current limit and
over current protection for both voltage and current
modes, as well as a line monitoring input with hysteresis
to reduce stress on the power components. A ramp pin
allows for slope compensation to be programmed by
external resistors for current mode. This also allows for
operation in voltage mode with voltage feed forward.
A unique oscillator is utilized which allows two SC4806
to be synchronized together and work out-of-phase. This
feature minimizes the input and output ripples, and
reduces stress and size on input/output filter components.
The outputs are configured for push-pull format, dead time
between the 2 outputs is programmable depending on the
size of the timing components.
The SC4806 features a turn on threshold of 8 volts .
The device is available at a MLP-12 package.
‹ 90 µA starting current
‹ Pulse-by-pulse current limit for both voltage/current
‹
‹
‹
‹
‹
‹
‹
‹
‹
‹
‹
modes
Programmable operating frequency up to 1MHz
Programmable external soft start
Programmable line undervoltage lockout
Programmable external slope compensation
Over current shutdown with separate pin
Dual output drive stages on push-pull configuration
Programmable mode of operation (peak current mode
or voltage mode)
External frequency synchronization
Bi-phase mode of operation
Lead free MLP-12 package,WEEE and RoHS
compliant
-40 to 105 °C operating temperature
Applications
‹
‹
‹
‹
‹
‹
‹
Typical Application Circuit
Telecom equipment and power supplies
Networking power supplies
Industrial power supplies
Push-pull converter
Half bridge converter
Full bridge converter
Isolated VRMs
+VIN
+Vo
+
+
-VIN
-Vo
I sense
ON/OFF
Vcc
Rsense
1
SC4806
LUVLO
RC
SS
SYNC
4
2
SYNC
3
REF
VCC
Vcc
12
REF
OUTA
OUTB
SC1301A
11
FB
SC431
10
0
9
7
8
RAMP
FB
6
ILIM
GND(heatsink)
GND
SC1301A
5
REF
REF
FB
I sense
Revision: October 13, 2006
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SC4806
POWER MANAGEMENT
Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in
the Electrical Characteristics section is not implied.
Parameter
Symbol
Maximum
Units
Supply Voltage
V CC
-0.5 to18
V
Supply Current
ICC
20
mA
-0.5 to 7
V
SYNC, RC,RAMP, LUVLO, REF, ILM, SS to GND
FB to GND
V FB
-0.5 to (VREF+ 0.5)
V
REF Current
IREF
10
mA
VOUTA/B
-0.5 to 18
V
Isource
-250
mA
OUTA/OUTB Sink Current (peak)
Isink
250
mA
Thermal Resistance, Junction to Ambient
θJ A
32
°C/W
Thermal Resistance, Junction to Case
θJ C
3
°C/W
Junction Temperature
TJ
-55 to 150
°C
Storage Temperature Range
TSTG
-65 to 150
°C
Peak IR Reflow Temperature 10 - 40s
TPKG
260
°C
ESD Rating (Human Body Model)
ESD
2
kV
OUTA/OUTB to GND
OUTA/OUTB Source Current (peak)
Electrical Characteristics
Unless specified: VCC = 12V; CL = 100pF; TA = -40°C to 105°C
Parameter
45455
Test Conditions
Min
Typ
Max
Units
VCC Start Threshold
7.4
8
8.6
V
Hysteresis
1.17
1.5
1.83
V
VCC Supply
Startup Current
VCC < start threshold
150
µA
Operating Supply Current
FB = 0V, RAMP = 0V
7
mA
VCC Zener Shunt Voltage
IDD = 10mA
16
Maximum Duty Cycle
Fosc = 50kHz, FB = 5V,
Measured at OUTA or OUTB
48
Minimum Duty Cycle
Fosc = 50kHz, FB = 1.5V,
Measured at OUTA or OUTB
V
PWM
49
50
%
0
%
600
mV
Current Sense/Limit
ILM Cycle by Cycle Current Limit Threshold
450
ILM to Output Delay
525
50
ns
ILM Auto Restart Over Current Threshold
750
850
950
mV
FB to RAMP Offset
1.20
1.40
1.60
V
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SC4806
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Unless specified: VCC = 12V; CL = 100pF; TA = -40°C to 105°C
Parameter
Test Conditions
Min
Typ
Max
Unit
Start Threshold
Rhigh = 14kΩ, Rlow = 10kΩ
-3%
VREF
+3%
V
Hysteresis
Rhigh = 14kΩ, Rlow = 10kΩ
Line Under Voltage Lockout
5.5% of
VREF
mV
Soft Start
Internal Soft Start Charge
Current (ISS)
VSS = 1.5V
Internal Discharge Current
VSS = 1.5V
25
35
45
10
µA
µA
Oscillator
Oscillator Frequency
Rosc = 10kΩ, Cosc = 200pF
450
Guaranteed by characterization
200
RC pin to GND Capacitance
Oscillator Frequency Range
550
VREF/2
+0.25
Oscillator Ramp
Oscillator Fall Time
500
V
250
22
Guaranteed by characterization
50
KHz
ns
pF
1000
KHz
Sync/CLOCK
Clock SYNC Threshold
Sync Frequency Range
1.75
Guaranteed by characterization
V
FOSC *1.3
KHz
5.25
V
B an d g ap
ReferenceVoltage
4.75
5.0
Reference Load Regulation
IREF = 0 - 5mA
10
mV/mA
Reference Line Regulation
VCC = 8.5V to 15V
0.3
mV/V
Output
OUT Low Level
0.5
OUT High Level
V C C = 12V
Rise Time
Fall Time
10.85
0.7
V
11.20
V
Load 1nF
35
ns
Load 1nF
35
ns
Minimal Dead Time
200
250
ns
Thermal Shutdow n
Thermal Shutdown
Threshold TSD
175
°C
Thermal Shutdown
Hysteresis
15
°C
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SC4806
POWER MANAGEMENT
Pin Configuration
Ordering Information
TOP VIEW
VCC
12
OUTA OUTB
11
1
9
GND
SS
2
8
REF
SYNC
3
7
FB
4
5
RC ILIM
PACKAGE
Temp. Range (TJ)
SC4806MLTRT(2)
MLPQ-12
-40°C to 105°C
Notes:
(1) Only available in tape and reel packaging. A reel
contains 3000 devices.
(2) Lead free product. This product is fully WEEE and
RoHS compliant.
10
LUVLO
DEVICE(1)
6
RAMP
BOTTOM VIEW
RC
4
SYNC
3
SS
2
LUVLO
1
ILIM
5
RAMP
6
GND
12
VCC
11
7
FB
8
REF
9
GND
10
OUTA OUTB
(MLPQ-12 4x4)
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SC4806
POWER MANAGEMENT
Pin Descriptions
LUVLO (Pin 1):
RC (Pin 4):
Line undervoltage lockout pin. An external resistive divider from the Input supply will program the undervoltage
lockout level. The external divider should be referenced
to the quiet analog ground. During the LUVLO, the driver
outputs are disabled. This pin can also function as an
Enable/Disable.
The oscillator programming pin. The oscillator should be
referenced to a stable reference voltage for an accurate and stable frequency. Only two components are required to program the oscillator, a resistor (tied to Vref
and RC), and a capacitor (tied to the RC and GND). The
following formula can be used for a close approximation
of the oscillator frequency.
SS (Pin 2):
FOSC ≅
An internal 35µA current source charges the external
capacitor connected to this pin. This pin is connected to
one of the inputs of the PWM comparator. When the voltage on this SS pin increases, but less than 1/3 of the
feedback voltage VFB, the pulse width of OUTA and OUTB
gradually increases to achieve soft start. As the output
voltage increases and feedback loop enters regulation,
the PWM modulator is controlled by VFB. At normal operation, the voltage at SS pin is clamped at Vref.
where:
CTOT = COSC + CSC4806 + CCircuit
CSC4806 ≅ 22pF
The recommended range of timing resistors is between
10kohm and 200kohm and range of timing capacitors
is between 100pF and 1000pF. Timing resistors less
than 10kohm should be avoided.
Refer to layout guidelines in Application Information section to achieve best results.
When the Over Current is tripped, both OUTA and OUTB
are pulled low after a typical time delay (Typ. 100ns). At
the same time, the SS cap is gradually discharged via an
equivalent 10µA internal current source. When the voltage on SS pin is dropped below 0.8V, a new SS cycle is
initiated while the SS cap is charged with 35µA again.
ILim (Pin 5):
The internal thermal protection circuit monitors the die
temperature. If the temperature exceeds 175oC, the controller is completely shutdown. When the temperature is
dropped below 160oC, defined by the hysteresis, the controller re-starts with soft start process.
The current signal from a sense resistor is applied to
peak current and overcurrent comparators through ILM
pin.
Under normal operation condition, the comparators are
not trigged. When the current signal sensed at ILM pin
exceeds the first threshold -- pulse-by-pulse current limit,
the corresponding on-time is terminated for the remainder of the switching cycle. In this case, the circuit output
voltage loses regulation even though it continues to provide full load current.
SYNC (Pin 3):
SYNC is a positive edge triggered input with a threshold
set to 1.75V. In a single controller operation, SYNC could
be grounded or connected to an external synchronization clock within the SYNC frequency range. In Bi-Phase
operation mode SYNC pins could be connected to the
Cosc (Timing Capacitors) of the other controller. This will
force an out-of-phase operation (see Application Information part).
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R OSCCTOT
When the load current continuously increases and the
sensed signal at ILM pin reaches the second threshold - over current limit, the controller turns off both OUTA
and OUTB. At the same time, the SS cap is discharged
with equivalent 10uA current source. When the voltage
at SS pin is below 0.5V, the controller initiates re-start.
The pins Ramp and ILM are discharged by the internal
FETs at the end of each switching cycle.
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SC4806
POWER MANAGEMENT
Pin Descriptions (Cont.)
Ramp (Pin 6):
GND (Pin 9):
The signal at this pin will be used as the PWM ramp signal that will be compared to the FB to achieve regulation. The modes of operation can be programmed depending on how this pin is configured (For more details
see Application section).
Device power and analog ground. The exposed paddle
area on the back of the package must be connected to
the GND (pin9). Careful attention should be paid to the
layout of the ground planes.
OUTB (Pin 10) and OUTA (Pin 11):
For voltage mode control, the PWM ramp is generated
via external RC circuit connected from a voltage source
to the Ramp pin. Connection to a fixed voltage source
(REF) will provide a constant peak ramp with a frequency
set by the internal oscillator frequency programed at
the RC pin. Connection to a variable source such as the
VIN will provide the added benefit of the feed forward
function enhancing the converter static and dynamic performance.
Out of phase gate drive stages. The driver’s peak source
and sink current drive capability of 100mA, enables the
use of an external MOSFET driver or a NPN/PNP transistor totem pole driver.
The oscillator RC network programs the oscillator frequency, which is twice the OUTA/OUTB frequency. To insure that the outputs do not overlap, a dead time can be
generated between the two outputs by sizing the oscillator timing capacitor (see Application Information section).
For Current mode control the current information from
the ILim pin can be directly connected to the Ramp pin
without the need for the external RC circuit at the Ramp
pin.
VCC (Pin 12):
The supply input for the device. Once VCC has exceeded
the UVLO limit, the internal reference, oscillator, drivers
and logic are powered up. A low ESR capacitor, should
be placed right at the pin to minimize noise problems. It
is recommended that the VCC rising rate during start-up
be smaller than 10V/mS.
If current mode of operation with slope compensation is
required, an external resistor connected from the ILim
pin to the Ramp pin will provide the slope compensation. The percentage of the slope compensation will be
inversely proportional to the value of the resistor ( the
higher resistor lower slope compensation, the lower resistor higher slope compensation). 1/3 of external feedback signal to FB pin by an internal 3 to 1 resistor divider compares to the combined current signal to generate PWM control signal.
THERMAL PAD:
Pad for heatsinking purposes. Connect to ground plane
using multiple thermal vias. Not connected internally.
FB (Pin 7):
The inverting input to the PWM comparator through an
internal 3 to 1 resistor divider. Stray inductances and
parasitic capacitance should be minimized by utilizing
ground planes and correct layout guidelines.
REF (Pin 8):
Bandgap reference output. It is recommended by placing a minimum 2.2uF low ESR capacitor right at the pin.
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SC4806
POWER MANAGEMENT
Block Diagram
RAMP
35uA
10uA
ABOA
Marking Information
Top View
yyww = Date Code (Example: 0012)
xxxxxx = Semtech Lot #
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SC4806
POWER MANAGEMENT
Application Information
To generate PWM control signal, 1/3 of external feedback signal to FB pin by an internal 3 to 1 resistor divider
compares to the combined current signal if an external
resistor is connected from ILIM to RAMP. The value of
the resistor will determine the level of slope compensation. The slope signal to RAMP is generated from either
input voltage or VREF with external RC. Voltage mode of
operation can be achieved if the slope signal is only used.
SC4806 is a versatile double ended, high speed, low
power, pulse width modulator optimized for applications
requiring minimum space.
The device contains all of control and drive circuity required for isolated or non isolated power supplies where
an external error amplifier is used. A fixed oscillator frequency (up to 1MHz) can be programmed by an external
RC network.
Two levels of undervoltage lockout are also available.
The LUVLO (line under voltage lockout) pin via an external resistive divider programs input voltage turn-on level.
During the LUVLO, the driver outputs are disabled and
the soft-start is reset.
SC4806 is a peak current or voltage mode controller,
depending on the amount of slope compensation,
programmable with only one external resistor. The cycle
by cycle peak current limit prevents core saturation when
a transformer is used for isolation while the auto-restart
over-current circuitry initiates the soft-start cycle.
The VCC UVLO (under voltage lockout) determines VCC
voltage turn-on level. Once VCC exceeds the UVLO limit,
the internal reference, oscillator, drivers and logic are
powered up.
SC4806 dual output drive stages are arranged for double
ended configurations. Both outputs switch at half the
oscillator frequency using a toggle flip flop. The dead time
between the two outputs is programmable depending
on the values of the timing capacitor and resistors, thus
limiting each output stage duty cycle to less than 50%.
SYNC is a positive edge triggered input with a threshold
set to 1.75V. By connecting an external control signal to
the SYNC pin, the internal oscillator frequency will be
synchronized to the positive edge of the external control
signal. In a single controller operation, SYNC should be
grounded or connected to an external synchronization
clock within the SYNC frequency range. In the Bi-phase
operation mode, a very unique oscillator is utilized to allow two SC4806s to be synchronized together and work
out of phase. This feature is set up by simple connection
of the SYNC input of one part to the RC pin of the other.
The master oscillator forces the two PWMs to operate
out of phase. This feature minimizes the input and output ripples, and may reduce input and output capacitors.
SC4806 also provides flexibility with programmable
LUVLO thresholds, with built-in hysteresis.
PO
WER SUPPL
Y
POWER
SUPPLY
A single supply, VCC is used to provide the bias for the
internal reference, oscillator, drivers, and logic circuitry
of SC4806.
PWM CONTROLLER
OL
TAGE LLOCK
OCK OUT
VCC
VOL
OLT
CC UNDER V
SC4806 is a double ended PWM controller that can be
used in voltage or current mode applications. The oscillator frequency is programmed by a resistor and a capacitor network connected to an external reference provided by the SC4806. The two outputs, OUTA and OUTB,
are 180 degrees out-of-phase and run at half of the
oscillator frequency.
Depending on the application and the voltages available,
the SC4806 (UVLO = 8V) can be used to provide the VCC
undervoltage lock out function to ensure the converters
controlled start up.
Before the VCC UVLO has been reached, the internal reference, oscillator, OUTA/OUTB drivers, and logic are disabled.
An external error amplifier will provide the error signal to
the FB pin of the SC4806. The current limit input and
external slope compensation are provided separately via
the ILIM and RAMP pins. The current limit signal from a
sense resistor or a current sense transformer is used
for the peak current and auto-restart overcurrent
comparators.
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LINE UNDER V
OL
TAGE LLOCK
OCK OUT
VOL
OLT
The SC4806 also provides a line undervoltage (LUVLO =
Vref) function. The LUVLO pin is programmed via an ex8
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SC4806
POWER MANAGEMENT
Application Information (Cont.)
The oscillator has a ramp voltage of about Vref/2. The
oscillator frequency is twice the frequency of the OUTA
and OUTB gate drive controls.
ternal resistor divider connected as shown below. The
actual start-up voltage can be calculated by using the
equation below:
V Startup = V REF
The oscillator capacitor CT is charged from the Vref
through RT. Once the RC pin reaches about Vref/2, the
capacitor is discharged internally by the SC4806. It
should be noted that larger capacitor values will result in
a longer dead time during the down slope of the ramp.
The following equation can be used as an approximation
of the oscillator frequency and the Dead time:
R1
)
× (1 +
R2
+VIN
+
-VIN
R1
ON/OFF
where:
5
VCC
OUTA
OUTB
1
2
SS
C TOT = C OSC + C SC4806 + C Circuit
Vcc
12
CSC4806 ≅ 22pF
11
10
Tdeadtime ≅
0
9
7
FB
RAMP
REF
ILim
6
SC4806
LUVLO
RC
GND(heatsink)
GND
SYNC
3
SYNC
4
REF
I sense
REFERENCE
A 5V reference voltage is available that can be used to
source a typical current of 5mA to the external circuitry.
The Vref can be used to provide the oscillator RC network with a regulated bias.
SYNC/Bi-Phase operation
In noise sensitive applications where synchronization of
the oscillator frequency to a reference frequency may
be required, the SYNC pin can accept the external clock.
By connecting an external control signal to the SYNC pin,
the internal oscillator frequency will be synchronized to
the positive edge of the external control signal. SYNC is
a positive edge triggered input with a threshold set to
1.75V.
OSCILLA
TOR
OSCILLATOR
The oscillator frequency is set by connecting a RC network as shown below.
+VIN
In a single controller operation, SYNC should be grounded
or connected to an external synchronization clock within
the SYNC frequency range.
RAMP
7
LUVLO
SS
1
GND(heatsink)
GND
ILIM
FB
6
REF
5
8
CT
RC
SC4806
VCC
OUTA
OUTB
In the Bi-phase operation mode a very unique oscillator
is utilized to allow two SC4806’s to be synchronized
together and work out of phase. This feature is set up
by a simple connection of the SYNC input to the RC pin
of the other part. The master oscillator forces two
PWMs to operate out of phase. This feature minimizes
the input and output ripples, and may reduce input and
output capacitors.
Vcc
12
11
10
0
9
3
SYNC
RT
2
SYNC
4
REF
FB
I sense
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C OSC × VREF × 0.5
3 ⋅ 10 − 3
The recommended range of timing resistors is between
10 kohm and 200kohm, range of timing capacitors is
between 100pF and 1000pF. Timing resistors less than
10 kohm should be avoided.
FB
REF
1
R OSC C TOT
R2
8
REF
FOSC ≅
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SC4806
6
RAMP
1
LUVLO
SS
3
SYNC
ILIM
GND(heatsink)
GND
10
5
REF
11
RC
FB
OUTB
4
Cosc2
The signal at the FB pin is then compared to the 3X signal from the current sense/ slope compensation RAMP
pin. Matched out of phase signals are generated to control the OUTA and OUTB gate drives of the two phases. A
single ramp signal is used to generate the control signals
for both phases, hence achieving a tightly matched per
phase operation.
Vcc
VCC
OUTA
OUTB
12
11
10
Voltages below 1.5V at the FB pin, will produce a 0%
duty cycle at the OUTA/OUTB gate drives. This offset is to
provide enough head room for the opto coupler used in
isolated applications.
0
9
OUTA
12
8
1
VCC
7
7
Rosc2
LUVLO
SS
RAMP
FB
6
ILIM
Vcc
GND(heatsink)
GND
5
RC
REF
4
Cosc1
SYNC
Rosc1
M aster
S C 4806
0
9
3
REF
2
S lave
S C 4806
8
REF
2
POWER MANAGEMENT
Application Information (Cont.)
GATE DRIVERS
OUTA (PWM1)
OUTA and OUTB are out of phase bipolar gate drive output stages, that are supplied from VCC and provide a
peak source/sink current of about 100mA. Both stages
are capable of driving the logic input of external MOSFET
drivers or a NPN/PNP transistor buffer. The output stages
switch at half the oscillator frequency. When the voltage
on the RC pin is rising, one of the two outputs is high, but
during fall time, both outputs are off. This “dead time”
between the two outputs, along with a slower output rise
and fall time, insures that the two outputs can not be on
at the same time. The dead time is programmable and
depends upon the timing capacitor.
OUTB (PWM1)
OUTA (PWM2)
OUTB (PWM2)
FEED BACK
The error signal from output of an external error amplifier such as SC431 or SC4431 is applied to the inverting
input of the PWM comparator at the FB pin either directly or via an opto-coupler for the isolated applications.
For best stability, keep the FB trace length as short as
possible.
It should be noted that if high speed/high current drivers
such as the SC1301 are used, careful layout guide lines
must be followed in order to minimize stray inductance,
which might cause negative voltages at the output of
the drivers. This negative voltage can be clamped to a
reasonable level by placing a small Schottky diode directly at the output of the driver as shown below:
+Vo
Lo1
+
VCC
3
5
Co1
-Vo
D_B1
Gate_A
1
D_B2
VCC
OUTA
OUTB
2
LUVLO
2
SS
4
12
SC1301A
11
10
VCC
3
5
7
FB
GND(heatsink)
GND
RAMP
FB
6
ILIM
REF
5
RC
1
0
9
4
8
REF
SYNC
3
S C 4 80 6
D_A1
1
SC431
4
Gate_B
2
D_A2
SC1301A
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SC4806
POWER MANAGEMENT
Application Information (Cont.)
In current mode control, the ramp voltage is not derived
artificially from a ramp generator. It is instead provided
from a power converter inductor current by a current
sensing transformer or resistor. Thus a second, inner
control loop is formed by comparing the inductor current
ramp to control voltage from outer voltage loop. Now
the control voltage programs the inductor current via the
inner loop and no longer controls the duty cycle directly.
The current mode control corrects most of problems with
direct duty cycle control in voltage mode. The chief advantage of the methods its inherent feed-forward characteristics and simplified loop dynamics. An added benefits is the reduction or elimination of transformer saturation problems in full-bridge or push-pull isolated converters. The current mode configuration with SC4806 is
as shown below:
OPERA
TION MODE
OPERATION
SC4806 can be configured in either voltage mode or current mode. In voltage mode, a ramp is externally generated by RC network. The R can be connected to Vref or
other fixed voltage source as shown below. By comparing control signal to the ramp, PWM duty cycle is derived.
SC4806 Voltage mode (Non-Feed Forward)
Vref or other fixed Voltage source
R1
Ramp
C1
SC4806 100% Current mode (No Slope Compensation)
R3
Isense
ILIM
Ramp
C2
R3
Isense
Voltage mode with feed-forward operation is implemented if the R is connected to input voltage as shown
below. With this implementation, the ramp amplitude
varies directly with input voltage. If control signal to FB is
constant, the duty cycle varies inversely with input voltage. Thus the volt-second product, Vin*D, remains constant without any control change. Open loop line regulation better than direct duty cycle control as shown above.
Good dynamic response is achieved with less closed loop
gain required.
ILIM
C2
The current mode control ling the peak inductor current
results in circuit instability whenever the steady state duty
cycle is greater than 0.5. An artificial slope has to be
added to avoid such problem. Power transformer magnetizing current riding on the reflected inductor current
acts to provide some slope compensation, but the
amount is rather variable and indeterminate. The current mode with slope compensation is as shown below:
SC4806 Voltage mode (Feed Forward)
SC4806 Current mode (With Slope Compensation)
Vin
Vref or other fixed Voltage source
R1
Ramp
RC
C1
Ramp
R3
Isense
ILIM
ILIM
C2
Isense
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SC4806
POWER MANAGEMENT
Application Information (Cont.)
LA
YOUT GUIDELINES
LAY
SOFT S
TART
ST
Careful attention to layout requirements are necessary for
successful implementation of the SC4806 PWM controller.
During start up of the converter, the discharged output
capacitor and the load current have large supply current
requirements. To avoid this a soft start scheme is usually implemented where the duty cycle of the regulator is
gradually increased from 0% until the soft start duration
is elapsed.
High current switching is present in the application and
their effect on ground plane voltage differentials must be
understood and minimized.
SC4806 has soft start circuit with an external capacitor
that limits the duty cycle for a duration approximated by
the formula below. Also the soft start circuitry is activated if an over current condition occurs. After an over
current condition, OUTA and OUTB are disabled and kept
low. After the delay, the OUTA and OUTB are enabled while
the soft start limits the duty cycle. If the over current
condition persists, the soft start cycle repeats indefinitely.
1) The high power parts of the circuit should be laid out
first. A ground plane should be used, the number and position of ground plane interruptions should be such as to
not unnecessarily compromise ground plane integrity. Isolated or semi-isolated areas of the ground plane may be
deliberately introduced to constrain ground currents to
particular areas, such as the input capacitor and FET
ground.
START UP SEQUENCE
2) In the loop formed by the Input Capacitor(s) (Cin), the
FET must be kept as small as possible. This loop contains
all the high current, fast transition switching. Connections
should be as wide and as short as possible to minimize
loop inductance. Minimizing this loop area will a) reduce
EMI, b) lower ground injection currents, resulting in electrically “cleaner” grounds for the rest of the system and c)
minimize source ringing, resulting in more reliable gate
switching signals.
Initially during the power up, the SC4806 is in under voltage lock out condition. As the Vcc supply exceeds the
UVLO limit of the SC4806, the internal reference, oscillator, and logic circuitry are powered up.
The OUTA and OUTB drivers are not enabled until the line
under voltage lock out limit is reached. At that point, once
the FB pin is above 1.5V, soft start circuitry starts the
output drivers, and gradually increases the duty cycle from
0%.
3) The connection between FETs and the Transformer
should be a wide trace or copper region. It should be as
short as practical. Since this connection has fast voltage
transitions, keeping this connection short will minimize
EMI.
As the output voltage starts to increase, the error signal
from the error amplifier starts to decrease. If isolation is
required, the error amplifier output can drive the LED of
the opto isolator. The output of the opto is connected in
a common emitter configuration with a pull-up resistor
to a reference voltage connected to the FB pin of the
SC4806. The voltage level at the FB pin provides the
duty cycle necessary to achieve regulation.
4) The Output Capacitor(s) (Cout) should be located as
close to the load as possible. Fast transient load currents are supplied by Cout only, and connections between
Cout and the load must be short, wide copper areas to
minimize inductance and resistance.
5) A SC4806 is best placed over a quiet ground plane
area. Avoid pulse currents in the Cin FET loop flowing in
this area. GND should be returned to the ground plane
close to the package and close to the ground side of
(one of) the VCC supply capacitor(s). Under no circumstances should GND be returned to a ground inside the
Cin, Q1, Q2 loop. Avoid making a star connection be-
If an over current condition occurs, the outputs are disabled and after a soft start delay time of about 100µs,
the soft-start sequence mentioned above is repeated.
 2006 Semtech Corp.
12
www.semtech.com
SC4806
POWER MANAGEMENT
Application Information (Cont.)
tween the quiet GND planes that the SC4806 will be
connected to and the noisy high current GND planes
connected to the FETs.
6) The feed back connection between the error amplifier and the FB pin should be kept as short as possible
The GND connections should be connected to the quiet
GND used for the SC4806.
7) If an Opto isolator is used for isolation, quiet primary
and secondary ground planes should be used. The same
precautions should be followed for the primary GND plane
as mentioned in item 5 mentioned above. For the secondary GND plane, the GND plane method mentioned in item
4 should be followed.
8) All the noise sensitive components such as LUVLO
resistive divider, reference by pass capacitor, Vcc bypass
capacitor, current sensing circuitry, feedback circuitry,
and the oscillator resistor/capacitor network should be
connected as close as possible to the SC4806. The GND
return should be connected to the quiet SC4806 GND
plane.
9) The connection from the OUTA and OUTB of the
SC4806 should be minimized to avoid any stray inductance. If the layout can not be optimized due to constraints, a small Schottky diode may be connected from
the OUTA/B pins to the ground directly at the IC. This will
clamp excessive negative voltages at the IC. If drivers
are used, the Schottky diodes should be connected directly at the IC from the output of the driver to the driver
ground.
10) If the SYNC function is not used, the SYNC pin should
be grounded at the SC4806 GND to avoid noise pick up.
 2006 Semtech Corp.
13
www.semtech.com
SC4806
POWER MANAGEMENT
Push Pull Evaluation Board Sch
FZT853
Q2
B
C25
1nF
Vin+
J2
J5
VCC
R24
10
C27
0.1u
1
VCC
VCC
4
D7
D8
JP5
2.2
G_A
G_A
U3
SC1301A
G_B
0
R17
1
MA1
SUD19N20-90
10k
C28
22nF
0
R19
JP4
G_A_cap
100
R15
100p
C23
2.2
JP8
0
R11
1
MB1
SUD19N20-90
10k
G_B
0
R12
JP7
100
R10
100p
C7
JP1
1
3
T4
PE-68386
T3
P8208T
JP2
3
R9
250
VCC
VCC = 12V
R22
10k
J4
LUVLO & ON/OFF & OVP
11
12
U1
SC4806
VCC
OUTA
10
8
1
R8
49.9k
SS
J1
C
OUTB
JP3
JP6
L2
2
1
VCC
6
4
2
4
3
5
1
6
3
0
0
R31
6T
T1
1T
1T
PA0810
6T
4T
R18
16.2
U2
RH02
10u,16V
0
R26
C24
2
1
J3
C26
0.1uF 16V
ILim
RC
JP25 SYNC
4
5
RAMP
LS4448
A
4
1
7
N = 100
CON1
C9 1u,100V
ILim
6
D13
D14
ILim_in
C
10k
R3
3
2
Vin+
R21
56.2k
C8 1u,100V
R_Slope_I
C33
0.1u
4
1k
R1
D3
R_GS_MB1
2
4
REF
R25
15k
R_Slope_V
301
1
U6
SC1301A
R_GS_MA1
ON/OFF
Vin-
R_Pull_Up
3.01k
20k
C10 1u,100V
11
10
8
7
D9
JP9
JP11
JP10
JP12
1u,16V
C31
D11
D12
D10
10
R14
R16
2.2n C13
10
2.2n C15
R33
1k
REF
Sy nc Driv e Supply
J7
D1
3
MBRB2535CTL
1
4
D2
U7
3
MBRB2535CTL
1
4
8
1
3
2
6
4
7
5
MOCD207
1
L1
0.9uH
R43
100
2
R28
2.2k
2.2k
R37
C34
0.1u
C16
22u,6.3V
C43
0.1u
1N5819HW
D15
C35
22n
5
5
C17
22u,6.3V
C44
22n
Sy nc Driv e Supply
C18
22u,6.3V
4
15k
R38
100pF C40
1nF
C41
Sy nc Driv e Supply
4
U5
SC4431
C21
22u,6.3V
0
R32
18.2k
R30
37.4k
C22
0.1u
U8
SC4431
R13
0
C37
.1uF
0
R20
C14
0.1u
R23
TBD
R41
15k
R42
TBD
Vout-
Sens
Trim
Sens
CON2
9
Vout+
8
7
6
5
C42
470pF
R36
11.5k
5output_half _brick
R39
25.5k
www.semtech.com
14
 2006 Semtech Corp.
C20
22u,6.3V
Vref
Vref
3
2
15
R4
CMOSH-3
C
A
C19
22u,6.3V
1
2
1
2
CMOSH-3
C
A
C
A
CMOSH-3
CMOSH-3
C
A
CMOSH-3
CMOSH-3
D4
ZM4743A
C
A
E
C12
10u,16V
1
C36
2.2u,16V
J6
82p
C2
JP28
C
A
Q_Slope_Comp
FMMT718
0.1u,25V
C29
C
AC
A
C
AC
A
CMOSH-3
CMOSH-3
3
5
2
3
5
2
2
SS
REF
REF 8
LUVLO
GND(heatsink)
GND
0
9
C11
.1u,16V
3
SYNC
FB
7
C30
82pF
SC4806
POWER MANAGEMENT
Evaluation Board Bill of Materials
SC4806 Slope Compensation Current Mode Push Pull 3.3V 35W non Synchronous
SC4806EVB__non_sync
Revision: 1.1
Bill Of Materials
March 30,2005
Item Quantity
Reference
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
1
1
2
3
1
2
2
6
6
2
1
1
1
1
1
2
1
1
1
1
2
1
1
25
8
26
8
27
1
28
14
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
1
1
1
1
1
1
1
1
1
2
1
1
3
1
1
1
2
1
1
1
2
2
2
1
1
1
2
1
3
2
1
1
1
1
1
1
1
1
1
1
2
2
1
 2006 Semtech Corp.
CON1
CON2
C2
C23,C7
C8,C9,C10
C11
C24,C12
C13,C15
C14,C22,C27,C33,C34,C43
C16,C17,C18,C19,C20,C21
C41,C25
C26
C28
C29
C30
C31
C44,C35
C36
C37
C40
C42
D2,D1
D3
D4
D5,D6,R12,R13,R19,R20,
R26,R31
D7,D8,D9,D10,D11,D12,D13,
D14
D15
JP1,JP2,JP3,JP4,JP5,JP6,
JP7,JP8,JP9,JP10,JP11,
JP12,JP25,JP28
J1
J2
J3
J4
J5
J6
J7
L1
L2
MB1,MA1
Q_Slope_Comp
Q2
R_GS_MB1,R_GS_MA1,R3
R_Pull_Up
R_Slope_I
R_Slope_V
R1,R33
R4
R8
R9
R10,R15
R17,R11
R16,R14
R18
R21
R22
R42,R23
R24
R25,R38,R41
R37,R28
R30
R32
R36
R39
R43
T1
T3
T4
U1
U2
U6,U3
U5,U8
U7
11:27:17
Part
Manufacturer #
3input_half_brick
5output_half_brick
82p
100p
1u,100V
.1u,16V
10u,16V
2.2n
0.1u
22u,6.3V
1nF
0.1uF 16V
22nF
0.1u,25V
82pF
1u,16V
22n
2.2u,16V
.1uF
100pF
470pF
MBRB2535CTL
LS4448
ZM4743A
GRM44-1X7R105K250AL(muRata)
GRM32DR61C106KA01(muRata)
GRM32DR60J226KA01(muRata)
GRM32RR71H105KA011(muRata)
0
Foot Print
CON\3INPUT_HALF_BRICK
CON\5OUTPUT_HALF_BRICK
SM/C_0805
SM/C_1206
SM/C_2220
SM/C_0805
SM/C_1210_GRM
SM/C_1206
SM/C_0805
SM/C_1210_GRM
SM/C_0805
SM/C_0603
SM/C_1206
SM/C_1206
SM/C_0805
SM/C_1210_GRM
SM/C_0805
SM/C_1206
SM/C_0805
SM/C_0805
SM/C_0805
DIODE_D2PAK
SM/DO213AC
SMB/DO214
SM/R_0805
CMOSH-3
CMOSH-3 (Central Semiconductor)
SOD523
1N5819HW
SOD123
short
VIA\2P
SS
Vcc
SYNC
OUTA
OUTB
REF
FB
0.9uH
LQH43MN102K011
SUD19N20-90
FMMT718
FZT853
10k
3.01k
301
20k
1k
15
49.9k
250
100
2.2
10
16.2
56.2k
10k
TBD
10
15k
2.2k
37.4k
18.2k
11.5k
25.5k
100
PA0810
P8208T
PE-68386
SC4806
RH02
SC1301A
SC4431
MOCD207
ED5052
ED5052
ED5052
ED5052
ED5052
ED5052
ED5052
PG0006
SDIP0302
DPAKFET
SM/SOT23_BEC
SM/SOT223_BCEC
SM/R_0805
SM/R_0805
SM/R_0805
SM/R_0805
SM/R_0805
SM/R_0805
SM/R_1206
SM/R_1210_MCR
SM/R_1206
SM/R_0805
SM/R_1206
SM/R_0805
SM/R_1206
SM/R_1206
SM/R_0805
SM/R_0805
SM/R_0805
SM/R_0805
SM/R_0805
SM/R_0805
SM/R_0805
SM/R_0805
SM/R_0805
PA0810
P8208T
PE-68386
MLPQ-12 (4X4)
RH02
SOT23_5PIN
SOT23_5PIN
SO-8
15
PG0006.102(Pulse)
LQH43MN102K01L(muRata)
SUD19N20-90(vishay)
FMMT718 (Zetex)
FZT853 (Zetex)
PA0810(Pulse)
P8208T(Pulse)
PE-68386(Pulse)
SC4806(Semtech)
RH02(Diodes Inc.)
SC1301A(Semtech)
SC4431(Semtech)
www.semtech.com
SC4806
POWER MANAGEMENT
Evaluation Board Gerber Plots
Board Layout Assembly TOP
Board Layout Assembly Bottom
2
1
Board Layout Top
 2006 Semtech Corp.
Board Layout Bottom
16
www.semtech.com
SC4806
POWER MANAGEMENT
Evaluation Board Gerber Plots (Cont.)
Board Layout Inner1
Board Layout Inner2
Evaluation Board Modifications
1
R Slope I
Q Slope Comp
D15
R43
R Pull up
R Slope V
2
Board Layout Bottom
 2006 Semtech Corp.
17
www.semtech.com
SC4806
POWER MANAGEMENT
HB Evaluation Board Schematics
1
R8
49.9k
FZT853
Q2
B
C25
1nF
R9
250
VCC = 12V
VCC
R22
10k
LUVLO & ON/OFF & OVP
J2
VCC
R24
10
C27
0.1u
1
VCC
Vin+
4
D7
D8
G_A
U3
SC1301A
G_B
JP16
2.2
R11
R17
2.2
0
0
R12
0
JP17
1
MB1
SUD19N20-90
10k
1
MA1
SUD19N20-90
R7
10k
C5
10
G_B
0
R19
PA0264
T2
JP14
R6
2.2n
JP13
C1
10
G_A_cap
2.2n
JP15
C28
22nF
100
R10
100p
C7
100
R15
100p
C23
JP19
JP18
JP20
T4
PE-68386
T3
P8208T
1
3
1
2
JP21
L2
VCC
6
4
C24
2
4
3
5
1
6
R26
0
4T
1T
1T
1T
1T
PA0801
4T
4T
T1
16.2
R18
U2
RH02
10u,16V
0
R31
0
11
10
9
8
7
D9
1u,16V
C31
D11
JP22
JP24
JP23
D12
D10
10
R14
R16
2.2n C13
2.2n C15
10
R33
1.1k
REF
Sy nc Driv e Supply
J7
D1
3
MBRB2535CTL
1
4
3
MBRB2535CTL
1
4
D2
U7
7
3
2
1
6
4
8
5
MOCD207
1
L1
2
R37
R35
0
C34
0.1u
2.2k
R28
1.9uH
C39
6.8nF
1.1k
C35
22n
5
5
C17
47u,6.3V
C44
22n
4
47pF
0
25.5k
R38
C40
C21
47u,6.3V
U5
SC4431
Sy nc Driv e Supply
C18
47u,6.3V
Sy nc Driv e Supply
C41
4
2.2nF
R32
18.2k
R30
37.4k
C22
0.1u
U8
SC4431
R13
0
C37
.1uF
0
R20
C14
0.1u
Vin+
SS
10
11
12
U1
SC4806
VCC
OUTA
VCC
3
2
CON1
C8 1u,100V
R21
56.2k
J3
C26
0.1uF 16V
J1
C11
.1u,16V
JP25 SYNC
RC
ILim
J5
3
2
4
R25
15k
4
5
6
C10 1u,100V
J4
D13
8
1
3
2
3
2
C
OUTB
4
3
4
1
7
N = 100
R_GS_MB1
R_GS_MA1
N/OFF
Vin-
REF
C9 1u,100V
ILim
RAMP
C33
0.1u
1
D14
U4
4
3
C4
2.2u,50V
C6
2.2u,50V
U6
SC1301A
ILim_in
4
1k
R1
6
1
C16
47u,6.3V
C43
0.1u
C20
47u,6.3V
Vref
Vref
5
2
R43
100
1N5819HW
D15
C19
47u,6.3V
1
2
1
2
1
15
R4
CMOSH-3
2
82p
C2
RH02
CMOSH-3
R23
TBD
R41
15k
R42
TBD
Vout-
Sens
Trim
Sens
CON2
9
Vout
8
7
6
5
C42
680pF
R36
1.62k
5output_half _brick
R39
25.5k
www.semtech.com
18
 2006 Semtech Corp.
C
A
CMOSH-3
C
A
C
A
C
A
CMOSH-3
C
A
CMOSH-3
CMOSH-3
CMOSH-3
CMOSH-3
D4
ZM4743A
C
A
E
C36
2.2u,16V
J6
0.1u,25V
C29
C
AC
A
C
AC
A
3
5
2
3
5
2
2
C12
10u,16V
1
LUVLO
GND(heatsink)
GND
0
9
SS
REF
REF 8
Vin+
JP26
C30
82pF
3
SYNC
FB
7
R27
316k
C32
82pF
SC4806
POWER MANAGEMENT
Evaluation Board Bill of Materials
SC4806 Feed Forward Half bridge 3.3V 35W non Synchronous
SC4806EVB__non_sync
Revision: 1.1
Bill Of Materials
March 30,2005
Item Quantity
Reference
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
1
1
2
1
2
2
3
1
2
2
6
6
1
1
1
1
2
1
2
1
1
1
1
1
1
2
1
28
8
29
8
30
1
31
14
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
1
1
1
1
1
1
1
1
1
2
1
2
1
1
3
1
1
2
2
2
1
1
1
2
2
1
1
1
1
2
1
1
2
1
1
1
1
1
1
2
2
2
1
 2006 Semtech Corp.
CON1
CON2
C1,C5
C2
C4,C6
C23,C7
C8,C9,C10
C11
C12,C24
C15,C13
C14,C22,C27,C33,C34,C43
C16,C17,C18,C19,C20,C21
C25
C26
C28
C29
C32,C30
C31
C44,C35
C36
C37
C39
C40
C41
C42
D1,D2
D4
D5,D6,R12,R13,R19,R20,
R26,R31
D7,D8,D9,D10,D11,D12,D13,
D14
D15
JP13,JP14,JP15,JP16,JP17,
JP18,JP19,JP20,JP21,JP22,
JP23,JP24,JP25,JP26
J1
J2
J3
J4
J5
J6
J7
L1
L2
MB1,MA1
Q2
R_GS_MB1,R_GS_MA1
R1
R4
R6,R7,R24
R8
R9
R15,R10
R17,R11
R16,R14
R18
R21
R22
R23,R42
R41,R25
R27
R28
R30
R32
R33,R37
R35
R36
R39,R38
R43
T1
T2
T3
T4
U1
U4,U2
U6,U3
U5,U8
U7
10:47:27
Part
Manufacturer #
3input_half_brick
5output_half_brick
2.2n
82p
2.2u,50V
100p
1u,100V
.1u,16V
10u,16V
2.2n
0.1u
47u,6.3V
1nF
0.1uF 16V
22nF
0.1u,25V
82pF
1u,16V
22n
2.2u,16V
.1uF
6.8nF
47pF
2.2nF
680pF
MBRB2535CTL
ZM4743A
GRM44-1X7R105K250AL(muRata)
GRM32DR61C106KA01(muRata)
GRM43-2X5R476K6.3(muRata)
GRM32RR71H105KA011(muRata)
0
Foot Print
CON\3INPUT_HALF_BRICK
CON\5OUTPUT_HALF_BRICK
SM/C_0805
SM/C_0805
SM/C_2220
SM/C_1206
SM/C_2220
SM/C_0805
SM/C_1210_GRM
SM/C_1206
SM/C_0805
SM/C_1210_GRM
SM/C_0805
SM/C_0603
SM/C_1206
SM/C_1206
SM/C_0805
SM/C_1210_GRM
SM/C_0805
SM/C_1206
SM/C_0805
SM/C_0603
SM/C_0805
SM/C_0805
SM/C_0805
DIODE_D2PAK
SMB/DO214
SM/R_0805
CMOSH-3
CMOSH-3 (Central Semiconductor)
SOD523
1N5819HW
SOD123
short
VIA\2P
SS
Vcc
SYNC
OUTA
OUTB
REF
FB
1.9uH
LQH43MN102K011
SUD19N20-90
FZT853
10k
1k
15
10
49.9k
250
100
2.2
10
16.2
56.2k
10k
TBD
15k
316k
2.2k
37.4k
18.2k
1.1k
0
1.62k
25.5k
100
PA0801
PA0264
P8208T
PE-68386
SC4806
RH02
SC1301A
SC4431
MOCD207
ED5052
ED5052
ED5052
ED5052
ED5052
ED5052
ED5052
PG0006
SDIP0302
DPAKFET
SM/SOT223_BCEC
SM/R_0805
SM/R_0805
SM/R_0805
SM/R_0805
SM/R_1206
SM/R_1210_MCR
SM/R_1206
SM/R_0805
SM/R_1206
SM/R_0805
SM/R_1206
SM/R_1206
SM/R_0805
SM/R_0805
SM/R_0805
SM/R_0805
SM/R_0805
SM/R_0805
SM/R_0805
SM/R_0603
SM/R_0805
SM/R_0805
SM/R_0805
PA0805
PE-68386
P8208T
PE-68386
MLPQ-12 (4X4)
RH02
SOT23_5PIN
SOT23_5PIN
SO-8
19
PG0006.212(Pulse)
LQH43MN102K01L(muRata)
SUD19N20-90(vishay)
FZT853 (Zetex)
PA0801(Pulse)
PA0264 (Pulse)
P8208T(Pulse)
PE-68386(Pulse)
SC4806(Semtech)
RH02(Diodes Inc.)
SC1301A(Semtech)
SC4431(Semtech)
www.semtech.com
SC4806
POWER MANAGEMENT
Evaluation Board Gerber Plots
Board Layout Assembly TOP
Board Layout Assembly Bottom
2
Board Layout Top
 2006 Semtech Corp.
Board Layout Bottom
20
www.semtech.com
SC4806
POWER MANAGEMENT
Evaluation Board Gerber Plots (Cont.)
Board Layout Inner1
Board Layout Inner2
Evaluation Board Modifications
D15
R43
2
Board Layout Bottom
 2006 Semtech Corp.
21
www.semtech.com
SC4806
POWER MANAGEMENT
Outline Drawing - MLPQ-12, 4 x 4
A
D
DIM
B
PIN 1
INDICATOR
(LASER MARK)
A
A1
A2
b
D
D1
E
E1
e
L
N
aaa
bbb
E
A2
A
DIMENSIONS
INCHES
MILLIMETERS
MIN NOM MAX MIN NOM MAX
.031
.040
.002
.000
(.008)
.010 .012 .014
.153 .157 .161
.074 .085 .089
.153 .157 .161
.074 .085 .089
.031 BSC
.018 .022 .026
12
.003
.004
0.80
1.00
0.05
0.00
(0.20)
0.25 0.30 0.35
3.90 4.00 4.10
1.90 2.15 2.25
3.90 4.00 4.10
1.90 2.15 2.25
0.80 BSC
0.45 0.55 0.65
12
0.08
0.10
SEATING
PLANE
aaa C
C
A1
D1
LxN
E/2
E1
2
1
N
bxN
bbb
e
C A B
D/2
NOTES:
1.
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2.
COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.
Land Pattern - MLPQ-12, 4 x 4
K
DIM
2x (C)
H
2x G
Y
X
2x Z
C
G
H
K
P
X
Y
Z
DIMENSIONS
INCHES
MILLIMETERS
(.148)
.106
.091
.091
.031
.016
.041
.189
(3.75)
2.70
2.30
2.30
0.80
0.40
1.05
4.80
P
NOTES:
1.
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
Contact Information
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805)498-2111 FAX (805)498-3804
 2006 Semtech Corp.
22
www.semtech.com