Data Sheet

SG6901A
CCM PFC/Flyback PWM Combination Controller
Features
Description
ƒ
ƒ
ƒ
ƒ
Interleaved PFC/PWM Switching
Innovative Switching Charge Multiplier Divider
The highly integrated SG6901A is designed for power
supplies with boost PFC and flyback PWM. It requires
very few external components to achieve versatile
protections. It is available in a 20-pin SOP package.
Multi-vector Control for Improved PFC Output
Transient Response
A proprietary interleave-switching feature synchronizes
the PFC and PWM stages and reduces switching noise.
ƒ
ƒ
Average-Current-Mode Control for PFC
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
PFC and PWM Feedback Open-Loop Protection
For PFC stage, the proprietary multi-vector control
scheme provides a fast transient response in a lowbandwidth PFC loop, in which the overshoot and
undershoot of the PFC voltage are clamped. If the
feedback loop is broken, the SG6901A shuts off PFC to
prevent extra-high voltage on output.
Low Startup and Operating Current
Programmable Two-Level PFC Output Voltage
Protections
Cycle-by-Cycle Current Limiting for PFC/PWM
Slope Compensation for PWM
H/L Line Over-Power Compensation for PWM
Brownout Protection
Over-Temperature Protection (OTP)
For the flyback PWM, the synchronized slope
compensation ensures the stability of the current loop
under continuous-conduction-mode operation. Built-in
line-voltage compensation maintains constant outputpower limit. Hiccup operation during output overloading
is also guaranteed.
In addition, SG6901A provides protection functions,
such as brownout and RI pin open/short protection.
Applications
ƒ
Switching Power Supplies with Active PFC and
Standby Power
ƒ
High-Power Adaptors
Ordering Information
Part Number
Operating
Temperature Range
Eco
Status
-30°C to +85°C
RoHS
Package
Packing
Method
20-Lead, Small Outline Integrated
SG6901ASZ
Circuit (SOIC), JEDEC
MS013, .300 inch, Wide Body
Tape & Reel
For Fairchild’s definition of “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
© 2008 Fairchild Semiconductor Corporation
SG6901A • Rev. 1.0.2
www.fairchildsemi.com
SG6901A — CCM PFC / Flyback PWM Combination Controller
February 2009
SG6901A — CCM PFC / Flyback PWM Combination Controller
Application Circuit
Figure 1. Typical Application
© 2008 Fairchild Semiconductor Corporation
SG6901A • Rev. 1.0.2
www.fairchildsemi.com
2
SG6901A — CCM PFC / Flyback PWM Combination Controller
Block Diagram
Figure 2. Block Diagram
© 2008 Fairchild Semiconductor Corporation
SG6901A • Rev. 1.0.2
www.fairchildsemi.com
3
T- S=SOP
P- Z=Lead Free
Null=regular package
XXXXXXXX- Wafer Lot
Y: Year; WW: Week
V: Assembly Location
Figure 3. Top Mark
Pin Configuration
SG6901A — CCM PFC / Flyback PWM Combination Controller
Marking Information
Figure 4. Pin Configuration
© 2008 Fairchild Semiconductor Corporation
SG6901A • Rev. 1.0.2
www.fairchildsemi.com
4
Pin #
Name
Description
1
VRMS
Line voltage detection. The pin is used for PFC multiplier, RANGE control of PFC output
voltage, and brownout protection. For brownout protection, the controller is disabled after a
delay time when the VRMS voltage drops below a threshold.
2
RI
Reference setting. One resistor connected between RI and ground determines the switching
frequency. The switching frequency is equal to [1560 / RI] KHz, where RI is in KΩ. For example,
if RI is equal to 24KΩ, the switching frequency is 65KHz.
3
OTP
Over-temperature protection. A constant current is output from this pin. An external NTC
thermistor must be connected from this pin to ground. The impedance of the NTC thermistor
decreases whenever the temperature increases. Once the voltage of the OTP pin drops below
the OTP threshold, the SG6901A is disabled.
4
IEA
PFC current amplifier output. The signal from this pin is compared with an internal sawtooth
to determine the pulse width for PFC gate drive.
5
IPFC
The inverting input of the PFC current amplifier. Proper external compensation circuits result
in excellent input power factor via average-current-mode control.
6
IMP
The non-inverting input of the PFC current amplifier and the output of multiplier. Proper
external compensation circuits results in excellent input power factor via average-current-mode
control.
7
ISENSE
Current limit. A resistor from this pin to GND sets the current limit.
8
FBPWM
The control input for voltage-loop feedback of PWM stage. It is internally pulled high
through a 6.5kΩ resistance. Usually an external opto-coupler from secondary feedback circuit is
connected to this pin.
9
IPWM
The current-sense input for the flyback PWM. Via a current sense resistor, this pin provides
the control input for peak-current-mode control and cycle-by-cycle current limiting.
10
AGND
Signal ground.
11
SS
Soft start. During startup, the SS pin charges an external capacitor with a 50µA (RI=24KΩ)
constant current source. The voltage on FBPWM is clamped by SS during startup. In the event
of a protection condition occurring and/or PWM being disabled, the SS pin is quickly
discharged.
12
OPWM
The totem-pole output drive for the flyback PWM MOSFET. This pin is internally clamped under
17V to protect the MOSFET.
13
GND
Power ground.
14
OPFC
The totem-pole output drive for the PFC MOSFET. This pin is internally clamped under 17V
to protect the MOSFET.
15
VDD
16
RANGE
17
OVP
18
FBPFC
The feedback input for PFC voltage loop. The inverting input of PFC error amplifier. This pin
is connected to the PFC output through a divider network.
19
VEA
The error amplifier output for PFC voltage feedback loop. A compensation network (usually
a capacitor) is connected between this pin and ground. A large capacitor value results in a
narrow bandwidth and improves the power factor.
20
IAC
This input is used to provide current reference for the multiplier.
SG6901A — CCM PFC / Flyback PWM Combination Controller
Pin Definitions
The power supply pin.
The RANGE pin has high impedance whenever the VRMS voltage is lower than a threshold.
The PFC output voltage at low line can be reduced to improve efficiency.
The PFC stage over-voltage input. The comparator disables the PFC output driver if the
voltage at this input exceeds a threshold. This pin can be connected to FBPFC or it can be
connected to the PFC boost output through a divider network.
© 2008 Fairchild Semiconductor Corporation
SG6901A • Rev. 1.0.2
www.fairchildsemi.com
5
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
Max.
Unit
VDD
DC Supply Voltage
25
V
IAC
Input AC Current
2
mA
VHIGH
OPWM, OPFC, IAC
-0.3
25.0
V
VLOW
Others
-0.3
7.0
V
1.15
W
PD
Power Dissipation at TA< 50℃
TJ
Operating Junction Temperature
-40
+125
°C
TSTG
Storage Temperature Range
-55
+150
°C
ӨJC
Thermal Resistance (Junction-to-Case)
+23.64
°C/W
TL
Lead Temperature (Soldering)
+260
°C
Human Body Model, JESD22-A114
4.5
KV
Machine Model, JESD22-A115
250
V
ESD
Electrostatic Discharge Capability
Notes:
1. All voltage values, except differential voltage, are given with respect to GND pin.
2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
SG6901A — CCM PFC / Flyback PWM Combination Controller
Absolute Maximum Ratings
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
TA
Parameter
Operating Ambient Temperature
© 2008 Fairchild Semiconductor Corporation
SG6901A • Rev. 1.0.2
Min.
Max.
Unit
-30
+85
°C
www.fairchildsemi.com
6
VDD=15V and TA=25°C unless otherwise specified.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
20
V
VDD SECTION
VDD-OP
Continuously Operating Voltage
IDD-ST
Startup Current
0V < VDD < VDD-ON
10
25
µA
IDD-OP
Operating Current
VDD=15V; OPFC,
OPWM Open; RI=24KΩ
6
10
mA
VDD-ON
Start Threshold Voltage
11
12
13
V
VDD-OFF
Minimum Operating Voltage
9
10
11
V
VDD-OVP
VDD OVP Threshold
23.5
24.5
25.5
V
tD-VDDOVP
Debounce Time of VDD OVP
25
µs
68
KHz
47.0
KΩ
8
OSCILLATOR SECTION
fOSC
RI
PWM Frequency
RI=24KΩ
RI Pin Resistance Range
62
65
15.6
RI-OPEN
RI Pin Open Protection
If RI>RI-OPEN, SG6901A
Turns Off
RI-SHORT
RI Pin Short Protection
If RI<RI-SHORT,
SG6901A Turns Off
200
KΩ
2
KΩ
VRMS SECTION (for UVP and RANGE)
VRMS-UVP-1
RMS AC Voltage Under-Voltage
Protection Threshold (with tUVP delay)
VRMS-UVP-2
Recovery Level on VRMS
0.75
0.80
VRMS-UVP1+
0.16V
UVP-1 +
VRMS-
0.18V
tUVP-
0.85
VRMS-
UVP-1 +
V
SG6901A — CCM PFC / Flyback PWM Combination Controller
Electrical Characteristics
V
0.2V
tD-PWM
When UVP Occurs, Interval from PFC
Off to PWM Off
Min+9
tUVP
Under-Voltage Protection Delay Time
150
195
240
ms
VRMS-H
High VRMS Threshold for RANGE
Comparator
1.90
1.95
2.00
V
VRMS-L
Low VRMS Threshold for RANGE
Comparator
1.55
1.60
1.65
V
tRANGE
Range-Enable Delay Time
140
170
200
ms
tUVP-
Min+14
ms
VOL
Output Low Voltage of RANGE Pin
Io=1mA
0.5
V
IOH
Output High Leakage Current of
RANGE Pin
RANGE=5V
50
nA
Continued on the following page…
© 2008 Fairchild Semiconductor Corporation
SG6901A • Rev. 1.0.2
www.fairchildsemi.com
7
VDD=15V and TA=25°C unless otherwise specified.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
2.95
3.00
3.05
V
PFC STAGE
Voltage Error Amplifier
VREF
Reference Voltage
Av
Open-Loop Gain
60
dB
Zo
Output Impedance
110
KΩ
OVPPFC
3.20
3.25
3.30
V
PFC Feedback Voltage Protection
Hysteresis
60
90
120
mV
tOVP-PFC
Debounce Time of PFC OVP
40
70
120
µs
VFBPFC-H
Clamp-High Feedback Voltage
3.10
3.15
3.20
V
GFBPFC-H
Clamp-High Gain
VFBPFC-L
Clamp-Low Feedback Voltage
GFBPFC-L
Clamp-Low Gain
IFBPFC-L
Maximum Source Current
IFBPFC-H
Maximum Sink Current
△OVPPFC
PFC Over-Voltage Protection (OVP Pin)
UVPFBPFC
PFC Feedback Under-Voltage Protection
tUVP-FBPFC
Debounce Time of PFC UVP
0.5
2.75
2.85
µA/mV
2.90
V
6.5
mA/mV
1.5
2.0
mA
70
110
µA
0.35
0.40
0.45
V
40
70
120
µs
SG6901A — CCM PFC / Flyback PWM Combination Controller
Electrical Characteristics
CURRENT ERROR AMPLIFIER
VOFFSET
AI
BW
CMRR
Input Offset Voltage ((-) > (+))
8
mV
Open-Loop Gain
60
dB
Unit Gain Bandwidth
1.5
MHz
70
dB
Common Mode Rejection Ratio
VOUT-HIGH
Output High Voltage
VOUT-LOW
Output Low Voltage
IMR1, IMR2
Reference Current Source
IL
Maximum Source Current
IH
Maximum Sink Current
VCM=0 to +1.5V
3.2
RI=24KΩ
(IMR=20+IRI•0.8)
V
50
3
0.2
V
70
µA
mA
0.25
mA
Continued on the following page…
© 2008 Fairchild Semiconductor Corporation
SG6901A • Rev. 1.0.2
www.fairchildsemi.com
8
VDD=15V and TA=25°C unless otherwise specified.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
90
100
110
µA
0.15
0.20
0.25
V
0.35
0.40
0.45
V
200
ns
450
ns
360
µA
PEAK CURRENT LIMIT
IP
VPK
Constant Current Output
RI=24KΩ
Peak Current Limit Threshold
VRMS=1.05V
Voltage Cycle-by-Cycle Limit (VSENSE
VRMS=3V
< VPK)
tPD-PFC
Propagation Delay
tLEB-PFC
Leading-Edge Blanking Time
270
350
MULTIPLIER
IAC
Input AC Current
Multiplier Linear Range
0
IMO–max
Maximum Multiplier Current Output
RI=24KΩ
IMO-1
Multiplier Current Output (Low-line,
High-Power)
VRMS=1.05V; IAC=90µA;
VEA=7.5V; RI=24KΩ
200
250
IMO–2
Multiplier Current Output (High-line,
High-Power)
VRMS=3V; IAC=264µA;
VEA=7.5V; RI=24KΩ
65
85
VIMP
Voltage of IMP Open
3.4
3.9
4.4
V
16
18
V
1.5
V
14.0
ms
250
µA
280
µA
µA
PFC OUTPUT DRIVER
VZ
VOL-PFC
tPFC
VOH-PFC
Output Voltage Maximum (Clamp)
VDD=20V
Output Voltage Low
VDD=15V; IO=100mA
Interval OPFC Lags Behind OPWM
at Startup
9.0
11.5
Output Voltage High
VDD=13V; IO=100mA
8
tR-PFC
Rising Time
VDD=15V; CL=5nF;
O/P=2V to 9V
40
70
120
ns
tF-PFC
Falling Time
VDD=15V; CL=5nF;
O/P=9V to 2V
40
60
110
ns
98
%
DCYMAX
SG6901A — CCM PFC / Flyback PWM Combination Controller
Electrical Characteristics
V
Maximum Duty Cycle
93
FB to Current Comparator
Attenuation
2.5
3.1
3.5
V/V
4
5
7
KΩ
0.8
1.2
1.5
mA
4.2
4.5
4.8
V
PWM Open-Loop Protection Delay
Time
45
56
70
ms
Interval of PWM Open-Loop
Protection Reset
450
600
750
ms
PWM STAGE
FBPWM
Av-PWM
ZFB
Input Impedance
IFB
Maximum Source Current
FBOPEN-LOOP PWM Open-Loop Protection Voltage
tOPEN-PWM
tOPEN-PWMHiccup
Continued on the following page…
© 2008 Fairchild Semiconductor Corporation
SG6901A • Rev. 1.0.2
www.fairchildsemi.com
9
VDD=15V and TA=25°C unless otherwise specified.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
120
ns
PWM CURRENT SENSE
tPD-PWM
Propagation Delay to
Output
VDD=15V, OPWM<=9V
VLIMIT-1
Peak Current Limit
Threshold Voltage1
RANGE=Open
0.65
0.70
0.75
V
VLIMIT-2
Peak Current Limit
Threshold Voltage2
RANGE=Ground
0.60
0.65
0.70
V
tLEB-PWM
Leading-Edge Blanking
Time
270
350
450
ns
0.45
0.50
0.55
V
16
18
V
1.5
V
60
△VS=△VSLOPE x (Ton/T)
△VSLOPE
Slope Compensation
△VS: Compensation
Voltage Added to Current
Sense
PWM OUTOUT DRIVER
VZ-PWM
Output Voltage Maximum
(Clamp)
VDD=20V
VOL-PWM
Output Voltage Low
VDD=15V; IO=100mA
VOH-PWM
Output Voltage High
VDD=13V; IO=100mA
8
tR-PWM
Rising Time
VDD=15V; CL=5nF;
O/P=2V to 9V
30
60
120
ns
tF-PWM
Falling Time
VDD=15V; CL=5nF;
O/P=9V to 2V
30
50
110
ns
73
78
83
%
90
100
110
µA
DCYMAXPWM
Maximum Duty Cycle
V
SG6901A — CCM PFC / Flyback PWM Combination Controller
Electrical Characteristics
OTP SECTION
IOTP
OTP Pin Output Current
VOTP-ON
Recovery Level on OTP
1.35
1.40
1.45
V
VOTP-OFF
OTP Threshold Voltage
1.15
1.20
1.25
V
25
µs
56
µA
tOTP
RI=24KΩ
OTP Debounce Time
8
SOFT START SECTION
ISS
Constant Current Output
for Soft-Start
RD
Discharge RDSON
© 2008 Fairchild Semiconductor Corporation
SG6901A • Rev. 1.0.2
RT=24KΩ
44
50
470
Ω
www.fairchildsemi.com
10
Minimum Operating Voltage (VDD-OFF ) vs. Temperature
25
11.0
20
10.6
VDD-OFF (V)
IDD-ST (µA)
Startup Current (IDD-ST ) vs. Temperature
15
10
5
10.2
9.8
9.4
0
-40
-25
-10
5
20
35
50
65
80
95
110
9.0
125
-40
T emperature (°C)
Figure 5. Startup Current
-10
5
80
95
110
125
PWM Frequency (f
OSC
) vs. Temperature
68
10.0
67
fOSC (KHz)
8.8
7.6
6.4
66
64
63
5.2
4.0
62
-40
-25
-10
5
20
35
50
65
80
95
110
125
-40
-25
-10
5
20
35
50
Temperature (°C)
Temperature (°C)
Figure 7. Operating Current
65
80
95
110
125
Figure 8. PWM Frequency
VDD Over-Voltage Protection (VDD-OVP) vs. Temperature
Start Threshold Voltage (VDD-ON) vs. Temperature
13.0
25.5
12.6
25.1
12.2
VDD-OVP (V)
VDD-ON (V)
20
35
50
65
T emperature (°C)
Figure 6. VDD Turn-Off Threshold Voltage
Operating Current (IDD-OP) vs. Temperature
IDD-OP (mA)
-25
SG6901A — CCM PFC / Flyback PWM Combination Controller
Typical Performance Characteristics
11.8
11.4
24.7
24.3
23.9
11.0
23.5
-40
-25
-10
5
20
35
50
65
80
95
110
125
-40
Temperature (°C)
-10
5
20
35
50
65
80
95
110
125
Temperature (°C)
Figure 9. VDD Turn-On Threshold Voltage
© 2008 Fairchild Semiconductor Corporation
SG6901A • Rev. 1.0.2
-25
Figure 10. VDD OVP Threshold Voltage
www.fairchildsemi.com
11
2.00
3.05
1.98
3.03
1.96
3.01
VREF (V)
VRMS-H (V)
High VRMS Threshold for RANGE Comparator (VRMS-H) vs. Temperature
1.94
1.92
Reference Voltage (VREF ) vs. Temperature
2.99
2.97
1.90
2.95
-40
-25
-10
5
20
35
50
65
80
95
110
125
-40
-25
-10
5
Temperature (°C)
Figure 11. High VRMS Threshold for RANGE Comparator
35
50
65
80
95
125
110
125
110
125
Rising Time (tR-PFC) vs. Temperature
120
1.65
104
1.63
tR-PFC (ns)
1.61
1.59
88
72
56
1.57
40
1.55
-40
-25
-10
5
20
35
50
65
80
95
110
-40
125
-25
-10
5
20
35
50
65
80
95
Temperature (°C)
Temperature (°C)
Figure 13. Low VRMS Threshold for RANGE Comparator
Figure 14. OPFC Rising Time
PFC Over-Voltage Protection (OVPPFC) vs. Temperature
Falling Time (tF-PFC) vs. Temperature (°C)
110
3.30
96
tF-PFC (ns)
3.28
OVPPFC (V)
110
Figure 12. Reference Voltage
Low VRMS Threshold for RANGE Comparator (VRMS-L) vs. Temperature
VRMS-L (V)
20
Temperature (°C)
SG6901A — CCM PFC / Flyback PWM Combination Controller
Typical Performance Characteristics
3.26
3.24
82
68
54
3.22
3.20
40
-40
-25
-10
5
20
35
50
65
80
95
110
125
-40
Figure 15. PFC OVP Threshold Voltage
© 2008 Fairchild Semiconductor Corporation
SG6901A • Rev. 1.0.2
-25
-10
5
20
35
50
65
80
95
Temperature (°C)
Temperature (°C)
Figure 16. OPFC Falling Time
www.fairchildsemi.com
12
Maximum Duty Cycle (DCY MAX) vs. Temperature
Peak Current Limit Threshold Voltage 1 (VLIMIT-1) vs. Temperature
98
0.75
0.73
VLIMIT-1 (V)
DCY MAX (%)
97
96
95
0.71
0.69
0.67
94
0.65
93
-40
-25
-10
5
20
35
50
65
80
95
110
-40
125
-25
-10
5
Figure 17. PFC Maximum Duty Cycle
50
65
80
95
110
125
Peak Current Limit Threshold Voltage 2 (VLIMIT-2) vs. Temperature
0.70
4.80
0.68
4.68
VLIMIT-2 (V)
FBOPEN-LOOP (V)
35
Figure 18. Peak Current Limit Threshold Voltage
PWM Open-Loop Protection Voltage (FBOPEN-LOOP) vs. Temperature
4.56
4.44
4.32
0.66
0.64
0.62
4.20
0.60
-40
-25
-10
5
20
35
50
65
80
95
110
125
-40
-25
-10
5
Temperature (°C)
20
35
50
65
80
95
110
125
Temperature (°C)
Figure 19. PWM Open-Loop Protection Voltage
Figure 20. Peak Current Limit Threshold Voltage2
Falling Time (tF-PWM) vs. Temperature
PWM Maximum Duty Cycle (DCYMAXPWM ) vs. Temperature (°C)
110
83
DCYMAXPWM (%)
94
tF-PWM (ns)
20
Temperature (°C)
Temperature (°C)
SG6901A — CCM PFC / Flyback PWM Combination Controller
Typical Performance Characteristics
78
62
46
81
79
77
75
30
73
-40
-25
-10
5
20
35
50
65
80
95
110
125
-40
Figure 21. OPWM Falling Time
© 2008 Fairchild Semiconductor Corporation
SG6901A • Rev. 1.0.2
-25
-10
5
20
35
50
65
80
95
110
125
Temperature (°C)
Temperature (°C)
Figure 22. PWM Maximum Duty Cycle
www.fairchildsemi.com
13
SG6901A — CCM PFC / Flyback PWM Combination Controller
Typical Performance Characteristics
OTP Threshold Voltage (VOTP-OFF) vs. Temperature
1.25
VOTP-OFF (V)
1.23
1.21
1.19
1.17
1.15
-40
-25
-10
5
20
35
50
65
80
95
110
125
Temperature (°C)
Figure 23. VDD OTPurn Threshold Voltage
© 2008 Fairchild Semiconductor Corporation
SG6901A • Rev. 1.0.2
www.fairchildsemi.com
14
improve the efficiency at low-line input. The RANGE pin
(open-drain structure) is used for the two-level output
voltage setting.
SG6901A is a highly integrated PFC/PWM combination
controller. Many functions and protections are built in to
provide a compact design. The following sections
describe the operation and function.
Switching Frequency and Current Sources
The switching frequency can be programmed by the
resistor RI connected between RI pin and GND. The
relationship is:
fOSC =
1560
(kHz)
RI (kΩ )
(1)
Figure 25. Interleaved Switching Pattern
For example, a 24KΩ resistor RI results in a 65KHz
switching frequency. Accordingly, a constant current, IT,
flows through RI:
1.2V
IT =
(mA)
RI (kΩ )
PFC Operation
The purpose of a boost active power factor corrector
(PFC) is to shape the input current of a power supply.
The input current waveform and phase follow that of the
input voltage. Average-current-mode control is utilized
for continuous-current-mode operation for the PFC
booster. With the innovative multi-vector control for
voltage loop and switching charge multiplier-divider for
current reference, excellent input power factor is
achieved with good noise immunity and transient
response. Figure 26 shows the total control loop for the
average-current-mode control circuit.
(2)
IT is used to generate internal current reference.
Line Voltage Detection (VRMS)
Figure 24 shows a resistive divider with low-pass
filtering for line-voltage detection on the VRMS pin. The
VRMS voltage is used for the PFC multiplier, brownout
protection, and range control.
The current source output from the switching charge
multiplier-divider can be expressed as:
For brownout protection, SG6901A is disabled with a
195ms delay if the voltage VRMS drops below 0.8V.
I MO = K ×
For PFC multiplier and range control, refer to the PFC
Operation section below for details.
VRMS 2
(µA)
(3)
As shown in Figure 26, the current output from the IMP
pin is the summation of IMO and IMR1. IMR1 and IMR2
are identical fixed-current sources used to pull high the
operating point of the IMP and IPFC pins since the
voltage across RS goes negative with respect to
ground. Constant current sources IMR1 and IMR2 are
typically 60µA.
Through the differential amplification of the signal
across RS, better noise immunity is achieved. The
output of IEA is compared with an internal sawtooth
and the pulse width for PFC is determined. Through the
average current-mode control loop, the input current IS
is proportional to IMO:
Figure 24. Line Voltage Detection Circuit
IMO × R 2 = IS × R S
Interleave Switching
(4)
According to Equation 4, the minimum value of R2 and
maximum of RS can be determined since IMO should
not exceed the specified maximum value.
The SG6901A uses interleaved switching to
synchronize the PFC and flyback stages, which
reduces switching noise and spreads the EMI
emissions. Figure 25 shows off-time, tOFF, inserted
between the turn-off of the PFC gate drive and the turnon of the PWM.
There are different concerns in determining the value of
the sense resistor RS. The value of RS should be small
enough to reduce power consumption, but large
enough to maintain the resolution. A current
transformer (CT) may be used to improve efficiency of
high-power converters.
For an universal input (90 ~ 264VAC) power supply
applying active boost PFC and flyback as a second
stage, the output voltage of PFC is usually designed
around 250V at low line and 390V at high line. This can
© 2008 Fairchild Semiconductor Corporation
SG6901A • Rev. 1.0.2
I AC × VEA
SG6901A — CCM PFC / Flyback PWM Combination Controller
Functional Description
www.fairchildsemi.com
15
f1 =
1
Pin = VIN (rms) × IIN (rms)
∝ VRMS × IMO
∝ VRMS ×
∝ VRMS ×
= 2×
(5)
2π × Z O × CEA
I AC × VEA
VRMS 2
Vin
× VEA
R AC
VRMS
(6)
2
VEA
R AC
From Equation 6, VEA, the output of the voltage error
amplifier, controls the total input power and the power
delivered to the load.
SG6901A — CCM PFC / Flyback PWM Combination Controller
The average total input power can be expressed as:
To achieve good power factor, the voltage for VRMS and
VEA should be kept as constant as possible, according
to Equation 5. Good RC filtering for VRMS and narrow
bandwidth (lower than the line frequency) for voltage
loop are suggested for better input current shaping.
The transconductance error amplifier has output
impedance ZO and a capacitor CEA (1µF ~ 10µF)
should be connected to ground. This establishes a
dominant pole f1 for the voltage loop:
Figure 26. Average-Current-Mode Control Loop
Multi-Vector Error Amplifier
PFC Over-Voltage Protection
Although the PFC stage has a low bandwidth voltage
loop for better input power factor, the innovative multivector error amplifier provides a fast transient response
to clamp the overshoot and undershoot of the PFC
output voltage.
Using a voltage divider from the output of PFC to the
OVP pin, the PFC output voltage can be safely
protected. Once the voltage on the OVP pin is over
OVPPFC, the OPFC is disabled. THE OPFC is not
enabled again until the OVP voltage falls below
OVPPFC.
0 shows the block diagram of the multi-vector error
amplifier. When the variation of the feedback voltage
exceeds ±5% of the reference voltage, the
transconductance error amplifier adjusts its output
impedance to increase the loop response.
Cycle-by-Cycle Current Limiting
SG6901A provides cycle-by-cycle current limiting for
both PFC and PWM stages. Figure 28 shows the peak
current limit for the PFC stage. The PFC gate drive is
terminated once the voltage on the ISENSE pin goes
below VPK.
The voltage of VRMS determines the voltage of VPK. The
relationship between VPK and VRMS is shown in Figure 28.
The amplitude of the constant current, Ip, is determined
by the internal current reference according to:
IP = 2 ×
1.2V
RI
(8)
Figure 27. Multi-Vector Error Amplifier
© 2008 Fairchild Semiconductor Corporation
SG6901A • Rev. 1.0.2
www.fairchildsemi.com
16
Every time the output of the power supply is shorted or
overloaded, the FBPWM voltage increases. If the
FBPWM voltage is higher than a designed threshold,
FBOPEN-LOOP (4.5V) for longer than tOPEN-PWM
(56ms), the OPWM is turned off.
As long as the voltage on the VDD pin is larger than
VDD-OFF (minimum operating voltage), the OPWM is not
enabled. This protection is reset every tOPEN-PWM-Hiccup
interval. A low-frequency hiccup mode protection
prevents the power supply from being overheated
under overload conditions.
Figure 28. VRMS Controlled Current Limiting
The peak current of the ISENSE is given by
(VRMS<1.05V):
ISENSE_peak =
(IP × R P ) - 0.2V
RS
Over-Temperature Protection
(8)
The OTP pin provides for over-temperature protection.
A constant current is output from this pin. If RI is equal
to 24KΩ, the magnitude of the constant current is
100µA. An external NTC thermistor must be connected
from this pin to ground, as shown as Figure 30. When
the OTP voltage drops below VOTP-OFF (1.2V), SG6901A
is disabled and does not recover until OTP voltage
exceeds VOTP-ON (1.4V).
Flyback PWM and Slope Compensation
As shown in Figure 29, peak-current-mode control is
utilized for flyback PWM. The SG6901A inserts a
synchronized 0.5V ramp at the beginning of each
switching cycle. This built-in slope compensation
ensures stable operation for continuous current-mode
operation.
When the IPWM voltage, across the sense resistor,
reaches the threshold voltage (0.9V), the OPWM is
turned off after a small propagation delay tPD-PWM.
To improve stability or prevent sub-harmonic
oscillation, a synchronized positive-going ramp is
inserted at every switching cycle.
SG6901A — CCM PFC / Flyback PWM Combination Controller
Limited Power Control
Figure 30. OTP Function
Soft Start
During startup of PWM stage, the SS pin charges an
external capacitor with a constant current source. The
voltage on FBPWM is clamped by the SS voltage
during startup. In the event of a protected condition
and/or PWM is disabled, the SS pin quickly discharges.
Gate Driver
SG6901A output stage is a fast totem-pole gate driver.
The output driver is clamped by an internal 18V Zener
diode to protect the external power MOSFET.
Figure 29. Peak Current Control Loop
© 2008 Fairchild Semiconductor Corporation
SG6901A • Rev. 1.0.2
www.fairchildsemi.com
17
13.00
12.60
A
11.43
20
11
B
9.50
10.65 7.60
10.00 7.40
2.25
1
0.51
0.35
PIN ONE
INDICATOR
1.27
0.25
M
10
0.65
1.27
C B A
LAND PATTERN RECOMMENDATION
2.65 MAX
SEE DETAIL A
0.33
0.20
C
0.75
0.25
X 45°
0.10 C
0.30
0.10
SEATING PLANE
NOTES: UNLESS OTHERWISE SPECIFIED
(R0.10)
A) THIS PACKAGE CONFORMS TO JEDEC
MS-013, VARIATION AC, ISSUE E
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) CONFORMS TO ASME Y14.5M-1994
GAGE PLANE
(R0.10)
SG6901A — CCM PFC / Flyback PWM Combination Controller
Physical Dimensions
0.25
8°
0°
1.27
0.40
SEATING PLANE
(1.40)
DETAIL A
E) LANDPATTERN STANDARD: SOIC127P1030X265-20L
F) DRAWING FILENAME: MKT-M20BREV3
SCALE: 2:1
Figure 31. 20-Pin Small Outline Integrated Circuit (SOIC)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2008 Fairchild Semiconductor Corporation
SG6901A • Rev. 1.0.2
www.fairchildsemi.com
18
SG6901A — CCM PFC / Flyback PWM Combination Controller
© 2008 Fairchild Semiconductor Corporation
SG6901A • Rev. 1.0.2
www.fairchildsemi.com
19