RT9025 2A, Ultra Low Dropout LDO General Description Features The RT9025 is a high performance positive voltage regulator designed for use in applications requiring very low Input voltage and extremely low dropout voltage at up to 2A(Peak). It operates with a VIN as low as 1V and VDD voltage 3V with programmable output voltage as low as 0.8V. The RT9025 features ultra low dropout that is ideal for applications where VOUT is very close to VIN. Additionally, it has an enable pin to further reduce power dissipation while shutdown and provides excellent regulation over variations in line, load and temperature. The RT9025 provides a power good signal to indicate if the voltage level of Vo reaches 90% of its rating value. The RT9025 is available in the SOP-8 and SOP-8 (Exposed Pad) package with 1.05V, 1.2V, 1.5V, 1.8V and 2.5V internally preset outputs that are also adjustable by using external resistors. l Ordering Information RT9025Package Type S : SOP-8 SP : SOP-8 (Exposed Pad-Option 1) Lead Plating System P : Pb Free G : Green (Halogen Free and Pb Free) Z : ECO (Ecological Element with Halogen Free and Pb free) Output Voltage 1K : 1.05V/Adj 12 : 1.2V/Adj 15 : 1.5V/Adj 18 : 1.8V/Adj 25 : 2.5V/Adj l l l l l l l Ultra Low Dropout Voltage 230mV at 2A Output Current up to 2A High Accuracy Output Voltage 2% Power Good Output Output Voltage Pull Low Resistor when Disable Over Current Protection Thermal Shutdown Protection RoHS Compliant and 100% Lead (Pb)-Free Applications l l Note Book PC Applications Motherboard Applications Pin Configurations (TOP VIEW) PGOOD 8 GND EN 2 7 ADJ VIN 3 6 VOUT VDD 4 5 NC SOP-8 PGOOD EN 2 VIN 3 VDD 8 GND 7 ADJ GND 9 6 4 5 VOUT NC SOP-8 (Exposed Pad) Note : Richtek products are : } RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. } Suitable for use in SnPb or Pb-free soldering processes. DS9025-05 March 2011 www.richtek.com 1 RT9025 Typical Application Circuit VIN VIN CIN 10µF Chip Enable VDD Chip Enable ADJ PGOOD VDD VIN CIN 10µF COUT 10µF RT9025 EN VIN VOUT VOUT VOUT = 0.8 × R1 + R2 R2 VDD GND CF RT9025 R2 PGOOD VDD GND 100k R1 COUT 10µF ADJ EN 1µF VOUT VOUT 100k 1µF VOUT VOUT Figure 1. Fixed Voltage Regulator Figure 2. Adjustable Voltage Regulator Functional Pin Description Pin No. Pin Name Pin Function 1 PGOOD Power Good Open Drain Output. 2 EN Chip Enable (Active High). 3 VIN Supply Input Voltage. 4 VDD Supply Voltage of Control Circuit. 5 NC No Internal Connection. 6 VOUT Output Voltage. 7 ADJ 8, 9 (Exposed Pad) Set the output voltage by the internal feedback resistors when ADJ is grounded. If external feedback resistors is used, VOUT = 0.8V x (R2 + R1) / R2. Ground. The exposed pad must be soldered to a large PCB and connected to GND GND for maximum power dissipation. Function Block Diagram VOUT VIN SD OTP VDD POR 0.8V Error Amplifier - EN + OCP Mode ADJ PGOOD 0.72V + GND www.richtek.com 2 DS9025-05 March 2011 RT9025 Absolute Maximum Ratings l l l l l l l l l (Note 1) Supply Input Voltage, VIN ------------------------------------------------------------------------------------------ 6V Control Voltage ------------------------------------------------------------------------------------------------------- 6V Output Voltage ------------------------------------------------------------------------------------------------------- 6V Power Dissipation, PD @ TA = 25°C SOP-8 ------------------------------------------------------------------------------------------------------------------ 0.833W SOP-8 (Exposed Pad) ---------------------------------------------------------------------------------------------- 1.333W Package Thermal Resistance (Note 2) SOP-8, θJA ------------------------------------------------------------------------------------------------------------ 120°C/W SOP-8, θJC ------------------------------------------------------------------------------------------------------------ 60°C/W SOP-8 (Exposed Pad), θJA ---------------------------------------------------------------------------------------- 75°C/W SOP-8 (Exposed Pad), θJC ---------------------------------------------------------------------------------------- 15°C/W Lead Temperature (Soldering, 10 sec.)-------------------------------------------------------------------------- 260°C Junction Temperature ----------------------------------------------------------------------------------------------- 150°C Storage Temperature Range --------------------------------------------------------------------------------------- −65°C to 150°C ESD Susceptibility (Note 3) HBM (Human Body Mode) ----------------------------------------------------------------------------------------- 2kV MM (Machine Mode) ------------------------------------------------------------------------------------------------ 200V Recommended Operating Conditions l l l l (Note 4) Supply Input Voltage, VIN ------------------------------------------------------------------------------------------ 1.4V to 5.5V Control Voltage, VDD ------------------------------------------------------------------------------------------------- 4.5V to 5.5V Junction Temperature Range -------------------------------------------------------------------------------------- −40°C to 125°C Ambient Temperature Range -------------------------------------------------------------------------------------- −40°C to 85°C Electrical Characteristics (VIN = VOUT + 500mV, VEN = VDD = 5V, CIN = COUT = 10µF, TA = 25°C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit -- 0.6 1.2 mA VIN Quiescent Current (GND Current) (Note 5) IQ VDD = 5V VDD VDD Input Range 4.5 -- 5.5 V VDD = 5V −2 0 2 % ∆VLOAD VDD = 5V, I OUT = 2A, VIN = VOUT + 1V -- 0.2 1 % VOUT Line Regulation (VIN) ∆VLINE_IN VDD = 5V, VIN = VOUT + 1V to 5V IOUT = 1mA -- 0.2 0.6 % Dropout Voltage VDROP VDD = 5V, I OUT = 2A -- 230 300 VDD = 5V, I OUT = 1A -- 115 150 VDD VDD Operation Range VOUT Fixed Output Voltage VOUT Load Regulation (Note 6) (Note 7) mV To be Continued DS9025-05 March 2011 www.richtek.com 3 RT9025 Min Typ Max Unit VDD = 5V, V IN = 3.6V -- 3.5 -- A Short Circuit Current VDD = 5V , VOUT < 0.2V -- 1.8 -- A In-rush Current VDD = 5V, COU T = 10µF, Enable Start-up, ILOAD = 2A -- 0.5 -- A VEN = 0V -- 150 -- Ω 10% to 90%, VOUT = 1.8V -- 200 600 µs 0.788 0.8 0.812 V -- 0.2 -- V POR Threshold 2.4 2.7 3.0 V POR Falling Hysteresis 0.15 0.2 -- V Parameter Current Limit Symbol ILIM V OUT Pull Low Resistance V OUT Rising Time Test Conditions ADJ Reference Voltage VREF VDD = 5V, V OUT = 2.5V ADJ Pin Threshold Power-On Reset Power Good Power Good Rising Threshold VDD = 5V -- 90 -- % Power Good Hysteresis VDD = 5V -- 10 -- % Power Good Sink Capability VDD = 5V, IOUT = 10mA -- 0.2 0.4 V Chip Enable Logic-High VEN _H VDD = 5V 1.2 -- -- V Logic-Low VEN _L VDD = 5V -- -- 0.6 V EN Pin Bias Current IEN VEN = 5V -- 12 -- µA V DD Shutdown Current ISHDN VDD = 5V, V EN = 0V -- -- 1 µA -- 160 -- °C -- 90 -- °C EN Threshold Voltage Over Temperature Protection Thermal Shutdown Temperature TSD Thermal Shutdown Returned Temperature Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. θJA is measured in the natural convection at TA = 25°C on a 4-layers high effective thermal conductivity test board of JEDEC 51-7 thermal measurement standard. The case point of θJC is on the expose pad for SOP-8 (Exposed Pad) package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. Quiescent, or ground current, is the difference between input and output currents. It is defined by IQ = IIN - IOUT under no load condition (IOUT = 0mA). Note 6. Regulation is measured at constant junction temperature by using a 2ms current pulse. Devices are tested for load regulation in the load range from 1mA to 2A. Note 7. The dropout voltage is defined as VIN -VOUT, which is measured when VOUT is VOUT(NORMAL) − 100mV. www.richtek.com 4 DS9025-05 March 2011 RT9025 Typical Operating Characteristics Load Transient Response Load Transient Response VOUT (20mV/Div) VOUT (20mV/Div) IOUT (1A/Div) IOUT (1A/Div) VDD = 5V, VIN = 1.8V, VOUT = 1.2V ADJ VDD = 5V, VIN = 3.3V, VOUT = 2.5V FIX Time (2.5ms/Div) Time (2.5ms/Div) VIN Line Transient Response VIN (1V/Div) VIN Line Transient Response VIN (1V/Div) 3 4 3 2 VOUT (50mV/Div) VOUT (50mV/Div) VDD = 5V, VOUT = 1.2V ADJ, IOUT = 0A VDD = 5V, VOUT = 2.5V FIX, IOUT = 0A Time (250μs/Div) Time (250μs/Div) VDD Line Transient Response VDD Line Transient Response 5 5 VDD (1V/Div) 4 VDD (1V/Div) 4 VOUT (20mV/Div) VOUT (20mV/Div) VIN = 1.8V, VOUT = 1.2V ADJ, IOUT = 0A Time (250μs/Div) DS9025-05 March 2011 VIN = 3.3V, VOUT = 2.5V FIX, IOUT = 0A Time (250μs/Div) www.richtek.com 5 RT9025 Dropout Voltage vs. Load Current Start Up from Enable and PGOOD Delay 350 125°C Dropout Voltage (mV) 300 VEN (5V/Div) 25°C 250 VOUT (1V/Div) 200 150 PGOOD (1V/Div) -40°C 100 I IN (1A/Div) 50 VDD = VEN = 5V, VIN = 1.8V, VOUT = 1.2V ADJ, IOUT = 2A 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 Time (1ms/Div) Load Current (A) Start Up from VDD Start Up from VIN VDD (5V/Div) VIN (1V/Div) VOUT (1V/Div) VOUT (1V/Div) I IN (1A/Div) VDD = 5V, VIN = VEN = 1.8V, VOUT = 1.2V ADJ, IOUT = 2A I IN (1A/Div) VDD = 5V, VIN = VEN = 1.8V, VOUT = 1.2V ADJ, IOUT = 2A Time (1ms/Div) Time (1ms/Div) Short Circuit Current vs. Temperature Short Circuit Protection Short Circuit Current (A) 1 2.6 VOUT (1V/Div) IOUT (1A/Div) 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 Time (500μs/Div) -50 -25 0 25 50 75 100 Temperature (°C) www.richtek.com 6 DS9025-05 March 2011 RT9025 Quiescent Current vs. Temperature 1200 1.15 1100 1.10 1000 1.05 Quiescent Current (µA) 1 Enable Threshold Voltage (V) 1 Enable Threshold Voltage vs. Temperature 1.20 Rising 1.00 0.95 0.90 Falling 0.85 0.80 0.75 0.70 0.65 VIN = 3.3V, VOUT = 2.5V, IOUT = 0A 900 800 700 600 VIN = 1.8V, VOUT = 1.2V, IOUT = 0A 500 400 300 200 100 0.60 0 -50 -25 0 25 50 75 100 -50 -25 0 Temperature (°C) 25 50 75 100 125 Temperature (°C) Fixed Output Voltage Range vs. Temperature Reference Voltage vs. Temperature 2.60 0.84 VIN = 3.3V, VADJ = 0V, VOUT = 2.5V, IOUT = 0A 0.83 Reference Voltage (V) 1 Fixed Output Voltage (V) 2.58 2.56 2.54 2.52 2.50 2.48 2.46 2.44 0.82 0.81 0.80 0.79 0.78 0.77 2.42 0.76 2.40 -50 -25 0 25 50 75 100 125 -50 -25 Temperature (°C) 0.28 ADJ Threshold Voltage (V) 0.30 2.95 2.90 POR Voltage (V) 1 50 75 100 125 ADJ Threshold Voltage Range vs. Temperature VDD POR Threshold Voltage vs. Temperature Rising 2.80 2.75 2.70 Falling 2.65 25 Temperature (°C) 3.00 2.85 0 2.60 2.55 2.50 0.26 0.24 0.22 0.20 0.18 0.16 0.14 0.12 2.45 0.10 2.40 -50 -25 0 25 50 Temperature (°C) DS9025-05 March 2011 75 100 -50 -25 0 25 50 75 100 Temperature (°C) www.richtek.com 7 RT9025 Application information Adjustable Mode Operation Enable The RT9025 goes into shutdown mode when the EN pin is in the logic low condition. During this condition, the pass transistor, error amplifier, and band gap are turned off, reducing the supply current to 10µA typical. The RT9025 goes into operation mode when the EN pin is in the logic high condition. If the EN pin is floating, please notice the RT9025 internal initial logic level. For RT9025, the EN pin function pulls low level internally. So the regulator will be turn off when EN pin is floating. Input Capacitor Good bypassing is recommended from input to ground to improve AC performance. A 10µF input capacitor or greater located as close as possible to the IC is recommended. Region of Stable COUT ESR vs. Output Current 10 RegionofofStable StableCCOUT Region ESR (Ω) (Ω) OUT ESR The output voltage of RT9025 is adjustable from 0.8V to VIN by external voltage divider resisters as shown in Typical Application Circuit (Figure 2). The value of resisters R1 and R2 should be more than 10kΩ to reduce the power loss. The output voltage can be calculated by the following equation : R1 VOUT = VREF × 1 + R2 where VREF is the reference voltage (0.8V typical). Unstable Region 1 0.1 Stable Region 0.01 Unstable Region (Simulation Verity) VDD = 5V, VIN = 1.8V, VOUT = 1.2V R1 = R2 = 100kΩ, CIN = COUT = 10µF/X5R 0.001 0 0.5 1 1.5 2 2.5 3 Output Current (A) Figure 3. Region of Stable COUT ESR vs. Output Current Current Limit The RT9025 contains an independent current limit and the short circuit current protection to prevent unexpected applications. The current limit monitors and controls the pass transistor's gate voltage, limiting the output current to higher than 3.5A typical. When the output voltage is less than 0.2V, the short circuit current protection starts the current fold back function and maintains the loading current 1.8A. The output can be shorted to ground indefinitely without damaging the part. Output Capacitor The output capacitor must meet both requirements for Power Good minimum amount of capacitance and ESR in all LDOs application. The RT9025 is designed specifically to work The power good function is an open-drain output. Connects 100kΩ pull up resistor to VOUT to obtain an output voltage. with low ESR ceramic output capacitor in space-saving and performance consideration. Using a ceramic capacitor The PGOOD pin will output high immediately after the output voltage arrives 90% of normal output voltage. which value is at least 10µF with ESR is > 15mΩ on the RT9025 output ensures stability. The RT9025 still works Thermal Shutdown Protection well with output capacitor of other types due to the wide stable ESR range. Figure 3 shows the curves of allowable ESR range as a function of load current for various output capacitor values. Output capacitor of larger capacitance can reduce noise and improve load transient response, stability, and PSRR. The output capacitor should be located not more than 0.5 inch from the VOUT pin of the RT9025 and returned to a clean analog ground. www.richtek.com 8 Thermal protection limits power dissipation to prevent IC over temperature in RT9025. When the operation junction temperature exceeds 160°C, the over temperature protection circuit starts the thermal shutdown function and turns the pass transistor off. The pass transistor turns on again after the junction temperature cools by 30°C. RT9025 lowers its OTP trip level from 160°C to 90°C when output short circuit occurs (VOUT < 0.2V). It limits DS9025-05 March 2011 RT9025 IC case temperature under 100°C and provides maximum safety to customer while output short circuit occurring. Power Dissipation For continuous operation, do not exceed absolute maximum operation junction temperature 125°C. The power dissipation definition in device is: (a) Copper Area = (2.3 x 2.3) mm2, θJA = 75°C/W PD = (VIN − VOUT ) x IOUT + VIN x IQ The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junctions to ambient. The maximum power dissipation can be calculated by following formula : PD(MAX) = (TJ(MAX) − TA) / θJA (b) Copper Area = 10mm2, θJA = 64°C/W Where T J(MAX) is the maximum operation junction temperature, TA is the ambient temperature and the θJA is the junction to ambient thermal resistance. For recommended operating conditions specification of RT9025,the maximum junction temperature is 125°C. The junction to ambient thermal resistance for SOP-8 (Exposed Pad) package is 75°C/W on the standard JEDEC 51-7 (4 layers, 2S2P) thermal test board. The copper thickness is 2oz. The maximum power dissipation at TA = 25°C can be calculated by following formula : (c) Copper Area = 30mm2, θJA = 54°C/W PD(MAX) = (125°C − 25°C) / (75°C/W) = 1.33W (SOP-8 Exposed Pad on the minimum layout) Layout Considerations The thermal resistance θJA of SOP-8 (Exposed Pad) is determined by the package design and the PCB design. However, the package design had been designed. If (d) Copper Area = 50mm2, θJA = 51°C/W possible, it's useful to increase thermal performance by the PCB design. The thermal resistance θJA can be decreased by adding a copper under the exposed pad of SOP-8 (Exposed Pad) package. As shown in Figure 4, the amount of copper area to which the SOP-8 (Exposed Pad) is mounted affects thermal performance. When mounted to the standard SOP-8 (Exposed Pad) pad (Figure 4.a), θJA is 75°C/W. Adding copper area of pad under the SOP-8 (Exposed Pad) (Figure 4.b) reduces the θJA to 64°C/W. Even further, increasing the copper area of pad to 70mm2 (Figure 4.e) reduces the θJA to 49°C/W. DS9025-05 March 2011 (e) Copper Area = 70mm2, θJA = 49°C/W Figure 4. Thermal Resistance vs. Copper Area Layout Thermal Design www.richtek.com 9 RT9025 The maximum power dissipation depends on operating ambient temperature for fixed T J(MAX) and thermal resistance θJA. For RT9025 packages, the Figure 5 of derating curves allows the designer to see the effect of rising ambient temperature on the maximum power allowed. 2.2 Power Dissipation (W) 2.0 Copper Area 70mm2 50mm2 30mm2 10mm2 Min. layout 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 JEDEC 4-Layers PCB 0.0 0 20 40 60 80 100 120 140 Ambient Temperature (°C) Figure 5. Derating Curve for Package www.richtek.com 10 DS9025-05 March 2011 RT9025 Outline Dimension H A M J B F C I D Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 4.801 5.004 0.189 0.197 B 3.810 3.988 0.150 0.157 C 1.346 1.753 0.053 0.069 D 0.330 0.508 0.013 0.020 F 1.194 1.346 0.047 0.053 H 0.170 0.254 0.007 0.010 I 0.050 0.254 0.002 0.010 J 5.791 6.200 0.228 0.244 M 0.400 1.270 0.016 0.050 8-Lead SOP Plastic Package DS9025-05 March 2011 www.richtek.com 11 RT9025 H A M EXPOSED THERMAL PAD (Bottom of Package) Y J X B F C I D Dimensions In Millimeters Symbol Dimensions In Inches Min Max Min Max A 4.801 5.004 0.189 0.197 B 3.810 4.000 0.150 0.157 C 1.346 1.753 0.053 0.069 D 0.330 0.510 0.013 0.020 F 1.194 1.346 0.047 0.053 H 0.170 0.254 0.007 0.010 I 0.000 0.152 0.000 0.006 J 5.791 6.200 0.228 0.244 M 0.406 1.270 0.016 0.050 X 2.000 2.300 0.079 0.091 Y 2.000 2.300 0.079 0.091 X 2.100 2.500 0.083 0.098 Y 3.000 3.500 0.118 0.138 Option 1 Option 2 8-Lead SOP (Exposed Pad) Plastic Package Richtek Technology Corporation Richtek Technology Corporation Headquarter Taipei Office (Marketing) 5F, No. 20, Taiyuen Street, Chupei City 5F, No. 95, Minchiuan Road, Hsintien City Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)86672399 Fax: (8862)86672377 Email: [email protected] Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek. www.richtek.com 12 DS9025-05 March 2011