RT5045A Power Management Unit Total Power Solution for SSD General Description Features The RT5045A is a total power management solution for SSD (Solid State Drive) and applicable the dedicated powered by 3.3V or 5V input. RT5045A provides six step-down converters, one LDO and is designed to be flexible PMIC for supporting different output load applications with regulated power sequence. CH2 CH3 RT5045A provides configurable outputs for core power of SSD controller, NAND Flash memory, I/O power and : 0.7V to 1.3V in 25mV step, Output 2A max. CH5 : 0.7V to 1.3V in 25mV step, Output 1A max. CH6 Solid State Devices Ordering Information Voltage One low quiescent current LDO with Output 200mA max. Low Power Mode (LPM) for Ultra Low Quiescent Current High-speed I2C Interfaces for Programming Outputs POR Threshold Selection and Open-Drain POR Indicator Power Sequence Control During Startup RT5045A Package Type WSC : WL-CSP-52B 3.19x3.59 (BSC) Note : Richtek products are : RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. : 0.7V to 1.3V in 25mV step, Output 3.5A max. 2MHz CH4/5/6 2.5MHz Default Switching Frequency and Programmable 1 to 3MHz 2MHz Default Switching Frequency and Programmable 0.8 to 2.3MHz (CH1) VSEL0 & VSEL1 for Programmable Default Output CH2/3 Applications : 0.9V to 1.6V in 25mV step, Output 1A max. : 1.5V to 2.1V in 25mV step, Output 1A max. CH4 DRAM power. It supports dynamic voltage scaling by a dedicated I2C interface and also apply low power mode to minimize the standby power consumption. Supply Input Voltage Range : 2.9V to 5.5V Six High Efficiency, Low Voltage Buck Converters Up to 85% Efficiency at 10mA, and at Half Rated Output Current CH1 : 2.3V to 3V in 25mV step, Output 4A max. SuiTable for use in SnPb or Pb-free soldering processes. OVP, UVP, UVLO Thermal Shutdown Protection Simplified Application Circuit AVIN PVIN AVDD PVIN1 PVIN2 RT5045A CH1 SW1 FB1 CH2 SW2 FB2 CH3 SW3 FB3 CH4 SW4 FB4 CH5 SW5 FB5 CH6 SW6 FB6 PVIN3 PVIN4 PVIN5 PVIN6 I2C VR Volt Default Setting POR Vth Selection POR Information SCL SDA VSEL0 VSEL1 PORSEL POR Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5045A-00 March 2015 LDO SSD is a registered trademark of Richtek Technology Corporation. www.richtek.com 1 RT5045A Pin Configurations Marking Information (TOP VIEW) A1 A2 A3 A4 LDO SCL SDA AGND B2 B3 B4 B1 FB1 C1 A5 A6 AVDD AGND B5 B6 A7 A8 POR FB6 B7 B8 C2 D1 D2 LX1 LX1 C7 C8 LX6 LX6 D7 D8 PVIN6 PVIN6 E1 E2 E7 E8 PVIN1 PVIN1 PGND FB5 F7 F8 F1 F2 FB2 PGND G1 G2 PGND PGND5 PGND2 PGND LX2 RT5045AWSC : Product Number YMDNN : Date Code PGND PGND PORSEL VSEL0 VSEL1 PGND6 PGND6 PGND1 PGND1 H1 RT5045A WSC YMDNN H2 H3 PGND PVIN3 J1 J2 J3 PVIN2 FB3 PVIN3 H4 H5 H6 LX3 PGND3/4 LX4 J4 J5 J6 LX3 PGND3/4 LX4 G7 G8 PGND LX5 H7 H8 PVIN4 PVIN5 J7 J8 PVIN4 FB4 WL-CSP-52B 3.19x3.59 (BSC) Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 2 is a registered trademark of Richtek Technology Corporation. DS5045A-00 March 2015 RT5045A Functional Pin Description Pin No. Pin Name Pin Function A1 LDO LDO Output. A2 SCL I2C Interface Clock Signal. A3 SDA I2C Interface Data Signal. A4, A6 AGND Analog Ground. A5 AVDD Analog Power Input for Control Logic and LDO Input. A7 POR Power On Reset Information. When AVDD > VPORTH, POR = high level. When AVDD < VPORTH – 100mV, POR = low level. A8 FB6 CH6 Buck Converter Output Voltage Feedback Input. B1 FB1 CH1 Buck Converter Output Voltage Feedback Input. B2, B3, E7, F2, F7, PGND G2, G7, H2 Power Ground. B4 PORSEL POR Threshold Voltage Select. B5 VSEL0 Power Rails Default Voltage Select Pin0. Pull down resistance 1.5M typ. B6 VSEL1 Power Rails Default Voltage Select Pin1. Pull down resistance 1.5M typ. B7, B8 PGND6 CH6 Buck Converter Power Ground. C1, C2 PGND1 CH1 Buck Converter Power Ground. C7, C8 LX6 CH6 Buck Converter Switched Output. D1, D2 LX1 CH1 Buck Converter Switched Output. D7, D8 PVIN6 CH6 Buck Converter Input. E1, E2 PVIN1 CH1 Buck Converter Input. E8 FB5 CH5 Buck Converter Output Voltage Feedback Input. F1 FB2 CH2 Buck Converter Output Voltage Feedback Input. F8 PGND5 CH5 Buck Converter Power Ground. G1 PGND2 CH2 Buck Converter Power Ground. G8 LX5 CH5 Buck Converter Switched Output. H1 LX2 CH2 Buck Converter Switched Output. H3, J3 PVIN3 CH3 Buck Converter Input. H4, J4 LX3 CH3 Buck Converter Switched Output. H5, J5 PGND3/4 CH3 and CH4 Buck Converter Power Ground. H6, J6 LX4 CH4 Buck Converter Switched Output. H7, J7 PVIN4 CH4 Buck Converter Input. H8 PVIN5 CH5 Buck Converter Input. J1 PVIN2 CH2 Buck Converter Input. J2 FB3 CH3 Buck Converter Output Voltage Feedback Input. J8 FB4 CH4 Buck Converter Output Voltage Feedback Input. Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5045A-00 March 2015 is a registered trademark of Richtek Technology Corporation. www.richtek.com 3 RT5045A Function Block Diagram AVDD CH4 CH1 PVIN4 PVIN1 LX4 LX1 PGND4 FB4 PGND1 0.7V to 1.3V 2A 2.3V to 3V 4A CH2 CH5 PVIN5 PVIN2 LX5 LX2 PGND5 FB5 PGND2 0.7V to 1.3V 1A CH6 Power Control 0.9V to 1.6V 1A PVIN3 LX3 LX6 PGND3 PGND6 0.7V to 1.3V 3.5A AVDD 1.656V to 2.16V 2.3V to 3V 0.2A POR Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 4 1.5V to 2.1V 1A I2C LDO LDO FB2 CH3 PVIN6 FB6 FB1 Voltage Select POR Select FB3 SCL SDA VSEL0 VSEL1 PORSEL AGND is a registered trademark of Richtek Technology Corporation. DS5045A-00 March 2015 RT5045A Operation The RT5045A provides six synchronous Buck regulators and one LDO to satisfy the entire power system of SSD. This device can communicate with processors through I2C interface for programming the voltage, monitoring the status, or in/out the power saving mode. Buck Converter The RT5045A incorporates six high-efficiency synchronous switching Buck converters that deliver various voltages. CH1 features peak current mode architecture of Buck converter. For preventing the unstable when duty > 50% traditionally, it adds external ramp and compensation to reduce duty cycle perturbation and stabilize the current loop. CH1 can operate up to 100% duty to let the lowest input voltage still maintain the regulator work. And the output voltage will be the lowest input voltage decreases dropout voltage on the resistance of current path. Unlike CH1, the control scheme of other buck converters are constant-on-time current mode for low output voltage, quick transient response. The buck converters have a full set of protection. Buck Over-Current Protection The buck converters provides over current protection by detecting low-side MOSFET valley inductor current for CH2~CH6 and by detection high-side MOSFET peak current for CH1. If the sensed inductor current is over the current limit threshold, the OCP will be triggered. When OCP is tripped, the buck converter will keep the over current threshold level until the over current condition is removed. Buck Under Voltage Protection The output voltages are continuously monitored for under voltage protection. If the output voltage falls below 60% of the reference voltage, under voltage protection is triggered and then the high-side and lowside MOSFET will turn off. The UVP circuit will turn off all rails and latched. The way to cannel the latched behavior is to re-give AVDD power of RT5045A. Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5045A-00 March 2015 Buck Output Over Voltage Protection The output voltages are continuously monitored for over voltage protection. If the output voltage exceeds 120% of the reference, over voltage protection is triggered and then the high-side and low-side MOSFET will turn off. The power MOS will keep turn off until the over voltage condition is removed. Linear Dropout Regulator The RT5045A includes one performance linear dropout regulators. The LDO contains an independent current limit and under voltage protection circuit to prevent unexpected applications. When the path current is over the current limit, the current limit circuit fixes the gate voltage to limit the output current. And if the output voltage is less than 60% of reference voltage, the UVP circuit will shut-down all rails and latched. The way to cannel the latched behavior is to re-give AVDD power of RT5045A. Over-Temperature Protection If the temperature of the buck converter is over 150°C, the OTP circuit acts and makes all power rails shutdown. They recover back with power-up sequence when the temperature of PMIC is low to 125°C. VSEL0, VSEL1 The RT5045A applies four set default output voltages for all power rails when the device starts a power up sequence. PORSEL PORSEL is a logic pin to select the threshold voltage of AVDD to raise POR signal. If AVDD voltage is over the threshold voltage, the device starts a POR rising function. When set PORSEL = 1, the threshold voltage of AVDD is 3.8V, else the threshold voltage is 2.8V. POR POR pin is a signal to inform the system that the power up sequence of the RT5045A is completed. If AVDD voltage is larger than the POR rising threshold voltage, the POR will go high with a timing delay. If AVDD voltage is less than POR falling threshold voltage, the POR falls right away. is a registered trademark of Richtek Technology Corporation. www.richtek.com 5 RT5045A Absolute Maximum Ratings (Note 1) Supply Input Voltage, AVDD, PVIN1, PVIN2, PVIN3, PVIN4, PVIN5, PVIN6 ---------------------------0.3V to 6V Switch Node Voltage, LX1, LX2, LX3, LX4, LX5, LX6 ---------------------------------------------------------0.3V to 6V Other Pins ----------------------------------------------------------------------------------------------------------------0.3V to 6V Power Dissipation, PD @ TA = 25C WL-CSP-52B 3.19x3.59 (BSC) -------------------------------------------------------------------------------------3.84W Package Thermal Resistance (Note 2) WL-CSP-52B 3.19x3.59 (BSC), JA -------------------------------------------------------------------------------26C/W Lead Temperature (Soldering, 10 sec.) ---------------------------------------------------------------------------260C Junction Temperature -------------------------------------------------------------------------------------------------150C Storage Temperature Range ----------------------------------------------------------------------------------------65C to 150C ESD Susceptibility (Note 3) HBM (Human Body Model) ------------------------------------------------------------------------------------------2kV Recommended Operating Conditions (Note 4) Supply Input Voltage, AVDD, PVIN1, PVIN2, PVIN3, PVIN4, PVIN5, PVIN6 ---------------------------2.9V to 5.5V Other Pins, VSEL0, VSEL1, SCL, SDA, PORSEL, POR -----------------------------------------------------0V to 5.5V Ambient Temperature Range----------------------------------------------------------------------------------------40C to 85C Junction Temperature Range ---------------------------------------------------------------------------------------40C to 125C Electrical Characteristics (AVDD = 3.3V, PVIN = 3.3V, TA = 25C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit 2.9 3.3 5.5 V -- 15 25 A -- 15 25 A 1.2 -- -- V PMIC AVDD Supply Voltage VAVIN AVDD Supply Current AVDD Supply Current in Sleep Mode VSEL0, VSEL1, PORSEL High IAVIN VIH All Voltage Rails off CH5 = LPM, other voltage rails off Logic signal rising threshold VSEL0, VSEL1, PORSEL Low VIL Logic signal falling threshold -- -- 0.4 V Hysteresis -- 100 -- mV POR_OPTION = 0, PORSEL = 0, UVLO falling 2.673 2.7 2.727 POR_OPTION = 0, PORSEL = 1, UVLO falling 3.663 3.7 3.737 -- 100 -- POR_OPTION = 0, PORSEL = 0, POR falling 2.673 2.7 2.727 POR_OPTION = 0, PORSEL = 1, POR falling 3.663 3.7 3.737 Hysteresis -- 100 -- mV Sink current = 5mA -- -- 0.4 V AVDD UVLO Hysteresis AVDD UVLO Threshold VAVUV AVDD UVLO Hysteresis POR Threshold Hysteresis VPORTH POR Hysteresis POR Output Low VPORLO Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 6 V mV V is a registered trademark of Richtek Technology Corporation. DS5045A-00 March 2015 RT5045A Parameter Symbol AVDD > VPORTH, detect the POR rising edge. VSEL = 0, VSEL1 = 0 POR Rising Delay Time Thermal Shutdown Threshold Test Conditions TSD Thermal Shutdown Hysteresis Min Typ Max Unit 9 10 11 ms -- 150 -- C -- 25 -- C -- 25 35 A CH1 (4A) AVDD Quiescent Current IINQ Enable, no include IAVIN AVDD LPM Quiescent IINLP LPM enable, not include IAVIN -- 10 20 A 2 Controlled by I C 2.3 -- 3 V VSEL0 = 0, VSEL1 = 0 2% 2.5 +2% V -- 25 -- mV -- 0.5 -- %/V Output Voltage Scaling Output Voltage Default VOUT DC Output Voltage Programmable step VSTEP switching, not Line Regulation Load Regulation Force PWM -- 0.5 -- %/A Transient Load Regulation VIN = 3.3V, VOUT = 2.5V, L = 0.47H, COUT = 22F x 2, IOUT = 0.2 to 1.5A at SR = 0.13A/s -- -- 84 mV H/S Switch On Resistance RDS(ON)H VIN = 5V -- 35 -- m L/S Switch On Resistance RDS(ON)L VIN = 5V -- 18 -- m Current Limit IOC Peak current, IMAX[6:5] = 10 5 5.8 -- A Switching Frequency FSW FREQ[2:0] = 110 1.8 2 2.2 MHz Minimum On-Time TON -- 150 200 ns OVP Trip Threshold VOVP 115 120 125 % OVP Propagation Delay TOVPDLY -- 1 -- s UVP Trip Threshold UVP Propagation Delay (Note 5) Soft-Start Time VUVP 55 60 65 % TUVPDLY -- 2 -- s TSS -- 0.5 0.8 ms -- 50 -- VIN = 3.3V, VOUT = 2.5V, Load = 10mA 85 -- -- VIN = 3.3V, VOUT = 2.5V, Load = 1A 90 -- -- -- 25 35 A -- 10 20 A Controlled by I2C 0.9 -- 1.6 V VSEL0 = 0, VSEL1 = 0 2% 1.35 +2% V -- 25 -- mV -- 0.5 -- %/V -- 0.5 -- %/A OVP detected UVP detected Discharge Resistance Efficiency % CH2 (1A) AVDD Quiescent Current IINQ Enable, no include IAVIN AVDD LPM Quiescent IINLP LPM enable, not include IAVIN Output Voltage Scaling Output Voltage Default VOUT DC Output Voltage Programmable Step VSTEP Line Regulation Load Regulation Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5045A-00 March 2015 Force PWM switching, not is a registered trademark of Richtek Technology Corporation. www.richtek.com 7 RT5045A Parameter Symbol Transient Load Regulation Test Conditions Min Typ Max Unit VIN = 3.3V, VOUT = 1.5V -- -- 75 mV H/S Switch On Resistance RDS(ON)H VIN = 5V -- 40 -- m L/S Switch On Resistance RDS(ON)L VIN = 5V -- 20 -- m Current Limit IOC Valley current, IMAX[6:5] = 10, 2 2.5 -- A Switching Frequency FSW FREQ[2:0] = 101 1.8 2 2.2 MHz Minimum Off-Time TOFF -- 120 160 ns OVP Trip Threshold VOVP 120 125 130 % OVP Propagation Delay TOVPDLY 1 -- s UVP Trip Threshold UVP Propagation Delay (Note 5) Soft-Start Time VUVP 55 60 65 % TUVPDLY -- 2 -- s TSS -- 0.5 0.8 ms -- 100 -- VIN = 3.3V, VOUT = 1.5V, Load = 10mA 85 -- -- VIN = 3.3V, VOUT = 1.5V, Load = 500mA 85 -- -- -- 25 35 A OVP detected UVP detected Discharge Resistance Efficiency % CH3 (1A) AVDD Quiescent Current IINQ Enable, no include IAVIN AVDD LPM Quiescent IINLP LPM enable, not include IAVIN -- 10 20 A 2 Controlled by I C 1.5 -- 2.1 V VSEL0 = 0, VSEL1 = 0 2% 1.8 +2% V -- 25 -- mV -- 0.5 -- %/V Output Voltage Scaling Output Voltage Default VOUT DC Output Voltage Programmable step VSTEP switching, not Line Regulation Load Regulation Force PWM -- 0.5 -- %/A Transient Load Regulation VIN = 3.3V, VOUT = 1.8V -- -- 90 mV H/S Switch On Resistance RDS(ON)H VIN = 5V -- 45 -- m L/S Switch On Resistance RDS(ON)L VIN = 5V -- 25 -- m Current Limit IOC Valley current, IMAX[6:5] = 10 2 2.5 -- A Switching Frequency FSW FREQ[2:0] = 101 1.8 2 2.2 MHz Minimum Off-Time TOFF -- 120 160 ns OVP Trip Threshold VOVP 120 125 130 % OVP Propagation Delay TOVPDLY -- 1 -- s UVP Trip Threshold UVP Propagation Delay (Note 5) Soft-Start Time VUVP 55 60 65 % TUVPDLY -- 2 -- s TSS -- 0.5 0.8 ms -- 50 -- VIN = 3.3V, VOUT = 1.8V, Load = 10mA 85 -- -- VIN = 3.3V, VOUT = 1.8V, Load = 500mA 85 -- -- OVP detected UVP detected Discharge Resistance Efficiency Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 8 % is a registered trademark of Richtek Technology Corporation. DS5045A-00 March 2015 RT5045A Parameter Symbol Test Conditions Min Typ Max Unit -- 25 35 A CH4 (2A) AVDD Quiescent Current IINQ Enable, no include IAVIN AVDD LPM Quiescent IINLP LPM enable, not include IAVIN -- 10 20 A 2 Controlled by I C 0.7 -- 1.3 V VSEL0 = 0, VSEL1 = 0 2% 1 +2% V -- 25 -- mV -- 0.5 -- %/V Output Voltage Scaling Output Voltage Default VOUT DC Output Voltage Programmable step VSTEP switching, not Line Regulation Load Regulation Force PWM -- 0.5 -- %/A Transient Load Regulation VIN = 3.3V, VOUT = 1V -- -- 50 mV H/S Switch On Resistance RDS(ON)H VIN = 5V -- 45 -- m L/S Switch On Resistance RDS(ON)L VIN = 5V -- 25 -- m Current Limit IOC Valley current, IMAX[6:5] = 10 2.5 3 -- A Switching Frequency FSW FREQ[2:0] = 110 2.2 2.5 2.75 MHz Minimum Off-Time TOFF -- 120 160 ns OVP Trip Threshold VOVP 120 125 130 % OVP Propagation Delay TOVPDLY -- 1 -- s UVP Trip Threshold UVP Propagation Delay (Note 5) Soft-Start Time VUVP 55 60 65 % TUVPDLY -- 2 -- s TSS -- 0.5 0.8 ms Discharge Resistance TDIS -- 150 -- 85 -- -- 85 -- -- -- 25 35 A OVP detected UVP detected VIN = 3.3V, VOUT = 1V, Load = 10mA VIN = 3.3V, VOUT = 1V, Load = 1A Efficiency % CH5 (1A) AVDD Quiescent Current IINQ Enable, no include IAVIN AVDD LPM Quiescent IINLP LPM enable, not include IAVIN -- 10 20 A 2 Controlled by I C 0.7 -- 1.3 V VSEL0 = 0, VSEL1 = 0 2% 1 +2% V -- 25 -- mV -- 0.5 -- %/V Output Voltage Scaling Output Voltage Default VOUT DC Output Voltage Programmable Step VSTEP switching, not Line Regulation Load Regulation Force PWM -- 0.5 -- %/A Transient Load Regulation VIN = 3.3V, VOUT = 1V -- -- 50 mV H/S Switch On Resistance RDS(ON)H VIN = 5V -- 50 -- m L/S Switch On Resistance RDS(ON)L VIN = 5V -- 30 -- m Current Limit IOC Valley current, IMAX[6:5] = 10 2 2.5 -- A Switching Frequency FSW FREQ[2:0] = 110 2.2 2.5 2.75 MHz Minimum Off-Time TOFF -- 120 160 ns Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5045A-00 March 2015 is a registered trademark of Richtek Technology Corporation. www.richtek.com 9 RT5045A Parameter Symbol Min Typ Max Unit 120 125 130 % -- 1 -- s 55 60 65 % TUVPDLY -- 2 -- s TSS -- 0.5 0.8 ms -- 150 -- VIN = 3.3V, VOUT = 1V, Load = 1mA, LPM 85 -- -- VIN = 3.3V, VOUT = 1V, Load = 500mA 85 -- -- -- 25 35 A OVP Trip Threshold VOVP OVP Propagation Delay TOVPDLY UVP Trip Threshold UVP Propagation Delay (Note 5) Soft-Start Time VUVP Test Conditions OVP detected UVP detected Discharge Resistance Efficiency % CH6 (3.5A) AVDD Quiescent Current IINQ Enable, no include IAVIN AVDD LPM Quiescent IINLP LPM enable, not include IAVIN -- 10 20 A 2 Controlled by I C 0.7 -- 1.3 V VSEL0 = 0, VSEL1 = 0 2% 1 +2% V -- 25 -- mV -- 0.5 -- %/V Output Voltage Scaling Output Voltage Default VOUT DC Output Voltage Programmable Step VSTEP switching, not Line Regulation Load Regulation Force PWM -- 0.5 -- %/A Transient Load Regulation VIN = 3.3V, VOUT = 1V -- -- 50 mV H/S Switch On Resistance RDS(ON)H VIN = 5V -- 40 -- m L/S Switch On Resistance RDS(ON)L VIN = 5V -- 20 -- m Current Limit IOC Valley current, IMAX[6:5] = 10 4.5 5 -- A Switching Frequency FSW FREQ[2:0] = 110 2.2 2.5 2.75 MHz Minimum Off-Time TOFF -- 120 160 ns OVP Trip Threshold VOVP 120 125 130 % OVP Propagation Delay TOVPDLY -- 1 -- s UVP Trip Threshold UVP Propagation Delay (Note 5) Soft-Start Time VUVP 55 60 65 % TUVPDLY -- 2 -- s TSS -- 0.5 0.8 ms -- 150 -- 85 -- -- 85 -- -- OVP detected UVP detected Discharge Resistance VIN = 3.3V, VOUT = 1V, Load = 10mA VIN = 3.3V, VOUT = 1V, Load = 1A Efficiency % LDO (0.2A) AVDD Quiescent Current IINQ Enable, not include IAVIN -- 28 38 A AVDD LPM Quiescent IINLP LPM enable, not include IAVIN VSEL0 = 0, VSEL1 = 0 VSEL0 = 0, VSEL1 = 1 VSEL0 = 1, VSEL1 = 0 VSEL0 = 1, VSEL1 = 1 -- 15 25 A 2.3 -- 3 Output Voltage Scaling Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 10 V 1.656 -- 2.16 is a registered trademark of Richtek Technology Corporation. DS5045A-00 March 2015 RT5045A Parameter Symbol Output Voltage Default DC Output Voltage Programmable Step Line Regulation Min Typ Max Unit 2% 2.5 +2% V -- 25 -- mV -- 0.5 -- %/V -- 0.5 -- %/A VIN = 3.3V, VOUT = 2.5V, Load = 20mA to 180mA during 5s -- -- 125 mV VIN = 3.3V, VOUT = 2.5V Load = 200mA -- 100 200 mV -- 0.4 -- A 55 60 65 % TUVPDLY -- 2 -- s VOUT Test Conditions VSEL0 = 0, VSEL1 = 0 VSTEP Load Regulation Transient Load Regulation Dropout Voltage VDROP Current Limit IOC UVP Trip Threshold UVP Propagation Delay (Note 5) Soft-Start Time VUVP TSS -- 0.3 0.6 ms Discharge Resistance TDIS -- 100 -- Power Supply Rejection Rate PSRR Load = 100mA, F = 100Hz -- 50 -- Load = 100mA, F = 100kHz -- 28 -- Min Typ Max High-Level 1.2 -- -- Low-Level -- -- 0.4 -- -- 400 kHz UVP detected dB I2C for Fast Mode Parameter SDA, SCL Input Voltage Symbol Test Conditions Unit V Fast Mode SCL Clock Rate f SCL Hold Time (Repeated) START Condition. After this Period, the First Clock Pulse is Generated tHD;STA 0.6 -- -- s LOW Period of the SCL Clock tLOW 1.3 -- -- s HIGH Period of the SCL Clock tHIGH 0.6 -- -- s Set-Up Time for a Repeated START Condition tSU;STA 0.6 -- -- s Data Hold Time tHD;DAT 0 -- 0.9 s Data Set-Up Time tSU;DAT 100 -- -- ns Set-Up Time for STOP Condition tSU;STO 0.6 -- -- s 1.3 -- -- s 20 -- 300 ns 20 -- 300 ns 2 -- -- mA Bus Free Time between a STOP tBUF and START Condition Rising Time of both SDA and tr SCL Signals Falling Time of both SDA and tf SCL Signals SDA and SCL Output Low Sink Current IOL SDA or SCL Voltage = 0.4V Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5045A-00 March 2015 is a registered trademark of Richtek Technology Corporation. www.richtek.com 11 RT5045A I2C High Speed Mode Parameter SDA, SCL Input Voltage Symbol Test Conditions Min Typ Max Unit High-Level 1.2 -- -- Low-Level -- -- 0.4 -- -- 3.4 MHz V High Speed Mode SCL Clock Rate f SCL Hold Time (Repeated) START Condition. After this Period, the First Clock Pulse is Generated tHD;STA 160 -- -- ns LOW Period of the SCL Clock tLOW 160 -- -- ns HIGH Period of the SCL Clock tHIGH 60 -- -- ns Set-Up Time for a Repeated START Condition tSU;STA 60 -- -- ns Data Hold Time tHD;DAT 0 -- 70 ns Data Set-Up Time tSU;DAT 10 -- -- ns Set-Up Time for STOP Condition tSU;STO 160 -- -- ns Rising Time of both SDA and SCL Signals tr 10 -- 80 ns Falling Time of both SDA and SCL Signals tf 10 -- 80 ns SDA and SCL Output Low Sink Current IOL 2 -- -- mA SDA or SCL Voltage = 0.4V Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. JA is measured at TA = 25C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. Note 3. Devices are ESD sensitive. Handling precaution recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. Design Guaranteed. Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 12 is a registered trademark of Richtek Technology Corporation. DS5045A-00 March 2015 RT5045A Typical Application Circuit H7, J7 PVIN PVIN4 RT5045A PVIN1 E1, E2 PVIN 10µF x 2 10µF 0.47µH CH4, 2A H6, J6 22µF J8 J5 H8 PVIN LX4 FB4 LX1 FB1 PGND4 PGND1 PVIN5 PVIN2 D1, D2 0.47µH CH1, 4A 22µF x 2 B1 C1, C2 J1 PVIN 10µF 10µF 0.47µH CH5, 1A 22µF G8 E8 F8 D7,D8 PVIN LX5 FB5 LX2 FB2 PGND5 PGND2 PVIN6 PVIN3 H1 0.47µH CH2, 1A 22µF F1 G1 H3, J3 PVIN 10µF x 2 0.47µH CH6, 3.5A 22µF x 2 10µF C7, C8 A8 B7, B8 AVIN LX6 FB6 PGND6 LX3 FB3 PGND3 AVDD 100k 2.2k 2.2k A2 A3 B5 B6 B4 A7 March 2015 0.47µH J2 CH3, 1A 22µF H5 A5 AVIN 2.2µF SCL SDA VSEL0 VSEL1 PORSEL POR Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5045A-00 H4, J4 AGND LDO A4, A6 A1 LDO, 0.2A 4.7µF PGND B2, B3, E7, F2, F7, G2, G7, H2 is a registered trademark of Richtek Technology Corporation. www.richtek.com 13 RT5045A Functional Register Table Table 1. RT5045A Register Summary Name Type Register Reset Address Offset POWER_GOOD RO 0x00 0x00 CH1_CFG_REG RW 0x56 0x01 CH1_SEL_REG RW 0x00 0x02 CH2_CFG_REG RW 0x55 0x03 CH2_SEL_REG RW 0x00 0x04 CH3_CFG_REG RW 0x55 0x05 CH3_SEL_REG RW 0x00 0x06 CH4_CFG_REG RW 0x56 0x07 CH4_SEL_REG RW 0x00 0x08 CH5_CFG_REG RW 0x56 0x09 CH5_SEL_REG RW 0x00 0x0A CH6_CFG_REG RW 0x56 0x0B CH6_SEL_REG RW 0x00 0x0C LDO_SEL_REG RW 0x00 0x0D DCDCCTRL0_REG RW 0x00 0x11 SLEEP_REG RW 0x00 0x12 DCDCCTRL1_REG RW 0x00 0x13 DISCHARGE_REG RW 0xFE 0x14 POR_OPTION_REG RW 0x00 0x17 DCDCTRL2_REG RW 0x00 0x18 WK_TIME1 RW 0x00 0x19 WK_TIME2 RW 0x00 0x1A WK_TIME3 RW 0x00 0x1B WK_TIME4 RW 0x00 0x1C PRODUCT_ID_REG RO 0x01 0x20 MANUFACTURER_ID RO 0x01 0x21 REVISION_NUMBER RO 0x00 0x22 Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 14 is a registered trademark of Richtek Technology Corporation. DS5045A-00 March 2015 RT5045A Table 2. POWER_GOOD_REG Address : 0x00 Description : Power good information register. When Voltage Rails achieve 90% of VID target, the relative bit will set to 1. Bits Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Name CH1_PG CH2_PG CH3_PG CH4_PG CH5_PG CH6_PG LDO_PG POR Reset Value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R Bit2 Bit1 Bit0 Bits Name Description 7 CH1_PG Status bit. Indicates power good on CH1 6 CH2_PG Status bit. Indicates power good on CH2 5 CH3_PG Status bit. Indicates power good on CH3 4 CH4_PG Status bit. Indicates power good on CH4 3 CH5_PG Status bit. Indicates power good on CH5 2 CH6_PG Status bit. Indicates power good on CH6 1 LDO_PG Status bit. Indicates power good on LDO 0 POR Status bit. Indicates POR Table 3. CH1_CFG_REG Address : 0x01 Description : CH1 config register. Set CH1 current limited, VID change slew rate, PWM frequency. Bits Bit7 Name Reserved Reset Value 0 1 0 1 0 1 1 0 Read/Write R R/W R/W R/W R/W R/W R/W R/W Bits Name 7 Reserved 6:5 4:3 2:0 Bit6 Bit5 ILMAX Bit3 TSTEP Reserved bit ILMAX ILMAX[6:5] = 00 : 3.8A ILMAX[6:5] = 01 : 4.8A ILMAX[6:5] = 10 : 5.8A (default) ILMAX[6:5] = 11 : 6.8A TSTEP TSTEP[4:3] = 00 : 20mV/s TSTEP[4:3] = 01 : 15mV/s TSTEP[4:3] = 10 : 10mV/s (default) TSTEP[4:3] = 11 : 5mV/s FREQ FREQ[2:0] = 000 to 010, 0.8MHz FREQ[2:0] = 011, 1.1MHz FREQ[2:0] = 100, 1.4MHz FREQ[2:0] = 101, 1.7MHz FREQ[2:0] = 110, 2.0MHz (default) FREQ[2:0] = 111, 2.3MHz March 2015 FREQ Description Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5045A-00 Bit4 is a registered trademark of Richtek Technology Corporation. www.richtek.com 15 RT5045A Table 4. CH1_SEL_REG Address : 0x02 Description : CH1 VID setting register. CH1 VID setting and power on/off status and control. Bits Bit7 Name Reserved Reset Value 0 0 0 0 0 0 0 0 Read/Write R R/W R/W R/W R/W R/W R/W R/W Bits Name 7 Reserved 6:2 SEL 1:0 Reserved Bit6 Bit5 Bit3 Bit2 Bit1 SEL Bit0 Reserved Description Reserved bit Supply voltage, SEL[6:2] = 00000 to 00011 : 2.3V SEL[6:2] = 100 : 2.325V SEL[6:2] = 101 : 2.35V SEL[6:2] = 110 : 2.375V SEL[6:2] = 111 : 2.4V SEL[6:2] = 1000 : 2.425V SEL[6:2] = 1001 : 2.45V SEL[6:2] = 1010 : 2.475V SEL[6:2] = 1011 : 2.5V SEL[6:2] = 1100 : 2.525V SEL[6:2] = 1110 : 2.575V SEL[6:2] = 1111 : 2.6V SEL[6:2] = 10000 : 2.625V SEL[6:2] = 10001 : 2.65V SEL[6:2] = 10010 : 2.675V SEL[6:2] = 10011 : 2.7V SEL[6:2] = 10100 : 2.725V SEL[6:2] = 10101 : 2.75V SEL[6:2] = 10110 : 2.775V SEL[6:2] = 10111 : 2.8V SEL[6:2] = 11000 : 2.825V SEL[6:2] = 11001 : 2.85V SEL[6:2] = 11010 : 2.875V SEL[6:2] = 11011 : 2.9V SEL[6:2] = 11100 : 2.925V SEL[6:2] = 11111 : 3V VOUT = SEL[6:2] x 0.025V + 2.225V, from SEL[6:2] = 3 to 1F (hex) (After each UVLO rising, the voltage is set to the value by VSEL0/VSEL1 setting : VSEL0 = 0, VSEL1 = 0, VOUT = 2.5V VSEL0 = 0, VSEL1 = 1, VOUT = 2.5V VSEL0 = 1, VSEL1 = 0, VOUT = 2.5V VSEL0 = 1, VSEL1 = 1, VOUT = 2.5V) Reserved bit Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 16 Bit4 is a registered trademark of Richtek Technology Corporation. DS5045A-00 March 2015 RT5045A Table 5. CH2_CFG_REG Address : 0x03 Description : CH2 config register. Set CH2 current limited, VID change slew rate, PWM frequency. Bits Bit7 Name Reserved Reset Value 0 1 0 1 0 1 0 1 Read/Write R R/W R/W R/W R/W R/W R/W R/W Bits Name 7 Reserved 6:5 4:3 2:0 Bit6 Bit5 ILMAX Bit3 Bit1 Bit0 FREQ Description Reserved bit ILMAX ILMAX[6:5] = 00 : 1.5A ILMAX[6:5] = 01 : 2A ILMAX[6:5] = 10 : 2.5A (default) ILMAX[6:5] = 11 : 3A TSTEP TSTEP[4:3] = 00 : 20mV/s TSTEP[4:3] = 01 : 15mV/s TSTEP[4:3] = 10 : 10mV/s (default) TSTEP[4:3] = 11 : 5mV/s FREQ FREQ[2:0] = 000 to 011, 1MHz FREQ[2:0] = 100, 1.5MHz FREQ[2:0] = 101, 2.0MHz (default) FREQ[2:0] = 110, 2.5MHz FREQ[2:0] = 111, 3.0MHz March 2015 Bit2 TSTEP Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5045A-00 Bit4 is a registered trademark of Richtek Technology Corporation. www.richtek.com 17 RT5045A Table 6. CH2_SEL_REG Address : 0x04 Description : CH2 VID setting register. CH2 VID setting and power on/off status and control. Bits Bit7 Name Reserved Reset Value 0 0 0 0 0 0 0 0 Read/Write R R/W R/W R/W R/W R/W R/W R/W Bits Name 7 Reserved 6:2 SEL Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 SEL Bit0 Reserved Description Reserved bit Supply voltage, SEL[6:2] = 00000 to 00011 : 0.9V SEL[6:2] = 100 : 0.925V SEL[6:2] = 101 : 0.95V SEL[6:2] = 110 : 0.975V SEL[6:2] = 111 : 1V SEL[6:2] = 1000 : 1.025V SEL[6:2] = 1001 : 1.05V SEL[6:2] = 1010 : 1.075V SEL[6:2] = 1011 : 1.1V SEL[6:2] = 1100 : 1.125V SEL[6:2] = 1110 : 1.175V SEL[6:2] = 1111 : 1.2V SEL[6:2] = 10000 : 1.225V SEL[6:2] = 10001 : 1.25V SEL[6:2] = 10010 : 1.275V SEL[6:2] = 10011 : 1.3V SEL[6:2] = 10100 : 1.325V SEL[6:2] = 10101 : 1.35V SEL[6:2] = 10110 : 1.375V SEL[6:2] = 10111 : 1.4V SEL[6:2] = 11000 : 1.425V SEL[6:2] = 11001 : 1.45V SEL[6:2] = 11010 : 1.475V SEL[6:2] = 11011 : 1.5V SEL[6:2] = 11100 : 1.525V SEL[6:2] = 11111 : 1.6V VOUT = SEL[6:2] x 0.025V + 0.825V, from SEL[6:2] = 3 to 1F (hex) (After each UVLO rising, the voltage is set to the value by VSEL0/VSEL1 setting : VSEL0 = 0, VSEL1 = 0, VOUT = 1.35V VSEL0 = 0, VSEL1 = 1, VOUT = 1.35V VSEL0 = 1, VSEL1 = 0, VOUT = 1.35V VSEL0 = 1, VSEL1 = 1, VOUT = 1.2V) 1:0 Reserved Reserved bit Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 18 is a registered trademark of Richtek Technology Corporation. DS5045A-00 March 2015 RT5045A Table 7. CH3_CFG_REG Address : 0x05 Description : CH3 config register. Set CH3 current limited, VID change slew rate, PWM frequency. Bits Bit7 Name Reserved Reset Value 0 1 0 1 0 1 0 1 Read/Write R R/W R/W R/W R/W R/W R/W R/W Bits Name 7 Reserved 6:5 4:3 2:0 Bit6 Bit5 ILMAX Bit3 Bit1 Bit0 FREQ Description Reserved bit ILMAX ILMAX[6:5] = 00 : 1.5A ILMAX[6:5] = 01 : 2A ILMAX[6:5] = 10 : 2.5A (default) ILMAX[6:5] = 11 : 3A TSTEP TSTEP[4:3] = 00 : 20mV/s TSTEP[4:3] = 01 : 15mV/s TSTEP[4:3] = 10 : 10mV/s (default) TSTEP[4:3] = 11 : 5mV/s FREQ FREQ[2:0] = 000 to 011, 1MHz FREQ[2:0] = 100, 1.5MHz FREQ[2:0] = 101, 2.0MHz (default) FREQ[2:0] = 110, 2.5MHz FREQ[2:0] = 111, 3.0MHz March 2015 Bit2 TSTEP Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5045A-00 Bit4 is a registered trademark of Richtek Technology Corporation. www.richtek.com 19 RT5045A Table 8. CH3_SEL_REG Address : 0x06 Description : CH3 VID setting register. CH3 VID setting and power on/off status and control. Bits Bit7 Name Reserved Reset Value 0 0 0 0 0 0 0 0 Read/Write R R/W R/W R/W R/W R/W R/W R/W Bits Name 7 Reserved 6:2 SEL Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 SEL Bit0 Reserved Description Reserved bit Supply voltage, SEL[6:2] = 00000 to 00011 : 1.5V SEL[6:2] = 100 : 1.525V SEL[6:2] = 101 : 1.55V SEL[6:2] = 110 : 1.575V SEL[6:2] = 111 : 1.6V SEL[6:2] = 1000 : 1.625V SEL[6:2] = 1001 : 1.65V SEL[6:2] = 1010 : 1.675V SEL[6:2] = 1011 : 1.7V SEL[6:2] = 1100 : 1.725V SEL[6:2] = 1110 : 1.775V SEL[6:2] = 1111 : 1.8V SEL[6:2] = 10000 : 1.825V SEL[6:2] = 10001 : 1.85V SEL[6:2] = 10010 : 1.875V SEL[6:2] = 10011 : 1.9V SEL[6:2] = 10100 : 1.925V SEL[6:2] = 10101 : 1.95V SEL[6:2] = 10110 : 1.975V SEL[6:2] = 10111 : 2V SEL[6:2] = 11000 : 2.025V SEL[6:2] = 11001 : 2.05V SEL[6:2] = 11010 : 2.075V SEL[6:2] = 11011 to 11111 : 2.1V VOUT = SEL[6:2] x 0.025V + 1.425V, from SEL[6:2] = 3 to 1B (hex) (After each UVLO rising, the voltage is set to the value by VSEL0/VSEL1 setting : VSEL0 = 0, VSEL1 = 0, VOUT = 1.8V VSEL0 = 0, VSEL1 = 1, VOUT = 1.8V VSEL0 = 1, VSEL1 = 0, VOUT = 1.8V VSEL0 = 1, VSEL1 = 1, VOUT = 1.8V) 1:0 Reserved Reserved bit Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 20 is a registered trademark of Richtek Technology Corporation. DS5045A-00 March 2015 RT5045A Table 9. CH4_CFG_REG Address : 0x07 Description : CH4 config register. Set CH4 current limited, VID change slew rate, PWM frequency. Bits Bit7 Name Reserved Reset Value 0 1 0 1 0 1 1 0 Read/Write R R/W R/W R/W R/W R/W R/W R/W Bits Name 7 Reserved 6:5 4:3 2:0 Bit6 Bit5 ILMAX Bit3 Bit1 Bit0 FREQ Description Reserved bit ILMAX ILMAX[6:5] = 00 : 2A ILMAX[6:5] = 01 : 2.5A ILMAX[6:5] = 10 : 3A (default) ILMAX[6:5] = 11 : 3.5A TSTEP TSTEP[4:3] = 00 : 20mV/s TSTEP[4:3] = 01 : 15mV/s TSTEP[4:3] = 10 : 10mV/s (default) TSTEP[4:3] = 11 : 5mV/s FREQ FREQ[2:0] = 000 to 011, 1MHz FREQ[2:0] = 100, 1.5MHz FREQ[2:0] = 101, 2.0MHz FREQ[2:0] = 110, 2.5MHz (default) FREQ[2:0] = 111, 3.0MHz March 2015 Bit2 TSTEP Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5045A-00 Bit4 is a registered trademark of Richtek Technology Corporation. www.richtek.com 21 RT5045A Table 10. CH4_SEL_REG Address : 0x08 Description : CH4 VID setting register. CH4 VID setting and power on/off status and control. Bits Bit7 Name Reserved Reset Value 0 0 0 0 0 0 0 0 Read/Write R R/W R/W R/W R/W R/W R/W R/W Bits Name 7 Reserved 6:2 SEL Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 SEL Bit0 Reserved Description Reserved bit Supply voltage, SEL[6:2] = 00000 : 0.7V SEL[6:2] = 1 : 0.725V SEL[6:2] = 10 : 0.75V SEL[6:2] = 11 : 0.775V SEL[6:2] = 100 : 0.8V SEL[6:2] = 101 : 0.825V SEL[6:2] = 110 : 0.85V SEL[6:2] = 111 : 0.875V SEL[6:2] = 1000 : 0.9V SEL[6:2] = 1001 : 0.925V SEL[6:2] = 1010 : 0.95V SEL[6:2] = 1011 : 0.975V SEL[6:2] = 1100 : 1V SEL[6:2] = 1110 : 1.05V SEL[6:2] = 1111 : 1.075V SEL[6:2] = 10000 : 1.1V SEL[6:2] = 10001 : 1.125V SEL[6:2] = 10010 : 1.15V SEL[6:2] = 10011 : 1.175V SEL[6:2] = 10100 : 1.2V SEL[6:2] = 10101 : 1.225V SEL[6:2] = 10110 : 1.25V SEL[6:2] = 10111 : 1.275V SEL[6:2] = 11000 to 11111 : 1.3V VOUT = SEL[6:2] x 0.025V + 0.7V, from SEL[6:2] = 0 to 18 (hex) (After each UVLO rising, the voltage is set to the value by VSEL0/VSEL1 setting : VSEL0 = 0, VSEL1 = 0, VOUT = 1.0V VSEL0 = 0, VSEL1 = 1, VOUT = 1.0V VSEL0 = 1, VSEL1 = 0, VOUT = 1.2V VSEL0 = 1, VSEL1 = 1, VOUT = 1.2V) 1:0 Reserved Reserved bit Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 22 is a registered trademark of Richtek Technology Corporation. DS5045A-00 March 2015 RT5045A Table 11. CH5_CFG_REG Address : 0x09 Description : CH5 config register. Set CH5 current limited, VID change slew rate, PWM frequency. Bits Bit7 Name Reserved Reset Value 0 1 0 1 0 1 1 0 Read/Write R R/W R/W R/W R/W R/W R/W R/W Bits Name 7 Reserved 6:5 4:3 2:0 Bit6 Bit5 ILMAX Bit3 Bit1 Bit0 FREQ Description Reserved bit ILMAX ILMAX[6:5] = 00 : 1.5A ILMAX[6:5] = 01 : 2.0A ILMAX[6:5]= 10 : 2.5A (default) ILMAX[6:5] = 11 : 3A TSTEP TSTEP[4:3] = 00 : 20mV/s TSTEP[4:3] = 01 : 15mV/s TSTEP[4:3] = 10 : 10mV/s (default) TSTEP[4:3] = 11 : 5mV/s FREQ FREQ[2:0] = 000 to 011, 1MHz FREQ[2:0] = 100, 1.5MHz FREQ[2:0] = 101, 2.0MHz FREQ[2:0] = 110, 2.5MHz (default) FREQ[2:0] = 111, 3.0MHz March 2015 Bit2 TSTEP Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5045A-00 Bit4 is a registered trademark of Richtek Technology Corporation. www.richtek.com 23 RT5045A Table 12. CH5_SEL_REG Address : 0x0A Description : CH5 VID setting register. CH5 VID setting and power on/off status and control. Bits Bit7 Name Reserved Reset Value 0 0 0 0 0 0 0 0 Read/Write R R/W R/W R/W R/W R/W R/W R/W Bits Name 7 Reserved 6:2 SEL Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 SEL Bit0 Reserved Description Reserved bit Supply voltage, SEL[6:2] = 00000 : 0.7V SEL[6:2] = 1 : 0.725V SEL[6:2] = 10 : 0.75V SEL[6:2] = 11 : 0.775V SEL[6:2] = 100 : 0.8V SEL[6:2] = 101 : 0.825V SEL[6:2] = 110 : 0.85V SEL[6:2] = 111 : 0.875V SEL[6:2] = 1000 : 0.9V SEL[6:2] = 1001 : 0.925V SEL[6:2] = 1010 : 0.95V SEL[6:2] = 1011 : 0.975V SEL[6:2] = 1100 : 1V SEL[6:2] = 1110 : 1.05V SEL[6:2] = 1111 : 1.075V SEL[6:2] = 10000 : 1.1V SEL[6:2] = 10001 : 1.125V SEL[6:2] = 10010 : 1.15V SEL[6:2] = 10011 : 1.175V SEL[6:2] = 10100 : 1.2V SEL[6:2] = 10101 : 1.225V SEL[6:2] = 10110 : 1.25V SEL[6:2] = 10111 : 1.275V SEL[6:2] = 11000 to 11111 : 1.3V VOUT = SEL[6:2] x 0.025V + 0.7V, from SEL[6:2] = 0 to 18 (hex) (After each UVLO rising, the voltage is set to the value by VSEL0/VSEL1 setting : VSEL0 = 0, VSEL1 = 0, VOUT = 1.0V VSEL0 = 0, VSEL1 = 1, VOUT = 1.0V VSEL0 = 1, VSEL1 = 0, VOUT = 0.9V VSEL0 = 1, VSEL1 = 1, VOUT = 0.9V) 1:0 Reserved Reserved bit Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 24 is a registered trademark of Richtek Technology Corporation. DS5045A-00 March 2015 RT5045A Table 13. CH6_CFG_REG Address : 0x0B Description : CH6 config register. Set CH6 current limited, VID change slew rate, PWM frequency. Bits Bit7 Name Reserved Reset Value 0 1 0 1 0 1 1 0 Read/Write R R/W R/W R/W R/W R/W R/W R/W Bits Name 7 Reserved 6:5 4:3 2:0 Bit6 Bit5 ILMAX Bit3 Bit1 Bit0 FREQ Description Reserved bit ILMAX ILMAX[6:5] = 00 : 4A ILMAX[6:5] = 01 : 4.5A ILMAX[6:5] = 10 : 5A (default) ILMAX[6:5] = 11 : 5.5A TSTEP TSTEP[4:3] = 00 : 20mV/s TSTEP[4:3] = 01 : 15mV/s TSTEP[4:3] = 10 : 10mV/s (default) TSTEP[4:3]= 11 : 5mV/s FREQ FREQ[2:0] = 000 to 011, 1MHz FREQ[2:0] = 100, 1.5MHz FREQ[2:0] = 101, 2.0MHz FREQ[2:0] = 110, 2.5MHz (default) FREQ[2:0] = 111, 3.0MHz March 2015 Bit2 TSTEP Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5045A-00 Bit4 is a registered trademark of Richtek Technology Corporation. www.richtek.com 25 RT5045A Table 14. CH6_SEL_REG Address : 0x0C Description : CH6 VID setting register. CH5 VID setting and power on/off status and control. Bits Bit7 Name Reserved Reset Value 0 0 0 0 0 0 0 0 Read/Write R R/W R/W R/W R/W R/W R/W R/W Bits Name 7 Reserved 6:2 SEL Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 SEL Bit0 Reserved Description Reserved bit Supply voltage, SEL[6:2] = 00000 : 0.7V SEL[6:2] = 1 : 0.725V SEL[6:2] = 10 : 0.75V SEL[6:2] = 11 : 0.775V SEL[6:2] = 100 : 0.8V SEL[6:2] = 101 : 0.825V SEL[6:2] = 110 : 0.85V SEL[6:2] = 111 : 0.875V SEL[6:2] = 1000 : 0.9V SEL[6:2] = 1001 : 0.925V SEL[6:2] = 1010 : 0.95V SEL[6:2] = 1011 : 0.975V SEL[6:2] = 1100 : 1V SEL[6:2] = 1110 : 1.05V SEL[6:2] = 1111 : 1.075V SEL[6:2] = 10000 : 1.1V SEL[6:2] = 10001 : 1.125V SEL[6:2] = 10010 : 1.15V SEL[6:2] = 10011 : 1.175V SEL[6:2] = 10100 : 1.2V SEL[6:2] = 10101 : 1.225V SEL[6:2] = 10110 : 1.25V SEL[6:2] = 10111 : 1.275V SEL[6:2] = 11000 to 11111 : 1.3V VOUT = SEL[6:2] x 0.025V + 0.7V, from SEL[6:2] = 0 to 18 (hex) (After each UVLO rising, the voltage is set to the value by VSEL0/VSEL1 setting : VSEL0 = 0, VSEL1 = 0, VOUT = 1.0V VSEL0 = 0, VSEL1 = 1, VOUT = 1.0V VSEL0 = 1, VSEL1 = 0, VOUT = 0.9V VSEL0 = 1, VSEL1 = 1, VOUT = 0.9V) 1:0 Reserved Reserved bit Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 26 is a registered trademark of Richtek Technology Corporation. DS5045A-00 March 2015 RT5045A Table 15. LDO_SEL_REG Address : 0x0D Description : LDO VID setting register. LDO VID setting and power on/off status and control. Bits Bit7 Name Reserved Reset Value 0 0 0 0 0 0 0 0 Read/Write R R/W R/W R/W R/W R/W R/W R/W Bits Name 7 Reserved 6:2 SEL Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 SEL Bit0 Reserved Description Reserved bit Supply voltage. After each UVLO rising, the voltage is set to the value by VSEL0/VSEL1 setting : VSEL0 = 0, VSEL1 = 0, VOUT = 2.5V VSEL0 = 0, VSEL1 = 1, VOUT = 2.5V SEL[6:2] = 00000 to 00011 : 2.3V SEL[6:2] = 100 : 2.325V SEL[6:2] = 101 : 2.35V SEL[6:2] = 110 : 2.375V SEL[6:2] = 111 : 2.4V SEL[6:2] = 1000 : 2.425V SEL[6:2] = 1001 : 2.45V SEL[6:2] = 1010 : 2.475V SEL[6:2] = 1011 : 2.5V SEL[6:2] = 1100 : 2.525V SEL[6:2] = 1110 : 2.575V SEL[6:2] = 1111 : 2.6V SEL[6:2] = 10000 : 2.625V SEL[6:2] = 10001 : 2.65V SEL[6:2] = 10010 : 2.675V SEL[6:2] = 10011 : 2.7V SEL[6:2] = 10100 : 2.725V SEL[6:2] = 10101 : 2.75V SEL[6:2] = 10110 : 2.775V SEL[6:2] = 10111 : 2.8V SEL[6:2] = 11000 : 2.825V SEL[6:2] = 11001 : 2.85V SEL[6:2] = 11010 : 2.875V SEL[6:2] = 11011 : 2.9V SEL[6:2] = 11100 : 2.925V SEL[6:2] = 11101 : 2.95V SEL[6:2] = 11110 : 2.975V SEL[6:2] = 11111 : 3V VOUT = SEL[6:2] x 0.025V + 2.225V, from SEL[6:2] = 3 to 1F (hex) After each UVLO rising, the voltage is set to the value by VSEL0/VSEL1 setting : VSEL0 = 1, VSEL1 = 0, VOUT = 1.8V VSEL0 = 1, VSEL1 = 1, VOUT = 1.8V SEL[6:2] = 00000 to 00011 : 1.656V SEL[6:2] = 100 : 1.674V SEL[6:2] = 101 : 1.692V SEL[6:2] = 110 : 1.71V SEL[6:2] = 111 : 1.728V SEL[6:2] = 1000 : 1.746V SEL[6:2] = 1001 : 1.764V Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5045A-00 March 2015 is a registered trademark of Richtek Technology Corporation. www.richtek.com 27 RT5045A 6:2 SEL 1:0 Reserved SEL[6:2] = 1010 : 1.782V SEL[6:2] = 1011 : 1.8V SEL[6:2] = 1100 : 1.818V SEL[6:2] = 1101 : 1.836V SEL[6:2] = 1110 : 1.854V SEL[6:2] = 1111 : 1.872V SEL[6:2] = 10000 : 1.89V SEL[6:2] = 10001 : 1.908V SEL[6:2] = 10010 : 1.926V SEL[6:2] = 10011 : 1.944V SEL[6:2] = 10100 : 1.962V SEL[6:2] = 10101 : 1.98V SEL[6:2] = 10110 : 1.998V SEL[6:2] = 10111 : 2.016V SEL[6:2] = 11000 : 2.034V SEL[6:2] = 11001 : 2.052V SEL[6:2] = 11010 : 2.07V SEL[6:2] = 11011 : 2.088V SEL[6:2] = 11100 : 2.106V SEL[6:2] = 11101 : 2.124V SEL[6:2] = 11110 : 2.142V SEL[6:2] = 11111 : 2.16V Reserved bit Table 16. DCDCCTRL0_REG Address : 0x11 Description : DCDC high/low power mode control register. Bits Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Name CH1_ EN CH2_ EN CH3_ EN CH4_ EN CH5_ EN CH6_ EN LDO_ EN Reserved Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R Bits Name Description 7 CH1_ EN 0 : Disable 1 : Enable (After each UVLO rising, the value is set to 1) 6 CH2_ EN 0 : Disable 1 : Enable (After each UVLO rising, the value is set to 1) 5 CH3_ EN 0 : Disable 1 : Enable (After each UVLO rising, the value is set to 1) 4 CH4_ EN 0 : Disable 1 : Enable (After each UVLO rising, the value is set to 1) 3 CH5_ EN 0 : Disable 1 : Enable (After each UVLO rising, the value is set to 1) 2 CH6_ EN 0 : Disable 1 : Enable (After each UVLO rising, the value is set to 1) 1 LDO_ EN 0 : Disable 1 : Enable (After each UVLO rising, the value is set to 1) 0 Reserved Reserved bit Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 28 is a registered trademark of Richtek Technology Corporation. DS5045A-00 March 2015 RT5045A Table 17. SLEEP_REG Address : 0x12 Description : Sleep mode control register. Bits Bit6 CH2_ ALIVE 0 Bit5 CH3_ ALIVE 0 Bit4 CH4_ ALIVE 0 Bit3 CH5_ ALIVE 0 Bit2 CH6_ ALIVE 0 Bit1 LDO_ ALIVE 0 SLEEP Reset Value Bit7 CH1_ ALIVE 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Name Bits Name 7 CH1_ ALIVE 0 : When Sleep bit = 1 , CH1 turn off 1 : When Sleep bit = 1, CH1 alive and enter low power mode 6 CH2_ ALIVE 0 : When Sleep bit = 1 , CH2 turn off 1 : When Sleep bit = 1, CH2 alive and enter low power mode 5 CH3_ ALIVE 0 : When Sleep bit = 1 , CH3 turn off 1 : When Sleep bit = 1, CH3 alive and enter low power mode 4 CH4_ ALIVE 0 : When Sleep bit = 1 , CH4 turn off 1 : When Sleep bit = 1, CH4 alive and enter low power mode 3 CH5_ ALIVE 0 : When Sleep bit = 1 , CH5 turn off 1 : When Sleep bit = 1, CH5 alive and enter low power mode 2 CH6_ ALIVE 0 : When Sleep bit = 1 , CH6 turn off 1 : When Sleep bit = 1, CH6 alive and enter low power mode 1 LDO_ ALIVE 0 : When Sleep bit = 1 , LDO turn off 1 : When Sleep bit = 1, LDO alive and enter low power mode 0 SLEEP March 2015 0 Description 0 : Exit sleep mode 1 : Enter sleep mode Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5045A-00 Bit0 is a registered trademark of Richtek Technology Corporation. www.richtek.com 29 RT5045A Table 18. DCDCCTRL1_REG Address : 0x13 Description : DCDC PSKIP/PWM mode control register. Bits Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Name CH1_ PWM CH2_ PWM CH3_ PWM CH4_ PWM CH5_ PWM CH6_ PWM Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R R Bits Name Bit1 Bit0 Reserved Description 7 CH1_PWM CH1_PWM[7] = 0 : PSKIP mode. CH1_PWM[7] = 1 : Forced PWM mode 6 CH2_ PWM CH2_PWM[6] = 0 : PSKIP mode. CH2_PWM[6] = 1 : Forced PWM mode 5 CH3_ PWM CH3_PWM[5] = 0 : PSKIP mode. CH3_PWM[5] = 1 : Forced PWM mode 4 CH4_ PWM CH4_PWM[4] = 0 : PSKIP mode. CH4_PWM[4] = 1 : Forced PWM mode 3 CH5_ PWM CH5_PWM[3] = 0 : PSKIP mode. CH5_PWM[3] = 1 : Forced PWM mode 2 CH6_ PWM CH6_PWM[2] = 0 : PSKIP mode. CH6_PWM[2] = 1 : Forced PWM mode 1:0 Reserved Reserved bit Table 19. DISCHARGE_REG Address : 0x14 Description : Discharge enable register. Bits Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Name CH1_DIS CH2_DIS CH3_DIS CH4_DIS CH5_DIS CH6_DIS LDO_DIS Reserved Reset Value 1 1 1 1 1 1 1 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R Bits Name Description 7 CH1_DIS CH1_DIS[7] = 0 : discharge path disable CH1_DIS[7] = 1 : discharge path enable 6 CH2_DIS CH2_DIS[6] = 0 : discharge path disable CH2_DIS[6] = 1 : discharge path enable 5 CH3_DIS CH3_DIS[5] = 0 : discharge path disable CH3_DIS[5] = 1 : discharge path enable 4 CH4_DIS CH4_DIS[4] = 0 : discharge path disable CH4_DIS[4] = 1 : discharge path enable 3 CH5_DIS CH5_DIS[3] = 0 : discharge path disable CH5_DIS[3] = 1 : discharge path enable 2 CH6_DIS CH6_DIS[2] = 0 : discharge path disable CH6_DIS[2] = 1 : discharge path enable 1 LDO_DIS LDO_DIS[1] = 0 : discharge path disable LDO_DIS[1] = 1 : discharge path enable 0 Reserved Reserved bit Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 30 is a registered trademark of Richtek Technology Corporation. DS5045A-00 March 2015 RT5045A Table 20. POR_OPTION_REG Address : 0x17 Description : POR_OPTION select register. Bits Bit7 Bit6 Bit5 Name Bit4 Bit3 Bit2 Reserved Bit1 Bit0 POR_OPTION_SEL Reset Value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R/W R/W Bits Name 7:2 Reserved 0:1 POR_OPTION_ SEL Description Reserved bit Supply state POR_OPTION_SEL[1:0] = 00, depended on AVDD POR rising with delay time POR_OPTION_SEL[1:0] = 01, reserved. POR_OPTION_SEL[1:0] = 10, POR_OPTION = 0 POR_OPTION_SEL[1:0] = 11, POR_OPTION = 1 Table 21. DCDCTRL2_REG Address : 0x18 Description : DCDC high/low power mode control register. Bits Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Name CH1_ LPM CH2_ LPM CH3_ LPM CH4_ LPM CH5_ LPM CH6_ LPM LDO_ LPM Reserved Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R Bits Name Description 7 CH1_LPM CH1_LPM[7] = 0 : active high power mode. CH1_LPM[7] = 1 : active low power mode. 6 CH2_LPM CH2_LPM[6] = 0 : active high power mode. CH2_LPM[6] = 1 : active low power mode. 5 CH3_LPM CH3_LPM[5] = 0 : active high power mode. CH3_LPM[5] = 1 : active low power mode. 4 CH4_LPM CH4_LPM[4] = 0 : active high power mode. CH4_LPM[4] = 1 : active low power mode. 3 CH5_LPM CH5_LPM[3] = 0 : active high power mode. CH5_LPM[3] = 1 : active low power mode. 2 CH6_LPM CH6_LPM[2] = 0 : active high power mode. CH6_LPM[2] = 1 : active low power mode. 1 LDO_LPM LDO_LPM[1] = 0 : active high power mode. LDO_LPM[1] = 1 : active low power mode. 0 Reserved Reserved bit Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5045A-00 March 2015 is a registered trademark of Richtek Technology Corporation. www.richtek.com 31 RT5045A Table 22. Ch1/Ch2_Wake-up_time Address : 0x19 Description :. Ch1/Ch2_Wake-up_time Bit Bit7 Name Bit6 Bit5 Bit4 Bit3 Ch1_Wake-up_time Bit2 Bit1 Bit0 Ch2_Wake-up_time Reset Value 0 0 0 0 0 0 0 0 Read/Write RW RW RW RW RW RW RW RW Bits 7:4 3:0 Name Description Ch1_Wake-up_time CH1 sleep wake-up sequence Disable = 0000 Time slot1 = 0001 Time slot2 = 0010 Time slot3 = 0011 Time slot4 = 0100 Time slot5 = 0101 Time slot6 = 0110 Time slot7 = 0111 Time slot8 = 1000 Time slot9 = 1001 Time slot10 = 1010 Time slot11 = 1011 Time slot12 = 1100 Time slot13 = 1101 Time slot14 = 1110 Time slot15 = 1111 Time slot time = 512s Ch2_Wake-up_time CH2 sleep wake-up sequence Disable = 0000 Time slot1 = 0001 Time slot2 = 0010 Time slot3 = 0011 Time slot4 = 0100 Time slot5 = 0101 Time slot6 = 0110 Time slot7 = 0111 Time slot8 = 1000 Time slot9 = 1001 Time slot10 = 1010 Time slot11 = 1011 Time slot12 = 1100 Time slot13 = 1101 Time slot14 = 1110 Time slot15 = 1111 Time slot time = 512s Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 32 is a registered trademark of Richtek Technology Corporation. DS5045A-00 March 2015 RT5045A Table 23. Ch3/Ch4_Wake-up_time Address : 0x1A Description :. Ch3/Ch4_Wake-up_time Bit Bit7 Bit6 Name Bit5 Bit4 Bit3 Ch3_Wake-up_time Bit2 Bit1 Bit0 Ch4_Wake-up_time Reset Value 0 0 0 0 0 0 0 0 Read/Write RW RW RW RW RW RW RW RW Bits 7:4 3:0 Name Description Ch3_Wake-up_time CH3 sleep wake-up sequence Disable = 0000 Time slot1 = 0001 Time slot2 = 0010 Time slot3 = 0011 Time slot4 = 0100 Time slot5 = 0101 Time slot6 = 0110 Time slot7 = 0111 Time slot8 = 1000 Time slot9 = 1001 Time slot10 = 1010 Time slot11 = 1011 Time slot12 = 1100 Time slot13 = 1101 Time slot14 = 1110 Time slot15 = 1111 Time slot time = 512s Ch4_Wake-up_time CH4 sleep wake-up sequence Disable = 0000 Time slot1 = 0001 Time slot2 = 0010 Time slot3 = 0011 Time slot4 = 0100 Time slot5 = 0101 Time slot6 = 0110 Time slot7 = 0111 Time slot8 = 1000 Time slot9 = 1001 Time slot10 = 1010 Time slot11 = 1011 Time slot12 = 1100 Time slot13 = 1101 Time slot14 = 1110 Time slot15 = 1111 Time slot time = 512s Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5045A-00 March 2015 is a registered trademark of Richtek Technology Corporation. www.richtek.com 33 RT5045A Table 24. Ch5/Ch6_Wake-up_time Address : 0x1b Description :. Ch5/Ch6_Wake-up_time Bit Bit7 Name Bit6 Bit5 Bit4 Bit3 Ch5_Wake-up_time Bit2 Bit1 Bit0 Ch6_Wake-up_time Reset Value 0 0 0 0 0 0 0 0 Read/Write RW RW RW RW RW RW RW RW Bits 7:4 3:0 Name Description Ch5_Wake-up_time CH5 sleep wake-up sequence Disable = 0000 Time slot1 = 0001 Time slot2 = 0010 Time slot3 = 0011 Time slot4 = 0100 Time slot5 = 0101 Time slot6 = 0110 Time slot7 = 0111 Time slot8 = 1000 Time slot9 = 1001 Time slot10 = 1010 Time slot11 = 1011 Time slot12 = 1100 Time slot13 = 1101 Time slot14 = 1110 Time slot15 = 1111 Time slot time = 512s Ch6_Wake-up_time CH6 sleep wake-up sequence Disable = 0000 Time slot1 = 0001 Time slot2 = 0010 Time slot3 = 0011 Time slot4 = 0100 Time slot5 = 0101 Time slot6 = 0110 Time slot7 = 0111 Time slot8 = 1000 Time slot9 = 1001 Time slot10 = 1010 Time slot11 = 1011 Time slot12 = 1100 Time slot13 = 1101 Time slot14 = 1110 Time slot15 = 1111 Time slot time = 512s Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 34 is a registered trademark of Richtek Technology Corporation. DS5045A-00 March 2015 RT5045A Table 25. LDO Wake-up_time Address : 0x1C Description :LDO_Wake-up_time Bit Bit7 Bit6 Name Bit5 Bit4 Bit3 Bit2 LDO_Wake-up_time Bit1 Bit0 Reserved Reset Value 0 0 0 0 0 0 0 0 Read/Write RW RW RW RW R R R R Bit2 Bit1 Bit0 R R R Bits Name Description 7:4 LDO_Wake-up_time 3:0 Reserved LDO sleep wake-up sequence Disable = 0000 Time slot1 = 0001 Time slot2 = 0010 Time slot3 = 0011 Time slot4 = 0100 Time slot5 = 0101 Time slot6 = 0110 Time slot7 = 0111 Time slot8 = 1000 Time slot9 = 1001 Time slot10 = 1010 Time slot11 = 1011 Time slot12 = 1100 Time slot13 = 1101 Time slot14 = 1110 Time slot15 = 1111 Time slot time = 512s Reserved bits Table 26. PRODUCT_ID_REG Address : 0x20 Description : Product ID number register. Bits Bit7 Bit6 Bit5 Bit4 Bit3 Name PRODUCT_ID Reset Value 0x01 Read/Write R Bits Name 7:0 PRODUCT_ID R R March 2015 R Description Return the product ID number : 0x01 Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5045A-00 R is a registered trademark of Richtek Technology Corporation. www.richtek.com 35 RT5045A Table 27. MANUFACTURER_ID_REG Address : 0x21 Description : Manufacturer ID number register. Bits Bit7 Bit6 Bit5 Bit4 Bit3 Name MANUFACTURER_ID Reset Value 0x01 Read/Write R R Bits Name 7:0 MANUFACTURER_ID R R R Bit2 Bit1 Bit0 R R R Bit2 Bit1 Bit0 Description Return the manufacturer ID number : 0x01 Table 28. REVISION_NUMBER_REG Address : 0x22 Description : Revision number register. Bits Bit7 Bit6 Bit5 Name Bit4 Bit3 REVISION_NUMBER Reset Value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R Bits Name 7:0 REVISION_NUMBER Description Return the revision number : 0x00 Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 36 is a registered trademark of Richtek Technology Corporation. DS5045A-00 March 2015 RT5045A Typical Operating Characteristics CH1 Efficiency vs. Output Current CH2 Efficiency vs. OutputCurrent 100 100 98 95 94 Efficiency (%) Efficiency (%) 96 92 90 VIN = 3.3V 88 VIN = 5V 86 84 90 85 VIN = 3.3V VIN = 5V 80 75 82 VOUT = 2.5V VOUT = 1.35V 80 70 0.5 1 1.5 2 2.5 3 3.5 4 0.5 0.6 Output Current (A) 0.7 0.8 0.9 1 Output Current (A) CH3 Efficiency vs. Output Current CH4 Efficiency vs. Load Current 100 100 98 95 94 Efficiency (%) Efficiency (%) 96 92 90 VIN = 3.3V 88 VIN = 5V 86 84 90 85 VIN = 3.3V 80 VIN = 5V 75 82 VOUT = 1.8V VOUT = 1V 80 70 0.5 0.6 0.7 0.8 0.9 1 0.5 0.75 Output Current (A) CH5 Efficiency vs. Output Current 1.5 1.75 2 CH6 Efficiency vs. Output Current 100 95 95 90 90 Efficiency (%) Efficiency (%) 1.25 Load Current (A) 100 85 VIN = 3.3V 80 1 VIN = 5V 75 85 VIN = 3.3V 80 VIN = 5V 75 VOUT = 1V VOUT = 1V 70 70 0.5 0.6 0.7 0.8 0.9 Output Current (A) Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5045A-00 March 2015 1 0.5 1 1.5 2 2.5 3 3.5 Output Current (A) is a registered trademark of Richtek Technology Corporation. www.richtek.com 37 RT5045A CH2 Output Voltage vs. Output Current 1.40 2.54 1.39 2.53 1.38 Output Voltage (V) Output Voltage (V) CH1 Output Voltage vs. Output Current 2.55 2.52 2.51 2.50 VIN = 3.3V 2.49 VIN = 5V 2.48 2.47 1.37 1.36 1.35 1.34 VIN = 3.3V 1.33 VIN = 5V 1.32 2.46 1.31 VOUT = 2.5V 2.45 0 0.5 1 1.5 2 2.5 3 3.5 VOUT = 1.35V 1.30 4 0 0.2 0.4 Output Current (A) 1.84 1.04 1.83 1.03 1.82 1.81 1.80 1.79 1.78 VIN = 5V 1.77 1 1.02 1.01 1.00 0.99 VIN = 3.3V 0.98 VIN = 5V 0.97 1.76 0.96 VOUT = 1.8V 1.75 0 0.2 0.4 0.6 0.8 VOUT = 1V 0.95 1 0 0.25 0.5 Output Current (A) 1.04 1.04 1.03 1.03 Output Voltage (V) 1.05 1.02 1.01 1.00 0.99 0.98 VIN = 5V 1 1.25 1.5 1.75 2 CH6 Output Voltage vs. Output Current 1.05 VIN = 3.3V 0.75 Output Current (A) CH5 Output Voltage vs. Output Current Output Voltage (V) 0.8 CH4 Output Voltage vs. Output Current 1.05 Output Voltage (V) Output Voltage (V) CH3 Output Voltage vs. Output Current 1.85 VIN = 3.3V 0.6 Output Current (A) 0.97 1.02 1.01 1.00 0.99 VIN = 3.3V 0.98 VIN = 5V 0.97 0.96 0.96 VOUT = 1V 0.95 VOUT = 1V 0.95 0 0.2 0.4 0.6 0.8 Output Current (A) Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 38 1 0 0.5 1 1.5 2 2.5 3 3.5 4 Output Current (A) is a registered trademark of Richtek Technology Corporation. DS5045A-00 March 2015 RT5045A CH2 Output Voltage vs. Input Voltage 1.40 2.54 1.39 2.53 1.38 Output Voltage (V) Output Voltage (V) CH1 Output Voltage vs. Input Voltage 2.55 2.52 2.51 2.50 IOUT = 1A 2.49 IOUT = 2A 2.48 IOUT = 4A 2.47 1.37 1.36 1.35 1.34 IOUT = 0.5A 1.33 IOUT = 1A 1.32 2.46 1.31 VOUT = 2.5V 2.45 VOUT = 1.35V 1.30 3 3.5 4 4.5 5 5.5 3 3.5 4 Input Voltage (V) CH3 Output Voltage vs. Input Voltage 5 5.5 CH4 Output Voltage vs. Input Voltage 1.85 1.05 1.84 1.04 1.83 1.03 Output Voltage (V) Output Voltage (V) 4.5 Input Voltage (V) 1.82 1.81 1.80 1.79 IOUT = 0.5A 1.78 IOUT = 1A 1.77 1.02 1.01 1.00 0.99 IOUT = 2A 0.98 IOUT = 1A 0.97 1.76 0.96 VOUT = 1.8V 1.75 2.5 3 3.5 4 4.5 5 VOUT = 1V 0.95 5.5 3 3.5 4 4.5 5 5.5 Input Voltage (V) Input Voltage (V) CH5 Output Voltage vs. Input Voltage CH6 Output Voltage vs. Input Voltage 1.05 1.010 1.04 1.008 Output Voltage (V) Output Voltage (V) 1.03 1.02 1.01 1.00 0.99 IOUT = 0.5A 0.98 IOUT = 1A IOUT = 0.25A 0.97 1.005 1.003 1.000 IOUT = 2A 0.998 IOUT = 1A 0.995 0.993 0.96 VOUT = 1V VOUT = 1V 0.95 0.990 2.5 3 3.5 4 4.5 5 Input Voltage (V) Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5045A-00 March 2015 5.5 2.5 3 3.5 4 4.5 5 5.5 Input Voltage (V) is a registered trademark of Richtek Technology Corporation. www.richtek.com 39 RT5045A CH1 Load Transient Response CH2 Load Transient Response VOUT (10mV/Div) VOUT (50mV/Div) IOUT (500mA/Div) IOUT (1A/Div) VIN = 3.3V, VOUT = 2.5V, IOUT = 2A to 4A VIN = 3.3V, VOUT = 1.35V, IOUT = 0.5A to 1A Time (100s/Div) Time (200s/Div) CH3 Load Transient Response CH4 Load Transient Response VOUT (20mV/Div) VOUT (20mV/Div) IOUT (500mA/Div) IOUT (1A/Div) VIN = 3.3V, VOUT = 1V, IOUT = 1A to 2A VIN = 3.3V, VOUT = 1.8V, IOUT = 0.5A to 1A Time (200s/Div) Time (200s/Div) CH5 Load Transient Response CH6 Load Transient Response VOUT (20mV/Div) VOUT (20mV/Div) IOUT (500mA/Div) VIN = 3.3V, VOUT = 1V, IOUT = 0.5A to 1A Time (200s/Div) Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 40 IOUT (2A/Div) VIN = 3.3V, VOUT = 1V, IOUT = 1.5A to 3.5A Time (400s/Div) is a registered trademark of Richtek Technology Corporation. DS5045A-00 March 2015 RT5045A CH1 Output Voltage vs. Temperature CH2 Output Voltage vs. Temperature 1.40 2.54 1.39 1.38 Output Voltage (V) Output Voltage (V) 2.53 2.52 VIN = 3.3V 2.51 VIN = 3V 2.50 1.37 1.36 1.35 VIN = 3.3V 1.34 VIN = 2.9V 1.33 1.32 2.49 1.31 VOUT = 2.5V, IOUT = 0A VOUT = 1.35V, IOUT = 0A 1.30 2.48 -50 -25 0 25 50 75 100 -50 125 -25 0 Temperature (°C) 1.84 1.025 1.83 1.020 1.82 VIN = 3.3V VIN = 2.9V 1.80 1.79 1.78 75 100 125 1.015 1.010 VIN = 3.3V 1.005 VIN = 2.9V 1.000 0.995 VOUT = 1.8V, IOUT = 0A VOUT = 1V, IOUT = 0A 1.77 0.990 -50 -25 0 25 50 75 100 125 -50 -25 0 Temperature (°C) 50 75 100 125 CH6 Output Voltage vs. Temperature 1.030 1.025 1.025 1.020 1.020 Output Voltage (V) 1.030 1.015 1.010 1.005 VIN = 3.3V 1.000 25 Temperature (°C) CH5 Output Voltage vs. Temperature Output Voltage (V) 50 CH4 Output Voltage vs. Temperature 1.030 Output Voltage (V) Output Voltage (V) CH3 Output Voltage vs. Temperature 1.85 1.81 25 Temperature (°C) VIN = 2.9V 0.995 1.015 1.010 1.005 VIN = 3.3V 1.000 VIN = 2.9V 0.995 VOUT = 1V, IOUT = 0A VOUT = 1V, IOUT = 0A 0.990 0.990 -50 -25 0 25 50 75 100 Temperature (°C) Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5045A-00 March 2015 125 -50 -25 0 25 50 75 100 125 Temperature (°C) is a registered trademark of Richtek Technology Corporation. www.richtek.com 41 RT5045A Application Information The RT5045A provides six synchronous Buck regulators and one LDO to satisfy the entire power system of SSD. This device can communicate with processors through I2C interface for programming the voltage, monitoring the status, or in/out the power saving mode. Table 29 lists the power rails provided by the RT5045A. Table 29. Detail of Power Rails Resource Name Type Voltage Range Current Rating CH1 Buck Converter 2.3V – 3.0V, 25mV step 4000mA CH2 Buck Converter 0.9V – 1.6V, 25mV step 1000mA CH3 Buck Converter 1.5V – 2.1V, 25mV step 1000mA CH4 Buck Converter 0.7V – 1.3V, 25mV step 2000mA CH5 Buck Converter 0.7V – 1.3V, 25mV step 1000mA CH6 Buck Converter 0.7V – 1.3V, 25mV step 3500mA LDO LDO 2.3V – 3.0V, 25mV step 1.656V-2.16V,18mV step 200mA Buck Converter The RT5045A incorporates six high-efficiency synchronous switching Buck converters that deliver various voltages. CH1 features peak current mode architecture of Buck converter. For preventing the unstable when duty > 50% traditionally, it adds external ramp and compensation to reduce duty cycle perturbation and stabilize the current loop. CH1 can operate up to 100% duty to let the lowest input voltage still maintain the regulator work. And the output voltage will be the lowest input voltage decreases dropout voltage on the resistance of current path. Unlike CH1, the control scheme of other buck converters are constant-on-time current mode for low output voltage, quick transient response. Every switching regulator is specially designed for very low quiescent (<20A), high-efficiency operation throughout the load range. With high switching frequency (1M to 3MHz), the external LC filter can be small and keeps very low output voltage ripple. Additional features include soft-start, discharged, input UVLO protection, under-voltage protection, over voltage protection, over current protection and over thermal protection. Please note that the IC will latched when one power rail occurs under voltage protection. The other protections just make the rail output voltage Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 42 drop and recovery when the faults disabled. With I2C interface, every Buck converter can program output voltage, adjust VID slew rate, change the PWM frequency, and control the on/off state. Even PWM can switch to forced PWM mode, PSKIP mode or LPM mode (quiescent < 10A). Please see the back register tables for detail control. Inductor Selection For given input voltage (VIN), output voltage (VOUT), and operation frequency (FSW ), the inductor value (L) determines the inductor ripple current (IL) as shown in equation below : IL VOUT VIN VOUT FSW L VIN Having a lower ripple current reduces not only the ESR losses in the output capacitors, but also the output voltage ripple. A reasonable starting point for selecting the ripple current is IL = 0.3×IMAX to 0.4×IMAX. The largest ripple current occurs at the highest VIN. To guarantee that the ripple current stays below a specified maximum, the inductor value should be chosen according to the following equation : is a registered trademark of Richtek Technology Corporation. DS5045A-00 March 2015 RT5045A VOUT VINMAX VOUT L= FSW IL VINMAX CIN and CSYS Selection The input capacitance of every rail, CIN, needs to filter the trapezoidal current at the source of the high-side The current rating of the inductor must be large enough and will not saturate at the peak inductor current (IPEAK) : IPEAK IOUTMAX IL 2 MOSFET. To prevent large ripple voltage, a low ESR input capacitor for the maximum current should be used. The relation between CIN ripple voltage and current ripple is shown as the Figure 1. dV = D × IOUT × dt / CIN VPP CIN Ripple Voltage V = D × IOUT × ESR D × IOUT CIN Ripple Current - (1-D) × IOUT TON TOFF D = 0.5 Figure 1. Relationship of CIN Voltage Ripple and Current Ripple The CIN voltage ripple can use below equations to determine when FSW works at CCM mode. Next, it needs to consider the input bulk capacitance, CSYS, to ensure a stable input voltage during large load 1 D VCIN_PP D IOUTMAX ESR+ C IN FSW transient. The input host supply can not typically provide the enough input current for the converter to respond to Where D = VOUT / VIN. If use MLCC as the input current, the ESR is almost equal to zero. And the minimum input capacitance requirement could be estimate as below : CINMIN IOUTMAX a fast transient current. The input bulk capacitor will provide the energy necessary to source current until the host supply fill the demand, as shown as Figure 2. D 1 D VCIN_PPMAX FSW I Total input responded transient required Charge required from bulk capacitor ΔIINtr Input supply current tr t Figure 2. Charge Required from Input Bulk Capacitor During Transient. Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5045A-00 March 2015 is a registered trademark of Richtek Technology Corporation. www.richtek.com 43 RT5045A Figure 3 shows the diagram of every power rail of RT5045A sharing a single bank of bulk input capacitors. It can calculate the input required transient current using following equation : IINtr 6 VOUTn IOUTnMAX VIN ηn n=1 Where IINtr is the total input transient current required. IOUT is the maximum output transient current. η is the efficiency of the Buck at IOUT(MAX). LIN VIN CIN1 CSYS CIN2 CH2 ... ... CIN6 CH1 CH6 Figure 3. The Location of Bulk Input Capacitance Diagram When IINtr is confirmed, the input bulk capacitance, CSYS, can be decided with following estimating equation: CSYSMIN 1.21 IINtr 2 LIN VINPPMAX 2 Another parameter that has influence on the output voltage sag is the equivalent series inductance (ESL). The rapid change in load current results in di/dt during transient. Therefore, the ESL contributes to part of the voltage sag. Using a capacitor with low ESL can obtain better transient performance. Generally, using several capacitors connected in parallel can have better transient performance than using a single capacitor for the same total ESR. Unlike the electrolytic capacitor, the ceramic capacitor has relatively low ESR and can reduce the voltage deviation during load transient. However, the ceramic capacitor can only provide low capacitance value. Therefore, use a mixed combination of electrolytic capacitor and ceramic capacitor to obtain better transient performance. VSEL0, VSEL1 The RT5045A applies four set default output voltages for all power rails when the device starts a power up sequence. The detail of the initial output voltages shows in Table 30 lists the power rails provide by the RT5045A. Table 30 VSEL0 0 0 1 1 VSEL1 0 1 0 1 CH1 2.5V 2.5V 2.5V 2.5V CH2 1.35V 1.35V 1.35V 1.2V COUT selection CH3 1.8V 1.8V 1.8V 1.8V The output capacitor and the inductor form a low pass CH4 1.0V 1.0V 1.2V 1.2V filter in the buck topology. In steady state condition, the ripple current flowing into/out of the capacitor results in CH5 1.0V 1.0V 0.9V 0.9V CH6 1.0V 1.0V 0.9V 0.9V LDO POR delay time 2.5V 2.5V 1.8V 1.8V 10ms 10ms 6ms 6ms where VINPP(MAX) is the maximum ac voltage allowable. LIN is the input series filter inductance, if not used, put a reasonable value 50nH due to PCB layout. ripple voltage. The output voltage ripple (VOUTPP) can be calculated by the following equation: 1 VOUTPP IL ESR 8 COUT FSW When load transient occurs, the output capacitor supplies the load current before the controller can respond. Therefore, the ESR will dominate the output voltage sag during load transient. The output voltage under-shoot (VSAG) can be calculated by the following equation : VSAG ILOAD ESR For a given output voltage sag specification, the ESR value can be determined. Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 44 PORSEL PORSEL is a logic pin to select the threshold voltage of AVDD to raise POR signal. If AVDD voltage is over the threshold voltage, the device starts a POR rising function. When set PORSEL = 1, the threshold voltage of AVDD is 3.8V, else the threshold voltage is 2.8V. POR_OPTION Please refer to the following table to realize the POR_OPTION setting. is a registered trademark of Richtek Technology Corporation. DS5045A-00 March 2015 RT5045A Table 31. POR_OPTION Value Setting Condition POR_OPTION_REG POR_OPTION_SEL [0:1] POR POR pin is a signal to inform the system that the power up sequence of the RT5045A is completed. At Description 0x00 POR_OPTION = 0 0x01 Reversed. 0x02 POR_OPTION = 0 0x03 POR_OPTION = 1 POR_OPTION = 0 situation. If AVDD voltage is less than 100mV than VPORTH, the POR falls right away. When the device gets POR_OPTION = 1, POR will fall after SLEEP[0] = 0 turns to SLEEP[0] = 1, and POR comes after SLEEP [0] = 1 turn to SLEEP[0] = 0 with a 8ms delay. I2C Interface The RT5045A I2C slave address = 0x1b (hex). I2C interface supports standard slave mode (100kbps), and fast mode (400kbps). The write or read bit stream (N 1) is shown below : Read N bytes from RT5045A Slave Address Register Address S 0 A Slave Address MSB A Sr 1 MSB Data 2 Data for Address = m LSB MSB Data N LSB A A Register Address S 0 A R/W MSB Data 1 LSB A Assume Address = m P Data for Address = m + N - 1 Data for Address = m + 1 Write N bytes to RT5045A Slave Address LSB A Assume Address = m R/W Data 1 A MSB Data 2 LSB A Data for Address = m MSB A Data for Address = m + 1 Data N LSB A P Data for Address = m + N - 1 Driven by Master, Driven by Slave (RT5045A), P Stop, S Start, Sr Repeat Start SDA tLOW tF tSU,DAT tR tF tHD,STA tSP tR tBUF SCL tHD,STA S tHD,DAT tHIGH tSU,STA tSU,STO Sr P S Figure 4. I2C Read and Write Stream and Timing Diagram Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5045A-00 March 2015 is a registered trademark of Richtek Technology Corporation. www.richtek.com 45 RT5045A After the not-acknowledge bit ( A ), and the SCLH line has been pulled-up to a HIGH level, the active master switches to Hs-mode and enables (at time tH, see Serial Data Transfer Format in Hs-Mode Serial data transfer format in Hs-mode meets the Standard-mode I2C-bus specification. Hs-mode can Figure 6) the current-source pull-up circuit for the SCLH signal. As other devices can delay the serial transfer before tH by stretching the LOW period of the SCLH signal, the active master will enable its current-source pull-up circuit when all devices have released the SCLH line and the SCLH signal has reached a HIGH level, thus speeding up the last part of the rise time of the SCLH signal. only commence after the following conditions (all of which are in F/S-mode) : START condition (S) 8-bit master code (00001xxx) not-acknowledge bit ( A ) Figures 5 and Figure 6 show this in more detail. This master The active master then sends a repeated START condition (Sr) followed by a 7-bit slave address (or 10- code has two main functions: It allows arbitration and synchronization between bit slave address, see Section 14) with a R/W bit address, and receives an acknowledge bit ( A ) from the selected slave. competing masters at F/S-mode speeds, resulting in one winning master. It indicates the beginning of an Hs-mode transfer. After a repeated START condition and after each acknowledge bit ( A ) or not-acknowledge bit ( A ), the active master disables its current-source pull-up circuit. Hs-mode master codes are reserved 8-bit codes, which are not used for slave addressing or other purposes. Furthermore, as each master has its own unique master code, up to eight Hs-mode masters can be present on the one I2C-bus system (although master code 0000 1000 should be reserved for test and diagnostic purposes). The master code for an Hs-mode master This enables other devices to delay the serial transfer by stretching the LOW period of the SCLH signal. The active master re-enables its current-source pull-up circuit again. device is software programmable and is chosen by the System Designer. When all devices have released and the SCLH signal reaches a HIGH level, and so speeds up the last part of the SCLH signal’s rise time. Arbitration and clock synchronization only take place during the transmission of the master code and notacknowledge bit ( A ), after which one winning master remains active. The master code indicates to other Data transfer continues in Hs-mode after the next repeated START (Sr), and only switches back to F/Smode after a STOP condition (P). To reduce the overhead of the master code, it’s possible that a master links a number of Hs-mode transfers, separated by repeated START conditions (Sr). devices that an Hs-mode transfer is to begin and the connected devices must meet the Hs-mode specification. As no device is allowed to acknowledge the master code, the master code is followed by a notacknowledge ( A ). F/S-Mode Hs-Mode (current-source for SCLH enabled F/S-Mode A/A S Master Code A Sr Slave ADD. A R/W Data N bytes + ack. P Hs-Mode Continues Sr Slave ADD. Figure 5. Data Transfer Format in Hs-mode Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 46 is a registered trademark of Richtek Technology Corporation. DS5045A-00 March 2015 RT5045A 8-bit Master code 00001xxx t1 A tH S SDAH 1 SCLH 2 to 5 6 7 8 9 F/S-Mode 7-bit SLA R/W A 8 9 N x (8-bit data + A/A Sr P Sr SDAH SCLH 1 2 to 5 6 7 1 2 to 5 6 7 8 9 If P then F/S mode Hs-Mode If Sr (dotted lines) then Hs-mode tH tFS = MCS current source pull-up = Rp resistor pull-up Figure 6. A Complete Hs-mode Transfer Power On/Off Sequence The RT5045A starts a power up sequence when AVDD > UVLO rising threshold voltage, and the device shuts down with AVDD < UVLO falling threshold voltage. The RT5045A applies sleep mode of PMIC to save power consumption with setting the SLEEP bit of SLEEP_REG to 1. If the device goes to sleep mode, power rails are set to LPM and the alive rails depend on sleep mode control register setting. The power rails will exit from LPM to normal mode and wake up with a sequence as the same as the power-up-sequence when SLEEP bit = 0. The relations of all power rails of RT5045A and sleep off / wake up sequence with different POR_OPTION on VIN = 3.3V are shown as following Figure 7. The relations of all power rails of RT5045A and sleep off / wake up sequence with different POR_OPTION on VIN = 5V are shown as following Figure 8. Enter Sleep Exit Sleep 5V 5V AVDD 3.8V 150us 3.7V CH5 CH4 CH6 CH2 LDO CH3 CH1 POR (POR_OPTION=0) Tdelay POR (POR_OPTION=1) Time Slot 1 Time Slot 2 Time Slot 3 Time Slot 4 Time Slot 5 Time Slot 6 Time Slot 7 Tdelay Time Slot 8 Time Slot 15 Time Slot 1 VSEL0 = 0, Tdelay = 10ms VSEL0 = 1, Tdelay = 6ms Time Slot 2 Time Slot 3 Time Slot 4 Time Slot 5 Time Slot 6 Time Slot 7 Time Slot 8 Time Slot 15 Figure 7. For example : Power On/Off Sequence and Sleep Off / Wake up Sequence with Different POR_OPTION on VIN = 5V Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5045A-00 March 2015 is a registered trademark of Richtek Technology Corporation. www.richtek.com 47 RT5045A Enter Sleep Exit Sleep 3.3V 3.3V 2.8V 27V 150us AVDD CH5 CH4 CH6 CH2 LDO CH3 CH1 POR (POR_OPTION=0) Tdelay POR (POR_OPTION=1) Tdelay Time Time Time Time Slot 1 Time Slot 3 Time Slot 5 Time Slot 7 Time Slot 2 Slot 4 Slot 6 Slot 8 Time Slot 15 VSEL0 = 0, Tdelay = 10ms VSEL0 = 1, Tdelay = 6ms Time Time Time Time Slot 1 Time Slot 3 Time Slot 5 Time Slot 7 Time Slot 2 Slot 4 Slot 6 Slot 8 Time Slot 15 Figure 8. For example : Power On/Off Sequence and Sleep off / Wake up Sequence with Different POR_OPTION on VIN = 3.3V The relations quiescent current and LPM current of each channel table are shown as below. RT5045 PMODE1 PMODE2 PMODE3 PMODE4 PMODE5 PMODE6 PMODE7 PMODE8 Buck1 2.5V ON OFF OFF OFF OFF OFF OFF OFF Buck2 1.35V ON ON OFF OFF OFF OFF OFF OFF Buck3 1.8V ON ON ON OFF OFF OFF OFF OFF Buck4 1.0V ON ON ON ON OFF OFF OFF OFF Buck5 1.0V ON ON ON ON ON ON ON ON Buck6 1.0V ON ON ON ON ON ON OFF OFF LDO 2.5V ON ON ON ON ON OFF OFF OFF LPM OFF OFF OFF OFF OFF OFF OFF ON LPM ALL OFF Total (A) 184 155 135 110 87 50 Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 48 25 is a registered trademark of Richtek Technology Corporation. DS5045A-00 March 2015 RT5045A Thermal Considerations Layout Considerations For continuous operation, do not exceed absolute maximum junction temperature. The maximum power Layout is very important in high frequency switching dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and ambient temperature. The maximum power dissipation can be calculated by the following formula : PD(MAX) = (TJ(MAX) TA) / JA where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and JA is the junction to ambient thermal resistance. For recommended operating condition specifications, the maximum junction temperature is 125C. The junction to ambient thermal resistance, JA, is layout dependent. For WL-CSP-52B 3.19x3.59 (BSC) package, the thermal resistance, JA, is 26C/W on a standard JEDEC 51-7 four-layer thermal test board. The maximum power dissipation at TA = 25C can be calculated by the following formula : converter design. The PCB can radiate excessive noise and contribute to converter instability with improper layout. Power components should be placed on the same side of board, with power traces routed on the same layer. If it is necessary to route a power trace to another layer, choose a trace in low di/dt paths and use multiple vias for interconnection. When vias are used to connect PCB layers in the high current loop, multiple vias should be used to minimize via impedance. Certain points must be considered before starting a layout using the RT5045A. Make the traces of the main current paths as short and wide as possible. Place input decoupling capacitors as close as ossible as to PVIN1、PVIN2、PVIN3、PVIN4、PVIN5、 PVIN6. This cap provide the instant current into this PD(MAX) = (125C 25C) / (26C/W) = 3.84W for WL-CSP-52B 3.19x3.59 (BSC) pin when the internal MOSFET switching. It is The maximum power dissipation depends on the operating ambient temperature for fixed TJ(MAX) and directly to the pins without using vias. thermal resistance, JA. The derating curve in Figure 9 allows the designer to see the effect of rising ambient preferable to connect the decoupling capacitors Place the inductors close LX1、LX2、LX3、LX4、LX5、 LX6. To minimize the radiation noise, and the copper area should be minimized. However, the copper area temperature on the maximum power dissipation. Maximum Power Dissipation (W)1 is provided a heat sink to the internal MOSFET. Don’t 5.0 make the area of the node small by using narrow Four-Layer PCB traces, using wide and short traces instead. 4.0 3.0 For feedback signals FB1、FB2、FB3、FB4、FB5、 FB6, the sensing point which detects the output voltage must be connected after output capacitor and 2.0 keep the trace far away from the switching node or 1.0 inductor. Place the feedback network as close to the chip as possible. 0.0 0 25 50 75 100 Ambient Temperature (°C) 125 Place the bypass capacitor close to AVDD. Place the filter capacitor close to LDO、LX1、LX2、 LX3、LX4、LX5、LX6 to minimize trace inductance. Figure 9. Derating Curve of Maximum Power Dissipation The GND pin and Exposed Pad should be connected to a strong ground plane for heat sinking and noise protection. Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5045A-00 March 2015 is a registered trademark of Richtek Technology Corporation. www.richtek.com 49 RT5045A An example of PCB layout guide is shown in Figure 7.for reference. GND GND The Output capacitor must be placed near the IC Vout CH6 The Output capacitor must be placed near the IC A1 A2 A3 A4 LDO SCL SDA AGND B1 B2 B3 B4 PGND PORSEL FB1 PGND A5 AVDD B5 VSEL0 A6 AGND B6 VSEL1 A7 A8 POR FB6 B7 LX should be connected to inductor by wide and short trace. Keep sensitive components away from this trace. B8 PGND6 PGND6 GND C1 Input capacitor must be placed as close to the IC as possible C2 PGND1 Vout CH1 GND PVIN LX should be connected to inductor by wide and short trace. Keep sensitive components away from this trace. Vout CH2 PGND1 C8 LX6 D1 D2 D7 D8 LX1 LX1 PVIN6 PVIN6 E1 E2 PVIN1 PVIN1 GND E7 E8 PGND FB5 F2 F7 FB2 PGND PGND G1 G2 G7 G8 PGND2 PGND PGND LX5 H1 H2 H3 H4 H6 H7 H8 LX2 PGND PVIN3 LX3 LX4 PVIN4 J3 J4 J2 PVIN2 FB3 PVIN3 LX3 H5 PGND3/4 J5 PGND3/4 J6 LX4 PVIN Input capacitor must be placed as close to the IC as possible F8 F1 J1 GND C7 LX6 PGND5 J7 Vout CH5 The Output capacitor must be placed near the IC PVIN5 GND J8 PVIN4 FB4 The Output capacitor must be placed near the IC Vout CH3 GND PVIN GND Vout CH4 Input capacitor must be placed as close to the IC as possible PVIN PVIN PVIN Input capacitor must be placed as close to the IC as possible Figure 10. PCB Layout Guide Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 50 is a registered trademark of Richtek Technology Corporation. DS5045A-00 March 2015 RT5045A Outline Dimension Symbol Dimensions In Millimeters Dimensions In Inches Min. Max. Min. Max. A 0.500 0.600 0.020 0.024 A1 0.170 0.230 0.007 0.009 b 0.240 0.300 0.009 0.012 D 3.540 3.640 0.139 0.143 D1 E 3.200 3.140 0.126 3.240 0.124 0.128 E1 2.800 0.110 e 0.400 0.016 52B WL-CSP 3.19x3.59 Package (BSC) Richtek Technology Corporation 14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries. Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5045A-00 March 2015 is a registered trademark of Richtek Technology Corporation. www.richtek.com 51