TIMING AND SYNCHRONIZATION PRODUCT CATALOG ZL30110 ZL30112 ZL30113 Rate Conversion PLLs PDH ZL30106 Line Card Synchronizers SyncE/ SONET/SDH SyncE SONET/SDH SyncE GR-1244 Stratum 4/4E G.823, G.824 PDH GR-1244 Stratum 3 G.823, G.824 System Synchronizers G.8262 EEC Opt 1&2 GR-253 Stratum 3 G.813 (opt 1&2) SyncE SONET/SDH G.8262 EEC Opt 1&2 GR-1244 Stratum 2/3E GR-253 G.812 Type II & III ZL30131 ZL30132 ZL30145 ZL30146 ZL30108 ZL30321 ZL30136 ZL30100 ZL30102 ZL30109 ZL30101 ZL30105 ZL30142 ZL30143 ZL30130 ZL30138 QUICK GLANCE SELECTOR GUIDE LINE CARD SYNCHRONIZATION Zarlink offers the industry’s widest range of phase locked-loops (PLLs) for high performance line card synchronization. Complying with Telecordia and ITU-T jitter performance from T1/E1 up to 10G/OC-192/STM-64, the products support a wide range of input frequencies required for telecom and datacom equipment. The highly integrated, feature-rich chips—with multiple outputs, redundancy protection, and low-power consumption—help simplify the design of networking equipment that meets the latest performance requirements. Applications Optical equipment used in DWDM & WDM networks Passive Optical Network (PON) equipment Wireless base stations and Node B Wireless base station controllers and radio network controllers SONET/SDH equipment such as MultiService Provisioning Platforms (MSPP) Gateways Digital Subscriber Line Access Multiplexers (DSLAM) Metro Ethernet equipment Routers and switches Integrated Access Devices (IAD) Add-Drop Multiplexers (ADM) Multi-Service Access Platforms (MSAP) Product Features Meets Ethernet/SONET/SDH jitter generation requirements up to 10G/OC-192/STM-64 Output generates standard SONET/SDH clock rates or standard Ethernet clock rates Multiple PLLs per device for rate conversion Line card redundancy protection such as manual or automatic hitless reference switching Supports ITU-T G.8262 requirements for Synchronous Ethernet slave clocks (EEC option 1 & option 2) Low power consumption Input synchronizes to telecom reference clocks or to Ethernet reference clocks SyncE/SONET/SDH SONET/ SDH SyncE PDH ZL30131 ZL30132 ZL30146 ZL30145 ZL30136 ZL30321 ZL30108 ZL30106 up to 10G/ OC-192/ STM-64 up to 10G/ OC-192/ STM-64 up to 10G/ OC-192/ STM-64 up to 10G/ OC-192/ STM-64 Gigabit Gigabit OC-3/ STM-1 PDH, OC-3/ STM-1 2 1 2 1 1 2 1 1 622.08 622.08 622.08 622.08 125 125 19.44 65.536 CMOS 2 1 1 1 1 2 1 1 Differential 2 1 1 1 0 0 0 0 Number of PDH/TDM outputs (CMOS) 4 1 1 0 1 4 0 7 Number of frame pulse outputs (CMOS) 2 1 1 0 1 2 2 4 Programmable synthesizers (N x 8 kHz) 2 1 1 0 1 2 0 0 Number of reference inputs 8 3 5 1 3 8 2 3 Sync inputs for output frame pulse alignment 3 3 1 0 3 3 0 2 9 x 9 mm CABGA 9 x 9 mm CABGA 9 x 9 mm CABGA 9 x 9 mm CABGA 9 x 9 mm CABGA 9 x 9 mm CABGA 5 x 5 mm QFN 10 x 10 mm TQFP Jitter compliance Number of rate conversion Digital PLLs Maximum frequency (MHz) Number of SONET/SDH/ Ethernet outputs Package size TIMING CARD SYNCHRONIZATION Zarlink’s timing card synchronization products are easy-to-adopt, standards-compliant solutions that deliver critical end-to-end network timing performance while helping equipment manufactures reduce costs and speed time-to-market The highly integrated, single-chip solutions ease system integration, lower component count and reduce power consumption, while meeting ANSI, ETSI and Telecordia standards as well as the ITU-T Recommendation G.8262 for Synchronous Ethernet timing requirements. Deployed in a range of access, wireless, router and Metro Ethernet applications, Zarlink’s timing card synchronization solutions allow service providers to deliver truly reliable voice, video, data and mobile services over packet networks. Applications Optical equipment used in DWDM & WDM networks SONET/SDH equipment such as MultiService Provisioning Platforms (MSPP) Wireless base stations and Node B Wireless base station controllers and radio network controllers Metro Ethernet equipment Routers and switches Integrated Access Devices (IAD) Add-Drop Multiplexers (ADM) Multi-Service Access Platforms (MSAP) Passive Optical Network (PON) equipment Gateways Digital Subscriber Line Access Multiplexers (DSLAM) Product Features Meets the requirements of ITU-T G.8262 for synchronous Ethernet Equipment slave clocks (EEC Option 1 & Option 2) Provides automatic reference switching & holdover during loss of reference input Generates standard SONET/SDH clock rates or Ethernet clock rates up to 622 MHz Internal state machine automatically controls mode of operation (free-run, locked, hold-over) Additional programmable output synthesizer generates telecom clock frequencies from any multiple of 8 kHz to 100 MHz Supports master/slave configuration Generates several styles of telecom frame pulses with selectable pulse width, polarity & frequency Configurable input to output delay Configurable output to output phase alignment Lowest power for similar solutions SyncE/SONET/SDH ZL30138 ZL30130 ZL30143 ZL30142 ITU-T G.8262 (EEC Option 1/Option 2) GR-1244 SONET Stratum 2/3E GR-253 SONET Stratum 3 GR-1244 Stratum 3 GR-1244 Stratum 4/4E ITU-T G.813 Option 1/Option 2 Number of independent digital PLLs 2 2 2 1 Number of reference inputs 9 9 9 3 Sync inputs for output frame pulse alignment 4 4 4 3 2 2 2 1 Number of SONET/SDH/ Ethernet outputs CMOS 2 2 2 1 Number of PDH/TDM outputs (CMOS) Differential 4 4 4 1 Number of frame pulse outputs (CMOS) 4 4 4 1 Programmable synthesizers (N x 8 kHz) 2 2 2 1 up to 10G/OC-192/STM-64 up to 1G/OC-12/STM-4 up to 10G/OC-48/STM-16 up to 10G/OC-48/STM-16 312.5 125 312.5 312.5 Jitter compliance Maximum frequency Ethernet (MHz) Maximum frequency SONET/SDH (MHz) Package size 622.08 622.08 622.08 622.08 9 x 9 mm CABGA 9 x 9 mm CABGA 9 x 9 mm CABGA 9 x 9 mm CABGA Product Features Supports standards from Telecordia , ANSI, ETSI & ITU Holdover accuracy equal to or better than 1.5 x 10-7 Accepts wide range of common telecom input frequencies Manual or automatic hitless reference switching Provides a wide range of telecom clocks & frame pulses Simple hardware control interface ZL30105 ZL30101 ZL30102 ZL30109 ZL30100 GR-1244 Stratum 3 GR-1244 Stratum 4/4E Number of independent digital PLLs 1 1 1 1 1 Number of reference inputs 3 2 3 2 2 Sync inputs for output frame pulse alignment 1 0 1 0 0 Number of SONET/SDH/Ethernet outputs (CMOS) 1 0 0 1 0 Number of PDH/TDM outputs (CMOS) 7 5 7 5 5 Number of frame pulse outputs (CMOS) 4 3 3 4 3 up to OC-3/ STM-1 PDH Interfaces PDH Interfaces up to OC-3/ STM-1 PDH Interfaces 65.536 65.536 65.536 65.536 65.536 10 x 10 mm TGFP 10 x 10 mm TGFP 10 x 10 mm TGFP 10 x 10 mm TGFP 10 x 10 mm TGFP Jitter compliance Maximum output frequency (MHz) Package size RATE CONVERSION PLLs Zarlink’s telecom rate conversion phase locked loops (PLLs) provide accurate and reliable frequency conversion for telecom, enterprise and access equipment. Targeting volume designs, the products deliver required performance with integrated reference monitoring to ensure system reliability. Applications Passive Optical Network Terminal (ONT) Private Branch Exchange (PBX) Integrated Access Device (IAD) Channel bank Voice over IP (VoIP) line cards Product Features Standard input frequencies of 8 kHz, 2.048 MHz, 8.192 MHz, or 19.44 MHz Goes to free run mode when the reference fails Provides a selection of telecom frequencies Simple hardware control interface Less than 0.6 nspp intrinsic jitter on TDM clock outputs Small package: 5mm x 5mm, QFN package Provides reset pin for control Status output pins for lock indication & reference failure ZL30110 Rate conversion DPLL with stand by capability ZL30112 ZL30113 Number of reference inputs 1 1 1 Number of CMOS outputs 9 1 1 65.536 MHz, 100/66 MHz 125 & 25 MHz 2.048 MHz 8.192 MHz 65.536 MHz Synthesizers Fanout capability Number of frame pulse outputs 0 1 1 5 x 5 mm QFN 5 x 5 mm QFN 5 x 5 mm QFN Package Distributed Timing For Pizza Box Timing Distribution Bus via Backplane 20 MHz OCXO/ TCXO BITS A Pizza Box/Blade BITS B ZL30138/30 Rate Conversion Stratum 3E Synchronizer Output Synthesizers Frame Pulse n SONET Clocks n-Port OC-48 Framer, Mapper, SerDes Centralized System Timing And Blade Applications BITS A BITS B Input Reference Timing Distribution Bus via Backplane Derived Output 20 MHz OCXO/ TCXO 20 MHz OCXO/ TCXO Timing Card ZL30130/43 Rate Conversion Stratum 3 Synchronizer Timing Card Derived Output ZL30143 Rate Conversion Output Synthesizers Stratum 3 Synchronizer Output Synthesizers SONET/SDH Timing Distribution Bus via Backplane 20 MHz XTAL/ XO Line Card ZL30146 Rate Conversion Line Card Synchronizer Output Synthesizers n Frame Pulse SONET Clocks n-Port OC-48 Framer, Mapper, SerDes 20 MHz XTAL/ XO Line Card ZL30106 20 MHz XTAL/ XO Line Card ZL30146 Line Card Synchronizer Line Card Synchronizer Output Synthesizers Output Synthesizers Frame Pulse 1.544/2.048/ 34.368/ 44.736 MHz Clock n-Port DS1/E1, DS3/E3 Framer, Mapper 1G PHY Clocks PHY n Zarlink’s Timing and Synchronization solutions are based on a foundation of over 20 years of expertise in designing leading-edge products that ensure maximum network uptime while meeting strict performance requirements. Highly Integrated Solutions: Complete solutions that reduce bill-ofmaterial costs, board space and power consumption Simplify Design: Easy-to-adopt products, fully supported by design tools, evaluation boards, software and dedicated support teams, to simplify and shorten your design cycle Standards Compliant: Designed to meet the latest performance requirements, including ITU-T Recommendation G.8262 for Synchronous Ethernet, to achieve quality of transmission and reliable carrier-grade services Our state-of-the-art Line Card and Timing Card synchronization solutions increase performance, reduce costs and keep our customers ahead of the technology curve. w w w.zarlink .com/timing.htm Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries is believed to be reliable. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. ZARLINK, ZL, ZLE and the Zarlink logo are trademarks of Zarlink Semiconductor Inc. © April 2009, Zarlink Semiconductor Inc. All Rights Reserved. Publication Number 9ZS087