AZT70 Programmable Capacitive Tuning IC www.azmicrotek.com DESCRIPTION FEATURES The AZT70 is a digitally programmed capacitor specifically designed to tune a crystal or SAW based oscillator to a desired center frequency. The desired capacitance value for production trimming is set by a serial data stream when placed into a programming mode. The AZT70 is designed to be a labor and cost saving device within the oscillator production process. • Capacitive tuning range of 2.6pF to 14.55pF (See AZT71 for different values) • • Using EEPROM technology, the capacitance can be re-tuned as needed during the production process by repeating the programming steps thereby increasing production yield. • The AZT70 is available in an SON8 package (1.5mm x 1.0mm) for very small form factor oscillators. • • BLOCK DIAGRAM 0.063pF minimum step size Reprogrammable through nonvolatile EEPROM storage May be placed in parallel for greater capacitance values Very low supply current 2.5V to 5.0V supply voltage VDD X1 DA • CF • 2.6pF CLK CONTROLLER APPLICATIONS Cmid b8-b6 Fast production tuning of crystal or SAW oscillators Filters requiring capacitive tuning 0-9.8pF PV Clo b5-b1 0-1.953pF PACKAGE AVAILABILITY • VSS Order Number 1 AZT70QG SON8 o 1.5mm x 1.0mm x 0.4mm o Green/RoHS Compliant/Pb-Free Package Marking SON8 T <Date Code>2 1 Tape & Reel - Add 'R1' at end of order number for 7in (1k parts), 'R2' (2.5k) for 13in 2 See www.azmicrotek.com for date code format www.azmicrotek.com +1-480-962-5881 Request a Sample 1630 S Stapley Dr, Suite 127 Mesa, AZ 85204 USA December 2013, Rev 1.4 Arizona Microtek, Inc. AZT70 Programmable Capacitive Tuning IC PIN DESCRIPTION AND CONFIGURATION Table 1 - Pin Description X1 Name Type Function 1 X1 Output Capacitance 2 NC n/a not connected 3 VSS Power Negative Supply (GND) 4 VDD Power Positive Supply 5 DA Input Programming Data Input 6 CLK Input Programming Clock Input 7 NC n/a not connected 8 PV Input Programming Voltage 1 NC 2 VSS 3 VDD 4 T <date code> Pin 8 PV 7 NC 6 CLK 5 DA Figure 1 – Pin Configuration ENGINEERING NOTES CAPACITOR STRUCTURE The AZT70 capacitance value is composed of three parallel capacitor banks, CF is a fixed capacitor value of 2.6pF and Cmid & Clo are variable capacitors of differing ranges and resolutions as seen in Table 2. Capacitors composing Cmid and Clo are set with a binary control word through an 11-bit shift register described in PROGRAMMING the AZT70. The values of each Clo and Cmid stepping are detailed in the complete Nominal Capacitance Binary Mapping spreadsheet. CTotal = CF + Cmid + Clo Table 2 - AZT70 Capacitor Structure www.azmicrotek.com +1-480-962-5881 Request a Sample Internal Capacitor CF Cmid Clo Min Value (pF) 2.6 0 0 Max Value (pF) 2.6 9.8 1.953 Total 2.6 14.353 Step Size (pF) n/a 1.4 0.063 2 December 2013, Rev 1.4 Arizona Microtek, Inc. AZT70 Programmable Capacitive Tuning IC PROGRAMMING THE AZT70 CONTROL WORD The capacitance in the AZT70 is controlled by an 11-bit shift register with the data input bit definitions shown in Table 3. The control word data is inputted serially on the rising edge of the CLK signal with bit0 first and bit10 last. Table 3 - AZT70 Control Word Definition bit10 bit9 Not Used Not Used bit8 MSB 11-bit Control Word bit7 bit6 bit5 bit4 bit3 Cmid Clo --- LSB MSB --- --- bit2 bit1 --- LSB bit0 Not Used The control word mapping is a binary word for each of Cmid and Clo where higher number bits are more significant. Figure 2 shows the capacitance value mapping for the AZT70. The detailed Nominal Capacitance Binary Mapping can be located on the AZM website. Figure 2 – AZT70 Capacitance Value Mapping www.azmicrotek.com +1-480-962-5881 Request a Sample 3 December 2013, Rev 1.4 Arizona Microtek, Inc. AZT70 Programmable Capacitive Tuning IC AZT70 FUNCTIONAL MODES The AZT70 is designed to be used in 2 functional modes, Programming and Operational. In the Programming mode, the AZT70 is used by the manufacturer to set the capacitance value to control the desired center frequency of the oscillator. The programming mode uses either the shift registers or EEPROM (detailed later) and gives the manufacturer access to pins DA, CLK, and PV which allow the AZT70 to be programmed with an accompanying programming board (Figure 3). Arizona Microtek can provide this board (AZPB70) along with software that works through all the programming steps/functions described in the next sections. In the Operational mode, the EEPROM internal to the AZT70 has already been programmed with the desired factory settings. Pins DA, CLK, and PV are to be disconnected, thereby allowing the AZT70’s internal pull-downs to place the pins at ground potential. In the operational mode, only 3 pins are necessary for hookup (Figure 4). VDD DA DA AZT70 Programming CLK Board (PRT70) X1 CLK PV PV VSS OUT RESONATOR OSCILLATOR Figure 3 – AZT70 in Programming Mode VDD NC DA AZT70 X1 NC CLK NC PV VSS OUT RESONATOR OSCILLATOR Figure 4 – AZT70 in Operational Mode www.azmicrotek.com +1-480-962-5881 Request a Sample 4 December 2013, Rev 1.4 Arizona Microtek, Inc. AZT70 Programmable Capacitive Tuning IC PROGRAMMING MODES The AZT70 has two capacitance setting modes from which bits are set and the matching capacitors are selected. • Reading directly from the shift register o This is useful for testing the capacitance and subsequent oscillator frequency. This mode is active after the last bit is shifted in and when the CLK pin is left logic high. For the shift register, capacitors are selected when bits are active HIGH. • Reading from the value contained in the EEPROM o Prevents customer adjustment and retains factory programming and is active when the CLK pin is at logic low or not connected. For the EEPROM, capacitors are selected when bits are active LOW. PROGRAMMING FROM THE SHIFT REGISTER To initially determine the capacitance value for the desired center frequency of the oscillator one should set the capacitance of the AZT70 directly from the active shift register bits. To accomplish this, the CLK pin is left high after the last control word bit has been shifted in. Figure 5 shows the control word 11001100100 has been serially entered into the register. Note that bit0 is the 1st bit to enter and bit10 is the last. In the AZT70, bit0, bit9 & bit10 do not affect the capacitance value but still must be included in the serial bit stream. For the shift register, capacitors are selected when bits are active HIGH. bit 0 DA bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 Register data active when CLK is high bit 0 loaded 1st CLK t Figure 5 - Shift register programming WRITING DATA TO THE EEPROM Once the desired capacitance value has been determined, the digital control word can be written or re-written into the EEPROM. By storing the control word in the EEPROM, the customer is prevented from making adjustments from the factory set programming data. This is accomplished within the AZT70 with internal pull-downs on the DA, PV, and CLK pins. The detailed sequence for writing data to the EEPROM within the AZT70 is described in Table 4. Note that with EEPROM, capacitors are selected when bits are active LOW. www.azmicrotek.com +1-480-962-5881 Request a Sample 5 December 2013, Rev 1.4 Arizona Microtek, Inc. AZT70 Programmable Capacitive Tuning IC Table 4 – Data writing sequence for EEPROM Step 1 Action Determine the desired capacitor control word with the operational power supply voltage and desired oscillator conditions 2 Set the VDD supply voltage to +5.0V 3 If EEPROM is not already erased, erase EEPROM (see ERASING THE EEPROM) 4 Read the current state of the EEPROM bits (see READING BACK FROM THE EEPROM) 5 Compare the desired control word to the stored EEPROM control word. Count the number of differences so as to prevent double/redundant writing 6 One bit at a time, load the first desired control word bit (bit selection for EEPROM is active LOW) 7 Set the PV pin to +6V (≥5.6V, ≤6.1V) with the pulse and idle shown in timing diagram (Figure 8) 8 Progress through all necessary control word bits by repeating steps 5 & 6 until all bits are set to the desired control word. 9 Verify the correct EEPROM contents by reading back the individual bits For an example of writing bits into the EEPROM, suppose the desired capacitance is 3.43pF. The control word becomes ‘00000010100’ (Figure 6). Also suppose the EEPROM bits have been erased and therefore logic high (The AZT70 is initially shipped in this condition). Since bit0 is the first bit to be loaded, the bit sequence becomes 0-0-1-0-1-0-0-0-0-0-0. However, as described before, selecting bits for the EEPROM are active LOW, which will invert the logical values in the sequence to 1-1-0-1-0-1-1-1-1-1-1 (Figure 7). Note the differences between the EEPROM bits and the converted control word. Since there are 2 differences, two write cycles are required as only 1 bit should be written at a time. Figure 8 shows the timing for bit2 while Figure 9 shows the timing for bit4. bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 desired Figure 6 – Desired control word bit 0 bit 1 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 DA difference bit 2 difference bit 3 bit 4 EEPROM Figure 7 – Converted control word and differences from known EEPROM states www.azmicrotek.com +1-480-962-5881 Request a Sample 6 December 2013, Rev 1.4 Arizona Microtek, Inc. bit 0 DA bit 1 AZT70 bit 2 bit 3 bit 4 bit 5 bit 6 Programmable Capacitive Tuning IC bit 7 bit 8 bit 9 bit 10 bit 10 loaded last bit 0 loaded 1st CLK 10ms ≥5.6V, ≤6.1V 4µs min PV t Figure 8 – First programming cycle to program bit2 into the EEPROM bit 0 DA bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 10 loaded last bit 0 loaded 1st CLK 10ms ≥5.6V, ≤6.1V 4µs min PV t Figure 9 – Second programming cycle to program bit4 into the EEPROM READING BACK FROM THE EEPROM During programming, the PV pin is used to program the necessary control bits into the EEPROM. However, it is also used to read the bits currently programmed into the EEPROM. When the PV pin is not used during programming, the AZT70 provides a weak pull-up and pull-down on the pin. This allows the EEPROM data to be shifted out to the PV pin and read after the CLK sequence is complete and when the DA & CLK pins are high (Figure 10). Each EEPROM bit is selected by setting the DA signal low (EEPROM selection is active low) during the CLK sequence. With an external 68kΩ resistor pull-up to VDD on the PV pin, a low EEPROM bit produces ≤ 0.4*VDD level while a high EEPROM bit produces a ≥ 0.6*VDD level. www.azmicrotek.com +1-480-962-5881 Request a Sample 7 December 2013, Rev 1.4 Arizona Microtek, Inc. AZT70 Programmable Capacitive Tuning IC bit5 selection falling edge acceptable range bit 0 DA bit 1 bit 2 bit 3 bit0 loaded 1st bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit10 loaded last 2µs min 500ns max CLK ≥ 0.6*VDD Resulting voltage if bit5 was high in EEPROM With an external 68kΩ resistor pull-up to VDD PV indeterminate Resulting voltage if bit5 was low in EEPROM ≤ 0.4V t Figure 10 – Timing diagram to read bits from EEPROM ERASING THE EEPROM The EEPROM can be erased by initiating a programming cycle with all DA bits set high, including bit9 and bit10. After the programming cycle, all the EEPROM bits are set low (logical high) except for the check bit (bit0), which remains high. Table 5 – Erase sequence for EEPROM Step Action 1 Set the VDD supply voltage to +5.0V 2 Load the programming word bits all high. 3 Set the PV pin to +6V (≥5.6V, ≤6.1V) with the pulse and idle shown in timing diagram (Figure 11) 4 Verify the correct EEPROM contents by reading back the individual bits bit 0 DA bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit0 loaded 1st bit 10 bit10 loaded last CLK EEPROM has been erased (no capacitors selected) 10ms ≥5.6V, ≤6.1V 4µs min PV t Figure 11 – Programming Sequence for erasing the EEPROM www.azmicrotek.com +1-480-962-5881 Request a Sample 8 December 2013, Rev 1.4 Arizona Microtek, Inc. AZT70 Programmable Capacitive Tuning IC PROGRAMMING VOLTAGE LIMIT CIRCUIT Some existing programming circuits use a current source connected to a 6.5 – 8.0 V supply. That circuit produces an excessive voltage on the PV pin, which can damage the AZT70. A simple modification eliminates the issue and maintains full programming compatibility with existing programming methods. A 5.6 V, ½ watt Zener, 1N5232B or equivalent, placed between the PV pin and ground will limit the voltage while still allowing the programming circuit to generate the current required for programming fuse link type parts. www.azmicrotek.com +1-480-962-5881 Request a Sample 9 December 2013, Rev 1.4 Arizona Microtek, Inc. AZT70 Programmable Capacitive Tuning IC PERFORMANCE DATA Table 6 – General Specifications Parameter Description Conditions Min VDD Power Supply Supply voltages between 4.0V-4.5V may not allow for reliable operation 2.375 3.63 4.5 5.5 Vabsolute Power Supply 0 6.5 V Input Voltage -0.5 VDD + 0.5 V TA Operating Temperature Range -40 125 °C TSTG Storage Temperature Range -65 150 °C ESDHBM Human Body Model 2000 V ESDMM Machine Model 200 V ESDCDM Charged Device Model 2000 V VI 1 1 Typ Max Unit V PV Pin can exceed VDD by 1.2V during the programming interval Table 7 – DC Characteristics DC Characteristics (VDD = 2.375V to 5.5V unless otherwise specified, TA = -40 to 125 °C) Symbol Characteristic CPV Capacitance variation across process CVV Capacitance variation across output voltage CTV Capacitance variation across temperature Conditions Min Typ -15 Voltage variation at X1 pin, 100MHz 100MHz - Zero Code Max Unit +15 % ±150 ppm/V 325 1 100MHz - Mid Code 40 100MHz - Full Scale 130 VIH Input HIGH Voltage DA, CLK 0.8 * VDD 0.2 * VDD ppm/°C V VIL Input LOW Voltage DA, CLK RPD,D Pull-down Resistor DA 55k Ω RPD,CLK Pull-down Resistor CLK 75k Ω RPD,PV Pull-down Resistor PV 170k Ω VOH Output High Voltage 0.6 * VDD V 0.4 * VDD V VOL Output Low Voltage PV Pin when reading EEPROM bits 68kΩ pull-up resistor to VDD VPP Programming Voltage (VDD=5.0V) PV pin when programming EEPROM IDD Power Supply Current IDDPROG Power Supply Current tMEM EEPROM Data Retention Tprog Programming Temperature Cyprog Programming Cycle 1 5.6 V 6.0 6.1 Normal Operation, VDD <3.63V 10.0 35 Normal Operation, VDD >3.63V 20.0 70 Programming Mode 250 20 PV pulse width of 10ms µA µA yrs 125 10 V °C k Bit4, Bit7 High www.azmicrotek.com +1-480-962-5881 Request a Sample 10 December 2013, Rev 1.4 Arizona Microtek, Inc. AZT70 Programmable Capacitive Tuning IC Table 8 – AC Characteristics AC Characteristics (VDD = 2.375V to 5.5V unless otherwise specified, TA = -40 to 125 °C) Symbol Characteristic CF Fixed Capacitance 2.6 pF Step Size 1.4 pF Max Value 9.8 pF Step Size 0.063 pF Max Value 1.953 pF Cmid Clo CLK Max CLK rate Tprog Programming Time (VDD=5.0V, PV=6.0V) Q www.azmicrotek.com +1-480-962-5881 Request a Sample Q Value Conditions Min Typ 50% duty cycle Max 100 10.0 20MHz - Full Scale 200 320 20MHz - Mid Scale 100 200 100MHz - Full Scale 50 80 100MHz - Mid Scale 50 70 200MHz - Full Scale 25 40 200MHz - Mid Scale 35 50 800MHz - Full Scale 8 12 800MHz - Mid Scale 10 15 Unit kHz ms 11 December 2013, Rev 1.4 Arizona Microtek, Inc. AZT70 Programmable Capacitive Tuning IC PACKAGE DIAGRAM SON8 (1.5x1.0x0.4mm) Green/RoHS compliant/Pb-Free Arizona Microtek, Inc. reserves the right to change circuitry and specifications at any time without prior notice. Arizona Microtek, Inc. makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Arizona Microtek, Inc. assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Arizona Microtek, Inc. does not convey any license rights nor the rights of others. Arizona Microtek, Inc. products are not designed, intended or authorized for use as components in systems intended to support or sustain life, or for any other application in which the failure of the Arizona Microtek, Inc. product could create a situation where personal injury or death may occur. Should Buyer purchase or use Arizona Microtek, Inc. products for any such unintended or unauthorized application, Buyer shall indemnify and hold Arizona Microtek, Inc. and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Arizona Microtek, Inc. was negligent regarding the design or manufacture of the part. www.azmicrotek.com +1-480-962-5881 Request a Sample 12 December 2013, Rev 1.4