BCM4914xD1E5135yzz

VIA BCM® Bus Converter
BCM4914xD1E5135yzz
®
S
US
C
C
NRTL
US
Fixed-Ratio DC-DC Converter
Features & Benefits
Product Description
• Up to 35 A continuous output current
The VIA BCM is a high efficiency Bus Converter, operating from
a 260 to 410 VDC primary bus to deliver an isolated 32.5 to 51.3
VDC unregulated, Safety Extra Low Voltage (SELV)
secondary output.
• Fixed transformation ratio(K) of 1/8
• 695 W/in3 power density
• 97.6% peak efficiency
This unique ultra-low proﬁle module incorporates DC-DC
conversion, integrated ﬁltering, transient surge protection and
PMBus™ commands and controls in a chassis or PCB mount
form factor.
• 2121 Vdc isolation
• Built-in EMI filtering and In-rush limiting circuit
• Suitable for hot swap applications
The VIA BCM offers low noise, fast transient response and
industry leading efficiency and power density. A secondary
referenced PMBus™ compatible telemetry and control interface
provides access to the VIA BCM’s internal controller
conﬁguration, fault monitoring, and other telemetry functions.
• Parallel operation for multi-kW arrays
• OV, OC, UV, short circuit and thermal protection
• 4914 package
• High MTBF
• Thermally enhanced VIA™ package
Leveraging the thermal and density beneﬁts of Vicor’s VIA
packaging technology, the VIA BCM module offers ﬂexible
thermal management options with very low top and bottom
side thermal impedances.
• PMBusTM management interface
When combined with downstream Vicor DC-DC conversion
components and regulators, the VIA BCM allows the Power
Design Engineer to employ a simple, low-proﬁle design which
will differentiate his end system without compromising on cost
or performance metrics.
Typical Applications
• 380 DC Power Distribution
• Green Buildings and Microgrids
• Information and Communication Technology
•
•
•
•
•
(ICT) Equipment
High End Computing Systems
Automated Test Equipment
Industrial Systems
High Density Energy Systems
Transportation
Size:
4.91 x 1.40 x 0.37 in
124.77 x 35.54 x 9.30 mm
Part Ordering Information
Product
Function
B
C
Package
Length
M
BCM =
Bus Converter
Module
4
9
Package
Width
1
4
Length in
Width in
Inches x 10 Inches x 10
Package
Type
x
B = Board VIA
V = Chassis VIA
Input
Voltage
D
1
Range
Ratio
E
Output
Voltage
(Range)
Max
Output
Current
5
3
1
Internal Reference
VIA BCM® Bus Converter
Rev 1.2
vicorpower.com
Page 1 of 39
07/2015
800 927.9474
5
Product Grade
y
C = -20 to 100°C
T = -40 to 100°C
Option Field
z
z
02 = Chassis/PMBus
06 = Short Pin/PMBus
10 = Long Pin/PMBus
BCM4914xD1E5135yzz
Typical Application
Host μC
PMBus
+
V
EXT
–
SGND
BCA_SGND
VIA BCM
PRM
BCA_SGND
ENABLE
enable/disable
switch
EXT_BIAS
VAUX
SCL
SDA
SGND
}
3
PRM_SGND
R
BCA_SGND
R
ADDR
VT
SHARE/
CONTROL NODE
VC
V
Adaptive Loop Temperature Feedback
TM
VTM Start Up Pulse
AL_PRM
OUT
+OUT
VC
PC
IFB
R
C
O_PRM_DAMP
O_VTM_CER
LOAD
PRM_SGND
+IN
+OUT
–IN
–OUT
+IN
L
C
IN
AL
I_PRM_DAMP
FUSE
V
R
TRIM_PRM
VTM
REF/
REF_EN
TRIM
PRIMARY
+IN
L
I_PRM_FLT
R
I_BCM_ELEC
SOURCE_RTN
+OUT
O_PRM_FLT
I_PRM_CER
–IN
C
O_PRM_CER
–IN
–OUT
SGND
–OUT
PRIMARY
SECONDARY
SECONDARY
LOAD_RTN
ISOLATION BOUNDRY
ISOLATION BOUNDRY
PRM_SGND
VIA BCM BCM4914xD1E5135yzz + PRM + VTM, Adaptive Loop Configuration
Host μC
PMBus
V
EXT
+
SGND
–
BCA_SGND
BCA_SGND
V
REF
VIA BCM
SGND
EXT_BIAS
SDA
SGND
ADDR
}
SGND
BCA_SGND
R
SGND
OUT
Voltage Sense and Error Amplifier
(Differential)
GND
VTM
REF/
REF_EN
TRIM
3
IN
VAUX
ENABLE
enable/disable
switch
SCL
REF 3312
AL
VT
SHARE/
CONTROL NODE
VC
SGND
TM
+OUT
Voltage Reference with Soft Start
PRM_SGND
IFB
VTM Start up Pulse
V+
V–
VC
PC
VOUT
I_PRM_DAMP
+IN
–IN
SGND
R
O_PRM_DAMP
C
FUSE
V
IN
C
+IN
+OUT
–IN
–OUT
+IN
L
I_BCM_ELEC
I_PRM_FLT
C
PRIMARY
+IN
+OUT
External Current Sense
I_PRM_ELEC
L
–OUT
–IN
SGND
SOURCE_RTN
Voltage Sense
PRM
O_PRM_FLT
C
O_PRM_CER
–IN
–OUT
PRIMARY
SECONDARY
SECONDARY
ISOLATION BOUNDRY
ISOLATION BOUNDRY
PRM_SGND
BCM4914xD1E5135yzz + PRM + VTM, Remote Sense Configuration
VIA BCM® Bus Converter
Rev 1.2
vicorpower.com
Page 2 of 39
07/2015
800 927.9474
0Ω
O_VTM_CER
LOAD
BCM4914xD1E5135yzz
Pin Configuration
1
2
TOP VIEW
+IN A
A’ +OUT
B’
C’
D’
E’
F’
PMBus™
EXT BIAS
SCL
SDA
SGND
ADDR
G’ –OUT
–IN B
4914 VIA BCM - Chassis Mount
1
2
TOP VIEW
–IN B
G’ –OUT
PMBus™
F’
E’
D’
C’
B’
ADDR
SGND
SDA
SCL
EXT BIAS
A’ +OUT
+IN A
4914 VIA BCM - PCB Mount
Pin Descriptions
Pin Number
Signal Name
Type
Function
A1
+IN
INPUT POWER
Positive input power terminal
B1
–IN
INPUT POWER
RETURN
Negative input power terminal
A’2
+OUT
OUTPUT POWER
Positive output power terminal
B’2
EXT BIAS
INPUT
5 V Unregulated supply input
C’2
SCL
INPUT
I2C Clock, PMBus Compatible
D’2
SDA
INPUT/OUTPUT
I2C Data, PMBus Compatible
E’2
SGND
POWER
F’2
ADDR
INPUT
G’2
–OUT
OUTPUT POWER
RETURN
Signal Ground
Address assignment - Resistor based
Negative output power terminal
VIA BCM® Bus Converter
Rev 1.2
vicorpower.com
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07/2015
800 927.9474
BCM4914xD1E5135yzz
Absolute Maximum Ratings
The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause permanent damage to the device.
Parameter
Comments
Min
Max
Unit
+IN to –IN
-1
450
V
+OUT to –OUT
-1
60
V
-0.3
EXT BIAS to SGND
10
V
0.15
A
SCL to SGND
-0.3
5.5
V
SDA to SGND
-0.3
5.5
V
ADDR to SGND
-0.3
3.6
V
Dielectric Withstand*
See note below
Input-Case
Basic Insulation
2121
Vdc
Input-Output
Reinforced Insulation
2121
Vdc
Output-Case
Functional Insulation
707
Vdc
* Please see Dielectric Withstand section.
VIA BCM® Bus Converter
Rev 1.2
vicorpower.com
Page 4 of 39
07/2015
800 927.9474
BCM4914xD1E5135yzz
Electrical Specifications
Specifications apply over all line and load conditions, unless otherwise noted; Boldface specifications apply over the temperature range of -40°C ≤ TCASE
≤ 100°C (T-Grade); All other specifications are at TCASE = 20ºC unless otherwise noted.
Attribute
Symbol
Conditions / Notes
Min
Typ
Max
Unit
Powertrain
Input voltage range, continuous
VIN_DC
260
410
V
Input voltage range, transient
VIN_TRANS
260
410
V
VIN µController Active
VµC_ACTIVE
120
V
Quiescent current
VIN voltage where µC is initialized
Disabled, VIN = 400 V
IQ
2
TCASE ≤ 100ºC
4
VIN = 400 V, TCASE = 20ºC
No load power dissipation
Inrush current peak - EN
10.5
VIN = 400 V
PNL
IINR_P_EN
6
21
18
VIN = 260 V to 410 V
22
6
TCASE ≤ 100ºC
Inrush current peak - VIN
DC input current
Transformation ratio
Output power (continuous)
Output power (pulsed)
Output current (continuous)
Output current (pulsed)
Efficiency (ambient)
Efficiency (hot)
Efficiency (over load range)
Output resistance
IINR_P_VIN
IIN_DC
K
POUT_DC
IOUT_DC
IOUT_PULSE
A
VIN = 410 V, COUT = 56 µF,
RLOAD = 25% of full load current, Application of VIN
7
TCASE ≤ 100ºC
13
At POUT = 1750 W, TCASE ≤ 70ºC
4.5
1/8
A
V/V
See specified electrical and thermal operating area
1750
W
10 ms pulse, 25% Duty cycle
2000
W
35
A
40
A
See specified electrical and thermal operating area
10 ms pulse, 25% Duty cycle
VIN = 400 V, IOUT = 35 A
96.5
VIN = 260 V to 410 V, IOUT = 35 A
95.3
VIN = 400 V, IOUT = 17.5 A
96.8
97.6
hHOT
h20%
VIN = 400 V, IOUT = 35 A, TCASE = 70°C
95.7
96.2
7 A < IOUT < 35 A, TCASE ≤ 70ºC
94.5
ROUT_COLD
VIN = 400 V, IOUT = 35 A, TCASE = -40°C
20
24
28
ROUT_AMB
VIN = 400 V, IOUT = 35 A
20
25.5
31
ROUT_HOT
VIN = 400 V, IOUT = 35 A, TCASE = 70°C
32
38
42
1.05
1.10
1.14
hAMB
W
12
K = VOUT / VIN, at no load
POUT_PULSE
17
VIN = 260 V to 410 V, TCASE = 20ºC
VIN = 410 V, COUT = 56 µF,
RLOAD = 25% of full load current, Application of Enable
mA
Switching frequency
FSW
Frequency of the Output Voltage Ripple = 2x FSW
Output voltage ripple
VOUT_PP
Effective Output capacitance (internal)
COUT_INT
Effective value at 50 VOUT
Effective Output capacitance (external)
COUT_EXT
Excessive capacitance may drive module into
SC protection
Array Maximum external output
capacitance
COUT_AEXT
COUT_AEXT Max = N * 0.5*COUT_EXT Max
COUT = 0 F, IOUT = 35 A, VIN = 400 V, 20 MHz BW
97.2
%
%
%
250
TCASE ≤ 100ºC
550
37.6
VIA BCM® Bus Converter
Rev 1.2
vicorpower.com
Page 5 of 39
07/2015
800 927.9474
0
mΩ
MHz
mV
µF
56
µF
BCM4914xD1E5135yzz
Electrical Specifications (Cont.)
Specifications apply over all line and load conditions, unless otherwise noted; Boldface specifications apply over the temperature range of -40°C ≤ TCASE
≤ 100°C (T-Grade); All other specifications are at TCASE = 20ºC unless otherwise noted
Attribute
Symbol
Conditions / Notes
Min
Typ
Max
Unit
357.5
ms
Powertrain Protection
Auto Restart Time
tAUTO_RESTART
Startup into a persistent fault condition.
Non-Latching fault detection given VIN > VIN_UVLO+,
Module will ignore attempts to re-enable during time off
292.5
Input overvoltage lockout threshold
VIN_OVLO+
430
440
450
V
Input overvoltage recovery threshold
VIN_OVLO-
420
430
440
V
Input overvoltage lockout hysteresis
VIN_OVLO_HYST
Overvoltage lockout response time
tOVLO
Soft-Start time
tSOFT-START
Output overcurrent trip threshold
IOCP
Overcurrent Response Time Constant
tOCP
Short circuit protection trip threshold
ISCP
Short circuit protection response time
tSCP
Overtemperature shutdown threshold
From powertrain active Fast Current limit protection
disabled during Soft-Start
37.5
Effective internal RC filter
10
V
10
µs
1
ms
47
59
3.6
ms
52
A
1
Temperature sensor located inside controller IC
(Internal Temperature)
tOTP
A
µs
125
ºC
Powertrain Supervisory Limits
Input overvoltage lockout threshold
VIN_OVLO+
420
436
450
V
Input overvoltage recovery threshold
VIN_OVLO-
405
426
440
V
Input overvoltage lockout hysteresis
VIN_OVLO_HYST
10
V
Overvoltage lockout response time
tOVLO
100
µs
Input undervoltage lockout threshold
VIN_UVLO-
200
226
250
V
Input undervoltage recovery threshold
VIN_UVLO+
225
244
259
V
Input undervoltage lockout hysteresis
VIN_UVLO_HYST
15
V
Undervoltage lockout response time
tUVLO
100
µs
20
ms
Undervoltage startup delay
tUVLO+_DELAY
Output Overcurrent Trip Threshold
IOCP
Overcurrent Response Time Constant
tOCP
From VIN = VIN_UVLO+ to powertrain active,
EN floating, (i.e One time Startup delay from
application of VIN to VOUT)
42.5
47.5
2
Overtemperature shutdown threshold
tOTP
Temperature sensor located inside controller IC
(Internal Temperature)
Undertemperature shutdown threshold
tUTP
Temperature sensor located inside controller IC
(Internal Temperature)
Undertemperature restart time
45
tUTP_RESTART
Startup into a persistent fault condition. Non-Latching
fault detection given VIN > VIN_UVLO+
VIA BCM® Bus Converter
Rev 1.2
vicorpower.com
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07/2015
800 927.9474
A
ms
125
ºC
-45
3
ºC
s
BCM4914xD1E5135yzz
Output Current (A)
40
35
30
25
20
15
10
5
0
-60
-40
-20
0
20
40
60
80
100
120
Case Temperature (°C)
50
2100
2000
1900
1800
1700
1600
1500
1400
1300
1200
1100
1000
900
800
700
45
Output Current (A)
Output Power (W)
Figure 1 — Specified thermal operating area
40
35
30
25
20
15
10
5
0
260
275
290
305
320
335
350
365
380
395
410
260
275
290
Input Voltage (V)
P (ave)
305
320
I (ave)
P (pk), t < 10 ms
Figure 2 — Specified electrical operating area using rated ROUT_HOT
Output Capacitance
(% Rated COUT MAX)
335
350
365
380
395
Input Voltage (V)
110
100
90
80
70
60
50
40
30
20
10
0
0
10
20
30
40
50
60
70
80
90
Load Current (% IOUT_AVG)
Figure 3 — Specified Primary start-up into load current and external capacitance
VIA BCM® Bus Converter
Rev 1.2
vicorpower.com
Page 7 of 39
07/2015
800 927.9474
100 110
I (pk), t < 10 ms
410
BCM4914xD1E5135yzz
Reported Characteristics
Specifications apply over all line and load conditions, unless otherwise noted; Boldface specifications apply over the temperature range of -40°C ≤ TCASE
≤ 100°C (T-Grade); All other specifications are at TCASE = 20ºC unless otherwise noted
Monitored Telemetry
• The VIA BCM communication version is not intended to be used without a external µC.
ATTRIBUTE
INTERNAL µC
PMBusTM
READ COMMAND
ACCURACY
(RATED RANGE)
FUNCTIONAL
REPORTING RANGE
UPDATE
RATE
REPORTED UNITS
Input voltage
(88h) READ_VIN
± 5% ( LL - HL )
130 V to 450 V
100 µs
VACTUAL = VREPORTED x 10-1
Input current
(89h) READ_IIN
± 5% ( 10 - 133% of FL)
- 0.85 A to 5.9 A
100 µs
IACTUAL = IREPORTED x 10-3
Output voltage[1]
(8Bh) READ_VOUT
± 5% ( LL - HL )
16.25 V to 56.25 V
100 µs
VACTUAL = VREPORTED x 10-1
Output current
(8Ch) READ_IOUT
± 5% ( 10 - 133% of FL )
- 7 A to 47.5 A
100 µs
IACTUAL = IREPORTED x 10-2
Output resistance
(D4h) READ_ROUT
± 5% ( 50 - 100% of FL)
10 µΩ to 40 µΩ
100 ms
RACTUAL = RREPORTED x 10-5
(8Dh) READ_TEMPERATURE_1
± 7°C ( Full Range)
- 55ºC to 130ºC
100 ms
TACTUAL = TREPORTED
Temperature[2]
[1]
[2]
Default READ Output Voltage returned when unit is disabled = -300 V.
Default READ Temperature returned when unit is disabled = -273°C.
Variable Parameter
• Factory setting of all below Thresholds and Warning limits are 100% of listed protection values.
• Variables can be written only when module is disabled either EN pulled low or VIN < VIN_UVLO-.
• Module must remain in a disabled mode for 3 ms after any changes to the below variables allowing ample time to commit changes to EEPROM.
ATTRIBUTE
INTERNAL µC
PMBusTM
COMMAND
[3]
Input / Output Overvoltage
Protection Limit
(55h) VIN_OV_FAULT_LIMIT
Input / Output Overvoltage
Warning Limit
(57h) VIN_OV_WARN_LIMIT
Input / Output Undervoltage
Protection Limit
(D7h) DISABLE_FAULTS
CONDITIONS / NOTES
ACCURACY
(RATED RANGE)
FUNCTIONAL
REPORTING
RANGE
DEFAULT
± 5% ( LL - HL )
130 V to 435 V
100%
± 5% ( LL - HL )
130 V to 435 V
100%
± 5% ( LL - HL )
130 V or 260 V
100%
VIN_OVLO- is automatically 3%
lower than this set point
Can only be disabled to a preset
default value
VALUE
Input Overcurrent
Protection Limit
(5Bh) IIN_OC_FAULT_LIMIT
± 5% ( 10 - 133% of FL)
0 to 5.625 A
100%
Input Overcurrent
Warning Limit
(5Dh) IIN_OC_WARN_LIMIT
± 5% ( 10 - 133% of FL)
0 to 5.625 A
100%
Overtemperature Protection
Limit
(4Fh) OT_FAULT_LIMIT
Internal Temperature
± 7°C ( Full Range)
0 to 125°C
100%
Overtemperature
Warning Limit
(51h) OT_WARN_LIMIT
Internal Temperature
± 7°C ( Full Range)
0 to 125°C
100%
± 50 µs
0 to 100 ms
0 ms
Turn on Delay
[3]
(60h) TON_DELAY
Additional time delay to the
Undervoltage Startup Delay
Refer to internal µC datasheet for complete list of supported commands.
VIA BCM® Bus Converter
Rev 1.2
vicorpower.com
Page 8 of 39
07/2015
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BCM4914xD1E5135yzz
Signal Characteristics
Specifications apply over all line and load conditions, unless otherwise noted; Boldface specifications apply over the temperature range of -40°C ≤ TCASE
≤ 100°C (T-Grade); All other specifications are at TCASE = 20ºC unless otherwise noted
EXT. BIAS (VDDB) Pin
• Unregulated supply power input, required to power the circuitry internal to the VIA BCM adapter for communication signals such as SCL, SDA, ADDR etc
• Apply precise 5 V to this pin.
SIGNAL TYPE
STATE
Regular
POWER
Operation
INPUT
ATTRIBUTE
SYMBOL
VDDB Voltage
VVDDB
VDDB Current consumption
IVDDB
CONDITIONS / NOTES
MIN
TYP
MAX
UNIT
4.5
5
9
V
50
mA
Inrush Current Peak
IVDDB_INR
VVDDB Slew Rate = 1 V/µs
3.5
A
Turn on time
tVDDB_ON
From VVDDB_MIN to PMBus active
1.5
ms
Startup
SGND Pin
• This pin is power supply return pin for Ext. Bias (VDDB) pin.
• All input and output signals (SCL, SDA, ADDR) are referenced to SGND pin.
Address (ADDR) Pin
• This pin programs only a Fixed and Persistent slave address for VIA BCM Adapter.
• This pin programs the address using a resistor between ADDR pin and signal ground.
• The address is sampled during startup and is used until power is reset.
• This pin has 10 kΩ pullup resistor internally between ADDR pin and internal VDD.
• 16 addresses are available. Relative to nominal value of internal VDD (VVDD_NOM = 3.3 V), a 206.25 mV range per address.
SIGNAL TYPE
STATE
SYMBOL
CONDITIONS / NOTES
ADDR Input Voltage
VSADDR
See address section
Operation
ADDR leakage current
ISADDR
Leakage current
Startup
ADDR registration time
tSADDR
From VVDD_IN_MIN
Regular
MULTI-LEVEL
ATTRIBUTE
INPUT
VIA BCM® Bus Converter
Rev 1.2
vicorpower.com
Page 9 of 39
07/2015
800 927.9474
MIN
TYP
0
1
MAX
UNIT
3.3
V
1
µA
ms
BCM4914xD1E5135yzz
Serial Clock input (SCL) AND Serial Data (SDA) Pins
• High-power SMBus specification and SMBus physical layer compatible. Note that optional SMBALERT# is signal not supported.
• PMBusTM command compatible.
• The internal µC requires the use of a flip-flop to drive SSTOP. See system diagram section for more details.
SIGNAL TYPE
STATE
ATTRIBUTE
SYMBOL
CONDITIONS / NOTES
MIN
TYP
MAX
UNIT
Electrical Parameters
Input Voltage Threshold
Output Voltage Threshold
Leakage current
VIH
VVDD_IN = 3.3 V
V
VIL
VVDD_IN = 3.3 V
VOH
VVDD_IN = 3.3 V
VOL
VVDD_IN = 3.3 V
0.4
V
Unpowered device
10
µA
ILEAK-PIN
Signal Sink Current
2.1
ILOAD
0.8
3
VOL = 0.4 V
Signal Capacitive Load
CI
Signal Noise Immunity
VNOISE_PP
V
4
Total capacitive load of
mA
10
one device pin
10 MHz to 100 MHz
300
Idle state = 0 Hz
10
V
pF
mV
Timing Parameters
DIGITAL
INPUT/OUTPUT
Regular
Operation
Operating Frequency
FSMB
Free time between
Stop and Start Condition
tBUF
Hold time after Start or
Repeated Start condition
tHD:STA
Repeat Start Condition
Setup time
KHz
1.3
µs
0.6
µs
tSU:STA
0.6
µs
Stop Condition setup time
tSU:STO
0.6
µs
Data Hold time
tHD:DAT
300
ns
Data Setup time
tSU:DAT
100
ns
Clock low time out
tTIMEOUT
25
Clock low period
tLOW
1.3
Clock high period
tHIGH
0.6
Cumulative clock low
extend time
tLOW:SEXT
Clock or Data Fall time
tF
Clock or Data Rise time
tR
tLOW tR
SCL
First clock is generated
after this hold time
Measured from
(VIL_MAX - 0.15) to (VIH_MIN + 0.15)
0.9 • VVDD_IN_MAX to (VIL_MAX - 0.15)
tF
VIH
VIL
tHD,STA
tHD,DAT
tHIGH
tSU,DAT
tSU,STA
tSU,STO
SDA
VIH
VIL
tBUF
P
400
S
S
VIA BCM® Bus Converter
Rev 1.2
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Page 10 of 39
07/2015
800 927.9474
P
35
ms
µs
50
µs
25
ms
20
300
ns
20
300
ns
OUTPUT
INPUT
VOUT
+IN
L
VO
STARTUP
T
T
PU
IN
ON
ER
OV
LT
VO
OVER VOLTAGE
VIN_UVLO-
VIN_OVLO-
RN
U
T
VIN_OVLO+
U
TP
OU
VNOM
T
N
-O
tUVLO+_DELAY
VIN_UVLO+
VμC
I
UT
NP
GE
TA
N
UR
A
GE
VIA BCM® Bus Converter
Rev 1.2
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Page 11 of 39
07/2015
800 927.9474
tAUTO-RESTART
ENABLE CONTROL
OVER CURRENT
tWAIT ≥ tENABLE_OFF
tSCP
D D
AN N
IT
T
M MA
R
CU
M M
TA
R
O
I
S
C CO
C
RE
E
RT
T
B L BLE
O
U
A
A
P
S
SH
IN
D I EN
VO
L
GE
TA
SHUTDOWN
I
UT
NP
T
EN
EV
TU
FF
-O
N
R
BCM4914xD1E5135yzz
VIA BCM Bus Converter Timing diagram
BCM4914xD1E5135yzz
Application Characteristics
Product is mounted and temperature controlled VIA top side cold plate, unless otherwise noted. See associated figures for general trend data.
98.0
Full Load Efficiency (%)
18
16
14
12
10
8
Ò
ê
Ò
260
275
6ê
ê
Ò
ê
Ò
ê
Ò
ê
Ò
Ò
Ò
Ò
Ò
ê
ê
ê
ê
97.5
97.0
96.5
96.0
95.5
95.0
94.5
4
94.0
305
320
335
350
365
380
395
-40
410
-20
0
TCASE:
- 40°C
20°C
70°C
Ò
85°C
ê
40
60
80
100
260 V
400 V
410 V
Figure 5 — Full load efficiency vs. temperature; VIN
88
99
88
98
80
98
80
97
72
97
72
96
64
96
64
95
56
95
56
94
48
94
48
93
40
93
40
92
32
92
32
PD
91
24
Efficiency (%)
99
Power Dissipation (W)
Efficiency (%)
TCASE:
100°C
Figure 4 — No load power dissipation vs. VIN
91
90
16
89
8
89
88
0
88
0.0
3.5
7.0
260 V
400 V
16
8
0
0.0
10.5 14.0 17.5 21.0 24.5 28.0 31.5 35.0
24
PD
90
3.5
7.0
10.5 14.0 17.5 21.0 24.5 28.0 31.5 35.0
Load Current (A)
Load Current (A)
TCASE:
TCASE:
410 V
Figure 6 — Efficiency and power dissipation at TCASE = -40°C
260 V
400 V
410 V
Figure 7 — Efficiency and power dissipation at TCASE = 20°C
98
99
70
97
84
97
60
95
70
95
50
93
56
93
40
91
42
91
30
PD
89
28
87
14
85
0
0.0
3.5
7.0
10.5 14.0 17.5 21.0 24.5 28.0 31.5 35.0
Efficiency (%)
99
Power Dissipation (W)
Efficiency (%)
20
Case Temperature (°C)
Input Voltage (V)
PD
89
260 V
400 V
20
87
10
85
0
0.0
2.8
5.6
Load Current (A)
TCASE:
Power Dissipation (W)
290
8.4
11.2 14.0 16.8 19.6 22.4 25.2 28.0
Load Current (A)
VIN:
410 V
Figure 8 — Efficiency and power dissipation at TCASE = 70°C
260 V
400 V
410 V
Figure 9 — Efficiency and power dissipation at TCASE = 85°C
VIA BCM® Bus Converter
Rev 1.2
vicorpower.com
Page 12 of 39
07/2015
800 927.9474
Power Dissipation (W)
Power Dissipation (W)
20
BCM4914xD1E5135yzz
97
60
95
50
93
40
91
30
PD
89
20
87
10
85
0
0.0
1.8
3.6
5.4
7.2
9.0
10.8 12.6 14.4 16.2 18.0
40
ROUT (mΩ)
70
Power Dissipation (W)
Efficiency (%)
50
99
30
20
10
0
-40
-20
Load Current (A)
VIN:
260 V
400 V
0
20
40
60
80
100
Case Temperature (°C)
410 V
IOUT:
Figure 10 — Efficiency and power dissipation at TCASE = 100°C
35 A
Figure 11 — ROUT vs. temperature; Nominal VIN
Voltage Ripple (mVPK-PK)
250
200
150
100
50
0
0.0
3.5
7.0
10.5 14.0 17.5 21.0 24.5 28.0 31.5 35.0
Load Current (A)
VIN:
400 V
Figure 12 — VRIPPLE vs. IOUT ; No external COUT. Board mounted
module, scope setting : 20 MHz analog BW
Figure 13 — Full load ripple, 10 µF CIN; No external COUT. Board
mounted module, scope setting : 20 MHz analog BW
Figure 14 — 0 A– 35 A transient response:
CIN = 10 µF, no external COUT
Figure 15 — 35 A – 0 A transient response:
CIN = 10 µF, no external COUT
VIA BCM® Bus Converter
Rev 1.2
vicorpower.com
Page 13 of 39
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BCM4914xD1E5135yzz
Figure 16 — Start up from application of VIN = 400 V, 50% IOUT,
100% COUT
Marker 1 [T1]
Att 20 dB
53.07 dB V
339.00000000 kHz
INPUT 2
Det
MA Trd
Figure 17 — Start up from application of EN with pre-applied
VIN = 400 V, 50% IOUT, 100% COUT
Marker 1 [T1]
55022RED
Att 20 dB
ResBW
9 kHz
Meas T
20 ms Unit
dB V
10 MHz
1 [T1]
53.07 dB V
53.07 dB V
INPUT 2
328.00000000 kHz
100
100
1 MHz
1 MHz
Det
MA Trd
9 kHz
Meas T
20 ms Unit
dB V
10 MHz
1 [T1]
53.07 dB V
328.00000000 kHz
339.00000000 kHz
2 [T1]
90
80
45.84 dB V
1.09300000 MHz SGL
22QPA
55022RED
ResBW
1MA
2 [T1]
90
80
46.52 dB V
1.09000000 MHz SGL
22QPA
1MA
70
70
22QPB
22QPB
60
60
1
1
50
50
2
2
40
40
30
30
18.Apr 2015 12:55
20
Date:
150 kHz
30 MHz
18.APR.2015
Date:
12:55:46
Figure 18 — Typical EMI spectrum, Peak Scan, 10% load,
Nominal Input, Test circuit - See Filtering Section
Marker 1 [T1]
Att 20 dB
INPUT 2
57.72 dB V
150.00000000 kHz
100
18.Apr 2015 13:20
20
150 kHz
1 MHz
Det
MA Trd
18.APR.2015
Figure 19 — Typical EMI spectrum, Peak Scan, 50% load,
Nominal Input, Test circuit - See Filtering Section
55022RED
ResBW
9 kHz
Meas T
20 ms Unit
dB V
10 MHz
1 [T1]
57.72 dB V
150.00000000 kHz
2 [T1]
90
3 [T1]
47.82 dB V
1.08400000 MHz SGL
42.62 dB V
27.04000000 MHz
80
22QPA
1MA
70
22QPB
601
2
50
3
40
30
18.Apr 2015 14:19
20
150 kHz
Date:
18.APR.2015
30 MHz
13:20:35
30 MHz
14:19:26
Figure 20 — Typical EMI spectrum, Peak Scan, 90% load,
Nominal Input, Test circuit - See Filtering Section
VIA BCM® Bus Converter
Rev 1.2
vicorpower.com
Page 14 of 39
07/2015
800 927.9474
BCM4914xD1E5135yzz
General Characteristics
Specifications apply over all line, load conditions, unless otherwise noted; Boldface specifications apply over the temperature range of -40°C ≤ TCASE
≤ 100°C (T-Grade); All other specifications are at TCASE = 20ºC unless otherwise noted.
Attribute
Symbol
Conditions / Notes
Min
Typ
Max
Unit
Mechanical
Length
L
Lug Mount
124.52 / [4.90] 124.77 / [4.91] 125.02 / [4.92] mm / [in]
Length
L
PCB Mount
126.73 / [4.99] 126.98 / [5.00] 127.23 / [5.01] mm / [in]
Width
W
35.29 / [1.39]
35.54 / [1.40]
35.79 / [1.41]
mm / [in]
Height
H
9.05 / [0.36]
9.30 / [0.37]
9.55 / [0.38]
mm / [in]
Volume
Vol
Weight
W
Without heatsink
41.24 / [2.52]
cm3/ [in3]
156 / [5.5]
g / [oz]
Pin Material
C145 copper, 1/2 hard
Underplate
Low stress ductile Nickel
50
100
Palladium
0.8
6
Soft Gold
0.12
2
BCM4914xD1E5135yzz (T-Grade)
-40
125
BCM4914xD1E5135yzz (C-Grade)
-20
125
BCM4914VD1E5135T02 (T-Grade),
derating applied, see safe thermal
operating area
-40
100
BCM4914xD1E5135yzz (C-Grade),
derating applied, see safe thermal
operating area
-20
100
Pin Finish
µin
µin
Thermal
Operating junction temperature
Operating case temperature
Thermal resistance top side
Thermal Resistance Coupling between
top case and bottom case
Thermal resistance bottom side
TINTERNAL
TCASE
RJC-TOP
RHOU
RJC-BOT
°C
Estimated thermal resistance to
maximum temperature internal
component from isothermal top
1.52
°C/W
Estimated thermal resistance of thermal
coupling between the top and bottom
case surfaces
0.26
°C/W
Estimated thermal resistance to
maximum temperature internal
component from isothermal bottom
1.55
°C/W
32
Ws/°C
Thermal capacity
Assembly
Storage Temperature
TST
BCM4914xD1E5135yzz (T-Grade)
-40
125
°C
BCM4914xD1E5135yzz (C-Grade)
-40
125
°C
ESDHBM
Human Body Model,
"ESDA / JEDEC JDS-001-2012" Class I-C
(1kV to < 2 kV)
1000
ESDCDM
Charge Device Model,
"JESD 22-C101-E" Class II (200V to <
500V)
200
ESD Withstand
VIA BCM® Bus Converter
Rev 1.2
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BCM4914xD1E5135yzz
General Characteristics (Cont.)
Specifications apply over all line, load conditions, unless otherwise noted; Boldface specifications apply over the temperature range of -40°C ≤ TCASE
≤ 125°C (T-Grade); All other specifications are at TCASE = 20ºC unless otherwise noted.
Attribute
Symbol
Conditions / Notes
Min
Typ
Max
Unit
780
940
pF
Safety
Isolation capacitance
CIN_OUT
Unpowered unit
620
Isolation resistance
RIN_OUT
At 500 Vdc
10
MTBF
MΩ
MIL-HDBK-217Plus Parts Count - 25°C
Ground Benign, Stationary, Indoors /
Computer
3.53
MHrs
Telcordia Issue 2 - Method I Case III;
25°C Ground Benign, Controlled
3.90
MHrs
cTÜVus "EN 60950-1"
Agency approvals / standards
cURus "UL 60950-1"
CE Marked for Low Voltage Directive and RoHS Recast Directive, as applicable
EMI/EMC Compliance
FCC Part 15, EN55022,
CISPR22:2006+A1:2007,
Conducted Emissions
Class B Limits - with components connected as shown in Filtering Section
VIA BCM® Bus Converter
Rev 1.2
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Page 16 of 39
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800 927.9474
BCM4914xD1E5135yzz
System Diagram
5V
EXT_BIAS
SCL
VIA
BCM
SCL
SDA
SDA
SGND
Host
PMBus™
SGND
ADDR
The VIA BCM bus converter provides accurate telemetry monitoring and reporting, threshold and warning limits adjustment, in
addition to corresponding status flags.
The VIA BCM internal µC is referenced to secondary ground.
The VIA BCM provides the host system µC with access to standalone VIA BCM. The standalone VIA BCM is constantly polled for
status by the internal µC. Direct communication to VIA BCM is enabled by a page command. For example, the page (0x00) prior to a
telemetry inquiry points to the internal µC data and pages (0x01) prior to a telemetry inquiry points to the VIA BCM connected data.
The VIA BCM constantly polls it’s data through the PMBusTM.
The VIA BCM enables the PMBus compatible host interface with an operating bus speed of up to 400 kHz. The VIA BCM follows the
PMBus command structure and specification.
VIA BCM® Bus Converter
Rev 1.2
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Page 17 of 39
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BCM4914xD1E5135yzz
PMBusTM Interface
Where:
Refer to “PMBus Power System Management Protocol
SpeciﬁcationRevision 1.2, Part I and II” for complete PMBus
speciﬁcations details visit http://pmbus.org.
X, is a “real world” value in units (A, V, °C, s)
Y, is a two’s complement integer received from the internal μC
m, b and R are two’s complement integers deﬁned as follows:
Command
Device Address
The PMBus address (ADDR Pin) should be set to one of a
predetermined 16 possible addresses shown in the table below using a
resistor between ADDR pin and SGND pin.
The VIA BCM accepts only a ﬁxed and persistent address and does not
support SMBus address resolution protocol. At initial power-up, the
VIA BCM internal μC will sample the address pin voltage, and will hold
this address until device power is removed.
ID
Slave
Address
HEX
Recommended
Resistor RADDR (Ω)
1
1010 000b
50h
487
2
1010 001b
51h
1050
3
1010 010b
52h
1870
4
1010 011b
53h
2800
5
1010 100b
54h
3920
6
1010 101b
55h
5230
7
1010 110b
56h
6810
8
1010 111b
57h
8870
9
1011 000b
58h
11300
10
1011 001b
59h
14700
11
1011 010b
5Ah
19100
12
1011 011b
5Bh
25500
13
1011 100b
5Ch
35700
14
1011 101b
5Dh
53600
15
1011 110b
5Eh
97600
16
1011 111b
5Fh
316000
Code
m
R
b
TON_DELAY
60h
1
3
0
READ_VIN
88h
1
1
0
READ_IIN
89h
1
3
0
READ_VOUT
8Bh
1
1
0
READ_IOUT
8Ch
1
2
0
READ_TEMPERATURE_1
8Dh
1
0
0
READ_POUT
96h
1
0
0
MFR_VIN_MIN
A0h
1
0
0
MFR_VIN_MAX
A1h
1
0
0
MFR_VOUT_MIN
A4h
1
0
0
MFR_VOUT_MAX
A5h
1
0
0
MFR_IOUT_MAX
A6h
1
0
0
MFR_POUT_MAX
A7h
1
0
0
READ_K_FACTOR
D1h
65536
0
0
READ_BCM_ROUT
D4h
1
2
0
[1] Default READ Output Voltage returned when VIA BCM unit is disabled = -300 V.
[2] Default
READ Temperature returned when VIA BCM unit is disabled = -273°C.
No special formatting is required when lowering the supervisory limits
and warnings.
Reported DATA Formats
The VIA BCM internal μC employs a direct data format where all
reported internal μC measurements are in Volts, Amperes, Degrees
Celsius, or Seconds. The host uses the following PMBus speciﬁcation to
interpret received values metric preﬁxes. Note that the Coefficients
command is not supported:
X=
(
1
m
)
• (Y • 10-R - b)
VIA BCM® Bus Converter
Rev 1.2
vicorpower.com
Page 18 of 39
07/2015
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BCM4914xD1E5135yzz
Supported Command List
Command
Code
Function
Default Data Content
Data Bytes
PAGE
00h
Access VIA BCM stored information for all connected
devices
00h
1
OPERATION
01h
Turn VIA BCMs on or off
80h
1
ON_OFF_CONFIG
02h
Defines startup when power is applied as well
as immediate on/off control over the VIA BCMs
1Dh
1
CLEAR_FAULTS
03h
Clear all VIA BCM and all internal µC faults
N/A
None
CAPABILITY
19h
Internal µC PMBusTM key capabilities set by factory
20h
1
OT_FAULT_LIMIT
4Fh[1]
VIA BCM over temperature protection
64h
2
OT_WARN_LIMIT
51h[1]
VIA BCM over temperature warning
64h
2
VIN_OV_FAULT_LIMIT
55h[1]
VIA BCM VIN overvoltage warning
64h
2
VIN_OV_WARN_LIMIT
57h[1]
VIA BCM VIN overvoltage protection
64h
2
IIN_OC_FAULT_LIMIT
5Bh[1]
VIA BCM IOUT overcurrent protection
64h
2
IIN_OC_WARN_LIMIT
5Dh[1]
VIA BCM IOUT overcurrent warning
64h
2
TON_DELAY
60h[1]
Startup delay additional to any VIA BCM fixed delays
00h
2
STATUS_BYTE
78h
Summary of VIA BCM faults
00h
1
STATUS_WORD
79h
Summary of VIA BCM fault conditions
00h
2
STATUS_IOUT
7Bh
VIA BCM overcurrent fault status
00h
1
STATUS_INPUT
7Ch
VIA BCM overvoltage and under voltage fault status
00h
1
7Dh
VIA BCM over temperature and under temperature
fault status
00h
1
STATUS_CML
7Eh
Internal µC PMBus Communication fault
00h
1
STATUS_MFR_SPECIFIC
80h
Other VIA BCM status indicator
00h
1
READ_VIN
88h
VIA BCM input voltage
FFFFh
2
READ_IIN
89h
VIA BCM input current
FFFFh
2
READ_VOUT
8Bh
VIA BCM output voltage
FFFFh
2
READ_IOUT
8Ch
VIA BCM output current
FFFFh
2
READ_TEMPERATURE_1
8Dh
VIA BCM temperature
FFFFh
2
READ_POUT
96h
VIA BCM output power
FFFFh
2
PMBUS_REVISION
98h
Internal µC PMBus compatible revision
22h
1
MFR_ID
99h
Internal µC ID
"VI"
2
MFR_MODEL
9Ah
Internal µC or VIA BCM model
Part Number
18
FW and HW revision
18
“AP”
2
STATUS_TEMPERATURE
MFR_REVISION
9Bh
Internal µC or VIA BCM revision
MFR_LOCATION
9Ch
Internal µC or VIA BCM factory location
MFR_DATE
9Dh
Internal µC or VIA BCM manufacturing date
MFR_SERIAL
9Eh
Internal µC or VIA BCM serial number
MFR_VIN_MIN
A0h
MFR_VIN_MAX
A1h
MFR_VOUT_MIN
"YYWW"
4
Serial Number
16
VIA BCM Minimum rated VIN
Varies per VIA BCM
2
VIA BCM Maximum rated VIN
Varies per VIA BCM
2
A4h
VIA BCM Minimum rated VOUT
Varies per VIA BCM
2
MFR_VOUT_MAX
A5h
VIA BCM Maximum rated VOUT
Varies per VIA BCM
2
MFR_IOUT_MAX
A6h
VIA BCM Maximum rated IOUT
Varies per VIA BCM
2
MFR_POUT_MAX
A7h
VIA BCM Maximum rated POUT
Varies per VIA BCM
2
02h
1
BCM_EN_POLARITY
[1]
D0h[1]
Set VIA BCM EN pin polarity
READ_K_FACTOR
D1h
VIA BCM K factor
Varies per VIA BCM
2
READ_BCM_ROUT
D4h
VIA BCM Rout
Varies per VIA BCM
2
646464646464h
6
00h
2
SET_ALL_THRESHOLDS
D5h[1]
Set VIA BCM supervisory warning and protection
thresholds
DISABLE_FAULT
D7h[1]
Disable VIA BCM overvoltage, overcurrent or
under voltage supervisory faults
The VIA BCM must be in a disabled state during a write message.
VIA BCM® Bus Converter
Rev 1.2
vicorpower.com
Page 19 of 39
07/2015
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BCM4914xD1E5135yzz
Command Structure Overview
Write Byte protocol:
The Host always initiates PMBusTM communication with a START bit. All messages are terminated by the Host with a STOP bit. In a write message,
the master sends the slave device address followed by a write bit. Once the slave acknowledges, the master proceeds with the command code and
then similarly the data byte.
1
7
1
1
S
Slave Address
Wr
A
x=0
x=0
8
Command Code
1
8
1
1
A
Data Byte
A
P
x=0
x=0
S
Start Condition
Sr
Repeated start Condition
Rd
Read
Wr
Write
X
Indicated that field is required to have the value of x
A
Acknowledge (bit may be 0 for an ACK or 1 for a NACK)
P
Stop Condition
From Master to Slave
From Slave to Master
…
Continued next line
Figure 1 — PAGE COMMAND (00h), WRITE BYTE PROTOCOL
Read Byte protocol:
A Read message begins by ﬁrst sending a Write Command, followed by a REPEATED START Bit and a slave Address. After receiving the READ bit, the
internal μC begins transmission of the Data responding to the Command. Once the Host receives the requested Data, it terminates the message with
a NACK preceding a stop condition signifying the end of a read transfer.
1
7
1
1
S
Slave Address
Wr
A
x=0
x=0
8
Command Code
1
1
7
A Sr Slave Address
x=0
1
1
Rd
A
x=1
x=0
8
Data Byte
Figure 2 — ON_OFF_CONFIG COMMAND (02h), READ BYTE PROTOCOL
VIA BCM® Bus Converter
Rev 1.2
vicorpower.com
Page 20 of 39
07/2015
800 927.9474
1
1
A
P
x=1
BCM4914xD1E5135yzz
Write Word protocol:
When transmitting a word, the lowest order byte leads the highest order byte. Furthermore, when transmitting a Byte, the least signiﬁcant bit (LSB)
is sent last. Refer to System Management Bus (SMBus) speciﬁcation version 2.0 for more details.
Note: Extended command and Packet Error Checking Protocols are not supported.
1
7
1
1
S
Slave Address
Wr
A
x=0
x=0
8
1
8
A
Command Code
1
Data Byte Low
x=0
8
A
Data Byte High
x=0
1
1
A
P
x=0
Figure 3 — TON_DELAY COMMAND (60h)_WRITE WORD PROTOCOL
Read Word protocol:
1
7
1
1
S
Slave Address
Wr
A
x=0
x=0
8
1
Command Code
1
7
A Sr Slave Address
x=0
1
1
Rd
A
x=1
x=0
8
1
Data Byte Low
A
x=0
Figure 4 — MFR_VIN_MIN COMMAND (A0h)_READ WORD PROTOCOL
Write Block protocol:
1
7
1
1
S
Slave Address
Wr
A
x=0
x=0
8
Data Byte 2
1
A
x=0
...
...
...
8
1
8
Byte Count = N
A
Command Code
x=0
8
Data Byte N
1
A
8
Data Byte 1
x=0
1
1
A
P
1
A
x=0
x=0
Figure 5 — SET_ALL_THRESHOLDS COMMAND (D5h)_WRITE BLOCK PROTOCOL
VIA BCM® Bus Converter
Rev 1.2
vicorpower.com
Page 21 of 39
07/2015
800 927.9474
...
8
Data Byte High
1
1
A
P
x=1
BCM4914xD1E5135yzz
Read Block protocol:
1
7
1
1
S
Slave Address
Wr
A
x=0
x=0
1
8
Data Byte 1
8
1
7
x=0
8
A
1
1
Data Byte 2
A
x=0
x=0
1
1
Rd
A
x=1
x=0
A Sr Slave Address
Command Code
...
...
...
8
Data Byte N
1
1
A
P
8
1
Data Byte = N
A
x=0
x=1
Figure 6 — SET_ALL_THRESHOLDS COMMAND (D5h)_READ BLOCK PROTOCOL
Write Group Command protocol:
Note that only one command per device is allowed in a group command.
1
7
1
1
S
Slave Address
Wr
A
Command Code
A
First Device
x=0
x=0
First Command
x=0
1
7
Sr Slave Address
Second Device
1
7
Sr Slave Address
Nth Device
8
8
1
1
1
Wr
A
Command Code
A
x=0
x=0
Second Command
x=0
8
8
Data Byte Low
1
1
1
Wr
A
Command Code
A
x=0
x=0
Nth Command
x=0
8
Data Byte Low
1
8
Data Byte Low
1
8
1
A
Data Byte High
A
x=0
One or more Data Bytes
x=0
1
8
1
A
Data Byte High
A
x=0
One or more Data Bytes
x=0
1
8
...
...
1
A
Data Byte High
A
x=0
One or more Data Bytes
x=0
Figure 7 — DISABLE_FAULT COMMAND (D7h)_WRITE
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Supported Commands Transaction type
Page Command (00h)
A direct communication to the VIA BCM internal μC and a simulated
communication to non-PMBus™ devices is enabled by a page
command. Supported command access privileges with a pre-selected
PAGE are deﬁned in the following table. Deviation from this table
generates a communication error in STATUS_CML register.
The page command data byte of 00h prior to a command call will
address the internal μC speciﬁc data and a page data byte of FFh would
broadcast to all of the connected VIA BCMs. The value of the Data Byte
corresponds to the pin name trailing number with the exception of 00h
and FFh.
Command
Code
PAGE Data Byte
Access Type
00h
01h
PAGE
00h
R/W
R/W
OPERATION
01h
R
R/W
ON_OFF_CONFIG
02h
CLEAR_FAULTS
03h
W
W
CAPABILITY
19h
R
OT_FAULT_LIMIT
4Fh
R/W
OT_WARN_LIMIT
51h
R/W
VIN_OV_FAULT_LIMIT
55h
R/W
VIN_OV_WARN_LIMIT
57h
R/W
IIN_OC_FAULT_LIMIT
5Bh
R/W
IIN_OC_WARN_LIMIT
5Dh
R/W
TON_DELAY
60h
STATUS_BYTE
78h
R/W
STATUS_WORD
79h
R
R
STATUS_IOUT
7Bh
R
R/W
STATUS_INPUT
7Ch
R
R/W
STATUS_TEMPERATURE
7Dh
R
R/W
STATUS_CML
7Eh
R/W
STATUS_MFR_SPECIFIC
80h
R
READ_VIN
88h
READ_IIN
89h
READ_VOUT
8Bh
READ_IOUT
8Ch
R
R
READ_TEMPERATURE_1
8Dh
R
R
READ_POUT
96h
R
R
PMBUS_REVISION
98h
R
MFR_ID
99h
R
MFR_MODEL
9Ah
R
R
MFR_REVISION
9Bh
R
R
MFR_LOCATION
9Ch
R
R
MFR_DATE
9Dh
R
R
MFR_SERIAL
9Eh
R
R
MFR_VIN_MIN
A0h
R
R
MFR_VIN_MAX
A1h
R
R
MFR_VOUT_MIN
A4h
R
R
MFR_VOUT_MAX
A5h
R
R
MFR_IOUT_MAX
A6h
R
R
MFR_POUT_MAX
A7h
R
VIA BCM_EN_POLARITY
D0h
R/W
READ_K_FACTOR
D1h
R
READ_VIA BCM_ROUT
D4h
R
SET_ALL_THRESHOLDS
D5h
R/W
DISABLE_FAULT
D7h
R/W
R
Data Byte
Description
00h
µC
01h
VIA BCM
OPERATION Command (01h)
The Operation command can be used to turn on and off the connected
VIA BCM. Note that the host OPERATION command will not enable the
VIA BCM if the VIA BCM EN pin is disabled in hardware with respect to
the pre-set pin polarity. Only with the EN pin active, will the
OPERATION command provide ON/OFF control.
If synchronous startup is required in the system, it is recommended to
use the command from host PMBus in order to achieve simultaneous
array startup.
R/W
R
Unit is On when asserted (default)
Reserved
R/W
R
R
7
6
5
4
3
2
1
0
1
0
0
0
0
0
0
0
b
R
R
This command accepts only two data values: 00h and 80h. If any other
value is sent the command will be rejected and a CML Data error will
result.
R
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ON_OFF_CONFIG Command (02h)
OT_FAULT_LIMIT Command (4Fh),
OT_WARN_ LIMIT Command (51h),
VIN_OV_FAULT_ LIMIT Command (55h),
VIN_OV_WARN_ LIMIT Command (57h),
IIN_OC_FAULT_ LIMIT Command (5Bh),
IIN_OC_WARN_ LIMIT Command (5Dh)
Reserved for Future Use
Unit does not power up until commanded by the
CONTROL pin and operation command
Unit requires that that the on/off portion of the
OPERATION command is instructing the unit to run[1]
Unit requires the CONTROL pin to be asserted
to start the unit[2]
Not supported: Polarity of the CONTROL pin
[3]
Turn off the output and stop transferring
energy to the output as fast as possible[4]
7
6
5
4
3
2
1
0
0
0
0
1
1
1
0
1
b
[1]
The VIA BCM Enable pin is ALWAYS to be asserted for powerup. The
BCM_EN_POLARITY command (D0h) bit[(1) defines the logic level
required for the control pin (i.e VIA BCM Enable pin) to be asserted.
[2] With respect to the VIA BCM EN Control Pin if used in system
[3] See MFR_SPECIFIC_00 / VIA BCM_EN_POLARITY to change the Polarity of
the VIA BCM Enable Pin
[4] The VIA BCM powertrain once disabled cannot sink current
CLEAR_FAULTS Command (03h)
This command clears all status bits that have been previously set.
Persistent or active faults are re-asserted again once cleared. All faults
are latched once asserted in the internal μC. Registered faults will not
be cleared when shutting down the VIA BCM powertrain by recycling
the VIA BCM input voltage, or toggling the VIA BCM EN pin, or sending
the OPERATION command.
CAPABILITY Command (19h)
The values of these registers are set in non-volatile memory and can
only be written when the VIA BCMs are disabled.
The values of the above mentioned fault and warning are set by default
to a 100% of the respective VIA BCM model supervisory limits.
However these limits can be set to a lower value. For example: In order
for a limit percentage to be set to 80% one would send a write
command with a (50h) Data Word.
Any values outside the range of (00h – 64h) sent by a host will be
rejected, will not override the currently stored value and will set the
Unsupported Data bit in STATUS_CML.
The SET_ALL_THRESHOLDS COMMAND (D5h) combines in one block
over temperature fault and warning limits, VIN overvoltage fault and
warning limits as well as IOUT overcurrent fault and warning limits. A
delay prior to a read command of up to 200 ms following a write of new
value is required.
The VIN_UV_WARN_LIMIT (58h) and VIN_UV_FAULT_LIMIT (59h) are
set by the factory and cannot be changed by the host. However, a host
can disable the under voltage setting using the DISABLE_FAULT
COMMAND (D7h).
All FAULT_RESPONSE commands are unsupported. The VIA BCM
powertrain supervisory limits and powertrain protection will behave as
described in the VIA BCM datasheet. In general, once a fault is detected,
the VIA BCM powertrain will shut down and attempt to auto-restart
after a predetermined delay.
TON_DELAY Command (60h)
The value of this register word is set in non-volatile memory and can
only be written when the VIA BCMs are disabled.
Packet Error Checking is not supported
Maximum supported bus speed is 400 KHz
The Device does not have SMBALERT# pin and does
not support the SMBus Alert Response protocol
Reserved
7
6
5
4
3
2
1
0
0
0
1
0
0
0
0
0
The maximum possible delay is 100ms. Default value is set to (00h).
Follow this equation below to interpret the reported value.
TON_DELAYACTUAL = tREPORTED • 10 -3(s)
Staggering startup in an array is possible with TON_DELAY Command.
This delay will be in addition to any startup delay inherent in the VIA
BCM module. For example: startup delay from application of VIN is
typically 20 ms whereas startup with EN pin is typically 250 us. When
TON_DELAY is greater than zero, the set delay will be added to both.
b
The internal μC returns a default value of 20h. This value indicates that
the PMBusTM frequency supported is up to 400 KHz and that both
Packet Error Checking (PEC) and SMBALERT# are
not supported.
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STATUS_BYTE (78h) and STATUS_WORD (79h)
STATUS_WORD
High Byte
Low Byte
STATUS_BYTE
UNIT IS BUSY
Not Supported: UNKNOWN FAULT OR WARNING
UNIT IS OFF
Not Supported: OTHER
Not Supported: VOUT_OV_FAULT
Not Supported: FAN FAULT OR WARNING
IOUT_OC_FAULT
POWER_GOOD Negated*
VIN_UV_FAULT
STATUS_MFR_SPECIFIC
TEMPERATURE FAULT OR WARNING
INPUT FAULT OR WARNING
PMBusTM COMMUNCATION EVENT
IOUT/POUT FAULT OR WARNING
Not Supported: VOUT FAULT OR WARNING
NONE OF THE ABOVE
7
6
5
4
3
2
1
0
7
0
1
1
1
1
0
0
0
1
6
1
5
0
4
1
3
2
1
1
1
0
1
0
b
* equal to POWER_GOOD#
All fault or warning ﬂags, if set, will remain asserted until cleared by
the host or once the internal μC power is removed. This includes under
voltage fault, overvoltage fault, overvoltage warning, overcurrent
warning, over temperature fault, over temperature warning, under
temperature fault, reverse operation, communication faults and analog
controller shutdown fault.
Asserted status bits in all status registers, with the exception of
STATUS_WORD and STATUS_BYTE, can be individually cleared. This is
done by sending a data byte with one in the bit position corresponding
to the intended warning or fault to be cleared. Refer to the PMBus™
Power System Management Protocol Speciﬁcation – Part II – Revision
1.2 for details.
The POWER_GOOD# bit reﬂects the state of the device and does not
reﬂect the state of the POWER_GOOD# signal limits. The
POWER_GOOD_ON COMMAND (5Eh) and POWER_GOOD_OFF
COMMAND (5Fh) are not supported. The POWER_GOOD# bit is set
anytime the VIA BCM is not in the enabled state, to indicate that the
powertrain is inactive and not switching. The POWER_GOOD# bit is
cleared when the VIA BCM completes the enabling state, 5 ms after the
powertrain is activated allowing for soft-start to elapse.
POWER_GOOD# and OFF bits cannot be cleared as they always reﬂect
the current state of the device.
If the internal μC is still powered, it will retain the last status it received
from the VIA BCM and this information will be available to the user via
a PMBus Status request. This is in agreement with the PMBus standard
which requires that status bits remain set until speciﬁcally cleared.
Note that in this case where the VIA BCM VIN is lost, the status will
always indicate an under voltage fault, in addition to any other fault
that occurred.
NONE OF THE ABOVE bit will be asserted if either the
STATUS_MFR_SPECIFIC (80h) or the High Byte of the STATUS WORD is
set.
STATUS_IOUT (7Bh)
IOUT_OC_FAULT
Not Supported: IOUT_OC_LV_FAULT
IOUT_OC_WARNING
Not Supported: IOUT_UC_FAULT
Not Supported: Current Share Fault
Not Supported: In Power Limiting Mode
Not Supported: POUT_OP_FAULT
When Page (00h) is used the POWER_GOOD# bit reﬂects the OR-ing of
all active VIA BCMs’ POWER_GOOD# bits. When Page (01h – 04h) is
used POWER_GOOD# is clear only when the VIA BCM is active.
When Page (00h) is used UNIT IS OFF is SET when all VIA BCMs are not
active. When Page (01h – 04h) is used UNIT IS OFF is clear only when
the VIA BCM is active.
The Busy bit can be cleared using CLEAR_ALL Command (03h) or by
writing either data value (40h, 80h) to PAGE (00h) using the
STATUS_BYTE (78h).
Not Supported: POUT_OP_WARNING
7
6
5
4
3
2
1
0
1
0
0
1
0
0
0
0
b
Unsupported bits are indicated above. A one indicates a fault.
Fault reporting, such as SMBALERT# signal output, and host
notiﬁcation by temporarily acquiring bus master status is not
supported.
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The STATUS_CML data byte will be asserted when an unsupported
PMBusTM command or data or other communication fault occured.
STATUS_INPUT (7Ch)
STATUS_MFR_SPECIFIC (80h)
VIN_OV_FAULT
VIN_OV_WARNING
Not Supported: VIN_UV_WARNING
Reserved
VIN_UV_FAULT
PAGE Data Byte = (01h - 04h)
Reserved
Not Supported: Unit Off For Insufficient
Input Voltage
Reserved
Reserved
Not Supported: IIN_OC_FAULT
Reserved
Not Supported: IIN_OC_WARNING
BCM UART CML
Not Supported: PIN_OP_WARNING
Analog Controller Shutdown Fault
7
6
5
4
3
2
1
0
1
1
0
1
0
0
0
0
BCM Reverse Operation
b
Unsupported bits are indicated above. A one indicates a fault.
7
6
5
4
3
2
1
0
0
0
0
0
0
1
1
1
b
STATUS_TEMPERATURE (7Dh)
The reverse operation bit, if asserted, indicates that the VIA BCM is
processing current in reverse. Reverse current reported value is
not supported.
OT_FAULT
OT_WARNING
The VIA BCM has analog protections and internal μC protections. The
analog controller provides an additional layer of protection and has the
fastest response time. The analog controller shutdown fault, when
asserted, indicates that at least one of the powertrain protection faults is
triggered. This fault will also be asserted if a disabled fault event occurs
after asserting any bit using the DISABLE_FAULTS COMMAND.
Not Supported: UT_WARNING
UT_FAULT
Reserved
Reserved
Reserved
The VIA BCM UART is designed to operate with the internal μC UART. If
the VIA BCM UART CML is asserted, it may indicate a hardware or
connection issue between both devices.
Reserved
7
6
5
4
3
2
1
0
1
1
0
1
0
0
0
0
b
BCM at PAGE (04h) is present
PAGE Data Byte = (00h)
BCM at PAGE (03h) is present
Unsupported bits are indicated above. A one indicates a fault.
BCM at PAGE (02h) is present
BCM at PAGE (01h) is present
STATUS_CML (7Eh)
Reserved
BCM UART CML
Invalid Or Unsupported Command Received
Analog Controller Shutdown Fault
Invalid Or Unsupported Data Received
BCM Reverse Operation
Not Supported: Packet Error Check Failed
Not Supported: Memory Fault Detected
Not Supported: Processor Fault Detected
7
6
5
4
3
2
1
0
1
1
1
1
0
1
1
1
b
Reserved
Other Communication Faults
Not Supported: Other Memory Or Logic
Fault
7
6
5
4
3
2
1
0
1
1
0
0
0
0
1
0
b
Unsupported bits are indicated above. A one indicates a fault.
When PAGE COMMAND (00h) data byte is equal to (00h), the the BCM
Reverse operation, Analog Controller Shutdown Fault, and BCM UART
CML bit will return OR-ing result of active BCMs. The BCM UART CML
will also be asserted if any of the active BCMs stops responding. The
BCM must communicate at least once to the internal μC in order to
trigger this FAULT. The BCM UART CML can be cleared from the culprit
BCM once the internal μC is able to communicate with it once again or
can be cleared using PAGE (00h) CLEAR_FAULTS (03h) Command.
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READ_VIN Command (88h)
READ_POUT Command (96h)
If PAGE data byte is equal to (01h - 04h) command will return a
reported individual VIA BCM’s input voltage in the following format:
If PAGE data byte is equal to (01h - 04h) command will return a
reported individual VIA BCM's output power in the following format:
VVIN_ACTUAL = VVIN_REPORTED • 10 -1(V)
POUTACTUAL = POUTREPORTED (W)
If PAGE data byte is equal to (00h) command will return the sum of
active VIA BCMs’ ouput power.
READ_IIN Command (89h)
If PAGE data byte is equal to (01h - 04h) command will return a
reported individual VIA BCM's input current in the following format:
IIIN_ACTUAL = IIIN_REPORTED • 10 -3(A)
If PAGE data byte is equal (00h) command will return the sum of active
VIA BCMs’ input current.
MFR_VIN_MIN Command (A0h),
MFR_VIN_MAX Command (A1h),
MFR_VOUT_MIN Command (A4h),
MFR_VOUT_MAX Command (A5h),
MFR_IOUT_MAX Command (A6h),
MFR_POUT_MAX Command (A7h)
These values are set by the factory and indicate the device input output
voltage and output current range and output power capacity.
READ_VOUT Command (8Bh)
If PAGE data byte is equal to (01h - 04h) command will return a
reported individual VIA BCM's output voltage in the following format:
VVOUT_ACTUAL = VVOUT_REPORTED • 10 -1(V)
The internal μC will report rated VIA BCM input voltage minimum and
maximum in Volts, output voltage minimum and maximum in Volts,
output current maximum in Amperes and output power maximum in
Watts.
If PAGE data byte is equal to (00h) then:
n MFR_VIN_MIN COMMAND (A0h) will return the highest
MFR_VIN_MIN of all active VIA BCMs
READ_IOUT Command (8Ch)
n MFR_VIN_MAX COMMAND (A1h) will return the lowest
If PAGE data byte is equal to (01h - 04h) command will return a
reported individual VIA BCM's output current in the following format:
n MFR_VOUT_MIN COMMAND (A4h) will return the highest
MFR_VIN_MAX of all active VIA BCMs
MFR_VOUT_MIN of all active VIA BCMs
n MFR_VOUT_MAX COMMAND (A5h) will return the lowest
IIOUT_ACTUAL = IIOUT_REPORTED • 10 -2(A)
MFR_VOUT_MAX of all active VIA BCMs
n MFR_IOUT_MAX COMMAND (A6h) will return the SUM of
If PAGE data byte is equal (00h) command will return the sum of active
VIA BCMs’ output current.
MFR_IOUT_MAX of all active VIA BCMs
n MFR_POUT_MAX COMMAND (A7h) will return the SUM of
MFR_POUT_MAX of all active VIA BCMs
READ_TEMPERATURE_1 Command (8Dh)
If PAGE data byte is equal to (01h - 04h) command will return a
reported individual VIA BCM's temperature in the following format:
TACTUAL = ±TREPORTED (°C)
If PAGE data byte is equal (00h) command will return the maximum
temperature of active VIA BCMs.
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BCM_EN_POLARITY Command (D0h)
SET_ALL_THRESHOLDS Command (D5h)
Reserved
SET_ALL_THRESHOLDS_BLOCK (6 Bytes)
Reserved
IOUT_OC_WARN_ LIMIT
Reserved
IOUT_OC_FAULT_ LIMIT
Reserved
VIN_OV_WARN_ LIMIT
Reserved
VIN_OV_FAULT_ LIMIT
Reserved
OT_WARN_LIMIT
BCM EN Pin Polarity
OT_FAULT_LIMIT
Reserved
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
0
5
4
3
2
1
0
64 64 64 64 64 64
b
h
The value of this register is set in non-volatile memory and can only be
written when the BCMs are disabled.
Values of this register block is set in non-volatile memory and can only
be written when the BCMs are disabled.
When PAGE COMMAND (00h) data byte is equal to (01h – 04h), this
command deﬁnes the polarity of the EN pin. If BCM_EN_POLARITY is
set, the BCM will startup once VIN is greater than the under
voltage threshold.
This command provides a convenient way to conﬁgure all the limits, or
any combination of limits described previously using one command.
The BCM EN PIN is internally pulled-up to 3.3V. If the
BCM_EN_POLARITY is cleared, an external pull-down is then required.
Applying VIN greater than the under voltage threshold will not suffice
to start the BCM.
Vin Overvoltage, Overcurrent and over-Temperature values are all set
to 100% of the BCM datasheet supervisory limits by default and can
only be set to a lower percentage.
To leave a particular threshold unchanged, set the corresponding
threshold data byte to a value greater than (64h).
DISABLE_FAULT Command (D7h)
READ_K_FACTOR Command (D1h)
If PAGE data byte is equal to (01h - 04h) command will return a
reported individual BCM's K factor in the following format:
DISABLE_FAULT
MSB
K_FACTORACTUAL = K_FACTORREPORTED • 2 -16(V/V)
LSB
Reserved
Reserved
Reserved
Reserved
IOUT_OC_FAULT
Reserved
Reserved
The K factor is deﬁned in a BCM to represent the ratio of the
transformer winding and hence is equal to VOUT / VIN.
Reserved
VIN_OV_FAULT
Reserved
Reserved
Reserved
VIN_UV_FAULT
READ_BCM_ROUT Command (D4h)
Reserved
Reserved
If PAGE data byte is equal to (01h - 04h) command will return a
reported individual BCM's output resistance in the following format:
Reserved
7
6
5
4
3
2
1
0
0
1
0
0
0
0
0
0
7
0
6
0
5
1
4
0
3
1
2
0
1
0
0
0
b
BCM_ROUTACTUAL = BCM_ROUTREPORTED • 10 -5(Ω)
Unsupported bits are indicated above. A one indicates that the
supervisory fault associated with the asserted bit is disabled.
The value of these registers is set in non-volatile memory and can only
be written when the BCMs are disabled.
This command allows the host to disable the supervisory faults and
respective statuses. It does not disable the powertrain analog
protections or warnings with respect to the set limits in the
SET_ALL_THRESHOLDS Command.
The input under-voltage can only be disabled to a pre-set low limit as
shown in the functional reporting range in the BCM data sheet.
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3. The internal μC unsupported PMBus command code response as
described in the Fault Management and Reporting:
The internal µC Implementation vs.
PMBusTM Specification Rev 1.2
n Deviations from the PMBus speciﬁcation:
The internal μC is an I2C compliant, SMBus™ compatible device and
PMBus command compliant device. This section denotes some
deviation, perceived as differences from the PMBus Part I and Part II
speciﬁcation Rev 1.2.
a. PMBus section 10.2.5.3, exceptions
• The busy bit of the STATUS_BYTE as implemented can be
cleared (80h). In order to maintain compatibility with the
speciﬁcation (40h) can also be used.
1. The internal μC meets all Part I and II PMBus speciﬁcation
requirements with the following differences to the transport
requirement.
n Manufacturer Implementation of the PMBus Spec
a. PMBus section 10.5, setting the response to a detected fault
condition
Unmet DC parameter Implementation vs SMBus™ spec
Symbol
Parameter
D44TL1A0
SMBus™
Rev 2.0
Min
Max
Min
Max
Units
VIL[a]
Input Low Voltage
-
0.99
-
0.8
V
VIH[a]
Input High Voltage
2.31
-
2.1
VVDD_IN
V
10
22
-
±5
µA
ILEAK_PIN[b]
Input Leakage per Pin
• All powertrain responses are pre-set and cannot be changed.
Refer to the BCM datasheet for details.
b. PMBus section 10.6, reporting faults and warnings to the Host
• SMBALERT# signal and Direct PMBus Device to Host
Communication are not supported. However, the Digital
Supervisor will set the corresponding fault status bits and
will wait for the host to poll.
c. PMBus section 10.7, clearing a shutdown due to a fault
[a]
VVDD_IN = 3.3 V
[b] V
BUS = 5 V
• There is no RESET pin or EN pin in the internal μC.
Cycling power to the internal μC will not clear a
BCM Shutdown. The BCM will clear itself once the fault
condition is removed. Refer to the BCM datasheet for details.
2. The internal μC accepts 38 PMBus command codes. Implemented
commands execute functions as described in the PMBus speciﬁcation.
d. PMBus Section 10.8.1, corrupted data transmission faults:
n Deviations from the PMBus speciﬁcation:
• Packet error checking is not supported.
a. Section 15, fault related commands
• The limits and Warnings unit implemented is percentage (%)
a range from decimal (0-100) of the factory set limits.
Data Transmission Faults Implementation
This section describes data transmission faults as implemented in the internal µC.
Response to Host
Section
Description
NAK
FFh
STATUS_BYTE
CML
STATUS_CML
Other
Unsupported
Fault
Data
10.8.1
Corrupted data
10.8.2
Sending too few bits
X
X
10.8.3
Reading too few bits
X
X
10.8.4
Host sends or reads too
few bytes
X
X
10.8.5
Host sends too many
bytes
10.8.6
Reading too many bytes
10.8.7
Device busy
Notes
No response; PEC not supported
X
X
X
X
X
X
X
Device will ACK own address
BUSY bit in STATUS_BYTE even if
STATUS_WORD is set
X
VIA BCM® Bus Converter
Rev 1.2
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Data Content Faults Implementation
This section describes data content fault as implemented in the internal µC.
Section
Description
Response
to Host
STATUS_BYTE
NAK
CML
Other
Fault
X
STATUS_CML
Unsupported
Command
Notes
Unsupported
Data
10.9.1
Improperly Set Read Bit In
The Address Byte
X
X
10.9.2
Unsupported Command
Code
X
X
10.9.3
Invalid or Unsupported
Data
X
X
10.9.4
Data Out of Range
X
X
10.9.5
Reserved Bits
X
No response; not a fault
VIA BCM Sine Amplitude Converter™
The Sine Amplitude Converter (VIA BCM SAC™) uses a high frequency
resonant tank to move energy from input to output. (The resonant tank
is formed by Cr and Lr in the power transformer windings as shown in
the BCM module Block Diagram). The resonant LC tank, operated at
high frequency, is amplitude modulated as a function of input voltage
and output current. A small amount of capacitance embedded in the
input and output stages of the module is sufficient for full functionality
and is key to achieving high
power density.
The BCM4914xD1E5135yzz VIA BCM SAC can be simpliﬁed into the
preceeding model.
The use of DC voltage transformation provides additional interesting
attributes. Assuming that ROUT = 0 Ω and IQ = 0 A, Equation (3) now
becomes Equation (1) and is essentially load independent, resistor R is
now placed in series with VIN.
RRIN
VIN
Vin
+
–
VIA BCM
SACSAC™
1/8
KK==1/32
VVout
OUT
At no load:
VOUT = VIN • K
(1)
K represents the “turns ratio” of the VIA BCM SAC.
Rearranging Equation (1):
K=
VOUT
VIN
Figure 21 — K = 1/8 Sine Amplitude Converter
with series input resistor
The relationship between VIN and VOUT becomes:
(2)
VOUT = (VIN – IIN • RIN) • K
Substituting the simpliﬁed version of Equation (4)
(IQ is assumed = 0 A) into Equation (5) yields:
In the presence of load, VOUT is represented by:
VOUT = VIN • K – IOUT • ROUT
(3)
VOUT = VIN • K – IOUT • RIN • K2
and IOUT is represented by:
IOUT =
(5)
IIN – IQ
K
(4)
ROUT represents the impedance of the VIA BCM SAC, and is a function
of the RDSON of the input and output MOSFETs, input and output pc
board resistance and the winding resistance of the power transformer.
IQ represents the quiescent current of the VIA BCM SAC control, gate
drive circuitry, and core losses.
VIA BCM® Bus Converter
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This is similar in form to Equation (3), where ROUT is used to represent
the characteristic impedance of the VIA BCM SAC™. However, in this
case a real R on the input side of the VIA BCM SAC is effectively scaled
by K2 with respect to the output.
Assuming that R = 1 Ω, the effective R as seen from the secondary side is
15.6 mΩ, with K = 1/8 .
A similar exercise should be performed with the addition of a capacitor
or shunt impedance at the input to the VIA BCM SAC. A switch in series
with VIN is added to the circuit. This is depicted in Figure 22.
A solution for keeping the impedance of the VIA BCM SAC low involves
switching at a high frequency. This enables small magnetic components
because magnetizing currents remain low. Small magnetics mean small
path lengths for turns. Use of low loss core material at high frequencies
also reduces core losses.
S
VVin
IN
+
–
Low impedance is a key requirement for powering a high-current, lowvoltage load efficiently. A switching regulation stage should have
minimal impedance while simultaneously providing appropriate
ﬁltering for any switched current. The use of a VIA BCM SAC between
the regulation stage and the point of load provides a dual beneﬁt of
scaling down series impedance leading back to the source and scaling
up shunt capacitance or energy storage as a function of its K factor
squared. However, the beneﬁts are not useful if the series impedance of
the VIA BCM SAC is too high. The impedance of the VIA BCM SAC must
be low, i.e. well beyond the crossover frequency of the system.
C
VIA BCM SAC™
SAC
K = 1/8
K = 1/32
VVout
OUT
The two main terms of power loss in the VIA BCM module are:
n No load power dissipation (PNL): deﬁned as the power
used to power up the module with an enabled powertrain
at no load.
n Resistive loss (ROUT): refers to the power loss across
the VIA BCM module modeled as pure resistive impedance.
Figure 22 — Sine Amplitude Converter with input capacitor
PDISSIPATED = PNL + PROUT
A change in VIN with the switch closed would result in a change in
capacitor current according to the following equation:
IC(t) = C
dVIN
dt
Therefore,
(7)
Assume that with the capacitor charged to VIN, the switch is opened
and the capacitor is discharged through the idealized VIA BCM SAC. In
this case,
POUT = PIN – PDISSIPATED = PIN – PNL – PROUT
POUT = PIN – PNL – PROUT
PIN
PIN
(8)
substituting Equation (1) and (8) into Equation (7) reveals:
IOUT =
=
C • dVOUT
K2
dt
(9)
The equation in terms of the output has yielded a K2 scaling factor for
C, speciﬁed in the denominator of the equation.
(11)
The above relations can be combined to calculate the overall VIA
module efficiency:
h =
IC= IOUT • K
(10)
VIN • IIN – PNL – (IOUT)2 • ROUT
VIN • IIN
= 1–
(
)
PNL + (IOUT)2 • ROUT
VIN • IIN
A K factor less than unity results in an effectively larger capacitance on
the output when converted from the input. With a K = 1/8 as shown in
Figure 22, C=1 μF would appear as C = 64 μF when viewed
from the output.
VIA BCM® Bus Converter
Rev 1.2
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Input and Output Filtering
Thermal Considerations
The VIA BCM adapter has built-in EMI ﬁltering with hot-swap circuitry
input side. EMI ﬁltering helps to provide EN class B or class A for
conducted emission. VIA BCM does not require external EMI ﬁltering.
Typical EMI spectrum is shown in ﬁgures 18, 19, and 20 for test setup as
shown in Figure 23. Hot-swap circuitry provides inrush current
limiting through the MOSFET.
The VIA™ package provides effective conduction cooling from either of
the two module surfaces. Heat may be removed from the top surface,
the bottom surface or both. The extent to which these two surfaces are
cooled is a key component for determining the maximum power that
can be processed by a VIA, as can be seen from speciﬁed thermal
operating area in Figure 1. Since the VIA has a maximum internal
temperature rating, it is necessary to estimate this internal temperature
based on a system-level thermal solution. To this purpose, it is helpful
to simplify the thermal solution into a roughly equivalent circuit where
power dissipation is modeled as a current source, isothermal surface
temperatures are represented as voltage sources and the thermal
resistances are represented as resistors. Figure 24 shows the “thermal
circuit” for the VIA module.
Further, along with internal ceramic input and output capacitance, it
reduces the input and output voltage ripple. External output ﬁltering
can be added as needed. Ceramic capacitance can be used as an output
bypass for this purpose. Moreover, along with hot-swap circuitry, it
protects the adapter from overvoltage transients imposed by a system
that would exceed maximum ratings and induce stresses. Adapter
input and output voltage ranges shall not be exceeded. An internal
overvoltage function prevents operation outside of the normal
operating input range. Even when disabled, the adapter is exposed to
the applied voltage and adapter must withstand it.
Given the wide bandwidth of the adapter, the source response is
generally the limiting factor in the overall system response. Anomalies
in the response of the source will appear at the output of the module
multiplied by its K factor.
Total load capacitance at the output of the adapter shall not exceed the
speciﬁed maximum for correct operation of it in startup and steady
state conditions. Owing to the wide bandwidth and low output
impedance of the adapter, low frequency bypass capacitance and
signiﬁcant energy storage may be more densely and efficiently
provided by adding capacitance at the input of the adapter. At
frequencies less than 500 KHz, the adapter appears as an impedance of
ROUT between the source and load.
Within this frequency range, capacitance at the input appears as
effective capacitance on the output per the relationship deﬁned
in equatiion (13).
COUT =
CIN
(13)
K2
+
RJC_TOP
TC_TOP
–
RHOU
–
RJC_BOT
PDISS
s
TC_BOT
+
s
Figure 24 – Double sided cooling VIA thermal model
In this case, the internal power dissipation is PDISS, RJC_TOP and RJC_BOT
are thermal resistance characteristics of the VIA module and the top
and bottom surface temperatures are represented as TC_TOP, and TC_BOT.
It interesting to notice that the package itself provides a high degree of
thermal coupling between the top and bottom case surfaces
(represented in the model by the resistor RHOU). This feature enables
two main options regarding thermal designs:
n Single side cooling: the model of Figure 24 can be simpliﬁed by
calculating the parallel resistor network and using one simple
thermal resistance number and the internal power dissipation
curves; an example for bottom side cooling only is shown in
Figure 25.
EMI
Receiver
In this case, RJC can be derived as following:
LISN
DC
Power
Supply
Screen
Room /
Filters
Single
VIA BCM
(DUT)
Load
LISN
RJC =
(RJC_TOP + RHOU) • RJC_BOT
RJC_TOP + RHOU + RJC_BOT
Figure 23 – Typical test set-up block diagram for Conducted Emissions
Note: The measurement were evaluated against the class A and class B
limits of EN55022. Testing was performed with -OUT terminal of VIA BCM
connected to Chassis and Chassis was grounded.
VIA BCM® Bus Converter
Rev 1.2
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ZIN_EQ1
Vin
BCM®1
ZOUT_EQ1
Vout
R0_1
+ TC_BOT
–
RJC
s
ZIN_EQ2
PDISS
BCM®2
ZOUT_EQ2
R0_2
+ DC
Load
s
Figure 25 – Single-sided cooling VIA thermal model
ZIN_EQn
ZOUT_EQn
R0_n
n Double side cooling: while this option might bring limited
advantage to the module internal components (given the surfaceto-surface coupling provided), it might be appealing in cases where
the external thermal system requires allocating power to two
different elements, like for example heatsinks with independent
airﬂows or a combination of chassis/air cooling.
BCM®n
Figure 26 — VIA BCM module array
Fuse Selection
Current Sharing
The performance of the VIA BCM SAC™ topology is based on efficient
transfer of energy through a transformer without the need of closed
loop control. For this reason, the transfer characteristic can be
approximated by an ideal transformer with a positive temperature
coefficient series resistance.
This type of characteristic is close to the impedance characteristic of a
DC power distribution system both in dynamic (AC) behavior and for
steady state (DC) operation.
When multiple VIA BCM modules of a given part number are
connected in an array they will inherently share the load current
according to the equivalent impedance divider that the system
implements from the power source to the point of load.
Some general recommendations to achieve matched array impedances
include:
n Dedicate common copper planes/wires within the PCB/Chassis
to deliver and return the current to the VIA modules.
n Provide as symmetric a PCB/Wiring layout as possible among
VIA™ modules
For further details see AN:016 Using BCM Bus Converters
in High Power Arrays.
In order to provide ﬂexibility in conﬁguring power systems
Adapter modules are not internally fused. Input line fusing
of Adapter products is recommended at system level to provide thermal
protection in case of catastrophic failure.
The fuse shall be selected by closely matching system
requirements with the following characteristics:
n Current rating
(usually greater than maximum current of VIA BCM module)
n Maximum voltage rating
(usually greater than the maximum possible input voltage)
n Ambient temperature
n Nominal melting I2t
n Recommend fuse: 10 A Littelfuse 505 Series or 10 A
Littelfuse 487 Series.
Reverse Operation
VIA BCM modules are capable of reverse power operation. Once the
unit is started, energy will be transferred from secondary back to the
primary whenever the secondary voltage exceeds VIN • K. The module
will continue operation in this fashion for as long as no faults occur.
The BCM4914xD1E5135yzz has not been qualiﬁed for continuous
operation in a reverse power condition. Furthermore fault protections
which help protect the module in forward operation will not fully
protect the module in reverse operation.
Transient operation in reverse is expected in cases where there is
signiﬁcant energy storage on the output and transient voltages appear
on the input. Transient reverse power operation of less than 10 ms, 10%
duty cycle is permitted and has been qualiﬁed to cover these cases.
VIA BCM® Bus Converter
Rev 1.2
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Dielectric Withstand
VIA BCM Isolation
The chassis of the VIA BCM is required to be connected to Protective
Earth when installed in the end application and must satisfy the
requirements of IEC 60950-1 for Class I products.
The VIA BCM contains an internal safety approved isolating
component (VI ChiP) that provides the Reinforced Insulation from
Input to Output. The isolating component is individually tested for
Reinforced Insulation from Input to Output at 3000 Vac or 4242 Vdc
prior to the ﬁnal assembly of the VIA™.
When the VIA™ assembly is complete the Reinforced Insulation can
only be tested at Basic Insulation values as speciﬁed in the electric
strength Test Procedure noted in clause 5.2.2 of IEC 60950-1.
VI ChiP
Input
Output
VIA Input Circuit
SELV
VIA Output Circuit
RI
BI
PE
FI
Test Procedure Note from IEC 60950-1
“For equipment incorporating both REINFORCED INSULATION and
lower grades of insulation, care is taken that the voltage applied to the
REINFORCED INSULATION does not overstress BASIC INSULATION or
SUPPLEMENTARY INSULATION.”
Figure 28 – BCM VIA after final assembly
Hot Swap
Summary
The ﬁnal VIA assembly contains basic insulation from input to case,
reinforced insulation from input to output, and functional insulation
from output to case.Both sides of the housing are required to be
connected to Protective Earth to satisfy safety and EMI requirements.
Protective earthing can be accomplished through dedicated wiring
harness (example: ring terminal clamped by mounting screw) or
surface contact (example: pressure contact on bare conductive chassis
or PCB copper layer with no solder mask).
The output of the VIA complies with the requirements of SELV circuits
so only functional insulation is required from the output (SELV) to case
(PE) because the case is required to be connected to protective earth in
the ﬁnal installation. The construction of the VIA can be summarized
by describing it as a “Class II” component installed in a “Class I”
subassembly. The reinforced insulation from input to output can only
be tested at basic insulation values on the completely
assembled VIA product.
VI ChiP Isolation
Input
Output
SELV
RI
Figure 27 – VI Chip before final assembly in the VIA
Many applications use a power architecture based on a 380 Vdc
distribution bus. This supply level is emerging as a new standard and
efficient means for distributing power through boards, racks and
chassis mounted Telecom and Datacom system. The interconnect
between the different modules is accomplished with a backplane and
motherboard. Power is commonly provided to the various module slots
via a 380 Vdc distribution bus.
Removing the faulty module from the rack is relatively easy, provided
the remaining power modules can support the step increase in load.
Plugging in the replacement module has more potential for problems,
as it will present an uncharged capacitor load and draw a large inrush
current. This could cause a momentary, but unacceptable interruption
or sag to the backplane power bus if not limited. The problem can also
arise if ordinary power module connectors are used, since the
connector pins will engage and disengage in a random and
unpredictable sequence during insertion and removal.
Hot swap or hot plug is the highly desirable feature in many
applications, but it also creates several issues that must be addressed in
the system design. A number of related phenomena occur with a live
insertion and removal event, including bouncing, arcing between input
connector pins, larger voltage and current transients. Hot swap
circuitry in the converter modules protects the module and the rest of
the system from the problem associated with live insertion.
To meet the maintenance, reconﬁguration, redundancy and system
upgrade, this new VIA BCM module is being designed to address the
function of hot-swapping at the 380 Vdc distribution bus. This new
module provides a high level of integration for DC to DC converters in
380 Vdc distributions, saving the system designer design time and
critical board space. Hot swap circuitry as shown in Figure 29 uses an
active MOSFET switching device in the input line. During insertion, the
MOSFET is driven into a resistive state to limit the inrush current, and
then when the inserted module’s input capacitor has charged, the
MOSFET becomes fully conductive to avoid the voltage drop losses.
Performance veriﬁcation is further illustrated through scope plots of
circuit’s response to various live insertion events.
VIA BCM® Bus Converter
Rev 1.2
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Hot Swap Test – Scope Pictures
VIN of ChiP
BCM
IIN of VIA
BCM
VIN of VIA
BCM
VOUT of VIA
BCM
ChiP BCM
Charge
Pump
Hot-swap
Controller
Figure 29 – High-Level Diagram for 384 Vdc Hot Swap with ChiP BCM
DC-DC converter
Figure 31 – Hot swap start-up
Overall, the objective is always remains the same in hot swap
applications; to give system designer the opportunity to build hot swap
capability into redundant power module arrays. This allows telecoms
and other mission critical applications to continue without
interruption even through failure and replacement of one or possibly
more of their power modules.
Hot Swap Test – Test circuit and Procedure
Ch1: IIN of VIA BCM#2
Ch2: VOUT of VIA BCM#2
Ch3: VIN of VIA BCM#2 shows the fast input voltage transient at the
input terminal of VIA BCM#2
Ch4: VIN of ChiP BCM#2 shows the soft start charging the input
capacitor as shown, time constant depends upon the gate signal.
n Two VIA BCMs in parallel with mercury relay#1 open
n Close mercury relay#1 and measure inrush current going into #2 VIA BCM
4000μF
Maximum Input
Voltage
Electronic
Load
Max Load
VIA BCM (K)
#1
DC
Mercury
Relay #1
VIA BCM (K)
#2
Figure 32 – Same as figure 31 but at a bigger time scale shows the
appearance of the VIA BCM#2 output
Figure 30 – Test Circuit
VIA BCM® Bus Converter
Rev 1.2
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BCM4914xD1E5135yzz
VIA BCM Bus Converter Lug Mount, Cable, Adapter,
Mechanical Drawing and Recommended Hole Pattern
12.17
309.14
C
.37
9.30
A
.11
2.90
1.171
29.750
.152
3.861
THRU
TYP
B
1
3
INPUT
INSERT
(41816)
TO BE
REMOVED
PRIOR
TO USE
2
287387
,16(57
72%(
5(029('
35,25
7286(
4
86(7<&2/8*25
(48,9)25287387&211(&7,21
352'8&76$1'
86(7<&2/8*25
(48,9)25287387&211(&7,21
352'8&76$1'
86(7<&2/8*25
(48,9)25,1387&211(&7,21
$//352'8&76
1.40
35.54
NOTES:
1- RoHS COMPLIANT PER CST-0001 LATEST REVISION.
2- SEE PRODUCT DATA SHEET FOR PIN DESIGNATIONS.
PRODUCT
4914 VIA BCM
5 RED
6 BLACK
7 BLUE
8 WHITE
9 YELLOW
DIM 'A'
>@
DIM 'B'
>@
VIA BCM® Bus Converter
Rev 1.2
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DIM 'C'
>@
BCM4914xD1E5135yzz
VIA BCM Bus Converter PCB Mount, Connector, Adapter,
Mechanical Drawing and Recommended Hole Pattern
DIM 'A'
.15
3.86
(4) PL.
DIM 'B'
DIM 'E'
DIM 'C'
DIM 'L'
±.010 [.254]
0
.366±.010
9.300±.254
SEATING
PLANE
.080
2.032
(2) PL.
.025
.635
(5) PL.
DIM 'L'
SHORT
.103 [2.607]
LONG
.182 [4.613]
.150
3.810
(2) PL.
TOP VIEW
(COMPONENT SIDE)
.120±.003
3.048±.076
PLATED THRU
.030 [.762]
ANNULAR RING
(2) PL
DIM 'F'
±.003 [.076]
.112±.003
2.846±.076
1.171±.003
29.750±.076
.190±.003
4.826±.076
PLATED THRU
.030 [.762]
ANNULAR RING
(2) PL
DIM 'B''
±.003 [.076]
11
2
13
4
.452±.003
11.475±.076
.156±.003
3.970±.076
.268±.003
6.800±.076
.859±.003
21.810±.076
.947±.003
24.058±.076
SEE DETAIL A
1
.172±.003
4.369±.076
PLATED THRU
.064 [1.626]
ANNULAR RING
(4) PL.
10
3
12
.067±.003
1.700±.076
.201±.003
5.100±.076
.134±.003
3.400±.076
.040±.003
1.016±.076
PLATED THRU
.008 [.203]
ANNULAR RING
(5) PL
DIM 'D''
±.003 [.076]
DIM 'G''
±.003 [.076]
(COMPONENT SIDE)
7
DIM 'F'
±.010 [.254]
10
12
3
DETAIL A
SCALE 8 : 1
.201
5.100
.067
1.700
.859±.010
21.810±.254
.947±.010
24.058±.254
2
5
.134
3.400
1.171
29.750
.11
2.90
6
.023
.584
TYP
DIM 'D'
±.010 [.254]
.112±.010
2.846±.254
8
.046
1.168
(3) PL.
DIM 'G'
±.010 [.254]
1
9
.023
.584
TYP
RECOMMENDED HOLE PATTERN
11
13
4
.452±.010
11.475±.254
.268
6.800
5
6
7
8
9
1.40
35.54
.156
3.970
BOTTOM VEW
NOTES:
1- RoHS COMPLIANT PER CST-0001 LATEST REVISION.
2- SEE PRODUCT DATA SHEET FOR PIN DESIGNATIONS.
PRODUCT
DIM 'A'
DIM 'B'
DIM 'C'
DIM 'D'
DIM 'E'
DIM 'F'
DIM 'G'
4914 VIA BCM
2.17 [55.15]
1.757 [44.625]
4.91 [124.77]
4.517 [114.741]
5.00 [126.98]
1.999 [50.777]
4.781 [121.430]
VIA BCM® Bus Converter
Rev 1.2
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BCM4914xD1E5135yzz
Revision History
Revision
Date
Description
Page Number(s)
1.0
05/15/15
Initial release
n/a
1.1
06/10/15
Recommended Resistor (ID 1)
Summary note added
Updated Pin Information
18
34
37
1.2
07/07/15
Reassigned figures and figure numbers
12-14
30-35
VIA BCM® Bus Converter
Rev 1.2
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BCM4914xD1E5135yzz
Vicor’s comprehensive line of power solutions includes high density AC-DC and DC-DC modules and
accessory components, fully configurable AC-DC and DC-DC power supplies, and complete custom
power systems.
Information furnished by Vicor is believed to be accurate and reliable. However, no responsibility is assumed by Vicor for its use. Vicor makes no
representations or warranties with respect to the accuracy or completeness of the contents of this publication. Vicor reserves the right to make
changes to any products, specifications, and product descriptions at any time without notice. Information published by Vicor has been checked and
is believed to be accurate at the time it was printed; however, Vicor assumes no responsibility for inaccuracies. Testing and other quality controls are
used to the extent Vicor deems necessary to support Vicor’s product warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
Specifications are subject to change without notice.
Vicor’s Standard Terms and Conditions
All sales are subject to Vicor’s Standard Terms and Conditions of Sale, which are available on Vicor’s webpage or upon request.
Product Warranty
In Vicor’s standard terms and conditions of sale, Vicor warrants that its products are free from non-conformity to its Standard Specifications (the
“Express Limited Warranty”). This warranty is extended only to the original Buyer for the period expiring two (2) years after the date of shipment
and is not transferable.
UNLESS OTHERWISE EXPRESSLY STATED IN A WRITTEN SALES AGREEMENT SIGNED BY A DULY AUTHORIZED VICOR SIGNATORY, VICOR DISCLAIMS
ALL REPRESENTATIONS, LIABILITIES, AND WARRANTIES OF ANY KIND (WHETHER ARISING BY IMPLICATION OR BY OPERATION OF LAW) WITH
RESPECT TO THE PRODUCTS, INCLUDING, WITHOUT LIMITATION, ANY WARRANTIES OR REPRESENTATIONS AS TO MERCHANTABILITY, FITNESS FOR
PARTICULAR PURPOSE, INFRINGEMENT OF ANY PATENT, COPYRIGHT, OR OTHER INTELLECTUAL PROPERTY RIGHT, OR ANY OTHER MATTER.
This warranty does not extend to products subjected to misuse, accident, or improper application, maintenance, or storage. Vicor shall not be liable
for collateral or consequential damage. Vicor disclaims any and all liability arising out of the application or use of any product or circuit and assumes
no liability for applications assistance or buyer product design. Buyers are responsible for their products and applications using Vicor products and
components. Prior to using or distributing any products that include Vicor components, buyers should provide adequate design, testing and
operating safeguards.
Vicor will repair or replace defective products in accordance with its own best judgment. For service under this warranty, the buyer must contact
Vicor to obtain a Return Material Authorization (RMA) number and shipping instructions. Products returned without prior authorization will be
returned to the buyer. The buyer will pay all charges incurred in returning the product to the factory. Vicor will pay all reshipment charges if the
product was defective within the terms of this warranty.
Life Support Policy
VICOR’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS
PRIOR WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL COUNSEL OF VICOR CORPORATION. As used herein, life support
devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform
when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the
user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or system or to affect its safety or effectiveness. Per Vicor Terms and Conditions of Sale, the user of Vicor products
and components in life support applications assumes all risks of such use and indemnifies Vicor against all liability and damages.
Intellectual Property Notice
Vicor and its subsidiaries own Intellectual Property (including issued U.S. and Foreign Patents and pending patent applications) relating to the
products described in this data sheet. No license, whether express, implied, or arising by estoppel or otherwise, to any intellectual property rights is
granted by this document. Interested parties should contact Vicor's Intellectual Property Department.
The products described on this data sheet are protected by the following U.S. Patents Pending
Vicor Corporation
25 Frontage Road
Andover, MA, USA 01810
Tel: 800-735-6200
Fax: 978-475-6715
email
Customer Service: [email protected]
Technical Support: [email protected]
VIA BCM® Bus Converter
Rev 1.2
vicorpower.com
Page 39 of 39
07/2015
800 927.9474

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