AN34 - Silicon Labs

S i321 X H A R D W A R E R E F E R E N C E G U I D E
The Silicon Laboratories Si3210, Si3211, and Si3212
ProSLICs™ are excellent solutions for short loop
performance, care must be taken in selecting and
placing the appropriate components. This document
outlines component selection and critical component
layout issues. It should be used in conjunction with the
ProSLIC data sheet and other supporting ProSLIC
application notes.
Component Selection
In choosing components and tolerances for a bill of
materials (BOM), it is not always obvious what the
ramifications are for device performance parameters.
This section describes the general considerations and
related device performance issues in the selection of
BOM components for the ProSLIC. The ProSLIC name
is used to designate the entire family of devices. Each
component or related group of components is discussed
in separate sections. Each component’s reference
designator is used relative to the data sheet and
evaluation board schematic numbering.
R14—Bias Resistor
An internal voltage reference is dropped across R14 to
create a temperature-independent current source
on-chip. Errors in the R14 value affecting the internal
current source can degrade the SLIC calibration ranges
(din_gain and cin_gain cals) and cause all the analog
circuitry power dissipation to vary. Other functions
affected by the current source accuracy are the pulse
metering DAC gain, MADC gain, dc-dc converter
absolute accuracy, and ILIM absolute accuracy. The
tolerance is specified as ±1% in order to keep the
absolute value of the current well controlled. The
bandgap varies approximately ±2%; therefore, the total
current variation is less than ±3%. It is also important to
choose a resistor type with a low temperature
coefficient. A resistor variation from –40 to 85 °C of
more than 1% begins to degrade the overall internal
current source absolute accuracy. The power dissipated
in R14 is low: (1.2 V)2/40.2 kΩ = 36 µW.
C1, C2—SLIC Loop Filter
C1 and C2 are part of the low-pass filter used to
band-limit the SLIC control loops when audio
transmission is enabled during either active off-hook or
OHT operation. The capacitors are part of a pole/zero
passive filter where the resistor values setting the
pole/zero ratio are on-chip. A loose tolerance of ±20%
is chosen for low cost, and the minimum voltage
tolerance of 6 V is allowed because the voltage on the
caps can never exceed the power supply level applied
to the ProSLIC. A polarized capacitor with the negative
lead connected to QGND can be used. Due to the
nature of the low-level signals in C1 and C2,
low-leakage capacitors, such as ceramic or tantalum,
must be used. Changes in the C1 and C2 value affect
SLIC loop stability and should not be done. The line
pole caused by impedances on TIP and RING may
cause instability if C1 and C2 are varied.
R15—Audio Gm
R15 is used to set the gain of converting audio signal
voltages into currents driving TIP and RING. It is also
used by the two-wire impedance synthesis path. The
value of 243 Ω was chosen based on achieving
appropriate voltage amplitudes given specific loads on
TIP and RING. The resulting effect maximizes the use of
the ProSLIC circuit’s dynamic range and voltage
overhead. In PCM to TIP/RING applications, it is
normally required that a full-scale PCM audio code
translate into an accurate power of 3.14 dBm on the
line. It is important that R15 have high accuracy (±1%)
with low temperature drift. It must also be linear to the
–85 dB level. The power dissipated in R15 is low:
(1 V)2/243 Ω = 4 mW.
R1, R2, R3, R4, R5—SLIC Sense Resistors
The SLIC sense resistors are used to convert line
voltages into currents that can be processed on-chip by
the SLIC control loops. A tolerance of ±1% and 100 V is
chosen to minimize sensing gain error. It is also
important that the resistors have a low temperature drift.
The maximum power dissipated is (94.5 V)2/200 kΩ =
45 mW.
Errors in the sense resistor values can affect SLIC
calibration ranges (tracking loop gain mismatch,
Rev. 0.31 8/03
Copyright © 2003 by Silicon Laboratories
din_gain, cin_gain). It is particularly important that once
the gain mismatch is calibrated, the R3, R4, and R5
resistors do not drift away from one another. Therefore,
they should be located close to one another and away
from any large thermal gradients on the board. The
on-chip current sources derived from R14 and the
sense resistor currents interact; therefore, values are
not considered variable. Note that R2 and R4 should be
196 kΩ when using the Si3201.
R6, R7—Emitter Current Sensing Resistors
R6 and R7 are used to generate voltages proportional
to the emitter currents in Q5 and Q6. Changes in the R6
and R7 values affect the IE tracking loop sensing gain.
Ideally, a 15 mV signal internal to the SLIC signal path
generates exactly 1 mA of emitter current using the IE
tracking loop. Errors in R6 and R7 (and R3, R4, and R5)
cause this 15 mV/mA gain to be altered, creating a
mismatch in the Q1/Q2 current drive level versus the
Q5/Q6 current drive level. Mismatches of this type force
the SLIC common mode loop to work even when a
purely differential drive is needed on the line (differential
to longitudinal conversion). This is largely a dc effect
and does not change audio performance. As with the
other sense resistors, high absolute accuracy (±1%)
and low temperature drift are required. The power
dissipated is a maximum of (80 mA)2 x 80.6 Ω =
515 mW, although this should only occur in a transient
condition. The maximum dc power dissipation is more
likely to be based on the ILIM and BJTBIAS levels with
a maximum of (41 mA+16 mA)2 x 80.6 Ω = 261 mW. A
1/4 W resistor is recommended based on the dc
analysis. Note that R6 and R7 should be 4.02 kΩ while
R2 and R4 should be 196 kΩ when using the Si3201
R12, R13, C7, C8—IE Tracking Loop
The RC pairs of R12/C7 and R13/C8 create a low pass
filter for dominant pole compensation of the IE tracking
loop. Because the loop is highly stable, tolerances can
be loose on these components, thus, ±5% and ±20%
are chosen to minimize cost for the resistors and
capacitors, respectively. Because the capacitors may
receive the entire battery voltage (at least during a
transient) a 100 V voltage tolerance has been specified.
In steady state, the voltage across the capacitors is no
more than 16 V. Polarized capacitors with the negative
lead connected to VBAT can be used. The maximum
power dissipation in the resistors occurs when the
maximum current is flowing in Q5 or Q6, and is (0.7 V +
80.6 Ω x 80 mA)2/5 kΩ = 10 mW.
Large changes in the R12/C7 and R13/C8 time constant
could cause the tracking loops to become unstable. The
bandwidth has been chosen to be wide enough to
operate for the highest frequency ring signal (68 Hz),
but low enough to avoid parasitic poles from the SLIC
internal circuits which could degrade phase margin
(~300 kHz). For ringing, a much larger bandwidth is
needed than one might expect because the current
swings are a large signal for a heavy ringing load. Audio
noise performance is not dependent on these
component values. R12, R13, C7, and C8 are not used
in the Si3201 solution.
C5, C6—Line Compensation Capacitors
C5 and C6 provide a minimum capacitance from TIP
and RING to ground ensuring the stability of the SLIC
control loops for a no-load condition on the line. These
capacitors see the entire battery voltage in normal
operation and, as a result, are specified with a voltage
tolerance of 100 V. C5 and C6 are currently specified as
22 nF. Without the large C1 and C2 capacitors in the
(cap_bypass = 1),
transconductance of the SLIC loop combined with the
line capacitance determines the loop crossover
frequency. For the differential loop with a maximum gm
1/80 Ω,
1/(6.28 x 80 Ω x 22 nF) = 90 kHz. Lowering C5 and C6
excessively could cause this crossover frequency to be
too high, bringing in internal SLIC parasitic poles, which
can degrade loop phase margin. A maximum of
300–400 kHz is expected to be the limit for reasonable
stability margins.
In addition, C5 and C6 filter high-frequency differential
and common-mode signals coming from the line or
generated by the ProSLIC. This improves out-of-band
noise performance and high-frequency PSR. A
high-quality (low-lead inductance) capacitor should be
chosen to minimize RF signal transmission to help in
meeting FCC Part 15 EMI requirements.
Although raising the values of C5 and C6 is good for
SLIC control loop stability and noise, it adversely affects
audio performance. To compensate for the drop of input
impedance at the upper edge of the audio band due to
C5 and C6, a switched capacitor compensation has
been added to the impedance synthesis circuitry. This
compensation is programmable based on the C5/C6
value, with possible values ranging from 4.7 nF to
22 nF. With a 4.7 nF C5/C6, virtually no compensation
is required.
R8, R9, C3, C4—Audio Coupling Network
C3 and C4 are AC coupling capacitors used to couple
audio signals on the line into the chip with low distortion
(better than –85 dB) and low attenuation. They can be
Rev. 0.31
polarized caps with the positive lead connected on the
chip side (bias of 1.5 V) because TIP and RING do not
swing more than a diode drop above ground. The
capacitors may receive the entire battery voltage; so, a
100 V working voltage tolerance is specified. The surge
voltage should be considered also relative to the
protection voltage level. Absolute accuracy, although
important for low-frequency return loss, can be ±20% for
low cost.
C3 and C4, combined with on-chip resistors at the input
to the audio TX path, create a high-pass filter whose
pole is below the minimum audio band frequency. With
an on-chip input impedance of approximately 100 kΩ,
the hpf corner is 1/(6.28 x 100 kΩ x 220 nf) = 7 Hz. This
corner frequency has been chosen to be slightly above
the SLIC control loop corner frequency (2 Hz) so that
there is a smooth transition between the SLIC dc
common mode control loop and the audio ac common
mode control loop. A large gap between the two corner
frequencies would create a frequency band where there
is a high common-mode input impedance into the
SLIC/CODEC. The 7 Hz corner also is low enough to
prevent the hpf from affecting audio return loss
R8 and R9 provide series current limiting in the case of
transients on the line, protecting the C3 and C4 caps
and the ProSLIC’s STIPAC and SRINGAC pins. For a
fast fault transient (making the C3 or C4 capacitor
appear as a short circuit) a peak current of 100 V/470 Ω
= 212 mA would be generated into the ProSLIC pins.
This level of peak current should not cause latch-up or
damage to the device.
The value tolerance of C3 and C4 is also a
consideration in the return loss performance when
synthesizing a series RC network as described above.
To achieve nominal return loss of better than 20 db at
low frequency, a ±20% tolerance capacitor is
recommended. C3/C4 tolerance can be chosen tighter
to achieve better return loss.
R10, R11—Positive Surge Protection
R10 and R11 provide protection for Q1, Q2, and the
ESD networks of the ITIPP and IRINGP pins in case of
a positive going fault surge on the line. Without these
resistors, the positive protection diodes would share
current with a saturated Q1 and Q2 and the actual
current flowing in each path would be difficult to predict.
A slightly higher VBE for the protection diodes could
result in excessive current into the ProSLIC input pins.
R10 and R11 cause the preferred current path to
definitely be through the protection diodes. With 30 mA
of base current in Q1 operating in reverse mode (which
is low beta), there is a 300 mV drop across the resistor;
this is enough to limit the current in this path and cause
the protection diodes to take the bulk of the surge
current. The absolute accuracy of these resistors need
not be high; ±5% or less is adequate. The maximum
transient power for the case described above is 9 mW.
The only real limitations on the maximum value of R10
and R11 are headroom considerations for the audio gm
driver. With a maximum ILIM of 41 mA and a minimum
beta for Q1 of 30, 1.4 mA flows in the base, creating a
14 mV drop across R10. This is a negligible increase in
the voltage at ITIPP, which is already sitting at a VBE of
0.7 V. Too large a drop across R10 could raise ITIPP to
the point where the audio gm driver bias levels are
affected. A maximum drop of 50 mV across R10 or R11
is acceptable during normal operation. 10 Ω is selected
based on its common value and low impedance.
It may be possible that R10 and R11 are not actually
required to protect Q1, Q2, and the device. Low beta
reverse bipolar operation and finite device output
impedance at the ITIPP and IRINGP pins may limit the
current sufficiently. Experiments should be done to
check the possibility of removing them from the BOM.
R10 and R11 are not needed when using the Si3201
Q1, Q2—PNP Line Drivers
Q1 and Q2 directly pull up, in a common base
configuration, the TIP and RING leads. Both the SLIC
and audio paths control the emitter current of these
The Q1 and Q2 transistors are the most critical of the
external bipolars associated with driving the line.
Breakdown voltages, collector to emitter with base
shorted, must exceed the negative protection device
(sidactor) threshold, which is set above the maximum
battery voltage to be used. The maximum power
dissipation may occur in one of three possible cases:
Active with Loop Closure: For forward operation, Q1
carries the ILIM current, and its collector sits at about
–3 V. Maximum power dissipation for an ILIM of
41 mA is (3+0.7) x 41 mA = 150 mW. Q2 carries the
BJTBIAS current with its collector sitting at –3 V
minus the voltage drop across the off-hook terminal
device. Assuming a maximum off-hook voltage drop
of 12 V for the terminal device with BJTBIAS 12 mA,
the power dissipation is (3+0.7+12) x 12 mA =
188.4 mW.
! OHT: During OHT, BJTBIAS flows in both Q1 and
Q2. Assuming forward OHT, Q2 has a large VCE
equal to Voc+3.7 V. Assuming a VOC = 48 V and a
BJTBIAS of 4 mA, Q2’s power dissipation is
Rev. 0.31
(48+3+0.7) x (4 mA) = 207 mW. The 4 mA BJTBIAS
setting is specifically provided for the OHT case, and
it is highly recommended that 4 mA be used for the
BJTBIAS_OHT setting. The bias current of 4 mA is
more than adequate to drive a 600 Ω load with the
typical FSK amplitude of –3 dBm (requires less than
1 mA). Choosing a higher value for BJTBIAS_OHT
probably requires a more expensive package with
higher power dissipation capacity.
! Ringing: During ringing, the average power
dissipation in Q1 and Q2 is a function of the ring
amplitude, waveshape, battery voltage, and REN
load. A typical case would be sine wave ringing with
a peak voltage of 65 V driving a 5 REN load and
using a –75 V battery. In this case, the average
power dissipated in Q1 and Q2 is 200 mW. The
power for any other set of conditions would need to
be calculated.
From the three cases above, it can be seen that a
package with a maximum power capability of 250 mW
at maximum ambient temperature is adequate for most
applications, with an even lower requirement if an ILIM
less than 41 mA is used. Therefore, in most cases, a
SOT23 package can be used.
The other critical consideration in choosing a device for
Q1 and Q2 is the minimum beta. Low betas and large
beta mismatches create mismatched audio common
mode gains for the TIP and RING paths and low
longitudinal balance. For target values of longitudinal
balance below 60 dB where the on-chip longitudinal
balance calibration step size is not a factor, it is the beta
of Q1 and Q2 that limits performance. Longitudinal
balance in this case can be computed as Bal =
20 x log(∆α) – 6.9 dB. The 6.9 dB constant is a result of
the differential audio impedance helping the situation.
As an example, betas of 30 and 90 for Q1 and Q2 result
in 40 dB of balance. The same factor of three ratio in
betas, but with a minimum beta of 100 yields 50 dB of
balance. The on-chip longitudinal balance does not
correct for the effect of beta mismatches; therefore,
devices must be chosen with sufficiently high betas for
the desired balance performance.
Matched beta transistors improve balance performance
as do Darlington configurations. If a Darlington
configuration is used, the base must be connected to a
diode drop below ground to avoid voltage headroom
problems with the audio gm driver.
Q3, Q4—PNP Mirror Drivers
Q3 and Q4 are used to drive the current mirror that
creates the pulldown line drive current in Q5 and Q6.
Q3 and Q4 reside within the IE tracking loops and have
the most relaxed requirements of all of the external
BJTs. The beta of these transistors is a minor term in
the IE tracking loop gain equation, and the design has
assumed values as low as 30. The collector breakdown
voltage with base shorted must meet the same
requirement as Q1 and Q2.
Because the NPN current mirror of Q5/Q6 has a
minimum current gain of 18, the maximum current that
is required to flow in Q3 or Q4 is 80 mA/18 = 4.5 mA.
The maximum power dissipation for the three cases
described above is as follows:
Active w/ Loop Closure: In this case, the collector
voltage of Q3 (assuming forward operation) sits at
the battery voltage plus one VBE plus the drop
across R7. Assuming the maximum ILIM of 41 mA,
the minimum current mirror gain of 18, and a battery
voltage of –24 V, the power is:
(24 + 0.7 – 0.7–80.6 Ω x 41 mA) x (41 mA/18) =
! OHT: In OHT, both Q3 and Q4 have large VCEs
approximately equal to the battery voltage, but with
low collector currents. Assuming a battery voltage of
–75 V and a BJTBIAS_OHT of 4 mA, the power is
(75 + 0.7 – 0.7 – 80.6 Ω x 4 mA) x (4 mA/18) =
17 mW.
! Ringing: During ringing, Q3 and Q4 will probably
have their largest power dissipation. For a 5REN
load driven with a 50 Vrms sine wave, the peak
current in the load is (50 V x 1.41)/1380 Ω = 51 mA.
This creates a peak power dissipation in Q3 and Q4
of (75 + 0.7 – 0.7 – 80.6 Ω x 51 mA) x (51 mA/18) =
200 mW for a –75 V battery, from which we can
estimate an average power dissipation of
(2/3.14) x (1/2) x (200 mW) = 64 mW. The extra 1/2
factor results from the Q3 or Q4 current being
half-wave rectified during ringing.
Based on the above calculations, an inexpensive
SOT23 package should be adequate for Q3 and Q4.
Q5, Q6—NPN Line Drivers
Q5 and Q6 are the pulldown line drivers for TIP and
RING. The current in these devices is controlled through
the IE tracking loop, which senses the voltage across
the emitter resistors, R6 and R7.
The breakdown requirement for these transistors is the
same as for Q1, Q2, Q3, and Q4. Beta requirements are
relaxed because the emitter degeneration resistors
desensitize the NPN current mirror gain to beta
variations. A minimum value of 30 has been assumed.
The most important consideration in choosing Q5 and
Q6 is the maximum power dissipation. The calculation
for the three cases is as follows:
Rev. 0.31
Active w/ Loop Closure: This is likely to be the
highest power condition to be considered for Q5 and
Q6. Assuming forward operation, Q5 will be carrying
a large current, the sum of ILIM and BJTBIAS. The
worst case collector-to-emitter voltage occurs for a
short at TIP and RING. For an ILIM of 41 mA,
BJTBIAS = 12 mA, a battery of –24 V, and a short at
TIP and RING, the power is
(24 – 3 –80.6 Ω x 53 mA) x (53 mA) = 887 mW.
! OHT: For forward OHT, Q6 has the highest power
dissipation because of its large VCE. Assuming a
battery voltage of –75 V and a BJTBIAS of 4 mA, the
power is (75 – 3 – 80.6 Ω x 4 mA) x (4 mA) =
286 mW.
! Ringing: The power dissipation during ringing for Q5
and Q6 is similar to the dissipation seen in Q1 and
Q2. All devices have VCEs that swing from near 0 V
to near the battery voltage and peak currents
determined by the REN load and rms ringing
amplitude. As computed above for Q1 and Q2, the
power in this mode is approximately 200 mW.
From the above calculations, it can be seen that the
off-hook condition is likely to be the worst case power
condition for Q5 and Q6. To meet a 887 mW limit at
maximum ambient temperature, a SOT223 (~2 W at
room temperature) or equivalent package may be
needed. If the ILIM and BJTBIAS values are not set to
their maximum, it is possible that a smaller and perhaps
less expensive package can be used. SOT89s are
typically 1.2 W devices (although they may not be
cheaper) and some SOT23s have a rating of 500 mW or
even 650 mW at room temperature. For example, if
ILIM = 20 mA and BJTBIAS = 8 mA, the dissipation in
case #1 for a short circuit on the line is reduced to
525 mW.
Q5 and Q6 are not used in the audio signal processing
path and have no significant effect on audio
The Si3201 Line Voltage IC
The Si3201 IC can be used to replace the Q1, Q2, Q3,
Q4, Q5, and Q6 transistor circuits. The use of this IC
reduces the component count and simplifies the Si3210
circuit layout. “AN47: Si321x Linefeed Power Monitoring
and Protection” provides the recommendation for the
Si3201 power threshold setting based on the equivalent
Si3210–Si3201 provides layout recommendations for
the Si3201 IC.
Rev. 0.31
Figure 1. Circuit Solutions for the Si3211/12 Battery Switch
R16, C9, C10, D1, Q7—Solid State Battery
Switch for the Si3211/12
Figure 1 presents three distinct solutions for the battery
switch based on the user’s choice for the switching
device, Q8. The solution in Figure 1a is for users who
choose a bipolar device as a switch. In this case, R17 is
used to limit the power dissipation on Q7. Given βmin of
Q8 and Q7 and the maximum current drawn from VREG
(IVREG), the required emitter current for Q7 is as follows:
β minQ7 + 1
I EQ7 ≅  ------------------ + ----------------- × ---------------------------β minQ7
β minQ8
R16 = ----------------------------------0.01 × I DCSW
β minQ7 + 1
I EQ7 ≅  ------------------ + 0.01 × I DCSW × --------------------------- β minQ8
β minQ7
If IEQ7 ≤ IDCSW, the design is complete. If IEQ7 > IDCSW,
a bipolar for Q8 that has a higher βmin should be
chosen. If IEQ7 << IDCSW, the current provided by the
chip may be reduced by inserting a series resistor (R18)
in the emitter of Q7 given by the following equation:
By design, the maximum current provided to the DCSW
pin of Si3211/12 is IDCSW = 4 mA.
Select R16 such that IR16 = 0.01 x IDCSW. With this in
mind, consider the following:
Rev. 0.31
V DD – 0.66
R18 ≅ ----------------------------------- = ----------------------------I EQ7
Both Q7 and Q8 should be SOT23 330 mW devices.
Check the power dissipation on Q7 and Q8:
= I
= I
= I
⋅ (V
+ V
R16 = -----------------I R16
The solution in Figure 1b employs a MOS device. As
the gate current for Q8 is zero, the current through R16
can be quite small. Set IR16 = 0.5 mA (or lower).
Calculate R18 to generate this amount of current:
V DD – 0.66
R18 ≅ ----------------------------------- = ----------------------------I R16
I R16
Select Q7 as a low-power NPN device (e.g., 330 mW
For VDD = 3.3 V, IR16 = 0.5 mA and VGSQ8 = 10 V
(BSS123), R17 = 5.28 kΩ and R16 = 20 kΩ. Choose
R1 7= 5.1 kΩ and R16 = 20 kΩ. Check the power
dissipation on Q8:
P dQ8 = I
BSS123 (N-channel MOSFET from ZETEX, 5.5¢ for
1 Million parts, Vthmax = 2.8 V, RDS(on) = 6 Ω
at VGS = 10 V)
× R DS ( on )
Reconfirm that BS123 in a SOT23 package is enough in
terms of temperature derated power dissipation.
The solution in Figure 1c employs a Darlington bipolar
transistor. Table 1 presents choices for Darlington
devices. Since the βmin of the Darlington device is high
enough, the values for R16 and R18 can be calculated
using the equations on this page. Calculate the power
dissipation on Q8:
CMPT5401, PD = 330 mW.
Select Q8 as a low-power n-channel MOS device
(SOT23 package):
BSS123 Infineon or Philips
⋅ R17 )
As an initial value, select R17 = 6.2 kΩ/0.25 W. If PdQ7
exceeds the temperature derated maximum power
dissipation, slightly increase the value of R17. It is to be
expected that Q8, being in saturation, will not exceed
the temperature derated maximum power dissipation.
P dQ8 = I VREG ⋅ V CEsatQ8
Note: For a Darlington device, VCEsatQ8 is almost twice that
of a single transistor (≈ 0.8 V).
Table 1. Darlington Devices
Transistor Type
Manufacturer Package
625 mW
625 mW
625 mW
Important notes for the board layout design:
Si321x Layout Considerations
Reserve resistor space in the collector as well as the
emitter of Q7.
! Layout Q7 as a SOT23 device PD = 300 mW.
The ProSLIC circuit layout can be laid out to achieve
optimal noise performance. This document describes
the ProSLIC circuit parameters.
There are low-impedance, current input pins on the
ProSLIC that are highly sensitive to induced signals.
These include the sense input pins IREF, CAPP, CAPM,
SRINGAC, IGMN, and IGMP. The connection to the
passive component needs to be as short a trace as
possible. Sensitive trace passive components include
R14, C1, C2, R1, R3, R2, R5, R4, R8, R9, and R15.
Refer to the Si3210PPT-EVB data sheet for the
recommended layout of these components.
Layout Q8 as a SOT23 and TO92 device.
R16, R17, R18, R19, R20, C9, C10, L1, D1,
Q7, Q8—DC-DC Converter
For applications using the on-chip dc-dc converter
controller, a number of external components are needed
to generate the battery voltage. Refer to “AN45: Design
Guide for the Si3210/15/16 DC-DC Converter”
application note for component calculation and
The ProSLIC groups digital pins at one end of the
package and analog pins at the other end. The two ends
Rev. 0.31
are separated by ground and VDD pins. These are
meant to delineate the noisy region (digital) from the
sensitive end (analog). Retain this separation on all
layers. Multi-layer layouts allow for this.
The normal practice of placing a bypass ceramic
capacitor at each VDD pin should be followed. A
standard low-voltage X7R, 0.1 µF is sufficient. A 10 µF
should also be used on the VDDD pin. The application of
these components is discussed in the “Si3210
BJT-Inductor DC-to-DC Converter Circuit” section.
Capacitor C26 should be placed near the Q5/Q6 emitter
resistor connections to VBAT to ensure stability of the
output circuit.
Filter VBAT includes a 0.1 µF at 100 V placed on the
VBAT supply rail of all ProSLIC circuits. This capacitor
should be placed near the Q5 and Q6 emitter resistor
connections to VBAT (R6 and R7).
If more than two layers are required for the overall
board circuit, separate analog and digital trace layers
may enhance support. Digital signal and their property
as a noise source are best applied to a dedicated layer.
An optimal scenario is if the digital layers can be
separated from analog layers by a power/ground plane.
For robust power-up operation, a pull-down resistor
should be placed on the RESET pin of the ProSLIC.
The RESET pin should be pulled up by active logic for
normal operation.
Si3210 BJT-Inductor DC-to-DC Converter
The Si3210 dc-dc converter circuit operates in a current
pulse mode. This circuit needs to be laid out carefully to
minimize the contributed noise. The dc-dc converter has
specific current loops that must be further optimized to
minimize this noise effect. Following the schematic and
layout defined in the Si3210PPT-EVB data sheet is
These current paths are best dealt with by applying the
related components near the circuit. Current loop 1 in
Figure 2 is the primary input current loop for the dc-dc
converter from the +VDC power supply. +VDC
capacitors should include a 10 µF electrolytic, tantalum
or ceramic combined with a 0.1 µF ceramic X7R. The
+VDC 10 µF capacitor can be selected for appropriate
cost/voltage relative to availability and noise
requirements. These components should be placed
near the sense resistor (R18) to minimize the inductive
Current loop 2 is the secondary fly-back current path
which creates the negative VBAT potential. The VBAT
filtering should consist of a standard electrolytic and an
X7R ceramic combined with an RC network. The VBAT
electrolytic (C9) should be 10 µF, 100 V. The
high-frequency components that can modulate the
TIP/RING output circuitry. RFILT is a 15 Ω, 1/8 W, 0805
resistor. CFILT is a 0.1 µF, 100 V ceramic X7R
Current loop 3 is an ancillary current loop that assists
the dc-dc converter’s function. The Si3210 supplies
switching current from its DCFF pin, thus, the current
surges on VDDD are also a source of noise. A 10 µF
tantalum or ceramic capacitor should be applied at the
VDDD pin in parallel with the standard 0.1 µF X7R
bypass capacitor.
Note the potentially large current in the ground path
between L1 and C25 as well as L1 and C9. These
ground paths should be given dedicated and short
traces with a single connection to the ground plane.
This layout keeps current pulses out of the ground
plane. The C30 ground current is not as large as the
previous two ground currents mentioned.
R19, R20, and R18 should be placed as close to the
Si3210 as possible, and the circuit loop area formed by
these components and the Si3210 should be minimized
by running short parallel connection traces among the
components. In addition, Q9 should be placed as close
to the Si3210 as possible. SDCH and SDCL are
current-sensing pins and are sensitive to noise. The
presence of noise in these pins can cause the dc-dc
converter to skip cycles and result in higher floor noise
in the SLIC circuit and distortion to the ringing signal.
Since this current sensing loop circuit is located among
high current carrying traces and the magnetic
components (L1 or T1), it is likely to get coupling noise
through magnetic induction. The smaller surface loop
area in this current-sensing circuit reduces the magnetic
coupling and minimizes noise induction to the SDCH
and SDCL pins.
All sensitive current input pins on the Si3210 must still
have their respective components placed near the pin
for optimized noise performance. Digital routing must
also be kept away from these sensitive circuits. Refer to
the Si3210PPT-EVB data sheet for layout preference.
Example part numbers for the respective components
are as follows:
C9, C25: Panasonic, ECE-A2AGE100, Electrolytic
C30: Panasonic, ECS-T1CX106R, Tantalum (C1,
C2, C25, and C30 can be the same 10 µF tantalum
or ceramic part depending on +VDC selection)
! C11, C26: AVX, 12101C104MATA
To achieve a better noise floor (up to 2 dB), apply a
return trace from L1 to the +VDC source ground in
conjunction with the application of low ESR components
Rev. 0.31
to C9 and C25, and increase CFILT to 0.47 µF. (C25 is a
low ESR component if the same ceramic or tantalum as
C1, C2, and C30 is used.)
Loop 3
10 µ F
10 µ F
100 V
0.33 Ω
200 Ω
22 n
0.1 µ F
100 V
Loop 1
200 Ω
10 µ F
100 V
0.1 µ F
100 V
Localized ground traces
Loop 2
0.1 µ F
100 V
Single point connection
to ground plane.
Figure 2. BJT Inductor DC-DC Converter
Rev. 0.31
Si3210 Transformer-MOSFET DC-DC
Converter Circuit
Special Consideration For +VDC and VDD
Common Voltage Source
This is the second Si3210 dc-dc converter option that
provides improved +VDC input voltage range and better
efficiency. This circuit also has high-current loops that
need to be addressed carefully to minimize the coupling
noise to the sensitive SLIC circuit.
The Si3210 dc-dc converter can operate with a +VDC
voltage level as low as 3.3 V. This opens up a unique
Si3210 capability for applications that have only one
low-voltage 3.3 to 5 V supply. For this design to work
properly, it is critical to make sure that the single voltage
source has enough power for both the Si3210 IC and
the dc-dc converter circuit. The Si3210 data sheet
provides the Si3210 maximum current consumption,
and the Si3210 dc-dc converter interactive spreadsheet
provides peak and average currents required per
specific application design (REN loading, ringing
voltage, and line length). The Si3210 dc-dc switching
converter generates noise on the +VDC, and an
inductor with a minimum value of 47 µH, 120 mA and
maximum dc resistance of 2 Ω is recommended on the
Si3210 VDD current path to isolate the dc-dc converter
noise from the Si3210 sensitive VDD power pin. Another
inductor is recommended to isolate the dc-dc converter
noise from the power-feeding path to the rest of the
application circuit (DSP, Microcontroller, etc.).
Figure 3 provides the diagram for the three current
loops in the Transformer-MOSFET dc-dc converter.
These current paths are best dealt with by locating all
components in the related loop circuit near one another.
The selection for the components in these three loops is
similar to the process described in the previous section.
The detailed transformer, T1, and the MOSFET
selection information are provided in “AN45: Design
Guide for the Si3210 DC-DC Converter”. Refer to the
Si3210MPPT-EVB data sheet for specific layout
Loop 3
10 uF
Loop 1
R21 15
10 uF
CFILT 0.1 uF
Localized ground traces
Loop 2
--Single point connection
to ground plane
Figure 3. Transformer-MOSFET DC-DC Converter
0.1 uF
10 uF
Rev. 0.31
Layout Check List
For all designs, perform the following steps:
Si3201 design
1. Copy as much (ideally all) of the Si3210 evaluation
board/example layout as possible.
For the Si3201, perform the following steps:
3. No power/ground planes under protection circuitry.
1. Si3201 should be placed below pins 19 and 20 of the
Si3210 and oriented similarly to the Si3210 example layout
placement, with pins 1 and 16 facing pins 19 and 20 of the
4. Digital signals from the Si3210 routed above pins 1 and 38
end of Si3210 device as on the Si3210 evaluation board.
2. C5 and C6 placed as close as possible to Si3201 pins 1
and 3.
5. Analog traces routed away from digital traces. Not routed
near pins 1 and 38 end of Si3210.
3. The ac and dc sensing circuit for tip (R1, C3) and ring (R3,
C4) lines should be connected directly to C5 and C6
2. DC-DC converter placed above pins 1 and 38 end of the
Si3210 device as on the Si3210 evaluation board.
6. VDD caps should be placed close to the power and ground
pins. All power and ground connections between the
Si3210 IC power pins and the bypass caps should be
connected together via short traces.
7. Separate GND and digital trace layers if the board has four
or more layers. Ideally separated by power/GND plane.
8. R1, R2, R3, R4, R5, R8, R9, R14, R15 and C1, C2 placed
close to pins with no digital traces in path.
9. Thickness of high current traces (i.e. dc-dc conv, T/R
lines), etc., should be at least 50 mils.
10. Avoid running the digital/analog trace away from the high
current dc-dc converter components and traces: T1, L1,
D1, M1, C9, C25, R18.
11. Minimize the surface area formed by the R18, R19, and
R20. The R19 and R20 should be placed close to the
Si3210 IC, and the sensing trace between R18 to the R19
and R20 should be routed tightly in parallel or on top of
each other on two separate layers.
Discrete transistor design
For discrete transistors, perform the following steps:
1. Discrete transistors should be placed similarly to the
Si3210 evaluation board placement near pins 19 and 20 of
the Si3210.
2. C5 placed as close as possible to the collector of
transistors Q1 and Q6.
3. C6 placed as close as possible to the collector of
transistors Q2 and Q5.
4. C26 placed as close as possible to the emitter resistor of
transistors Q5 and Q6.
5. The ac and dc sensing circuit for tip (R1, C3) and ring (R3,
C4) lines should be connected directly to C5 and C6
For the Si3210, perform the following steps:
1. Localize ground trace connections for C25, C14, C9, and
L1 with a single connection point to the main ground plane.
2. Minimize the primary current loop area comprised of C15,
C14, R18, Q7, and L1.
3. Minimize the secondary current loop area comprised of
C9, D1, and L1.
For the Si3210M, perform the following steps:
1. Localize ground trace connections for C25, C14, C9,
transformer pin 10, and M1 source pin with a single trace
connection to the main ground plane.
2. Minimize the primary current loop area comprises of C15,
C14, R18, T1 primary coil, and M1.
3. Minimize the secondary current loop area comprised of
C9, D1, and T1 secondary coil.
Rev. 0.31
Document Change List
Revision 0.3 to Revision 0.31
Updated "R6, R7—Emitter Current Sensing
Resistors" on page 2.
! Updated "The Si3201 Line Voltage IC" on page 5.
! Added "Layout Check List" on page 11.
Rev. 0.31
Rev. 0.31
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Rev. 0.31