Si53308 D U A L 1 : 3 L O W - J I T T E R B UFFER / L EVEL T RANSLATOR Features Ordering Information: See page 28. Storage Telecom Industrial Servers Backplane clock distribution Q2 Q3 Q3 Q4 Q4 26 25 27 28 29 30 Vref Generator DIVA SFOUTA[1] SFOUTA[0] 1 24 2 23 SFOUTB[1] 3 22 SFOUTB[0] Q0 Q0 4 21 GND 6 19 Q5 Q5 VDDOB VDD 7 18 VDDOA NC 8 17 VREF GND PAD 15 16 LOS1 20 CLK1 5 DIVB Patents pending Functional Block Diagram VREF 31 The Si53308 is an ultra low jitter six output differential buffer with pin-selectable output clock signal format and divider selection. The device is a dual 1:3 buffer providing the functionality of two independent buffers in a single IC. The Si53308 utilizes Silicon Laboratories' advanced CMOS technology to fanout clocks from 1 to 725 MHz with guaranteed low additive jitter, low skew, and low propagation delay variability. The Si53308 features minimal cross-talk and provides superior supply noise rejection, simplifying low jitter clock distribution in noisy environments. Independent core and output bank supply pins provide integrated level translation without the need for external circuitry. Si53308 32 Description Pin Assignments 14 High-speed clock distribution Ethernet switch/router Optical Transport Network (OTN) SONET/SDH PCI Express Gen 1/2/3 13 12 OEA OEB CLK1 Applications Q1 Q2 11 CLK0 Q1 9 Loss of signal (LOS) monitors for loss of input clock Independent VDD and VDDO : 1.8/2.5/3.3 V Selectable LVCMOS drive strength to tailor jitter and EMI performance Small size: 32-QFN (5 mm x 5 mm) RoHS compliant, Pb-free Industrial temperature range: –40 to +85 °C 10 6 differential or 12 (in phase) LVCMOS outputs Ultra-low additive jitter: 45 fs rms Wide frequency range: 1 to 725 MHz Any-format input with pin selectable output formats: LVPECL, low power LVPECL, LVDS, CML, HCSL, LVCMOS Synchronous output enable Output clock division: /1, /2, /4 Low output-output skew: 25 ps LOS0 CLK0 Power Supply Filtering DIVA VDDOA SFOUTA[1:0] OEA CLK0 Q0, Q1, Q2 DivA CLK0 Q0, Q1, Q2 DIVB VDDOB SFOUTB[1:0] OEB Q3, Q4, Q5 CLK1 DivB CLK1 Rev. 0.9 6/13 Q3, Q4, Q5 Copyright © 2013 by Silicon Laboratories Si53308 Si53308 2 Rev. 0.9 Si53308 TABLE O F C ONTENTS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1. Universal, Any-Format Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2. Input Bias Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3. Universal, Any-Format Output Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.4. Synchronous Output Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.5. Flexible Output Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.6. Output Enable Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.7. Loss of Signal (LOS) Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.8. Power Supply (VDD and VDDOX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.9. Output Clock Termination Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 2.10. AC Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.11. Typical Phase Noise Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.12. Input Noise Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.13. Power Supply Noise Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3. Pin Description: 32-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.1. 5x5 mm 32-QFN Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 6.1. 5x5 mm 32-QFN Package Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.1. Si53308 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Rev. 0.9 3 Si53308 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Ambient Operating Temperature Supply Voltage Range* Output Buffer Supply Voltage* Symbol Test Condition Min Typ Max Unit –40 — 85 °C 1.71 1.8 1.89 V 2.38 2.5 2.63 V 2.97 3.3 3.63 V LVPECL, low power LVPECL, LVCMOS 2.38 2.5 2.63 V 2.97 3.3 3.63 V HCSL 2.97 3.3 3.63 V LVDS, CML 1.71 1.8 1.89 V 2.38 2.5 2.63 V 2.97 3.3 3.63 V LVPECL, low power LVPECL, LVCMOS 2.38 2.5 2.63 V 2.97 3.3 3.63 V HCSL 2.97 3.3 3.63 V TA VDD VDDOX LVDS, CML *Note: Core supply VDD and output buffer supplies VDDO are independent. Table 2. Input Clock Specifications (VDD=1.8 V 5%, 2.5 V 5%, or 3.3 V 10%, TA=–40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Differential Input Common Mode Voltage VCM VDD = 2.5 V 5%, 3.3 V 10% 0.05 — — V Differential Input Swing (peak-to-peak) VIN 0.2 — 2.2 V LVCMOS Input High Voltage VIH VDD = 2.5 V 5%, 3.3 V 10% VDD x 0.7 — — V LVCMOS Input Low Voltage VIL VDD = 2.5 V 5%, 3.3 V 10% — — VDD x 0.3 V Input Capacitance CIN CLK0 and CLK1 pins with respect to GND — 5 — pF 4 Rev. 0.9 Si53308 Table 3. DC Common Characteristics (VDD = 1.8 V 5%, 2.5 V 5%, or 3.3 V 10%,TA = –40 to 85 °C) Parameter Supply Current Output Buffer Supply Current (Per Clock Output) @100 MHz (diff) @200 MHz (CMOS) Symbol Test Condition Min Typ Max Unit — 65 100 mA LVPECL (3.3 V) — 35 — mA Low Power LVPECL (3.3 V)* — 35 — mA LVDS (3.3 V) — 20 — mA CML (3.3 V) — 35 — mA HCSL, 100 MHz, 2 pF load (3.3 V) — 35 — mA CMOS (2.5 V, SFOUT = Open/0), per output, CL = 5 pF, 200 MHz — 8 — mA CMOS (3.3 V, SFOUT = 0/1), per output, CL = 5 pF, 200 MHz — 15 — mA IDD IDDOX Voltage Reference VREF VREF pin (VDD = 2.5/3.3 V) — VDD/2 — V Input High Voltage VIH SFOUTX, DIVX, OEX 0.8xVDD — — V Input Mid Voltage VIM SFOUTX, DIVX 3-level input pins Input Low Voltage VIL SFOUTX, DIVX, OEX — — 0.2xVDD V Output Voltage High VOH IDD = –1 mA 0.8xVDD — — V Output Voltage Low VOL IDD = 1 mA — — 0.2xVDD V RDOWN DIVX, SFOUTX — 25 — k RUP DIVX, SFOUTX, OEX — 25 — k Internal Pull-down Resistor Internal Pull-up Resistor 0.45xVDD 0.5xVDD 0.55xVDD V *Note: Low-power LVPECL mode supports an output termination scheme that will reduce overall system power. Rev. 0.9 5 Si53308 Table 4. Output Characteristics (LVPECL) (VDD = VDDOX = 2.5 V ± 5%, or 3.3 V ± 10%,TA = –40 to 85 °C) Parameter Symbol Output DC Common Mode Voltage Min Typ Max Unit VCOM VDDOX – 1.595 — VDDOX – 1.245 V VSE 0.55 0.80 1.050 V Single-Ended Output Swing* Test Condition *Note: Unused outputs can be left floating. Do not short unused outputs to ground. Table 5. Output Characteristics (Low Power LVPECL) (VDD = VDDOX = 2.5 V ± 5%, or 3.3 V ± 10%,TA = –40 to 85 °C) Parameter Symbol Test Condition Min Output DC Common Mode Voltage VCOM RL = 100 across Qn and Qn VDDOX – 1.895 VSE RL = 100 across Qn and Qn 0.25 Single-Ended Output Swing* Typ 0.60 Max Unit VDDOX – 1.275 V 0.85 V *Note: RL = 100 across Qn and Qn. Table 6. Output Characteristics—CML (VDD = VDDOX = 1.8 V 5%, 2.5 V 5%, or 3.3 V 10%,TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Single-Ended Output Swing VSE Terminated as shown in Figure 7 (CML termination). 300 400 500 mV Table 7. Output Characteristics—LVDS (VDD = VDDOX = 1.8 V 5%, 2.5 V 5%, or 3.3 V 10%,TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Single-Ended Output Swing VSE RL = 100 Ω across QN and QN 247 — 454 mV Output Common Mode Voltage (VDDO = 2.5 V or 3.3V) VCOM1 VDDOX = 2.38 to 2.63 V, 2.97 to 3.63 V, RL = 100 Ω across QN and QN 1.10 1.25 1.35 V Output Common Mode Voltage (VDDO = 1.8 V) VCOM2 VDDOX = 1.71 to 1.89 V, RL = 100 Ω across QN and QN 0.85 0.97 1.10 V 6 Rev. 0.9 Si53308 Table 8. Output Characteristics—LVCMOS (VDD = VDDOX = 2.5 V 5%, or 3.3 V 10%,TA = –40 to 85 °C) Parameter Symbol Output Voltage High* Output Voltage Low* Test Condition Min Typ Max Unit VOH 0.80 x VDDOX — — V VOL — — 0.20 x VDDOX V *Note: IOH and IOL per the Output Signal Format Table for specific VDDOX and SFOUTX settings. Table 9. Output Characteristics—HCSL (VDD = VDDOX = 3.3 V ± 10%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Output Voltage High VOH RL = 50 Ω to GND 550 700 850 mV Output Voltage Low VOL RL = 50 Ω to GND –150 0 150 mV Single-Ended Output Swing VSE RL = 50 Ω to GND 550 700 850 mV Crossing Voltage VC RL = 50 Ω to GND 250 350 550 mV Table 10. AC Characteristics (VDD = VDDOX = 1.8 V 5%, 2.5 V 5%, or 3.3 V 10%,TA = –40 to 85 °C) Parameter LOS Deassertion Time1 LOS Assertion Time2 Frequency Duty Cycle Note: 50% input duty cycle. Symbol Test Condition Min Typ Max Unit TLOSCLR F < 100 MHz — Tper+15 — ns F > 100 MHz — 25 — ns — 15 — µs LVPECL, low power LVPECL, LVDS, CML, HCSL 1 — 725 MHz LVCMOS 1 — 200 MHz 200 MHz, 20/80%TR/TF<10% of period (LVCMOS) (12 mA drive) 40 50 60 % 20/80% TR/TF<10% of period (Differential) 48 50 52 % TLOSACT F DC Notes: 1. Measured from the initial transition of the corresponding input clock to the falling edge of LOS 2. Measured from the final transition of the corresponding input clock to the rising edge of LOS. 3. When using the on-chip clock divider, a minimum input clock slew rate of 30 mV/ns is required. 4. Measurements were made with receiver termination. See Figure 7 on page 18. 5. Output to Output skew specified for outputs with an identical configuration. 6. Defined as skew between any output on different devices operating at the same supply voltages, temperatures, and equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. 7. Measured for 156.25 MHz carrier frequency. Sine-wave noise added to VDDOX (3.3 V = 100 mVPP) and noise spur amplitude measured. See “AN491: Power Supply Rejection for Low-Jitter Clocks” for further details. Rev. 0.9 7 Si53308 Table 10. AC Characteristics (Continued) (VDD = VDDOX = 1.8 V 5%, 2.5 V 5%, or 3.3 V 10%,TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Minimum Input Clock Slew Rate3 SR Required to meet prop delay and additive jitter specifications (20–80%) 0.75 — — V/ns Output Rise/Fall Time TR/TF LVPECL, LVDS, CML, HCSL4, LowPower LVPECL 20/80% — — 350 ps 200 MHz, 20/80%, 2 pF load (LVCMOS) — — 750 ps 500 — — ps Minimum Input Pulse Width Additive Jitter (Differential Clock Input) Propagation Delay Output Enable Time Output Disable Time Output to Output Skew5 Part to Part Skew6 TW J VDD = VDDOX = 2.5/3.3 V, LVPECL/ LVDS, F = 725 MHz, 0.75 V/ns input slew rate — 50 65 fs TPLH, TPHL LVPECL 500 700 900 ps LVDS — 700 — ps TEN F = 1 MHz — 2500 — ns F = 100 MHz — 30 — ns F = 725 MHz — 5 — ns F = 1 MHz — 2000 — ns F = 100 MHz — 30 — ns F = 725 MHz — 5 — ns LVCMOS, drive 12 mA to 2 pF — 60 — ps LVPECL — 30 75 ps LVDS — 50 — ps Differential — — 150 ps TDIS TSK TPS Notes: 1. Measured from the initial transition of the corresponding input clock to the falling edge of LOS 2. Measured from the final transition of the corresponding input clock to the rising edge of LOS. 3. When using the on-chip clock divider, a minimum input clock slew rate of 30 mV/ns is required. 4. Measurements were made with receiver termination. See Figure 7 on page 18. 5. Output to Output skew specified for outputs with an identical configuration. 6. Defined as skew between any output on different devices operating at the same supply voltages, temperatures, and equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. 7. Measured for 156.25 MHz carrier frequency. Sine-wave noise added to VDDOX (3.3 V = 100 mVPP) and noise spur amplitude measured. See “AN491: Power Supply Rejection for Low-Jitter Clocks” for further details. 8 Rev. 0.9 Si53308 Table 10. AC Characteristics (Continued) (VDD = VDDOX = 1.8 V 5%, 2.5 V 5%, or 3.3 V 10%,TA = –40 to 85 °C) Parameter Power Supply Noise Rejection7 Symbol Test Condition Min Typ Max Unit PSRR 10 kHz sinusoidal noise — –65 — dBc 100 kHz sinusoidal noise — –62 — dBc 500 kHz sinusoidal noise — –60 — dBc 1 MHz sinusoidal noise — –55 — dBc Notes: 1. Measured from the initial transition of the corresponding input clock to the falling edge of LOS 2. Measured from the final transition of the corresponding input clock to the rising edge of LOS. 3. When using the on-chip clock divider, a minimum input clock slew rate of 30 mV/ns is required. 4. Measurements were made with receiver termination. See Figure 7 on page 18. 5. Output to Output skew specified for outputs with an identical configuration. 6. Defined as skew between any output on different devices operating at the same supply voltages, temperatures, and equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. 7. Measured for 156.25 MHz carrier frequency. Sine-wave noise added to VDDOX (3.3 V = 100 mVPP) and noise spur amplitude measured. See “AN491: Power Supply Rejection for Low-Jitter Clocks” for further details. Rev. 0.9 9 Si53308 Table 11. Additive Jitter, Differential Clock Input VDD Output Input1,2 Freq (MHz) Clock Format Amplitude VIN (Single-Ended, Peak-to-Peak) Differential Clock Format 20%-80% Slew Rate (V/ns) Additive Jitter (fs rms, 12 kHz to 20 MHz)3 Typ Max 3.3 725 Differential 0.15 0.637 LVPECL 45 65 3.3 725 Differential 0.15 0.637 LVDS 50 65 3.3 156.25 Differential 0.5 0.458 LVPECL 160 185 3.3 156.25 Differential 0.5 0.458 LVDS 150 200 2.5 725 Differential 0.15 0.637 LVPECL 45 65 2.5 725 Differential 0.15 0.637 LVDS 50 65 2.5 156.25 Differential 0.5 0.458 LVPECL 145 185 2.5 156.25 Differential 0.5 0.458 LVDS 145 195 Notes: 1. For best additive jitter results, use the fastest slew rate possible. See “AN766: Understanding and Optimizing Clock Buffer’s Additive Jitter Performance” for more information. 2. AC-coupled differential inputs. 3. Measured differentially using a balun at the phase noise analyzer input. See Figure 1. 10 Rev. 0.9 Si53308 Table 12. Additive Jitter, Single-Ended Clock Input VDD Output Input1,2 Freq (MHz) Clock Format Amplitude VIN (single-ended, peak to peak) Additive Jitter (fs rms, 12 kHz to 20 MHz)3 SE 20%-80% Slew Rate (V/ns) Clock Format Typ Max 3.3 200 Single-ended 1.70 1 LVCMOS4 120 160 3.3 156.25 Single-ended 2.18 1 LVPECL 160 185 3.3 156.25 Single-ended 2.18 1 LVDS 150 200 3.3 156.25 Single-ended 2.18 1 LVCMOS4 130 180 2.5 200 Single-ended 1.70 1 LVCMOS5 120 160 2.5 156.25 Single-ended 2.18 1 LVPECL 145 185 2.5 156.25 Single-ended 2.18 1 LVDS 145 195 2.5 156.25 Single-ended 2.18 1 LVCMOS5 140 180 Notes: 1. For best additive jitter results, use the fastest slew rate possible. See “AN766: Understanding and Optimizing Clock Buffer’s Additive Jitter Performance” for more information. 2. DC-coupled single-ended inputs. 3. Measured differentially using a balun at the phase noise analyzer input. See Figure 1. LVCMOS jitter is measured single-ended. 4. Drive Strength: 12 mA, 3.3 V (SFOUT = 11). 5. Drive Strength: 9 mA, 2.5 V (SFOUT = 11). PSPL 5310A CLK SYNTH SMA103A 50 Si533xx DUT Balun PSPL 5310A CLKx AG E5052 Phase Noise Analyzer 50ohm 50 /CLKx Balun Figure 1. Differential Measurement Method Using a Balun Rev. 0.9 11 Si53308 Table 13. Thermal Conditions Parameter Symbol Test Condition Value Unit Thermal Resistance, Junction to Ambient JA Still air 49.6 °C/W Thermal Resistance, Junction to Case JC Still air 32.3 °C/W Table 14. Absolute Maximum Ratings Parameter Symbol Storage Temperature Min Typ Max Unit TS –55 — 150 C Supply Voltage VDD –0.5 — 3.8 V Input Voltage VIN –0.5 — VDD+ 0.3 V Output Voltage VOUT — — VDD+ 0.3 V ESD Sensitivity HBM — — 2000 V ESD Sensitivity CDM — — 500 V Peak Soldering Reflow Temperature TPEAK — — 260 C — — 125 C Maximum Junction Temperature Test Condition HBM, 100 pF, 1.5 k Pb-Free; Solder reflow profile per JEDEC J-STD-020 TJ Note: Stresses beyond those listed in this table may cause permanent damage to the device. Functional operation specification compliance is not implied at these conditions. Exposure to maximum rating conditions for extended periods may affect device reliability. 12 Rev. 0.9 Si53308 2. Functional Description The Si53308 is a low-jitter, low-skew, dual 1:3 differential output buffer. The device has a universal input that accepts most common differential or LVCMOS input signals. Each output bank features control pins to select signal format, output enable, output divider setting and LVCMOS drive strength. 2.1. Universal, Any-Format Input The Si53308 has a universal input stage that enables simple interfacing to a wide variety of clock formats, including LVPECL, low-power LVPECL, LVCMOS, LVDS, HCSL, and CML. Tables 15 and 16 summarize the various ac- and dc-coupling options supported by the device. Figures 3 and 4 show the recommended input clock termination options. For the best high-speed performance, the use of differential formats is recommended. For both singleended and differential input clocks, the fastest possible slew rate is recommended since low slew rates can increase the noise floor and degrade jitter performance. Though not required, a minimum slew rate of 0.75 V/ns is recommended for differential formats and 1.0 V/ns for single-ended formats. Table 15. LVPECL, LVCMOS, and LVDS LVPECL LVCMOS LVDS AC-Couple DC-Couple AC-Couple DC-Couple AC-Couple DC-Couple 1.8 V N/A N/A N/A N/A Yes No 2.5/3.3 V Yes Yes No Yes Yes Yes Table 16. HCSL and CML HCSL CML AC-Couple DC-Couple AC-Couple DC-Couple 1.8 V N/A N/A Yes No 2.5/3.3 V Yes (3.3 V) Yes (3.3 V) Yes No 0.1 µF Si533xx CLKx 100 /CLKx 0.1 µF Figure 2. Differential HCSL, LVPECL, Low-Power LVPECL, LVDS, CML AC-Coupled Input Termination VDD 1 k VDDO= 3.3 V or 2.5 V VDD Si533xx CMOS Driver CLKx 50 /CLKx Rs 1 k VTERM = VDD/2 Figure 3. LVCMOS DC-Coupled Input Termination Rev. 0.9 13 Si53308 VDDO DC Coupled LVPECL Termination Scheme 1 R1 VDD R1 VDDO = 3.3V or 2.5V Si533xx CLKx 50 “Standard” LVPECL Driver /CLKx 50 R2 VTERM = VDDO – 2V R1 // R2 = 50 Ohm R2 3.3V LVPECL: R1 = 127 Ohm, R2 = 82.5 Ohm 2.5V LVPECL: R1 = 250 Ohm, R2 = 62.5 Ohm DC Coupled LVPECL Termination Scheme 2 VDD VDDO = 3.3V or 2.5V Si533xx 50 “Standard” LVPECL Driver CLKx /CLKx 50 50 50 VTERM = VDDO – 2V DC Coupled LVDS Termination VDD VDDO = 3.3V or 2.5V Si533xx CLKx 50 Standard LVDS Driver /CLKx 50 100 DC Coupled HCSL Source Termination Scheme VDDO = 3.3V VDD 33 Si533xx 50 Standard HCSL Driver CLKx /CLKx 33 50 50 50 Note: 33 Ohm series termination is optional depending on the location of the receiver. DC Coupled HCSL Receiver Termination Scheme VDDO = 3.3V Si533xx Q VDD 50 Standard HCSL Receiver Qn 50 50 50 Figure 4. Differential DC-Coupled Input Terminations 14 Rev. 0.9 Si53308 2.2. Input Bias Resistors Internal bias resistors ensure a differential output low condition in the event that the clock inputs are not connected. The noninverting input is biased with a 18.75 k pulldown to GND and a 75 k pullup to VDD. The inverting input is biased with a 75 k pullup to VDD. VDD RPU RPU + RPD CLK0 or CLK1 – RPU = 75 k RPD = 18.75 k Figure 5. Input Bias Resistors 2.3. Universal, Any-Format Output Buffer The Si53308 has highly flexible output drivers that support a wide range of clock signal formats, including LVPECL, low power LVPECL, LVDS, CML, HCSL, and LVCMOS. SFOUTX[1] and SFOUTX[0] are 3-level inputs that can be pin-strapped to select the Bank A or Bank B clock signal formats. This feature enables the device to be used for format translation in addition to clock distribution, minimizing the number of unique buffer part numbers required in a typical application and simplifying design reuse. For EMI reduction applications, four LVCMOS drive strength options are available for each VDDO setting. Table 17. Output Signal Format Selection SFOUTX[1] SFOUTX[0] VDDOX = 3.3 V VDDOX = 2.5 V VDDOX = 1.8 V Open* Open* LVPECL LVPECL N/A 0 0 LVDS LVDS LVDS 0 1 LVCMOS, 24 mA drive LVCMOS, 18 mA drive N/A 1 0 LVCMOS, 18 mA drive LVCMOS, 12 mA drive N/A 1 1 LVCMOS, 12 mA drive LVCMOS, 9 mA drive N/A Open* 0 LVCMOS, 6 mA drive LVCMOS, 4 mA drive N/A Open* 1 LVPECL low power LVPECL low power N/A 0 Open* CML CML CML 1 Open* HCSL N/A N/A *Note: SFOUTX are 3-level input pins. Tie low for “0” setting. Tie high for “1” setting. When left open, the pin floats to VDD/2. Rev. 0.9 15 Si53308 2.4. Synchronous Output Enable The Si53308 features a synchronous output enable (disable) feature. Output enable is sampled and synchronized on the falling edge of the input clock. This feature prevents runt pulses from being generated when the outputs are enabled or disabled. When OE is low, Q is held low and Q is held high for differential output formats. For LVCMOS output format options, both Q and Q are held low when OE is set low. The device outputs are enabled when the output enable pin is unconnected. See Table 9, “Output Characteristics—HCSL,” on page 7 for output enable and output disable times. 2.5. Flexible Output Divider The Si53308 provides optional clock division in addition to clock distribution. The divider setting for each bank of output clocks is selected via 3-level control pins as shown in the table below. Leaving the DIVX pins open will force a divider value of 1 which is the default mode of operation. Table 18. Post Divider Selection DIVX Divider Value Open* 1 (default) 0 2 1 4 *Note: DIVX are 3-level input pins. Tie low for “0” setting. Tie high for “1” setting. When left open, the pin floats to VDD/2. 2.6. Output Enable Logic Each 1:3 output has an independent clock input (CLK0/CLK1) and an output enable pin. Table 19 summarizes the input and output clock based upon the state of the input clock and the OE pin. Table 19. Input Clock and Output Enable Logic CLK OE1 Q2 L H L H H H X L L3 Notes: 1. Output enable active high. 2. On the next negative transition of CLK0 or CLK1. 3. Single-end: Q = low, Q = low. Differential: Q = low, Q = high. 2.7. Loss of Signal (LOS) Indicator The LOS0 and LOS1 indicators monitor for the presence of input clocks CLK0 and CLK1, respectively. In the event that an input clock is not present, the associated LOSx pin will assume a logic high (LOSx = 1) state. When a clock is present at the associated input clock pin, the LOSx pin will assume a logic low (LOSx = 0) state. 2.8. Power Supply (VDD and VDDOX) The device includes separate core (VDD) and output driver supplies (VDDOX). This feature allows the core to operate at a lower voltage than VDDO, reducing current consumption in mixed supply applications. The core VDD supports 3.3 V, 2.5 V, or 1.8 V. Each output bank has its own VDDOX supply, supporting 3.3 V, 2.5 V, or 1.8 V. 16 Rev. 0.9 Si53308 2.9. Output Clock Termination Options The recommended output clock termination options are shown below. Unused outputs can be left floating. Do not short unused outputs to ground. VDDO DC Coupled LVPECL Termination Scheme 1 R1 R1 VDDO = 3.3V or 2.5V Si533xx VDD = VDDO 50 Q LVPECL Receiver Qn 50 R2 VTERM = VDDO – 2V R1 // R2 = 50 Ohm R2 3.3V LVPECL: R1 = 127 Ohm, R2 = 82.5 Ohm 2.5V LVPECL: R1 = 250 Ohm, R2 = 62.5 Ohm DC Coupled LVPECL Termination Scheme 2 VDDO = 3.3V or 2.5V Si533xx VDD = VDDO 50 Q LVPECL Receiver Qn 50 50 50 VTERM = VDDO – 2V VDDO AC Coupled LVPECL Termination Scheme 1 R1 VDDO = 3.3V or 2.5V Si533xx R1 0.1 uF VDD = 3.3V or 2.5V 50 Q LVPECL Receiver Qn 50 0.1 uF Rb R2 Rb R2 VBIAS = VDD – 1.3V R1 // R2 = 50 Ohm 3.3V LVPECL: R1 = 82.5 Ohm, R2 = 127 Ohm, Rb = 120 Ohm 2.5V LVPECL: R1 = 62.5 Ohm, R2 = 250 Ohm, Rb = 90 Ohm AC Coupled LVPECL Termination Scheme 2 VDDO = 3.3V or 2.5V Si533xx 0.1 uF V DD = 3.3V or 2.5V 50 Q LVPECL Receiver Qn 50 0.1 uF Rb 50 Rb 50 V BIAS = V DD – 1.3 V 3.3V LVPECL: Rb = 120 Ohm 2.5V LVPECL: Rb = 90 Ohm Figure 6. LVPECL Output Termination Rev. 0.9 17 Si53308 DC Coupled LVDS and Low-Power LVPECL Termination VDDO = 3.3 V, 2.5 V, or 1.8 V (LVDS only) Si533xx VDD 50 Q LVDS Receiver Qn 50 100 AC Coupled LVDS and Low-Power LVPECL Termination VDDO = 3.3 V or 2.5 V or 1.8 V (LVDS only) Si533xx 0.1 uF VDD 50 Q LVDS Receiver Qn 50 0.1 uF 50 50 AC Coupled CML Termination VDDO = 3.3V or 2.5V or 1.8V Si533xx 0.1 uF VDD 50 Q CML Receiver 100 Qn 50 0.1 uF DC Coupled HCSL Receiver Termination VDDO = 3.3V Si533xx VDD 50 Q Standard HCSL Receiver Qn 50 50 50 DC Coupled HCSL Source Termination VDDO = 3.3V Si533xx VDD 42.2 50 Q Qn 42.2 50 86.6 Standard HCSL Receiver 86.6 Figure 7. LVDS, CML, HCSL, and Low-Power LVPECL Output Termination 18 Rev. 0.9 Si53308 CMOS Receivers Si533xx CMOS Driver Zout Zo Rs 50 Figure 8. LVCMOS Output Termination Table 20. Recommended LVCMOS RS Series Termination SFOUTX[1] SFOUTX[0] RS (ohms) 3.3 V 2.5 V 0 1 33 33 1 0 33 33 1 1 33 33 Open 0 0 0 Rev. 0.9 19 Si53308 2.10. AC Timing Waveforms TPHL TSK VPP/2 CLK Q VPP/2 QN QM VPP/2 VPP/2 TPLH TSK Propagation Delay Output-Output Skew TF Q 80% VPP 20% VPP Rise/Fall Time Figure 9. AC Waveforms 20 80% VPP 20% VPP Q Rev. 0.9 TR Si53308 2.11. Typical Phase Noise Performance Each of the following three figures shows three phase noise plots superimposed on the same diagram. Source Jitter: Reference clock phase noise. Total Jitter (SE): Combined source and clock buffer phase noise measured as a single-ended output to the phase noise analyzer and integrated from 12 kHz to 20 MHz. Total Jitter (Diff'l): Combined source and clock buffer phase noise measured as a differential output to the phase noise analyzer and integrated from 12 kHz to 20 MHz. The differential measurement as shown in each figure is made using a balun. See Figure 1 on page 11. Note: To calculate the total RMS phase jitter when adding a buffer to your clock tree, use the root-sum-square (RSS). The total jitter is a measure of the source plus the buffer's additive phase jitter. The additive jitter (rms) of the buffer can then be calculated (via root-sum-square addition). Figure 10. Source Jitter (156.25 MHz) Rev. 0.9 21 Si53308 Figure 11. Single-Ended Total Jitter (312.5 MHz) 22 Rev. 0.9 Si53308 Figure 12. Differential Total Jitter (625 MHz) Rev. 0.9 23 Si53308 2.12. Input Noise Isolation Figure 13. Input Noise Isolation 2.13. Power Supply Noise Rejection The device supports on-chip supply voltage regulation to reject noise present on the power supply, simplifying low jitter operation in real-world environments. This feature enables robust operation alongside FPGAs, ASICs and SoCs and may reduce board-level filtering requirements. For more information, see “AN491: Power Supply Rejection for Low Jitter Clocks”. 24 Rev. 0.9 Si53308 Q1 Q2 Q2 Q3 Q3 Q4 Q4 29 27 26 25 31 28 32 30 Q1 3. Pin Description: 32-Pin QFN DIVA 1 24 DIVB SFOUTA[1] SFOUTA[0] 2 23 SFOUTB[1] 3 22 SFOUTB[0] Q0 Q0 4 21 GND 6 19 Q5 Q5 VDDOB VDD 7 18 VDDOA NC 8 17 VREF 15 16 CLK1 LOS1 12 OEA OEB CLK1 14 11 20 CLK0 LOS0 CLK0 9 10 5 13 GND PAD Table 21. Pin Description Pin Name Description 1 DIVA Output divider control pin for Bank A. Three-level input control. Internally biased at VDD/2. Can be left floating or tied to ground or VDD. 2 SFOUTA[1] Output signal format control pin for Bank A. Three-level input control. Internally biased at VDD/2. Can be left floating or tied to ground or VDD. 3 SFOUTA[0] Output signal format control pin for Bank A. Three-level input control. Internally biased at VDD/2. Can be left floating or tied to ground or VDD. 4 Q0 Output clock 2 (complement). 5 Q0 Output clock 2. 6 GND Ground. 7 VDD Core voltage supply. Bypass with 1.0 µF capacitor and place close to the VDD pin as possible. 8 NC No connect. Rev. 0.9 25 Si53308 Table 21. Pin Description (Continued) 26 Pin Name Description 9 LOS0 The LOS0 status pin indicates whether a clock is present (LOS0 = 0) or not present (LOS0 = 1) at the CLK0 pin. 10 CLK0 Input clock 0. 11 CLK0 Input clock 0 (complement). When CLK0 is driven by a single-end input, connect CLK0 to VDD/2. 12 OEA Output enable—Bank A. When OE = high, the Bank A outputs are enabled. When OE = low, Q is held low and /Q is held high for differential formats. For LVCMOS, both Q and /Q are held low when OE is set low. OEA contains an internal pull-up resistor. 13 OEB Output enable—Bank B. When OE = high, the Bank B outputs are enabled. When OE = low, Q is held low and /Q is held high for differential formats. For LVCMOS, both Q and /Q are held low when OE is set low. OEB contains an internal pull-up resistor. 14 CLK1 Input clock 1. 15 CLK1 Input clock 1 (complement). When CLK1 is driven by a single-end input, connect CLK1 to VDD/2. 16 LOS1 The LOS1 status pin indicates whether a clock is present (LOS1 = 0) or not present (LOS1 = 1) at the CLK1 pin. 17 VREF Input reference voltage. 18 VDDOA Output Clock Voltage Supply—Bank A (Outputs: Q0 to Q2). Bypass with 1.0 µF capacitor and place close to the VDDOA pin as possible. 19 VDDOB Output Clock Voltage Supply—Bank B (Outputs: Q3 to Q5). Bypass with 1.0 µF capacitor and place close to the VDDOB pin as possible. 20 Q5 Output clock 5 (complement). 21 Q5 Output clock 5. 22 SFOUTB[0] Output signal format control pin for Bank B. Three-level input control. Internally biased at VDD/2. Can be left floating or tied to ground or VDD. 23 SFOUTB[1] Output signal format control pin for Bank B. Three-level input control. Internally biased at VDD/2. Can be left floating or tied to ground or VDD. Rev. 0.9 Si53308 Table 21. Pin Description (Continued) Pin Name Description 24 DIVB 25 Q4 Output clock 4 (complement). 26 Q4 Output clock 4. 27 Q3 Output clock 3 (complement). 28 Q3 Output clock 3. 29 Q2 Output clock 2 (complement). 30 Q2 Output clock 2. 31 Q1 Output clock 1 (complement). 32 Q1 Output clock 1. GND Pad GND Output divider control pin for Bank B. Three-level input control. Internally biased at VDD/2. Can be left floating or tied to ground or VDD. Ground Pad. Power supply ground and thermal relief. Rev. 0.9 27 Si53308 4. Ordering Guide 28 Part Number Package PB-Free, ROHS-6 Temperature Si53308-B-GM 32-QFN Yes –40 to 85 C Si53301/4-EVB NA Yes –40 to 85 C Rev. 0.9 Si53308 5. Package Outline 5.1. 5x5 mm 32-QFN Package Diagram Figure 14. Si53308 5x5 mm 32-QFN Package Diagram Table 22. Package Dimensions Dimension Min Nom Max A 0.80 0.85 1.00 A1 0.00 0.02 0.05 b 0.18 0.25 0.30 c 0.20 0.25 0.30 D D2 5.00 BSC 2.00 2.15 e 0.50 BSC E 5.00 BSC 2.30 E2 2.00 2.15 2.30 L 0.30 0.40 0.50 aaa 0.10 bbb 0.10 ccc 0.08 ddd 0.10 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MO-220. Rev. 0.9 29 Si53308 6. PCB Land Pattern 6.1. 5x5 mm 32-QFN Package Land Pattern Figure 15. Si53308 5x5 mm 32-QFN Package Land Pattern Table 23. PCB Land Pattern Dimension Min Max Dimension Min Max C1 4.52 4.62 X2 2.20 2.30 C2 4.52 4.62 Y1 0.59 0.69 Y2 2.20 2.30 E X1 0.50 BSC 0.20 0.30 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This Land Pattern Design is based on the IPC-7351 guidelines. Solder Mask Design 3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. Stencil Design 4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 5. The stencil thickness should be 0.125 mm (5 mils). 6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. 7. A 2x2 array of 0.75 mm square openings on 1.15 mm pitch should be used for the center ground pad. Card Assembly 8. A No-Clean, Type-3 solder paste is recommended. 9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 30 Rev. 0.9 Si53308 7. Top Marking 7.1. Si53308 Top Marking 7.2. Top Marking Explanation Mark Method: Laser Font Size: 2.0 Point (28 mils) Center-Justified Line 1 Marking: Device Part Number 53308 Line 2 Marking: Device Revision/Type B-GM Line 3 Marking: TTTTTT = Mfg Code Manufacturing Code. Line 4 Marking Circle = 0.5 mm Diameter Lower-Left Justified Pin 1 Identifier YY = Year WW = Work Week Corresponds to the year and work week of the mold date. Rev. 0.9 31 Si53308 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. Patent Notice Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analogintensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering team. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 32 Rev. 0.9