Si5330 Data Sheet

Si5330
1 . 8 / 2 . 5 / 3 . 3 V L O W - J I T T E R, L O W - S K EW
C L O C K B U F F E R / L E V E L TR A N S L A T O R
Features
18
OEB
19
CLK1A
17
20
CLK1B
16
21
VDDO1
15
22
VDDO2
CLK2A
CLK2B
GND
GND
RSVD_GND
6
7
VDD
RSVD_GND
5
Functional Block Diagram
23
14
IN3
RSVD_GND
24
4
PCI Express 2.0/3.0
 Fibre Channel
 MSAN/DSLAM/PON
 Telecom Line Cards

3
High Speed Clock Distribution
 Ethernet Switch/Router
 SONET / SDH

IN2
2
Applications
IN1
1
Small size: 24-lead, 4 x 4 mm
QFN
13

8
9
10
11
12
RSVD_GND

Pin Assignments
VDDO0

CLK0B

Ordering Information:
See page 14.
CLK3A

VDDO3

RSVD_GND


Output-output skew: 100 ps
Propagation delay: 2.5 ns typ
Single core supply with excellent
PSRR: 1.8, 2.5, or 3.3 V
Output driver supply voltage
independent of core supply: 1.5,
1.8, 2.5, or 3.3 V
Loss of Signal (LOS) indicator
allows system clock monitoring
Output Enable (OEB) pin allows
glitchless control of output clocks
Low power: 10 mA typical core
current
Industrial temperature range:
–40 to +85 °C
CLK0A


LOS


CLK3B

Supports single-ended or
differential input clock signals
Generates four differential
(LVPECL, LVDS, HCSL) or eight
single-ended (CMOS, SSTL,
HSTL) outputs
Provides signal level translation
Differential to single-ended
Single-ended to differential
Differential to differential
Single-ended to single-ended
Wide frequency range
LVPECL, LVDS: 5 to 710 MHz
HCSL: 5 to 250 MHz
SSTL, HSTL: 5 to 350 MHz
CMOS: 5 to 200 MHz
Additive jitter: 150 fs RMS typ
VDD

VDD
Si5330
VDDO0
CLK0
VDDO1
CLK1
Single-ended
or
Differential
IN
VDDO2
Single-ended
or
Differential
CLK2
VDDO3
LOS
OEB
Rev. 1.1 1/13
Control
CLK3
Copyright © 2013 by Silicon Laboratories
Si5330
Si5330
Functional Block Diagrams Based on Orderable Part Number*
1:8 Single-Ended to Single-Ended Buffer
1:4 Differential to Differential Buffer
Si5330A/B/C
VDDO0
Si5330F
CLK0A
CLK0B
IN2
VDDO1
CLK1A
IN3
CLK1B
CLK1B
IN1
VDDO2
CLK2A
IN3
VDDO2
CLK2A
IN2
CLK2B
LOS
OEB
Control
CLK2B
LOS
VDDO3
CLK3A
OEB
Control
CLK3B
1:4 Single-Ended to Differential Buffer
VDDO0
Si5330K/L/M
IN2
CLK0A
CLK0B
CLK0B
CLK1B
IN1
VDDO2
CLK2A
OEB
Control
VDDO2
CLK2A
IN2
CLK2B
CLK2B
LOS
VDDO1
CLK1A
IN3
CLK1B
IN3
LOS
VDDO3
CLK3A
OEB
Control
VDDO3
CLK3A
CLK3B
CLK3B
Figure 1. Si5330 Functional Block Diagrams
*Note: See Table 11 for detailed ordering information.
2
VDDO0
CLK0A
VDDO1
CLK1A
IN1
VDDO3
CLK3A
CLK3B
1:8 Differential to Single-Ended Buffer
Si5330G/H/J
CLK0A
CLK0B
VDDO1
CLK1A
IN1
VDDO0
Rev. 1.1
Si5330
TABLE O F C ONTENTS
Section
Page
1. Functional Block Diagrams Based on Orderable Part Number* . . . . . . . . . . . . . . . . . . .2
2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.1. VDD and VDDO Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.2. Loss Of Signal Indicator (LOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.3. Output Enable (OEB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.4. Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.5. Output Driver Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.6. Input and Output Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4. Ordering the Si5330 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6. Orderable Part Numbers and Device Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7. Package Outline: 24-Lead QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
8. Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
9. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
9.1. Si5330 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
9.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Rev. 1.1
3
Si5330
1. Electrical Specifications
Table 1. Recommended Operating Conditions
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85°C)
Parameter
Symbol
Ambient Temperature
Core Supply Voltage
Output Buffer Supply
Voltage
Test Condition
TA
VDD
VDDOn
Min
Typ
Max
Unit
–40
25
85
°C
2.97
3.3
3.63
V
2.25
2.5
2.75
V
1.71
1.8
1.98
V
1.4
—
3.63
V
Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.
Table 2. DC Characteristics
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85°C)
Parameter
Core Supply Current
Output Buffer Supply Current
4
Symbol
Test Condition
Min
Typ
Max
Unit
IDD
50 MHz refclk
—
10
—
mA
LVPECL, 710 MHz
—
—
30
mA
LVDS, 710 MHz
—
—
8
mA
HCSL, 250 MHz
2 pF load capacitance
—
—
20
mA
SSTL, 350 MHz
—
—
19
mA
CMOS, 50 MHz
15 pF load capacitance
—
—
28
mA
CMOS, 200 MHz
2 pF load capacitance
—
—
28
mA
HSTL, 350 MHz
—
—
19
mA
IDDOx
Rev. 1.1
Si5330
Table 3. Performance Characteristics
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85°C)
Parameter
Symbol
CLKIN Loss of Signal Assert
Time
Test Condition
tLOS
CLKIN Loss of Signal De-Assert
Time
tLOS_B
Input-to-Output Propagation
Delay
tPROP
After initial start-up time has
expired
Min
Typ
Max
Unit
—
2.6
5
µs
0.01
0.2
1
µs
—
2.5
4.0
ns
Output-Output Skew
tDSKEW
Outputs at same signal
format
—
—
100
ps
POR to Output Clock Valid
tSTART
Start-up time for output
clocks
—
—
2
ms
Table 4. Input and Output Clock Characteristics
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
5
—
710
MHz
Input Clock (AC Coupled Differential Input Clocks on Pin IN1/2)
Frequency
fIN
Differential Voltage Swing
VPP
710 MHz input
0.4
—
2.4
VPP
Rise/Fall Time
tR/tF
20%–80%
—
—
1.0
ns
Duty Cycle
DC
< 1 ns tr/tf
40
50
60
%
Input Impedance
RIN
10
—
—
k
Input Capacitance
CIN
—
3.5
—
pF
CMOS
5
—
200
MHz
HSTL, SSTL
5
—
350
MHz
–0.1
—
VDD
V
200 MHz, Tr/Tf = 1.3 ns
0.8
—
—
Vpp
Input Clock (DC-Coupled Single-Ended Input Clock on Pin IN3)
Frequency
fIN
Input Voltage
VI
Input Voltage Swing
(CMOS Standard)
Rise/Fall Time
tR/tF
20%–80%
—
—
4
ns
Duty Cycle
DC
< 2 ns tr/tf
40
50
60
%
Input Capacitance
CIN
—
2
—
pF
LVPECL, LVDS
5
—
710
MHz
HCSL
5
—
250
MHz
Output Clocks (Differential)
Frequency
fOUT
Rev. 1.1
5
Si5330
Table 4. Input and Output Clock Characteristics (Continued)
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
VOC
common mode
—
VDDO –
1.45 V
—
V
VSEPP
peak-to-peak singleended swing
0.55
0.8
0.96
VPP
VOC
common mode
1.125
1.2
1.275
V
VSEPP
peak-to-peak singleended swing
0.25
0.35
0.45
VPP
VOC
common mode
0.8
0.875
0.95
V
VSEPP
peak-to-peak singleended swing
0.25
0.35
0.45
VPP
VOC
common mode
0.35
0.375
0.400
V
VSEPP
peak-to-peak singleended swing
0.575
0.725
0.85
VPP
tR/tF
20%–80%
—
—
450
ps
CKn < 350 MHz
45
—
55
%
350 MHz < CLKn <
710 MHz
40
—
60
%
CMOS
5
—
200
MHz
SSTL, HSTL
5
—
350
MHz
LVPECL Output Voltage
LVDS Output Voltage
(2.5/3.3 V)
LVDS Output Voltage
(1.8 V)
HCSL Output Voltage
Rise/Fall Time
Duty Cycle*
DC
Output Clocks (Single-Ended)
Frequency
fOUT
CMOS 20%-80%
Rise/Fall Time
tR/tF
2 pF load
—
0.45
0.85
ns
CMOS 20%-80%
Rise/Fall Time
tR/tF
15 pF load
—
—
2.0
ns
CMOS Output
Resistance
—
50
—

SSTL Output Resistance
—
50
—

HSTL Output Resistance
—
50
—

VDDO–0.3
—
CMOS Output Voltage
VOH
4 mA load
VOL
4 mA load
VOH
VOL
VOH
SSTL Output Voltage
VOL
VOH
VOL
6
SSTL-3 VDDOx = 2.97 to
3.63 V
SSTL-2 VDDOx = 2.25 to
2.75 V
SSTL-18 VDDOx = 1.71
to 1.98 V
Rev. 1.1
V
—
0.3
V
0.45xVDDO+0.41
—
—
V
—
—
0.45xVDDO
–0.41
V
0.5xVDDO+0.41
—
—
V
—
—
0.5xVDDO–
0.41
V
0.5xVDDO+0.34
—
—
—
V
0.5xVDDO–
0.34
V
Si5330
Table 4. Input and Output Clock Characteristics (Continued)
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
VOH
HSTL Output Voltage
Duty Cycle*
Min
Typ
Max
Units
0.5xVDDO +0.3
—
—
V
—
—
0.5xVDDO
–0.3
V
45
—
55
%
VDDO = 1.4 to 1.6 V
VOL
DC
*Note: Input clock has a 50% duty cycle.
Table 5. OEB Input Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Input Voltage Low
VIL
—
—
0.3 x VDD
V
Input Voltage High
VIH
0.7 x VDD
—
—
V
Input Resistance
RIN
20
—
—
k
Table 6. Output Control Pins (LOS)
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Condition
Min
Typ
Max
Unit
Output Voltage Low
VOL
ISINK = 3 mA
0
—
0.4
V
Rise/Fall Time 20–80%
tR/tF
CL < 10 pf, pull up 1 k
—
—
10
ns
Table 7. Jitter Specifications
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85°C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Additive Phase Jitter
(12 kHz–20 MHz)
tRPHASE
0.7 V pk-pk differential input
clock at 622.08 MHz with
70 ps rise/fall time
—
0.150
—
ps RMS
Additive Phase Jitter
(50 kHz–80 MHz)
tRPHASEWB
0.7 V pk-pk differential input
clock at 622.08 MHz with
70 ps rise/fall time
—
0.225
—
ps RMS
Table 8. Thermal Characteristics
Parameter
Symbol
Test Condition
Value
Unit
Thermal Resistance
Junction to Ambient
JA
Still Air
37
°C/W
Thermal Resistance
Junction to Case
JC
Still Air
25
°C/W
Rev. 1.1
7
Si5330
Table 9. Absolute Maximum Ratings1,2,3,4,5
Parameter
Symbol
Test Condition
Value
Unit
DC Supply Voltage
VDD
–0.5 to 3.8
V
Storage Temperature Range
TSTG
–55 to 150
°C
ESD Tolerance
HBM
(100 pF, 1.5 k)
2.5
kV
ESD Tolerance
CDM
550
V
ESD Tolerance
MM
175
V
JESD78 Compliant
Latch-up Tolerance
Junction Temperature
TJ
150
°C
Soldering Temperature
(Pb-free profile)5
TPEAK
260
°C
TP
20–40
sec
Soldering Temperature Time at TPEAK
(Pb-free profile)5
Notes:
1. Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operational sections of this data sheet. Exposure to maximum rating
conditions for extended periods may affect device reliability.
2. 24-QFN package is RoHS compliant.
3. For more packaging information, go to www.silabs.com/support/quality/pages/RoHSInformation.aspx.
4. Moisture sensitivity level is MSL3.
5. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
8
Rev. 1.1
Si5330
2. Functional Description
2.3. Output Enable (OEB)
The Si5330 is a low-jitter, low-skew fanout buffer
optimized for high-performance PCB clock distribution
applications. The device produces four differential or
eight single-ended, low-jitter output clocks from a single
input clock. The input can accept either a single-ended
or a differential clock allowing the device to function as a
clock level translator.
2.1. VDD and VDDO Supplies
The output enable (OEB) pin allows disabling or
enabling of the outputs clocks (CLK0-CLK3). The output
enable is logically controlled to ensure that no glitches
or runt pulses are generated at the output as shown in
Figure 3.
IN
CLKn
The core VDD and output VDDO supplies have separate
and independent supply pins allowing the core supply to
operate at a different voltage than the I/O voltage levels.
Disable
OEB
Disable
Enable
Enable
Figure 3. OEB Glitchless Operation
The VDD supply powers the core functions of the device,
which operates from 1.8, 2.5, or 3.3 V. Using a lower
supply voltage helps minimize the device’s power
consumption. The VDDO supply pins are used to set the
output signal levels and must be set at a voltage level
compatible with the output signal format.
All outputs are enabled when the OEB pin is connected
to ground or below the VIL voltage for this pin.
Connecting the OEB pin to VDD or above the VIH level
will disable the outputs. Both VIL and VIH are specified
in Table 5. All outputs are forced to a logic “low” when
disabled. The OEB pin is 3.3 V tolerant.
2.2. Loss Of Signal Indicator (LOS)
2.4. Input Signals
The input is monitored for a valid clock signal using an
LOS circuit that monitors input clock edges and
declares an LOS condition when signal edges are not
detected over a 1 to 5 μs observation period. The LOS
pin is asserted “low” when activity on the input clock pin
is present. A “high” level on the LOS pin indicates a loss
of signal (LOS). The LOS pin must be pulled to VDD as
shown in Figure 2.
The Si5330 can accept single-ended and differential
input clocks. See “AN408: Termination Options for AnyFrequency, Any-Output Clock Generators and Clock
Buffers—Si5338, Si5334, Si5330” for details on
connecting a wide variety of signals to the Si5330
inputs.
Si5330
VDDO0
CLK0
VDDO1
CLK1
IN
VDD
LOS
Control
The Si5330 supports single-ended output formats of
CMOS, SSTL, and HSTL and differential formats of
LVDS, LVPECL, and HCSL. It is normally required that
the LVDS driver be dc-coupled to the 100  termination
at the receiver end. If your application requires an accoupled 100  load, contact the applications team for
advice. See AN408 for additional information on the
terminations for these driver types.
VDDO2
2.6. Input and Output Terminations
CLK2
See AN408 for detailed information.
3. Ordering the Si5330
VDDO3
1k
2.5. Output Driver Formats
CLK3
0 Valid Clock
1 No Clock
Figure 2. LOS Indicator with External Pull-Up
The Si5330 can be ordered to meet the requirements of
the most commonly-used input and output signal types,
such as CMOS, SSTL, HSTL, LVPECL, LVDS, and
HSCL. See Figure 1, “Si5330 Functional Block
Diagrams,” on page 2 and Table 11, “Order Numbers
and Device Functionality,” on page 14 for specific
ordering information.
Rev. 1.1
9
Si5330
18
CLK0B
VDDO0
OEB
19
CLK1A
17
CLK0A
20
CLK1B
16
RSVD_GND
21
VDDO1
15
3
VDDO2
CLK2A
CLK2B
GND
GND
4
5
7
8
9
10
11
12
VDD
LOS
CLK3B
CLK3A
VDDO3
RSVD_GND
6
RSVD_GND
22
14
2
IN3
RSVD_GND
23
13
IN2
RSVD_GND
24
1
IN1
VDD
4. Pin Descriptions
Note: Center pad must be tied to GND for normal operation.
Table 10. Si5330 Pin Descriptions
Pin #
Pin Name
I/O
Signal Type
1
IN1
I
Multi
Si5330A/B/C/G/H/J Differential Input Devices.
IN2
I
Multi
These pins are used as the differential clock input. IN1 is
the positive input; IN2 is the negative input. Refer to
“AN408: Termination Options for Any-Frequency, AnyOutput Clock Generators and Clock Buffers—Si5338,
Si5334, Si5330” for interfacing and termination details.
Si5330F/K/L/M Single-Ended Input Devices.
These pins are not used. Leave IN1 unconnected and
IN2 connected to ground.
2
Description
Si5330F/K/L/M Single-Ended Devices.
3
IN3
I
Multi
This is the single-ended clock input. Refer to AN408 for
interfacing and termination details.
Si5330A/B/C/G/H/J Differential Input Devices.
This pin is not used. Connect to ground.
10
4
RSVD_GND
Ground.
Must be connected to system ground.
5
RSVD_GND
Ground.
Must be connected to system ground.
6
RSVD_GND
Ground.
Must be connected to system ground.
Rev. 1.1
Si5330
Table 10. Si5330 Pin Descriptions (Continued)
Pin #
7
8
9
10
Pin Name
VDD
LOS
CLK3B
CLK3A
11
VDDO3
12
RSVD_GND
13
CLK2B
I/O
VDD
O
O
O
VDD
Signal Type
Description
Supply
Core Supply Voltage.
The device operates from a 1.8, 2.5, or 3.3 V supply. A
0.1 µF bypass capacitor should be located very close to
this pin.
Open Drain
Loss of Signal Indicator.
0 = CLKIN present.
1 = Loss of signal (LOS).
This pin requires an external 1 kpull-up resistor.
Multi
Si5330A/B/C/K/L/M Differential Output Devices.
This is the negative side of the differential CLK3 output.
Refer to AN408 for interfacing and termination details.
Leave unconnected when not in use.
Si5330F/G/H/J Single-Ended Output Devices.
This is one of the single-ended CLK3 outputs. Both
CLK3A and CLK3B single-ended outputs are in phase.
Refer to AN408 for interfacing and termination details.
Leave unconnected when not is use.
Multi
Si5330A/B/C/K/L/M Differential Devices.
This is the positive side of the differential CLK3 output.
Refer to AN408 for interfacing and termination details.
Leave unconnected when not in use.
Si5330F/G/H/J Single-Ended Devices.
This is one of the single-ended CLK3 outputs. Both
CLK3A and CLK3B single-ended outputs are in phase.
Refer to AN408 for interfacing and termination details.
Leave unconnected when not is use.
Supply
Output Clock Supply Voltage.
Supply voltage for CLK3A/B. Use a 0.1 µF bypass cap
as close as possible to this pin. If CLK3 is not used, this
pin must be tied to VDD (pin 7 and/or pin 24).
Ground.
Must be connected to system ground.
O
Multi
Si5330A/B/C/K/L/M Differential Output Devices.
This is the negative side of the differential CLK2 output.
Refer to AN408 for interfacing and termination details.
Leave unconnected when not in use.
Si5330F/G/H/J Single-Ended Output Devices.
This is one of the single-ended CLK2 outputs. Both
CLK2A and CLK2B single-ended outputs are in phase.
Refer to AN408 for interfacing and termination details.
Leave unconnected when not is use.
Rev. 1.1
11
Si5330
Table 10. Si5330 Pin Descriptions (Continued)
Pin #
14
15
16
17
18
19
20
12
Pin Name
CLK2A
VDDO2
VDDO1
CLK1B
CLK1A
OEB
VDDO0
I/O
O
VDD
VDD
O
O
I
VDD
Signal Type
Description
Multi
Si5330A/B/C/K/L/M Differential Devices.
This is the positive side of the differential CLK2 output.
Refer to AN408 for interfacing and termination details.
Leave unconnected when not in use.
Si5330F/G/H/J Single-Ended Devices.
This is one of the single-ended CLK2 outputs. Both
CLK2A and CLK2B single-ended outputs are in phase.
Refer to AN408 for interfacing and termination details.
Leave unconnected when not is use.
Supply
Output Clock Supply Voltage.
Supply voltage for CLK2A/B. Use a 0.1 µF bypass cap
as close as possible to this pin. If CLK2 is not used, this
pin must be tied to VDD (pin 7 and/or pin 24).
Supply
Output Clock Supply Voltage.
Supply voltage for CLK1A,B. Use a 0.1 µF bypass cap
as close as possible to this pin. If CLK1 is not used, this
pin must be tied to VDD (pin 7 and/or pin 24).
Multi
Si5330A/B/C/K/L/M Differential Output Devices.
This is the negative side of the differential CLK1 output.
Refer to AN408 for interfacing and termination details.
Leave unconnected when not in use.
Si5330F/G/H/J Single-Ended Output Devices.
This is one of the single-ended CLK1 outputs. Both
CLK1A and CLK1B single-ended outputs are in phase.
Refer to AN408 for interfacing and termination details.
Leave unconnected when not is use.
Multi
Si5330A/B/C/K/L/M Differential Devices.
This is the positive side of the differential CLK1 output.
Refer to AN408 for interfacing and termination details.
Leave unconnected when not in use.
Si5330F/G/H/J Single-Ended Devices.
This is one of the single-ended CLK1 outputs. Both
CLK1A and CLK1B single-ended outputs are in phase.
Refer to AN408 for interfacing and termination details.
Leave unconnected when not is use.
CMOS
Output Enable.
All outputs are enabled when the OEB pin is connected
to ground or below the VIL voltage for this pin. Connecting the OEB pin to VDD or above the VIH level will disable the outputs. Both VIL and VIH are specified in
Table 5. All outputs are forced to a logic “low” when disabled. This pin is 3.3 V tolerant.
Supply
Output Clock Supply Voltage.
Supply voltage for CLK0A,B. Use a 0.1 µF bypass cap
as close as possible to this pin. If CLK2 is not used, this
pin must be tied to VDD (pin 7 and/or pin 24).
Rev. 1.1
Si5330
Table 10. Si5330 Pin Descriptions (Continued)
Pin #
21
Pin Name
CLK0B
22
CLK0A
23
RSVD_GND
24
GND
PAD
VDD
GND
I/O
O
O
Signal Type
Description
Multi
Si5330A/B/C/K/L/M Differential Output Devices.
This is the negative side of the differential CLK0 output.
Refer to AN408 for interfacing and termination details.
Leave unconnected when not in use.
Si5330F/G/H/J Single-ended Output Devices.
This is one of the single-ended CLK0 outputs. Both
CLK0A and CLK0B single-ended outputs are in phase.
Refer to AN408 for interfacing and termination details.
Leave unconnected when not is use.
Multi
Si5330A/B/C/K/L/M Differential Devices.
This is the positive side of the differential CLK0 output.
Refer to AN408 for interfacing and termination details.
Leave unconnected when not in use.
Si5330F/G/H/J Single-ended Devices.
This is one of the single-ended CLK0 outputs. Both
CLK0A and CLK0B single-ended outputs are in phase.
Refer to AN408 for interfacing and termination details.
Leave unconnected when not is use.
Ground.
Must be connected to system ground.
VDD
GND
Supply
Core Supply Voltage.
The device operates from a 1.8, 2.5, or 3.3 V supply. A
0.1 µF bypass capacitor should be located very close to
this pin.
Supply
Ground Pad.
This is main ground connection for this device. It is
located at the bottom center of the package. Use as
many vias as possible to connect this pad to the main
ground plane. The device will not function as specified
unless this ground pad is properly connected to ground.
Rev. 1.1
13
Si5330
5. Orderable Part Numbers and Device Functionality
Table 11. Order Numbers and Device Functionality
Input Signal
Format
Output Signal
Format
Number
of
Outputs
Frequency
Range
Si5330A-B00200-GM
Differential
3.3 V LVPECL
4
5 to 710 MHz
Si5330A-B00202-GM
Differential
2.5 V LVPECL
4
5 to 710 MHz
Si5330B-B00204-GM
Differential
3.3 V LVDS
4
5 to 710 MHz
Si5330B-B00205-GM
Differential
2.5 V LVDS
4
5 to 710 MHz
Si5330B-B00206-GM
Differential
1.8 V LVDS
4
5 to 710 MHz
Si5330C-B00207-GM
Differential
3.3 V HCSL
4
5 to 250 MHz
Si5330C-B00208-GM
Differential
2.5 V HCSL
4
5 to 250 MHz
Si5330C-B00209-GM
Differential
1.8 V HCSL
4
5 to 250 MHz
Si5330F-B00214-GM
Single-Ended
3.3 V CMOS
8
5 to 200 MHz
Si5330F-B00215-GM
Single-Ended
2.5 V CMOS
8
5 to 200 MHz
Si5330F-B00216-GM
Single-Ended
1.8 V CMOS
8
5 to 200 MHz
Si5330G-B00217-GM
Differential
3.3 V CMOS
8
5 to 200 MHz
Si5330G-B00218-GM
Differential
2.5 V CMOS
8
5 to 200 MHz
Si5330G-B00219-GM
Differential
1.8 V CMOS
8
5 to 200 MHz
Si5330H-B00220-GM
Differential
3.3 V SSTL
8
5 to 350 MHz
Si5330H-B00221-GM
Differential
2.5 V SSTL
8
5 to 350 MHz
Si5330H-B00222-GM
Differential
1.8 V SSTL
8
5 to 350 MHz
Differential
1.5 V HSTL
8
5 to 350 MHz
Si5330K-B00224-GM
Single-Ended
3.3 V LVPECL
4
5 to 350 MHz
Si5330K-B00226-GM
Single-Ended
2.5 V LVPECL
4
5 to 350 MHz
Part Number1,2
LVPECL Buffers
LVDS Buffers
HCSL Buffers
CMOS Buffers
CMOS Buffers (Differential Input)
SSTL Buffers (Differential Input)
HSTL Buffers (Differential Input)
Si5330J-B00223-GM
LVPECL Buffers (Single-Ended Input)
Notes:
1. Custom configurations with mixed output types are also available. Please contact the factory for ordering details.
2. Add an “R” to the part number to specify tape and reel shipment media. When specifying non-tape-and-reel shipment
media, contact your sales representative for more information.
14
Rev. 1.1
Si5330
Table 11. Order Numbers and Device Functionality (Continued)
Input Signal
Format
Output Signal
Format
Number
of
Outputs
Frequency
Range
Si5330L-B00228-GM
Single-Ended
3.3 V LVDS
4
5 to 350 MHz
Si5330L-B00229-GM
Single-Ended
2.5 V LVDS
4
5 to 350 MHz
Si5330L-B00230-GM
Single-Ended
1.8 V LVDS
4
5 to 350 MHz
Si5330M-B00231-GM
Single-Ended
3.3 V HCSL
4
5 to 250 MHz
Si5330M-B00232-GM
Single-Ended
2.5 V HCSL
4
5 to 250 MHz
Si5330M-B00233-GM
Single-Ended
1.8 V HCSL
4
5 to 250 MHz
Part Number1,2
LVDS Buffers (Single-Ended Input)
HCSL Buffers (Single-Ended Input)
Notes:
1. Custom configurations with mixed output types are also available. Please contact the factory for ordering details.
2. Add an “R” to the part number to specify tape and reel shipment media. When specifying non-tape-and-reel shipment
media, contact your sales representative for more information.
Rev. 1.1
15
Si5330
6. Package Outline: 24-Lead QFN
Figure 4. 24-Lead Quad Flat No-Lead (QFN)
Table 12. Package Dimensions
Dimension
Min
Nom
Max
A
0.80
0.85
0.90
A1
0.00
0.02
0.05
b
0.18
0.25
0.30
D
D2
4.00 BSC.
2.35
2.50
e
0.50 BSC.
E
4.00 BSC.
2.65
E2
2.35
2.50
2.65
L
0.30
0.40
0.50
aaa
0.10
bbb
0.10
ccc
0.08
ddd
0.10
eee
0.05
Notes:
16
1.
2.
3.
4.
All dimensions shown are in millimeters (mm) unless otherwise noted.
Dimensioning and Tolerancing per ANSI Y14.5M-1994.
This drawing conforms to the JEDEC Outline MO-220, variation VGGD-8.
Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
5.
6.
7.
8.
J-STD-020 MSL rating: MSL3.
Terminal base alloy: Cu.
Terminal plating/grid array material: Au/NiPd.
For more packaging information, go to www.silabs.com/support/quality/pages/RoHSInformation.aspx.
Rev. 1.1
Si5330
7. Recommended PCB Layout
Table 13. PCB Land Pattern
Dimension
Min
Nom
Max
P1
2.50
2.55
2.60
P2
2.50
2.55
2.60
X1
0.20
Y1
0.75
0.25
0.80
0.30
0.85
C1
3.90
C2
3.90
E
0.50
Notes:
General
1.
2.
3.
4.
All dimensions shown are in millimeters (mm) unless otherwise noted.
Dimensioning and Tolerancing per ANSI Y14.5M-1994 specification.
This Land Pattern Design is based on the IPC-7351 guidelines.
Connect the center ground pad to a ground plane with no less than five vias to a ground plane that is no more than
20 mils below it. Via drill size should be no smaller than 10 mils. A longer distance to the ground plane is allowed if
more vias are used to keep the inductance from increasing.
Solder Mask Design
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is
to be 60 µm minimum, all the way around the pad.
Stencil Design
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder
paste release.
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins.
9. A 2x2 array of 1.0 mm square openings on 1.25 mm pitch should be used for the center ground pad.
Card Assembly
10. A No-Clean, Type-3 solder paste is recommended.
11. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.
Rev. 1.1
17
Si5330
8. Top Marking
8.1. Si5330 Top Marking
Si5330
Xxxxxx
RTTTTT
YYWW
8.2. Top Marking Explanation
Mark Method:
Laser
Line 1 Marking:
Device Part Number
Line 2 Marking:
Xxxxxx
X = Frequency and configuration code.
xxxxx = Input and output format configuration code.
See "5. Orderable Part Numbers and
Device Functionality" on page 14 for more
information.
Line 3 Marking:
R = Product revision.
TTTTT = Manufacturing trace code.
RTTTTT
Line 4 Marking:
Pin 1 indicator.
Circle with 0.5 mm diameter;
left-justified
YY = Year.
WW = Work week.
Characters correspond to the year and
work week of package assembly.
YYWW
18
Rev. 1.1
Si5330
Si5330
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 0.2
Clarified documentation to reflect that Pin 19 is OEB
(OE Enable Low).
 Updated Table 4, “Jitter Specifications” on page 7.

Revision 0.2 to Revision 0.3





Major editorial updates to improve clarity.
Updated “Additive Jitter” Specification Table.
Updated “Core Supply Current” Specification in
Table 2.
Removed the Low-Power LVPECL output options
from the ordering table in section 5.
Removed D/E ordering options.
Revision 0.3 to Revision 0.35
Typo of 150 ps on front page changed to 150 fs.
 Updated PCB layout notes.
 Added no ac coupling for LVDS outputs.
 Changed input rise/fall time spec to 2 ns.

Revision 0.35 to Revision 1.0
Added maximum junction temperature specification
to Table 9 on page 8.
 Added minimum and maximum duty cycle
specifications to Table 4 on page 5.
 Updated Table 3, “Performance Characteristics,” on
page 5.

Added
Added
maximum propagation delay spec (4 ns).
test condition to tLOS_B in Table 3 on page 5.
Removed
reference to frequency in Output-Output
Skew.

Updated Table 4, “Input and Output Clock
Characteristics,” on page 5.
Input
Input
voltage (max) changed “3.63” to “VDD”
voltage swing (max) change “3.63” with “—”.
Added Table 6, “Output Control Pins (LOS),” on
page 7.
 Added tape and reel ordering information to "5.
Orderable Part Numbers and Device Functionality"
on page 14.
 Added "8. Top Marking" on page 18.

Revision 1.0 to Revision 1.1
Updated ordering information to refer to revision B
silicon.
 Updated top marking explanation in section 8.2.

Rev. 1.1
19
Si5330
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Please visit the Silicon Labs Technical Support web page:
https://www.silabs.com/support/pages/contacttechnicalsupport.aspx
and register to submit a technical support request.
Patent Notice
Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analogintensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering team
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
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the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
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arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
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20
Rev. 1.1