DDR3 RDIMMs Channel

DDR3 RDIMMs Channel
Basics, Topology, Simulations,
and Timing
4/12/2007
©2007 Micron Technology, Inc. All rights reserved. Products are warranted only to meet Micron’s production data sheet specifications.
Information, products and/or specifications are subject to change without notice. All information is provided on an “AS IS” basis without
warranties of any kind. Dates are estimates only. Drawings not to scale. Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
Agenda
• DDR3 RDIMM Basics and Introduction
• DDR3 RDIMM – Topology, Simulation, and Timing
General System Assumptions
Improved Topology
Address/Command/Control
Clock
Data
• DDR3 RDIMM – Raw Cards and Types
• DDR3 RDIMM – Early Development and Micron Support
4/12/2007
©2007 Micron Technology, Inc. All rights reserved.
2
DDR3 RDIMM
Basics and Introduction
4/12/2007
Form Factor
•
The DDR3 RDIMMs keep the same 240-pin edge connector as
DDR2 RDIMMs, but with a different key placement
For DDR2 the key is between pins 64/65
For DDR3 the key is located between pins 48/49
Note the DDR3 RDIMM and DDR3 UDIMM utilize the same edge connector
4/12/2007
©2007 Micron Technology, Inc. All rights reserved.
4
Logic/Drivers
• The DDR3 RDIMMS look a bit different as the PLL is now
included in the same package as the register
Register
DDR2 RDIMM >>>
PLL
DDR3 RDIMM >>>
PLL and register are combined into a single package
4/12/2007
©2007 Micron Technology, Inc. All rights reserved.
5
Improved Termination for Pre-Register
• New for DDR3 – the address / command registers utilize
optional On-Die-Termination (ODT)
4/12/2007
©2007 Micron Technology, Inc. All rights reserved.
6
Improved Termination for Post-Register
• Due to the “Flyby” layout:
The clock/address/command/control traces feed both sides
of the module in a fly-by method
ƒ To better balance Vtt power, most (Left/Right side) address
signals are inverted
ƒ This signal group arrive at the DRAM simultaneously, but there
is a flight time variation between the different DRAM locations
ƒ Termination resistors have been added to the module and are
placed at both ends of the module
4/12/2007
©2007 Micron Technology, Inc. All rights reserved.
7
Additional Power Pins
• DDR3 RDIMMs now require Vtt power
Vtt power edge connector pins at 48, 49, 120 and 240
VTT – Pins 48, 49, 120 and 240
•
VDD(SPD) (pin 236)
To accommodate the temperature sensor option VDD(SPD), the
voltage requirements for the EPROM has changed
ƒ For DDR2 VDD(SPD) was 1.8V – 3.6V
ƒ For DDR3 VDD(SPD) is 3.0V – 3.6V
4/12/2007
©2007 Micron Technology, Inc. All rights reserved.
8
New Voltage Pins and Levels
•
DRAM core and I/O voltage levels, VDD/VDDQ = 1.5V
•
To help improve address/command voltage margins DDR3
RDIMMs also have isolated Vref, routed on two different (wide)
traces
ƒ VREF(DQ) is for data
ƒ VREF(CA) is for command/address
VREF(DQ) – Pin 1
VREF(CA) – Pin 67
4/12/2007
©2007 Micron Technology, Inc. All rights reserved.
9
Data Channel - Loads
• The DDR3 data channel is much like the DDR2 channel,
although DDR3 data rates are twice as fast
DDR3 data rates range from 800MT/s to 1,333MT/s and with
plans to support up to 1.6GT/s
• Most systems will support a maximum of two slots per
channel up to 1,066MT/s (or 4 data loads)
Number of RDIMMS
* DQ Loads
DDR3-800
Two - (DR)
4
DDR3-1067
Two - (DR)
4
DDR3-1333
Two - (DR)
Target (4)
* early assumptions
4/12/2007
©2007 Micron Technology, Inc. All rights reserved.
10
Improvements to the Data Channel
•
The DDR3 data channel can run faster due to enhancements in
the DDR3 component
DDR3 supports dynamic ODT
ƒ Dynamic ODT allows the termination value to change without issuing an
MRS command, which essentially changes the ODT termination “onthe-fly”
ƒ With Dynamic ODT enabled, the DRAM will switch from {normal} ODT to
Dynamic ODT (RTT_WR) when beginning a write burst; and will
subsequently switch back to ODT (RTT_nom) at the completion of the
write burst
DDR2 ODT values reflect only: 50Ω, 75Ω, 150Ω
DDR3 ODT values include: 20Ω, 30Ω, 40Ω, 60Ω, 120Ω
4/12/2007
©2007 Micron Technology, Inc. All rights reserved.
11
Optional Temperature Sensor
• Optional Temperature Sensor
Temperature reporting and threshold settings are accessed
through the SMBus
Threshold crossing is indicated on RDIMM pin 187 using an
open drain output
12 bit resolution
ƒ Has +/- 2°C accuracy, but could be better in the future
-20°C to +125°C range
Supply voltage 3.0V to 3.6V (same as EEPROM VDD(SPD)
• Early temperature sensor data sheets available
4/12/2007
©2007 Micron Technology, Inc. All rights reserved.
12
Agenda
• DDR3 RDIMM Basics and Introduction
• DDR3 RDIMM – Topology, Simulation, and Timing
General System Assumptions
Improved Topology
Address/Command/Control
Clock
Data
• DDR3 RDIMM – Raw Cards and Types
• DDR3 RDIMM – Early Development and Micron Support
4/12/2007
©2007 Micron Technology, Inc. All rights reserved.
13
DDR3 RDIMM
Topology, Simulation, and Timing
General System Assumptions
4/12/2007
General System Assumptions
• Although your actual values may vary, Micron has used
the following preliminary system level assumptions in our
simulations
• These should be referenced for a design starting point
only
A complete system simulation and timing analyses
must be completed to ensure functionality
4/12/2007
©2007 Micron Technology, Inc. All rights reserved.
15
General System Assumptions
• System Board Lead-in Nominal Impedance (UDIMM)
System Board Lead-in Nominal Impedance and Reference
DQ
40-ohms to 50-ohms
Ground
DQS/DQS (SINGLE ENDED)
40-ohms to 50-ohms
Ground
CMD/Address
40-ohms to 50-ohms
Ground
Control
40-ohms to 50-ohms
Power
Clocks (Differential)
40-ohms to 50-ohms
Power
For least amount of noise, all lead-In traces should be
“strip-line”
Signals should be power or ground plan reference
4/12/2007
©2007 Micron Technology, Inc. All rights reserved.
16
General System Assumptions
• Controller Break out Impedance and lengths used for
initial simulations (UDIMM)
Controller Break out Impedance
Length range for breakout
DQ
50-ohms to 60-ohms
0.2" to 1.0"
DQS/DQS (SINGLE ENDED)
50-ohms to 60-ohms
0.2" to 1.0"
CMD/Address
50-ohms to 60-ohms
0.2" to 1.0"
Control
50-ohms to 60-ohms
0.2" to 1.0"
Clocks
50-ohms to 60-ohms
0.2" to 1.0"
4/12/2007
©2007 Micron Technology, Inc. All rights reserved.
17
General System Assumptions
• System Board Lead-in Length (inches) including breakout
(UDIMM)
System Board Lead-in Length (inches) including breakout
DQ/DQS
1.0" to 7.0"
CMD/Address
1.0" to 5.0"
Control
1.0" to 5.0"
Clocks
1.0" to 5.5"
Byte lane lengths do not need to match, but within each byte
lane the lengths and propagation delay should match
4/12/2007
©2007 Micron Technology, Inc. All rights reserved.
18
General System Assumptions
• Ron Nominal Drive strength in ohms (UDIMM)
Actual register values from different vendors may vary
Ron Nominal Drive strength in Ohms
DQ
30-ohms to 40-ohms (1& 2-slots/ch)
Control
30-ohms to 40-ohms (1 & 2-slots/ch)
C/A
20-ohms to 40-ohms (2-slots/ch)
30-ohms to 40-ohms (1-slot/ch)
Clock
30-ohms to 40-ohms (1 & 2-slots/ch)
Controller drives a
heaver load on UDIMMs
4/12/2007
©2007 Micron Technology, Inc. All rights reserved.
RDIMM controller typically
only drives 2 loads
19
General System Assumptions
• Driver slew rate (Controller) - UDIMM
Driver slew rate (Controller)
DQ
V/ns
2V/ns to 5V/ns (PVT range)
into 50-ohms test load pulled up to VddQ/2
Control
V/ns
1V/ns to 3V/ns (PVT range)
into 50-ohms test load pulled up to VddQ/2
CMD/Address V/ns
1V/ns to 3V/ns (PVT range)
into 50-ohms test load pulled up to VddQ/2
Clock
2V/ns to 5V/ns (PVT range)
into 50-ohms test load pulled up to VddQ/2
V/ns
4/12/2007
©2007 Micron Technology, Inc. All rights reserved.
20
General System Assumptions
• Typical RDIMM spacing (UDIMM)
Typical RDIMM spacing
Distance between RDIMMs in a 2-slots/ch system
0.4" to 0.6"
Note: additional DIMM spacing may be required for module
thermal aspects
4/12/2007
©2007 Micron Technology, Inc. All rights reserved.
21
DDR3 RDIMM
Topology, Simulation, and Timing
Improved Topology, Fly-by
4/12/2007
Comparison of Tree to Fly-By
• DDR2 clock/command/control and addresses use a “tree”
topology
Each branch has multiple loads and stubs
VTT termination is on the system board and not at the end of
the individual stubs
• DDR3 uses a “fly-by” topology
The stub to each individual DRAM is very short
There is VTT termination at the far end of the bus
4/12/2007
©2007 Micron Technology, Inc. All rights reserved.
23
Comparison of Tree to Fly-By
• An example comparing the address structure of the two
topologies
Fly-By Topology (SR x8)
Tree Topology (SR x8 w/ECC)
4/12/2007
©2007 Micron Technology, Inc. All rights reserved.
24
Comparison of Tree to Fly-By
• Address data eye diagrams at the DRAM (1T)
Fly-By Topology
Tree Topology
At
4/12/2007
©2007 Micron Technology, Inc. All rights reserved.
0M
0
4
25
bp
s
Comparison of Tree to Fly-By
• For DDR3, the address/command and control are designed
to operate up to 800Mbps (DDR3-1600)
Fly-By Topology (Only)
4/12/2007
©2007 Micron Technology, Inc. All rights reserved.
26
Comparison of Tree to Fly-By
• Typical frequency response for:
Tree Topology
0
m2
m1
freq=234.0MHz
freq=333.0MHz
dB(U6)=-12.608 dB(U6)=-18.900
INDEX2=0.000000 INDEX2=0.000000
m1
m2
-10
0
-20
m3
freq= 801.0MHz
dB(D0)=-7.342
INDEX1=0.000000
m1
freq= 372.0MHz
dB(D0)=-6.137
INDEX1=0.000000
m1 m3
m2
m2
freq= 537.0MHz
dB(D0)=-9.577
INDEX1=0.000000
-10
-30
dB(D0)
dB(U6)
Fly-By Topology
-40
-50
-20
-30
-40
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
-50
freq, GHz
0.0
0.5
1.0
1.5
freq, GHz
4/12/2007
©2007 Micron Technology, Inc. All rights reserved.
27
2.0
2.5
3.0
Comparison of Tree to Fly-By
Tree Bus Topology
•
Fly-By Topology
Pros
•
Pros
Arrival time skew at
High bandwidth
various DRAM devices
It could be terminated
could be made very
better than tree bus at
small (negligible)
•
far end of the bus
Cons
•
Less data-eye margin
Cons
Arrival time skew at
various DRAM devices
4/12/2007
©2007 Micron Technology, Inc. All rights reserved.
28
DDR3 RDIMM
Topology, Simulation, and Timing
Command Bus and Timing
(Pre-Register and Post-Register)
4/12/2007
Pre Register Address Timing Example (Light Load)
• Pre-Register Timing DDR3-1333 (clock rate = 667 MHz)
Single R/C A (SRx8) module, in system
Measured at Slot 2
*The PRBS pattern will have a slightly smaller aperture
4/12/2007
©2007 Micron Technology, Inc. All rights reserved.
30
Pre Register Address Timing Example (Light Load)
• Pre-Register Timing DDR3-1333 (clock rate = 667 MHz)
Two R/C A (SRx8) modules, in system
Measured at Slot 2
*The PRBS pattern will have a slightly smaller aperture
4/12/2007
©2007 Micron Technology, Inc. All rights reserved.
31
Post Register Address Timing Example (Light Load)
• Topology for address/command/control left side
18.9
3.1
3.7
SDRAM
Register
13.6
U7
U6
U8
U5
Reg
U10
U2
U11
U1
U12
3.7
SDRAM
13.6
3.7
SDRAM
13.6
3.7
SDRAM
60 ohm Trace
All Dimensions are in mm
13.6
47 Ω
1.1
8.9
SDRAM
VTT
4/12/2007
©2007 Micron Technology, Inc. All rights reserved.
3.7
32
Post Register Address Timing Example (Light Load)
U7
U6
U8
U5
Reg
U10
U2
U11
U1
U12
• Topology for clock left side
VDD
2.3
SDRAM
2.3
0.1 uF
SDRAM
47 ohm
REGISTER
0.6
5
19
13.6
13.6
2.3
SDRAM
60 ohm Trace
All dimensions are in mm
4/12/2007
©2007 Micron Technology, Inc. All rights reserved.
33
13.6
13.6
2.3
SDRAM
1.2
10.3
2.3
SDRAM
Post Register Address Timing Example (Light Load)
POST-Register Timing Address to Clock
•
DDR3-1333 (clock rate = 667.67 MHz)
Single R/C A (SRx8) module in system
Measured at first DRAM to the left of the register
U7
U6
U8
U5
Reg
U10
U2
U11
U1
U12
•Using a moderate driver 20-25 ohms
•Fast Corner
•Clock shown as single ended
•DRAM tIS = 225ps tIH = 225ps
4/12/2007
©2007 Micron Technology, Inc. All rights reserved.
34
Post Register Address Timing Example (Light Load)
POST-Register Timing Address to Clock
•
DDR3-1333 (clock rate = 667.67 MHz)
Single R/C A (SRx8) module in system
Measured at second DRAM to the left of the register
U7
U6
U8
U5
Reg
U10
U2
U11
U1
U12
•Using a moderate driver 20-25 ohms
•Fast Corner
•Clock shown as single ended
•DRAM tIS = 225ps tIH = 225ps
4/12/2007
©2007 Micron Technology, Inc. All rights reserved.
35
Post Register Address Timing Example (Light Load)
POST-Register Timing Address to Clock
•
DDR3-1333 (clock rate = 667.67 MHz)
Single R/C A (SRx8) module in system
Measured at third DRAM to the left of the register
U7
U6
U8
U5
Reg
U10
U2
U11
U1
U12
•Using a moderate driver 20-25 ohms
•Fast Corner
•Clock shown as single ended
•DRAM tIS = 225ps tIH = 225ps
4/12/2007
©2007 Micron Technology, Inc. All rights reserved.
36
Post Register Address Timing Example (Light Load)
POST-Register Timing Address to Clock
•
DDR3-1333 (clock rate = 667.67 MHz)
Single R/C A (SRx8) module in system
Measured at forth DRAM to the left of the register
U7
U6
U8
U5
Reg
U10
U2
U11
U1
U12
•Using a moderate driver 20-25 ohms
•Fast Corner
•Clock shown as single ended
•DRAM tIS = 225ps tIH = 225ps
4/12/2007
©2007 Micron Technology, Inc. All rights reserved.
37
Post Register Address Timing Example (Light Load)
POST-Register Timing Address to Clock
•
ƒ DDR3-1333 (clock rate = 667.67 MHz)
ƒ Single R/C A (SRx8) module in system
ƒ Measured at fifth DRAM to the left of the register
U7
U6
U8
U5
Reg
U10
U2
U11
U1
U12
•Using a moderate driver 20-25 ohms
•Fast Corner
•Clock shown as single ended
•DRAM tIS = 225ps tIH = 225ps
4/12/2007
©2007 Micron Technology, Inc. All rights reserved.
38
Post Register Address Timing Example (Light Load) - SR x8
•Fast Corner @ 1,333MT/s (clock = 667 MHz)
POST-Register Timing Clock
U7
U6
U8
39
U5
Reg
U10
U2
U11
©2007 Micron Technology, Inc. All rights reserved.
U1
U12
4/12/2007
Single R/C A (SRx8) module
in system
DDR3-1333 (clock rate = 667
MHz)
Shows all CK0A and A6A from
the left side
Post Register Address Timing Example (Heavy Load) - DR x4
•Fast Corner @ 1,333MT/s (clock = 667 MHz)
R/C J , DR x4 (36 DRAM)
Shown with differential clocks
CK0A with moderate drive
WEA with moderate drive
4/12/2007
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40
DDR3 RDIMM
Topology, Simulation, and Timing
Data Bus and Timing
4/12/2007
Data Bus
• Topology (single slot) DR x4
12.03
DRAM 1
0.59
Outer Trace 55 ohm
1.55
Inner Trace 45 ohm
Outer Trace 60 ohm
15 ohm
Inner Trace 60 ohm
All Dimensions are in mm
3.10
12.70
Controller
4/12/2007
©2007 Micron Technology, Inc. All rights reserved.
152.00
12.70
7.62
SLOT 1
42
SLOT 2
Data Bus
•
Single slot populated (DR x4)
•
Write to Slot 1, Rank 1
•
Signal probed at DRAM
4/12/2007
©2007 Micron Technology, Inc. All rights reserved.
Clock Rate = 533 MHz
(DDR3-1066)
43
Data Bus
• Topology (both slots) DR x4
DRAM 1
DRAM 1
0.57
11.61
DRAM 2
11.61
1.1
7
0.57
1.1
7
15 ohm
Controller
152.00
12.70
DRAM 2
0.57
15 ohm
3.6
0
12.70
0.57
3.60
7.62
SLOT 1
Outer Trace 55 ohm
Inner Trace 45 ohm
SLOT 2
Outer Trace 60 ohm
Inner Trace 60 ohm
All Dimensions are in mm
4/12/2007
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44
Data Bus
•
Both slots populated (DR x4)
•
Write to Slot 1, Rank 1
•
Signal probed at DRAM
4/12/2007
©2007 Micron Technology, Inc. All rights reserved.
Clock Rate = 533 MHz
(DDR3-1066)
45
Data Bus
•
Single slot populated (DR x4)
•
READ from Slot 1, Rank 1
•
Signal probed at Controller, Controller ODT = 75 ohm
4/12/2007
©2007 Micron Technology, Inc. All rights reserved.
Clock Rate = 533 MHz
(DDR3-1066)
46
Data Bus
•
Both slots populated (DR x4)
•
READ from Slot 1, Rank 1
•
Signal probed at Controller, Controller ODT = 75 ohm
4/12/2007
©2007 Micron Technology, Inc. All rights reserved.
Clock Rate = 533 MHz
(DDR3-1066)
47
DRAM On-Die-Termination (ODT) Suggestions
• WRITE Table for a two slot channel
For transfer rates of 1,066Mb/s
Slot 1
Slot 2
Write To
Controll
er ODT
Rank 1
Rank 2
Rank 1
Rank 2
Slot 1
off
120Ω
ODT off
ODT off
30Ω
Slot 2
off
ODT off
30Ω
120Ω
ODT off
Slot 1
off
120Ω
ODT off
20Ω
na
Slot 2
off
ODT off
20Ω
120Ω
na
Slot 1
off
120Ω
na
ODT off
20Ω
Slot 2
off
20Ω
na
120Ω
ODT off
Slot 1
off
120Ω
na
30Ω
na
Slot 2
off
30Ω
na
120Ω
na
Slot 1
Slot 2
DR
DR
DR
SR
SR
DR
SR
SR
DR
Empty
Slot 1
off
40Ω
ODT off
na
na
Empty
DR
Slot 2
off
na
na
40Ω
ODT off
SR
Empty
Slot 1
off
40Ω
na
na
na
Empty
SR
Slot 2
off
na
na
40Ω
na
4/12/2007
©2007 Micron Technology, Inc. All rights reserved.
48
Dynamic ODT
Required
DRAM On-Die-Termination (ODT) suggestions
• READ Table for a two slot channel
For transfer rates of 1,066Mb/s
Slot 1
Slot 2
READ
From
Controll
er ODT
Rank 1
Rank 2
Rank 1
Rank 2
Slot 1
75Ω
ODT off
ODT off
ODT off
30Ω
Slot 2
75Ω
ODT off
30Ω
ODT off
ODT off
Slot 1
75Ω
ODT off
ODT off
20Ω
na
Slot 2
75Ω
ODT off
20Ω
ODT off
na
Slot 1
75Ω
ODT off
na
ODT off
20Ω
Slot 2
75Ω
20Ω
na
ODT off
ODT off
Slot 1
75Ω
ODT off
na
30Ω
na
Slot 2
75Ω
30Ω
na
ODT off
na
Slot 1
Slot 2
DR
DR
DR
SR
SR
DR
SR
SR
DR
Empty
Slot 1
75Ω
ODT off
ODT off
na
na
Empty
DR
Slot 2
75Ω
na
na
ODT off
ODT off
SR
Empty
Slot 1
75Ω
ODT off
na
na
na
Empty
SR
Slot 2
75Ω
na
na
ODT off
na
4/12/2007
©2007 Micron Technology, Inc. All rights reserved.
49
Early Timing Budget
• READs at DDR3-1066
4/12/2007
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50
Early Timing Budget
• WRITEs at DDR3-1066
4/12/2007
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51
Agenda
• DDR3 RDIMM Basics and Introduction
• DDR3 RDIMM – Topology, Simulation, and Timing
General System Assumptions
Improved Topology
Address/Command/Control
Clock
Data
• DDR3 RDIMM – Raw Cards and Types
• DDR3 RDIMM – Early Development and Micron Support
4/12/2007
©2007 Micron Technology, Inc. All rights reserved.
52
DDR3 RDIMM - R/C Options
• JEDEC modules supported by Micron
SR x8 (R/C A), Micron designed
DR x8 (R/C B)
SR x4 (R/C C)
DR x4 stacked (R/C D)
DR x4 planar (R/C J)
• Additional high density modules will be offered at increased
heights to address custom applications
4/12/2007
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53
DDR3 RDIMM - R/C Options
• VLP RDIMMs
Most Micron modules will be available at 17.9mm overall
height, currently the industry is considering 18.75mm tall
maximum for VLP
ƒ SR x8
ƒ DR x8
ƒ SR x4
ƒ DR x4 stacked
• A 18.75mm tall VLP may require a custom socket to make
the module fit into the ACTA form factor?
4/12/2007
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54
VLP RDIMMs – Sockets
• Micron supports a DDR3 17.9mm tall VLP!!!
Our DDR3 VLP will fit the ATCA form factor with a standard
socket (it will fit in the custom socket too)
Socket for Micron VLP
Industry Standard (short) VLP
Standard socket <$$$
4/12/2007
©2007 Micron Technology, Inc. All rights reserved.
55
Pending short
ATCA socket
(Option A)
Pending short
ATCA socket
(Option B)
Custom Socket will
have a higher
insertion force due
ultra short spring
connectors
Custom Socket will
have a higher lead-in
inductance which
could severally affect
high-speed
functionality?
Agenda
• DDR3 RDIMM Basics and Introduction
• DDR3 RDIMM – Topology, Simulation, and Timing
General System Assumptions
Improved Topology
Address/Command
Data
• DDR3 RDIMM – Raw Cards and Types
• DDR3 RDIMM – Early Development and Micron Support
4/12/2007
©2007 Micron Technology, Inc. All rights reserved.
56
System Verification
• Micron validates our models and modules in the lab
For our DR x8 (R/C A)
we have simulated with
HSPICE what the A13
signal should look like
if probed near DRAM
location U1
4/12/2007
©2007 Micron Technology, Inc. All rights reserved.
57
System Verification
• Micron validates our models and modules in the lab
For our DR x8 (R/C A) we
have simulated with
HSPICE what the A13
signal should look like if
probed near DRAM
location U1
Then in the lab, we
measure the signal to
correlate our simulations
4/12/2007
©2007 Micron Technology, Inc. All rights reserved.
58
System Development
Logic Analyzer Interface Modules (Snoop DIMMs)
4/12/2007
©2007 Micron Technology, Inc. All rights reserved.
59
Micron Development Tools
• Use passive probe hardware and software from NEXUS™
(http://www.nexustechnology.com/)
• Modules designed to interface to Tektronics™ Logic
Analyzer
• All DQ, clock, command, control and address signals probed
with no impact on module functionality
Micron Snoop RDIMMs available – 3Q07
• R/C A
• R/C C
• R/C D
4/12/2007
©2007 Micron Technology, Inc. All rights reserved.
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